kopia lustrzana https://github.com/espressif/esp-idf
101 wiersze
3.5 KiB
C
101 wiersze
3.5 KiB
C
/*
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* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "bootloader_random.h"
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#include "soc/soc.h"
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#include "soc/adc_reg.h"
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#include "soc/pmu_reg.h"
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#include "soc/regi2c_saradc.h"
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#include "soc/hp_sys_clkrst_reg.h"
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#include "soc/rtcadc_reg.h"
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#include "esp_private/regi2c_ctrl.h"
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#include "esp_rom_regi2c.h"
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// TODO IDF-6497: once ADC API is supported, use the API instead of defining functions and constants here
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#define I2C_SAR_ADC_INIT_CODE_VAL 2166
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typedef struct {
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int atten;
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int channel;
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} pattern_item;
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typedef struct {
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pattern_item item[4];
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} pattern_table;
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static void adc1_fix_initcode_set(uint32_t initcode_value)
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{
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uint32_t msb = initcode_value >> 8;
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uint32_t lsb = initcode_value & 0xff;
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REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SAR_ADC_SAR1_INIT_CODE_MSB, msb);
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REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SAR_ADC_SAR1_INIT_CODE_LSB, lsb);
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}
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//total 4 tables
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static void hpadc_sar1_pattern_table_cfg(unsigned int table_idx, pattern_table table)
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{
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uint32_t wdata = 0;
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wdata = (table.item[0].channel << 20 | table.item[0].atten << 18 |
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table.item[1].channel << 14|table.item[1].atten << 12 |
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table.item[2].channel << 8 |table.item[2].atten << 6 |
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table.item[3].channel << 2 |table.item[3].atten);
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WRITE_PERI_REG(ADC_SAR1_PATT_TAB1_REG + table_idx * 4, wdata);
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}
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void bootloader_random_enable(void)
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{
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pattern_table sar1_table[4] = {};
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uint32_t pattern_len = 0;
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SET_PERI_REG_MASK(HP_SYS_CLKRST_SOC_CLK_CTRL2_REG, HP_SYS_CLKRST_REG_ADC_APB_CLK_EN);
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SET_PERI_REG_MASK(HP_SYS_CLKRST_PERI_CLK_CTRL23_REG, HP_SYS_CLKRST_REG_ADC_CLK_EN);
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SET_PERI_REG_MASK(RTCADC_MEAS1_MUX_REG, RTCADC_SAR1_DIG_FORCE);
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SET_PERI_REG_MASK(PMU_RF_PWC_REG,PMU_XPD_PERIF_I2C);
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uint32_t sar1_clk_div_num = GET_PERI_REG_BITS2((HP_SYS_CLKRST_PERI_CLK_CTRL24_REG),
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(HP_SYS_CLKRST_REG_ADC_SAR1_CLK_DIV_NUM_M),
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(HP_SYS_CLKRST_REG_ADC_SAR1_CLK_DIV_NUM_S));
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SET_PERI_REG_MASK(ADC_CTRL_REG_REG, ADC_START_FORCE); //start force 1
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adc1_fix_initcode_set(I2C_SAR_ADC_INIT_CODE_VAL);
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// cfg pattern table
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sar1_table[0].item[0].channel = 10; //rand() % 6;
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sar1_table[0].item[0].atten = 3;
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sar1_table[0].item[1].channel = 10;
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sar1_table[0].item[1].atten = 3;
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sar1_table[0].item[2].channel = 10;
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sar1_table[0].item[2].atten = 3;
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sar1_table[0].item[3].channel = 10;
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sar1_table[0].item[3].atten = 3;
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hpadc_sar1_pattern_table_cfg(0, sar1_table[0]);
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SET_PERI_REG_BITS(ADC_CTRL_REG_REG, ADC_SAR1_PATT_LEN, pattern_len, ADC_SAR1_PATT_LEN_S);
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SET_PERI_REG_BITS(ADC_CTRL_REG_REG, ADC_XPD_SAR1_FORCE, 3, ADC_XPD_SAR1_FORCE_S);
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SET_PERI_REG_BITS(ADC_CTRL_REG_REG, ADC_XPD_SAR2_FORCE, 3, ADC_XPD_SAR2_FORCE_S);
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REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SAR_ADC_ENT_VDD_GRP1, 1);
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REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SAR_ADC_DTEST_VDD_GRP1, 0);
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CLEAR_PERI_REG_MASK(ADC_CTRL_REG_REG, ADC_START_FORCE);
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SET_PERI_REG_MASK(ADC_CTRL2_REG, ADC_TIMER_EN);
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SET_PERI_REG_BITS(ADC_CTRL2_REG, ADC_TIMER_TARGET, sar1_clk_div_num * 25, ADC_TIMER_TARGET_S);
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while (GET_PERI_REG_MASK(ADC_INT_RAW_REG, ADC_SAR1_DONE_INT_RAW) == 0) { }
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SET_PERI_REG_MASK(ADC_INT_CLR_REG, ADC_APB_SARADC1_DONE_INT_CLR);
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}
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void bootloader_random_disable(void)
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{
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// No-op for now TODO IDF-6497
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// ADC should be set to defaults here, once ADC API is implemented
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// OR just keep this empty and let application continue to use RNG initialized by the bootloader
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}
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