kopia lustrzana https://github.com/espressif/esp-idf
71 wiersze
3.2 KiB
C
71 wiersze
3.2 KiB
C
/*
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include "soc/soc.h"
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#include "soc/soc_caps.h"
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#include "soc/rtc_cntl_reg.h"
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#include "esp_attr.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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FORCE_INLINE_ATTR void cpu_utility_ll_reset_cpu(uint32_t cpu_no)
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{
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/*
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Note: This function can be called when the cache is disabled. We use "ternary if" instead of an array so that the
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"rodata" of the register masks/shifts will be stored in this function's "rodata" section, instead of the source
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file's "rodata" section (see IDF-5214).
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*/
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uint32_t rtc_cntl_rst = (cpu_no == 0) ? RTC_CNTL_SW_PROCPU_RST_M : RTC_CNTL_SW_APPCPU_RST_M;
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SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, rtc_cntl_rst);
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}
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#if SOC_CPU_CORES_NUM > 1 // We only allow stalling/unstalling of other cores
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FORCE_INLINE_ATTR void cpu_utility_ll_stall_cpu(uint32_t cpu_no)
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{
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/*
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We need to write the value "0x86" to stall a particular core. The write location is split into two separate
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bit fields named "c0" and "c1", and the two fields are located in different registers. Each core has its own pair of
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"c0" and "c1" bit fields.
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Note: This function can be called when the cache is disabled. We use "ternary if" instead of an array so that the
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"rodata" of the register masks/shifts will be stored in this function's "rodata" section, instead of the source
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file's "rodata" section (see IDF-5214).
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*/
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uint32_t rtc_cntl_c0_m = (cpu_no == 0) ? RTC_CNTL_SW_STALL_PROCPU_C0_M : RTC_CNTL_SW_STALL_APPCPU_C0_M;
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uint32_t rtc_cntl_c0_s = (cpu_no == 0) ? RTC_CNTL_SW_STALL_PROCPU_C0_S : RTC_CNTL_SW_STALL_APPCPU_C0_S;
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uint32_t rtc_cntl_c1_m = (cpu_no == 0) ? RTC_CNTL_SW_STALL_PROCPU_C1_M : RTC_CNTL_SW_STALL_APPCPU_C1_M;
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uint32_t rtc_cntl_c1_s = (cpu_no == 0) ? RTC_CNTL_SW_STALL_PROCPU_C1_S : RTC_CNTL_SW_STALL_APPCPU_C1_S;
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CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, rtc_cntl_c0_m);
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SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, 2 << rtc_cntl_c0_s);
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CLEAR_PERI_REG_MASK(RTC_CNTL_SW_CPU_STALL_REG, rtc_cntl_c1_m);
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SET_PERI_REG_MASK(RTC_CNTL_SW_CPU_STALL_REG, 0x21 << rtc_cntl_c1_s);
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}
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FORCE_INLINE_ATTR void cpu_utility_ll_unstall_cpu(uint32_t cpu_no)
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{
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/*
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We need to write clear the value "0x86" to unstall a particular core. The location of this value is split into
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two separate bit fields named "c0" and "c1", and the two fields are located in different registers. Each core has
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its own pair of "c0" and "c1" bit fields.
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Note: This function can be called when the cache is disabled. We use "ternary if" instead of an array so that the
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"rodata" of the register masks/shifts will be stored in this function's "rodata" section, instead of the source
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file's "rodata" section (see IDF-5214).
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*/
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uint32_t rtc_cntl_c0 = (cpu_no == 0) ? RTC_CNTL_SW_STALL_PROCPU_C0_M : RTC_CNTL_SW_STALL_APPCPU_C0_M;
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CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, rtc_cntl_c0);
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int rtc_cntl_c1 = (cpu_no == 0) ? RTC_CNTL_SW_STALL_PROCPU_C1_M : RTC_CNTL_SW_STALL_APPCPU_C1_M;
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CLEAR_PERI_REG_MASK(RTC_CNTL_SW_CPU_STALL_REG, rtc_cntl_c1);
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}
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#endif // SOC_CPU_CORES_NUM > 1
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#ifdef __cplusplus
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}
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#endif
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