kopia lustrzana https://github.com/espressif/esp-idf
36 wiersze
785 B
C
36 wiersze
785 B
C
/*
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdbool.h>
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#include "soc/soc_caps.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if SOC_USB_SERIAL_JTAG_SUPPORTED
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/**
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* @brief USJ test mode values
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*
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* Specifies the logic values of each of the USB FSLS Serial PHY interface
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* signals when in test mode.
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*/
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typedef struct {
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bool dp_pu; /**< D+ pull-up resistor enable/disable */
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bool dm_pu; /**< D- pull-up resistor enable/disable */
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bool dp_pd; /**< D+ pull-down resistor enable/disable */
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bool dm_pd; /**< D- pull-down resistor enable/disable */
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} usb_serial_jtag_pull_override_vals_t;
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#endif // SOC_USB_SERIAL_JTAG_SUPPORTED
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#ifdef __cplusplus
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}
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#endif
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