kopia lustrzana https://github.com/espressif/esp-idf
313 wiersze
11 KiB
C
313 wiersze
11 KiB
C
/*
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* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include "soc/soc_caps.h"
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#include "soc/assist_debug_reg.h"
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#include "soc/interrupt_reg.h"
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#include "esp_attr.h"
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#include "riscv/csr.h"
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#include "riscv/interrupt.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if SOC_CPU_HAS_CSR_PC
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/*performance counter*/
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#define CSR_PCER_MACHINE 0x7e0
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#define CSR_PCMR_MACHINE 0x7e1
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#define CSR_PCCR_MACHINE 0x7e2
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#endif /* SOC_CPU_HAS_CSR_PC */
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#if SOC_CPU_HAS_FPU
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/* FPU bits in mstatus start at bit 13 */
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#define CSR_MSTATUS_FPU_SHIFT 13
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/* FPU registers are clean if bits are 0b10 */
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#define CSR_MSTATUS_FPU_CLEAN_STATE 2
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/* FPU status in mstatus are represented with two bits */
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#define CSR_MSTATUS_FPU_MASK 3
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/* FPU is enabled when writing 1 to FPU bits */
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#define CSR_MSTATUS_FPU_ENA BIT(13)
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/* Set FPU registers state to clean (after being dirty) */
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#define CSR_MSTATUS_FPU_CLEAR BIT(13)
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#endif /* SOC_CPU_HAS_FPU */
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/* SW defined level which the interrupt module will mask interrupt with priority less than threshold during critical sections
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and spinlocks */
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#define RVHAL_EXCM_LEVEL 4
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/* --------------------------------------------------- CPU Control -----------------------------------------------------
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*
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* ------------------------------------------------------------------------------------------------------------------ */
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FORCE_INLINE_ATTR void __attribute__((always_inline)) rv_utils_wait_for_intr(void)
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{
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asm volatile ("wfi\n");
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}
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/* -------------------------------------------------- CPU Registers ----------------------------------------------------
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*
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* ------------------------------------------------------------------------------------------------------------------ */
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FORCE_INLINE_ATTR __attribute__((pure)) uint32_t rv_utils_get_core_id(void)
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{
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#if SOC_CPU_CORES_NUM == 1
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return 0; // No need to check core ID on single core hardware
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#else
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uint32_t cpuid;
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cpuid = RV_READ_CSR(mhartid);
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return cpuid;
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#endif
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}
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FORCE_INLINE_ATTR void *rv_utils_get_sp(void)
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{
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void *sp;
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asm volatile ("mv %0, sp;" : "=r" (sp));
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return sp;
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}
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FORCE_INLINE_ATTR uint32_t __attribute__((always_inline)) rv_utils_get_cycle_count(void)
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{
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#if !SOC_CPU_HAS_CSR_PC
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return RV_READ_CSR(mcycle);
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#else
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return RV_READ_CSR(CSR_PCCR_MACHINE);
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#endif
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}
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FORCE_INLINE_ATTR void __attribute__((always_inline)) rv_utils_set_cycle_count(uint32_t ccount)
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{
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#if !SOC_CPU_HAS_CSR_PC
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RV_WRITE_CSR(mcycle, ccount);
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#else
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RV_WRITE_CSR(CSR_PCCR_MACHINE, ccount);
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#endif
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}
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/* ------------------------------------------------- CPU Interrupts ----------------------------------------------------
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*
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* ------------------------------------------------------------------------------------------------------------------ */
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// --------------- Interrupt Configuration -----------------
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FORCE_INLINE_ATTR void rv_utils_set_mtvec(uint32_t mtvec_val)
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{
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RV_WRITE_CSR(mtvec, mtvec_val | MTVEC_MODE_CSR);
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}
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// ------------------ Interrupt Control --------------------
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FORCE_INLINE_ATTR void rv_utils_intr_enable(uint32_t intr_mask)
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{
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// Disable all interrupts to make updating of the interrupt mask atomic.
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unsigned old_mstatus = RV_CLEAR_CSR(mstatus, MSTATUS_MIE);
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esprv_int_enable(intr_mask);
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RV_SET_CSR(mstatus, old_mstatus & MSTATUS_MIE);
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}
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FORCE_INLINE_ATTR void rv_utils_intr_disable(uint32_t intr_mask)
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{
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// Disable all interrupts to make updating of the interrupt mask atomic.
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unsigned old_mstatus = RV_CLEAR_CSR(mstatus, MSTATUS_MIE);
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esprv_int_disable(intr_mask);
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RV_SET_CSR(mstatus, old_mstatus & MSTATUS_MIE);
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}
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FORCE_INLINE_ATTR void rv_utils_intr_global_enable(void)
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{
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RV_SET_CSR(mstatus, MSTATUS_MIE);
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}
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FORCE_INLINE_ATTR void rv_utils_intr_global_disable(void)
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{
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RV_CLEAR_CSR(mstatus, MSTATUS_MIE);
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}
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/**
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* The other rv_utils functions related to each interrupt controller are defined in `interrupt_clic.h`, `interrupt_plic.h`,
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* and `interrupt_intc.h`.
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*/
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#if SOC_CPU_HAS_FPU
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/* ------------------------------------------------- FPU Related ----------------------------------------------------
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*
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* ------------------------------------------------------------------------------------------------------------------ */
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FORCE_INLINE_ATTR bool rv_utils_enable_fpu(void)
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{
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/* Set mstatus[14:13] to 0b01 to start the floating-point unit initialization */
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RV_SET_CSR(mstatus, CSR_MSTATUS_FPU_ENA);
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/* On the ESP32-P4, the FPU can be used directly after setting `mstatus` bit 13.
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* Since the interrupt handler expects the FPU states to be either 0b10 or 0b11,
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* let's write the FPU CSR and clear the dirty bit afterwards. */
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RV_WRITE_CSR(fcsr, 1);
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RV_CLEAR_CSR(mstatus, CSR_MSTATUS_FPU_CLEAR);
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const uint32_t mstatus = RV_READ_CSR(mstatus);
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/* Make sure the FPU state is 0b10 (clean registers) */
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return ((mstatus >> CSR_MSTATUS_FPU_SHIFT) & CSR_MSTATUS_FPU_MASK) == CSR_MSTATUS_FPU_CLEAN_STATE;
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}
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FORCE_INLINE_ATTR void rv_utils_disable_fpu(void)
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{
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/* Clear mstatus[14:13] bits to disable the floating-point unit */
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RV_CLEAR_CSR(mstatus, CSR_MSTATUS_FPU_MASK << CSR_MSTATUS_FPU_SHIFT);
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}
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#endif /* SOC_CPU_HAS_FPU */
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/* -------------------------------------------------- Memory Ports -----------------------------------------------------
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*
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* ------------------------------------------------------------------------------------------------------------------ */
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/* ---------------------------------------------------- Debugging ------------------------------------------------------
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*
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* ------------------------------------------------------------------------------------------------------------------ */
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// --------------- Breakpoints/Watchpoints -----------------
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FORCE_INLINE_ATTR void rv_utils_set_breakpoint(int bp_num, uint32_t bp_addr)
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{
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/* The code below sets breakpoint which will trigger `Breakpoint` exception
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* instead transferring control to debugger. */
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RV_WRITE_CSR(tselect, bp_num);
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RV_WRITE_CSR(tcontrol, TCONTROL_MPTE | TCONTROL_MTE);
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RV_WRITE_CSR(tdata1, TDATA1_USER | TDATA1_MACHINE | TDATA1_EXECUTE);
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RV_WRITE_CSR(tdata2, bp_addr);
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}
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FORCE_INLINE_ATTR void rv_utils_set_watchpoint(int wp_num,
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uint32_t wp_addr,
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size_t size,
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bool on_read,
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bool on_write)
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{
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RV_WRITE_CSR(tselect, wp_num);
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RV_WRITE_CSR(tcontrol, TCONTROL_MPTE | TCONTROL_MTE);
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RV_WRITE_CSR(tdata1, TDATA1_USER |
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TDATA1_MACHINE |
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((size == 1) ? TDATA1_MATCH_EXACT : TDATA1_MATCH_NAPOT) |
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(on_read ? TDATA1_LOAD : 0) |
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(on_write ? TDATA1_STORE : 0));
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/* From RISC-V Debug Specification:
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* tdata1(mcontrol) match = 0 : Exact byte match
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*
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* tdata1(mcontrol) match = 1 : NAPOT (Naturally Aligned Power-Of-Two):
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* Matches when the top M bits of any compare value match the top M bits of tdata2.
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* M is XLEN − 1 minus the index of the least-significant bit containing 0 in tdata2.
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* Note: Expecting that size is number power of 2 (numbers should be in the range of 1 ~ 31)
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*
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* Examples for understanding how to calculate match pattern to tdata2:
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*
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* nnnn...nnnnn 1-byte Exact byte match
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* nnnn...nnnn0 2-byte NAPOT range
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* nnnn...nnn01 4-byte NAPOT range
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* nnnn...nn011 8-byte NAPOT range
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* nnnn...n0111 16-byte NAPOT range
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* nnnn...01111 32-byte NAPOT range
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* ...
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* n011...11111 2^31 byte NAPOT range
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* * where n are bits from original address
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*/
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uint32_t match_pattern = (wp_addr & ~(size-1)) | ((size-1) >> 1);
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RV_WRITE_CSR(tdata2, match_pattern);
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}
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FORCE_INLINE_ATTR void rv_utils_clear_breakpoint(int bp_num)
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{
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RV_WRITE_CSR(tselect, bp_num);
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/* tdata1 is a WARL(write any read legal) register
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* We can just write 0 to it
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*/
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RV_WRITE_CSR(tdata1, 0);
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}
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FORCE_INLINE_ATTR void rv_utils_clear_watchpoint(int wp_num)
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{
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/* riscv have the same registers for breakpoints and watchpoints */
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rv_utils_clear_breakpoint(wp_num);
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}
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FORCE_INLINE_ATTR bool rv_utils_is_trigger_fired(int id)
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{
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RV_WRITE_CSR(tselect, id);
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return (RV_READ_CSR(tdata1) >> TDATA1_HIT_S) & 1;
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}
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// ---------------------- Debugger -------------------------
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FORCE_INLINE_ATTR bool rv_utils_dbgr_is_attached(void)
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{
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return REG_GET_BIT(ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG, ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE);
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}
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FORCE_INLINE_ATTR void rv_utils_dbgr_break(void)
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{
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asm volatile("ebreak\n");
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}
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/* ------------------------------------------------------ Misc ---------------------------------------------------------
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*
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* ------------------------------------------------------------------------------------------------------------------ */
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FORCE_INLINE_ATTR bool rv_utils_compare_and_set(volatile uint32_t *addr, uint32_t compare_value, uint32_t new_value)
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{
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#if __riscv_atomic
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uint32_t old_value = 0;
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int error = 0;
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/* Based on sample code for CAS from RISCV specs v2.2, atomic instructions */
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__asm__ __volatile__(
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"cas: lr.w %0, 0(%2) \n" // load 4 bytes from addr (%2) into old_value (%0)
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" bne %0, %3, fail \n" // fail if old_value if not equal to compare_value (%3)
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" sc.w %1, %4, 0(%2) \n" // store new_value (%4) into addr,
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" bnez %1, cas \n" // if we failed to store the new value then retry the operation
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"fail: \n"
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: "+r" (old_value), "+r" (error) // output parameters
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: "r" (addr), "r" (compare_value), "r" (new_value) // input parameters
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);
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#else
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// For a single core RV target has no atomic CAS instruction, we can achieve atomicity by disabling interrupts
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unsigned old_mstatus;
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old_mstatus = RV_CLEAR_CSR(mstatus, MSTATUS_MIE);
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// Compare and set
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uint32_t old_value;
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old_value = *addr;
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if (old_value == compare_value) {
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*addr = new_value;
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}
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// Restore interrupts
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RV_SET_CSR(mstatus, old_mstatus & MSTATUS_MIE);
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#endif //__riscv_atomic
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return (old_value == compare_value);
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}
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#if SOC_BRANCH_PREDICTOR_SUPPORTED
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FORCE_INLINE_ATTR void rv_utils_en_branch_predictor(void)
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{
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#define MHCR 0x7c1
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#define MHCR_RS (1<<4) /* R/W, address return stack set bit */
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#define MHCR_BFE (1<<5) /* R/W, allow predictive jump set bit */
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#define MHCR_BTB (1<<12) /* R/W, branch target prediction enable bit */
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RV_SET_CSR(MHCR, MHCR_RS|MHCR_BFE|MHCR_BTB);
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}
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#endif
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#ifdef __cplusplus
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}
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#endif
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