kopia lustrzana https://github.com/espressif/esp-idf
428 wiersze
15 KiB
C
428 wiersze
15 KiB
C
/*
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* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdlib.h>
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#include "spi_flash_chip_generic.h"
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#include "spi_flash_defs.h"
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#include "esp_log.h"
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#include "string.h"
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#include <sys/param.h> // For MIN/MAX
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#include "hal/spi_flash_hal.h"
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#define CMD_OPI_FLASH_MXIC(cmd) ((((~(cmd) & 0xff) << 8)) | ((cmd) & 0xff))
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#define CMD_OPI_FLASH_MXIC_CHIP_ERASE 0x9F60
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#define CMD_OPI_FLASH_MXIC_READ_STR 0x13EC
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#define CMD_OPI_FLASH_MXIC_READ_DTR 0x11EE
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#define CMD_OPI_FLASH_MXIC_RDCR2 0x8E71
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#define CMD_OPI_FLASH_MXIC_WRCR2 0x8D72
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/* Driver for MXIC OPI flash chip */
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static const char chip_name[] = "mxic (opi)";
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esp_err_t spi_flash_chip_mxic_opi_probe(esp_flash_t *chip, uint32_t flash_id)
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{
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/* Check manufacturer and product IDs match our desired masks */
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const uint8_t MFG_ID = 0xC2;
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if (flash_id >> 16 != MFG_ID) {
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return ESP_ERR_NOT_FOUND;
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}
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if (chip->read_mode < SPI_FLASH_OPI_FLAG) {
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// The code here serve for opi flash under opi mode only, for ordinary mxic chip, go `spi_flash_chip_mxic.c`
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return ESP_ERR_NOT_FOUND;
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}
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return ESP_OK;
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}
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esp_err_t spi_flash_chip_mxic_opi_detect_size(esp_flash_t *chip, uint32_t *size)
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{
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uint32_t id = chip->chip_id;
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*size = 0;
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/* Can't detect size unless the high byte of the product ID matches the same convention, which is usually 0x40 or
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* 0xC0 or similar. */
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if (((id & 0xFFFF) == 0x0000) || ((id & 0xFFFF) == 0xFFFF)) {
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return ESP_ERR_FLASH_UNSUPPORTED_CHIP;
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}
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*size = 1 << ((id & 0xFF) - 0x20);
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return ESP_OK;
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}
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spi_flash_caps_t spi_flash_chip_mxic_opi_get_caps(esp_flash_t *chip)
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{
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spi_flash_caps_t caps_flags = 0;
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caps_flags |= SPI_FLASH_CHIP_CAP_32MB_SUPPORT;
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// flash-suspend is not supported yet. // IDF-3852
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// reading unique id is not supported.
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return caps_flags;
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}
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esp_err_t spi_flash_chip_mxic_opi_set_write_protect(esp_flash_t *chip, bool write_protect)
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{
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esp_err_t err = ESP_OK;
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err = chip->chip_drv->wait_idle(chip, chip->chip_drv->timeout->idle_timeout);
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spi_flash_trans_t t = {};
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if (err == ESP_OK || err == ESP_ERR_NOT_SUPPORTED) {
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if(write_protect) {
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t.command = CMD_OPI_FLASH_MXIC(CMD_WRDI);
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} else {
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t.command = CMD_OPI_FLASH_MXIC(CMD_WREN);
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}
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err = chip->host->driver->common_command(chip->host, &t);
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}
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bool wp_read;
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err = chip->chip_drv->get_chip_write_protect(chip, &wp_read);
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if (err == ESP_OK && wp_read != write_protect) {
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err = ESP_ERR_NOT_FOUND;
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}
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return err;
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}
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static void spi_flash_chip_mxic_opi_get_data_length_zoom(esp_flash_io_mode_t io_mode, uint32_t *length_zoom)
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{
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/* Under STR mode, one byte occupies one single clock. While under DTR mode, one byte occupies half clock.
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For exmaple, if an operation needs 3 clock dummy, host send 3 dummy bytes under STR mode, while 6 dummy bytes under DTR mode.
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Therefore, we need to adjust data zoom to fit the clock here. */
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assert((io_mode == SPI_FLASH_OPI_STR) || (io_mode == SPI_FLASH_OPI_DTR));
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*length_zoom = (io_mode == SPI_FLASH_OPI_STR) ? 1 : 2;
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}
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esp_err_t spi_flash_chip_mxic_opi_read_id(esp_flash_t *chip, uint32_t* out_chip_id)
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{
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uint64_t id_buf = 0;
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uint32_t length_zoom;
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spi_flash_chip_mxic_opi_get_data_length_zoom(chip->read_mode, &length_zoom);
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spi_flash_trans_t t = {
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.command = CMD_OPI_FLASH_MXIC(CMD_RDID),
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.miso_len = 3 * length_zoom,
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.dummy_bitlen = 4 * length_zoom,
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.address_bitlen = 32,
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.miso_data = ((uint8_t*) &id_buf),
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};
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chip->host->driver->common_command(chip->host, &t);
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if(chip->read_mode == SPI_FLASH_OPI_DTR) {
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// Adjust the id_buf in DTR mode, because in DTR mode, the data back in STR rule.
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// So it looks like [MD, MD, MT, MT, MID, MID], adjust it to [MD, MT, MID] here.
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ESP_EARLY_LOGV(chip_name, "raw_chip_id: %llx\n", id_buf);
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id_buf = (id_buf & 0xff) | ((id_buf & 0xff0000) >> 8) | ((id_buf & 0xff00000000) >> 16);
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} else {
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ESP_EARLY_LOGV(chip_name, "raw_chip_id: %X\n", id_buf);
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}
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uint32_t raw_flash_id = __builtin_bswap32(id_buf);
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if (raw_flash_id == 0xFFFFFF || raw_flash_id == 0) {
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ESP_EARLY_LOGE(chip_name, "no response\n");
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return ESP_ERR_FLASH_NO_RESPONSE;
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}
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*out_chip_id = (raw_flash_id >> 8);
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ESP_EARLY_LOGV(chip_name, "chip_id: %X\n", *out_chip_id);
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return ESP_OK;
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}
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esp_err_t spi_flash_chip_mxic_opi_read_reg(esp_flash_t *chip, spi_flash_register_t reg_id, uint32_t* out_reg)
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{
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uint32_t stat_buf = 0;
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uint32_t length_zoom;
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spi_flash_chip_mxic_opi_get_data_length_zoom(chip->read_mode, &length_zoom);
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spi_flash_trans_t t = {
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.command = CMD_OPI_FLASH_MXIC(CMD_RDSR),
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.miso_data = ((uint8_t*) &stat_buf),
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.miso_len = 1 * length_zoom,
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.address_bitlen = 32,
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.dummy_bitlen = 4 * length_zoom,
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};
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esp_err_t err = chip->host->driver->common_command(chip->host, &t);
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if (err != ESP_OK) {
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return err;
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}
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// For DTR mode, RDSR result like [SR1, SR1], just keeping one SR1.
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*out_reg = (stat_buf & 0xff);
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return ESP_OK;
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}
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esp_err_t spi_flash_chip_mxic_opi_get_write_protect(esp_flash_t *chip, bool *out_write_protected)
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{
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esp_err_t err = ESP_OK;
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uint32_t status;
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assert(out_write_protected!=NULL);
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err = chip->chip_drv->read_reg(chip, SPI_FLASH_REG_STATUS, &status);
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if (err != ESP_OK) {
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return err;
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}
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*out_write_protected = ((status & SR_WREN) == 0);
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return err;
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}
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esp_err_t spi_flash_chip_mxic_opi_erase_chip(esp_flash_t *chip)
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{
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esp_err_t err;
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err = chip->chip_drv->set_chip_write_protect(chip, false);
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if (err == ESP_OK) {
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err = chip->chip_drv->wait_idle(chip, chip->chip_drv->timeout->idle_timeout);
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}
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if (err == ESP_OK || err == ESP_ERR_NOT_SUPPORTED) {
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// Do erase chip here.
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spi_flash_trans_t t = {
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.command = CMD_OPI_FLASH_MXIC_CHIP_ERASE,
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};
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err = chip->host->driver->common_command(chip->host, &t);
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chip->busy = 1;
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#ifdef CONFIG_SPI_FLASH_CHECK_ERASE_TIMEOUT_DISABLED
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err = chip->chip_drv->wait_idle(chip, ESP_FLASH_CHIP_GENERIC_NO_TIMEOUT);
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#else
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err = chip->chip_drv->wait_idle(chip, chip->chip_drv->timeout->chip_erase_timeout);
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#endif
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}
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// Ensure WEL is 0, even if the erase failed.
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if (err == ESP_ERR_NOT_SUPPORTED) {
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chip->chip_drv->set_chip_write_protect(chip, true);
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}
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return err;
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}
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esp_err_t spi_flash_chip_mxic_opi_erase_sector(esp_flash_t *chip, uint32_t start_address)
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{
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esp_err_t err = chip->chip_drv->set_chip_write_protect(chip, false);
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if (err == ESP_OK) {
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err = chip->chip_drv->wait_idle(chip, chip->chip_drv->timeout->idle_timeout);
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}
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//The chip didn't accept the previous write command. Ignore this in preparationstage.
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if (err == ESP_OK || err == ESP_ERR_NOT_SUPPORTED) {
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spi_flash_trans_t t = {
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.command = CMD_OPI_FLASH_MXIC(CMD_SECTOR_ERASE_4B),
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.address_bitlen = 32,
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.address = start_address,
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};
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err = chip->host->driver->common_command(chip->host, &t);
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chip->busy = 1;
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#ifdef CONFIG_SPI_FLASH_CHECK_ERASE_TIMEOUT_DISABLED
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err = chip->chip_drv->wait_idle(chip, ESP_FLASH_CHIP_GENERIC_NO_TIMEOUT);
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#else
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err = chip->chip_drv->wait_idle(chip, chip->chip_drv->timeout->sector_erase_timeout);
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#endif
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}
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// Ensure WEL is 0, even if the erase failed.
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if (err == ESP_ERR_NOT_SUPPORTED) {
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err = chip->chip_drv->set_chip_write_protect(chip, true);
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}
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return err;
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}
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esp_err_t spi_flash_chip_mxic_opi_erase_block(esp_flash_t *chip, uint32_t start_address)
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{
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esp_err_t err = chip->chip_drv->set_chip_write_protect(chip, false);
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if (err == ESP_OK) {
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err = chip->chip_drv->wait_idle(chip, chip->chip_drv->timeout->idle_timeout);
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}
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//The chip didn't accept the previous write command. Ignore this in preparationstage.
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if (err == ESP_OK || err == ESP_ERR_NOT_SUPPORTED) {
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spi_flash_trans_t t = {
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.command = CMD_OPI_FLASH_MXIC(CMD_LARGE_BLOCK_ERASE_4B),
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.address_bitlen = 32,
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.address = start_address,
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};
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err = chip->host->driver->common_command(chip->host, &t);
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chip->busy = 1;
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#ifdef CONFIG_SPI_FLASH_CHECK_ERASE_TIMEOUT_DISABLED
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err = chip->chip_drv->wait_idle(chip, ESP_FLASH_CHIP_GENERIC_NO_TIMEOUT);
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#else
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err = chip->chip_drv->wait_idle(chip, chip->chip_drv->timeout->block_erase_timeout);
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#endif
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}
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// Ensure WEL is 0, even if the erase failed.
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if (err == ESP_ERR_NOT_SUPPORTED) {
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err = chip->chip_drv->set_chip_write_protect(chip, true);
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}
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return err;
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}
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esp_err_t spi_flash_chip_mxic_opi_page_program(esp_flash_t *chip, const void *buffer, uint32_t address, uint32_t length)
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{
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esp_err_t err;
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err = chip->chip_drv->wait_idle(chip, chip->chip_drv->timeout->idle_timeout);
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//The chip didn't accept the previous write command. Ignore this in preparationstage.
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if (err == ESP_OK || err == ESP_ERR_NOT_SUPPORTED) {
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// Perform the actual Page Program command
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spi_flash_trans_t t = {
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.command = CMD_OPI_FLASH_MXIC(CMD_PROGRAM_PAGE_4B),
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.address_bitlen = 32,
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.address = address,
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.mosi_len = length,
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.mosi_data = buffer,
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};
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chip->host->driver->common_command(chip->host, &t);
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chip->busy = 1;
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err = chip->chip_drv->wait_idle(chip, chip->chip_drv->timeout->page_program_timeout);
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}
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// Ensure WEL is 0, even if the page program failed.
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if (err == ESP_ERR_NOT_SUPPORTED) {
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err = chip->chip_drv->set_chip_write_protect(chip, true);
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}
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return err;
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}
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esp_err_t spi_flash_chip_mxic_opi_write(esp_flash_t *chip, const void *buffer, uint32_t address, uint32_t length)
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{
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esp_err_t err = ESP_OK;
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const uint32_t page_size = chip->chip_drv->page_size;
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uint32_t align_address;
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uint8_t temp_buffer[64]; //spiflash hal max length of write no longer than 64byte
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while (err == ESP_OK && length > 0) {
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memset(temp_buffer, 0xFF, sizeof(temp_buffer));
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uint32_t page_len = chip->host->driver->write_data_slicer(chip->host, address, length, &align_address, page_size);
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uint32_t left_off = address - align_address;
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uint32_t write_len = MIN(align_address + page_len, address + length) - address;
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memcpy(temp_buffer + left_off, buffer, write_len);
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err = chip->chip_drv->set_chip_write_protect(chip, false);
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if (err == ESP_OK && length > 0) {
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err = chip->chip_drv->program_page(chip, temp_buffer, align_address, page_len);
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address += write_len;
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buffer = (void *)((intptr_t)buffer + write_len);
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length -= write_len;
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}
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}
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// The caller is responsible to do host->driver->flush_cache, because this function may be
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// called in small pieces. Frequency call of flush cache will do harm to the performance.
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return err;
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}
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esp_err_t spi_flash_chip_mxic_opi_get_io_mode(esp_flash_t *chip, esp_flash_io_mode_t* out_io_mode)
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{
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uint32_t stat_buf = 0;
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uint32_t length_zoom;
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spi_flash_chip_mxic_opi_get_data_length_zoom(chip->read_mode, &length_zoom);
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spi_flash_trans_t t = {
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.command = CMD_OPI_FLASH_MXIC_RDCR2,
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.dummy_bitlen = 4 * length_zoom,
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.miso_data = ((uint8_t*) &stat_buf),
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.miso_len = 1 * length_zoom,
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.address_bitlen = 32,
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};
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esp_err_t err = chip->host->driver->common_command(chip->host, &t);
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if (err != ESP_OK) {
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return err;
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}
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// For DTR mode, RDSR result like [CR1, CR1], just keeping one CR1.
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switch (stat_buf & 0xff)
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{
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case 0x1:
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*out_io_mode = SPI_FLASH_OPI_STR;
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break;
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case 0x2:
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*out_io_mode = SPI_FLASH_OPI_DTR;
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break;
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default:
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// wrong mode.
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*out_io_mode = 0;
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break;
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}
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if (*out_io_mode != chip->read_mode) {
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// Current chip mode is not the mode we configured.
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*out_io_mode = 0;
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}
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return ESP_OK;
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}
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esp_err_t spi_flash_chip_xmic_opi_set_io_mode(esp_flash_t *chip)
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{
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// TODO: configure opi flash chip set io mode, only useful for external flash currently.
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// For main flash, we already set io mode when chip starts up. But for external flash,
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// We need to set mode when flash initialized, so keeping this for future usage.
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return ESP_OK;
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}
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// This function should only be called after opi mode initialization. So, only configure for OPI-STR/OPI-DTR mode
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// not support other mode in this file, return `ESP_ERR_FLASH_NOT_INITIALISED` directely.
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esp_err_t spi_flash_chip_xmic_opi_config_host_io_mode(esp_flash_t *chip, uint32_t flags)
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{
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uint32_t dummy_cyclelen_base;
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uint32_t addr_bitlen;
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uint32_t read_command;
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esp_flash_io_mode_t read_mode = chip->read_mode;
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switch (read_mode & 0xFFFF) {
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case SPI_FLASH_OPI_STR:
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addr_bitlen = SPI_FLASH_OPISTR_ADDR_BITLEN;
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dummy_cyclelen_base = SPI_FLASH_OPISTR_DUMMY_BITLEN;
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read_command = CMD_OPI_FLASH_MXIC_READ_STR;
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break;
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case SPI_FLASH_OPI_DTR:
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addr_bitlen = SPI_FLASH_OPIDTR_ADDR_BITLEN;
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dummy_cyclelen_base = SPI_FLASH_OPIDTR_DUMMY_BITLEN;
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read_command = CMD_OPI_FLASH_MXIC_READ_DTR;
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break;
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default:
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return ESP_ERR_FLASH_NOT_INITIALISED;
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}
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return chip->host->driver->configure_host_io_mode(chip->host, read_command, addr_bitlen, dummy_cyclelen_base, read_mode);
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}
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// Most of mxic opi implementations are totally different from that is generic.
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// Replace them to opi implementation.
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const spi_flash_chip_t esp_flash_chip_mxic_opi = {
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.name = chip_name,
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.timeout = &spi_flash_chip_generic_timeout,
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.probe = spi_flash_chip_mxic_opi_probe,
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.reset = spi_flash_chip_generic_reset,
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.detect_size = spi_flash_chip_mxic_opi_detect_size,
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.erase_chip = spi_flash_chip_mxic_opi_erase_chip,
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.erase_sector = spi_flash_chip_mxic_opi_erase_sector,
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.erase_block = spi_flash_chip_mxic_opi_erase_block,
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.sector_size = 4 * 1024,
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.block_erase_size = 64 * 1024,
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.get_chip_write_protect = spi_flash_chip_mxic_opi_get_write_protect,
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.set_chip_write_protect = spi_flash_chip_mxic_opi_set_write_protect,
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.num_protectable_regions = 0,
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.protectable_regions = NULL,
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.get_protected_regions = NULL,
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.set_protected_regions = NULL,
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.read = spi_flash_chip_generic_read,
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.write = spi_flash_chip_mxic_opi_write,
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.program_page = spi_flash_chip_mxic_opi_page_program,
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.page_size = 256,
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.write_encrypted = spi_flash_chip_generic_write_encrypted,
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.wait_idle = spi_flash_chip_generic_wait_idle,
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.set_io_mode = spi_flash_chip_xmic_opi_set_io_mode,
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.get_io_mode = spi_flash_chip_mxic_opi_get_io_mode,
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.read_id = spi_flash_chip_mxic_opi_read_id,
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.read_reg = spi_flash_chip_mxic_opi_read_reg,
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.yield = spi_flash_chip_generic_yield,
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.sus_setup = spi_flash_chip_generic_suspend_cmd_conf,
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.read_unique_id = spi_flash_chip_generic_read_unique_id_none,
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.get_chip_caps = spi_flash_chip_mxic_opi_get_caps,
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.config_host_io_mode = spi_flash_chip_xmic_opi_config_host_io_mode,
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};
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