kopia lustrzana https://github.com/espressif/esp-idf
76 wiersze
3.3 KiB
C
76 wiersze
3.3 KiB
C
/*
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* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "hal/log.h"
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#include "hal/mipi_csi_hal.h"
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#include "hal/mipi_csi_ll.h"
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#include "soc/mipi_csi_periph.h"
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#define MHZ (1000 * 1000)
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void s_mipi_csi_hal_phy_write_register(mipi_csi_hal_context_t *hal, uint8_t reg_addr, uint8_t reg_val)
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{
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mipi_csi_phy_ll_write_clock(hal->host_dev, 0, false);
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mipi_csi_phy_ll_write_reg_addr(hal->host_dev, reg_addr);
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mipi_csi_phy_ll_write_clock(hal->host_dev, 1, false);
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mipi_csi_phy_ll_write_clock(hal->host_dev, 0, false);
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mipi_csi_phy_ll_write_reg_val(hal->host_dev, reg_val);
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mipi_csi_phy_ll_write_clock(hal->host_dev, 1, false);
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mipi_csi_phy_ll_write_clock(hal->host_dev, 0, false);
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}
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void mipi_csi_hal_init(mipi_csi_hal_context_t *hal, const mipi_csi_hal_config_t *config)
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{
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hal->bridge_dev = MIPI_CSI_BRG_LL_GET_HW(0);
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hal->host_dev = MIPI_CSI_HOST_LL_GET_HW(0);
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int csi_lane_rate = config->lane_bit_rate_mbps * MHZ;
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// reset PHY
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mipi_csi_phy_ll_enable_shutdown_input(hal->host_dev, true);
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mipi_csi_phy_ll_enable_reset_output(hal->host_dev, true);
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mipi_csi_host_ll_enable_reset_output(hal->host_dev, true);
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//reset reg addr to default value
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mipi_csi_phy_ll_write_reg_addr(hal->host_dev, 0x0);
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//reset reg val to default value
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mipi_csi_phy_ll_write_clock(hal->host_dev, 0, 1);
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mipi_csi_phy_ll_write_clock(hal->host_dev, 0, 0);
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uint8_t hs_freq_sel = 0;
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for (size_t i = 0; i < num_of_soc_mipi_csi_phy_pll_ranges; i++) {
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if ((csi_lane_rate / 1000000) >= soc_mipi_csi_phy_pll_ranges[i].start_mbps &&
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(csi_lane_rate / 1000000) <= soc_mipi_csi_phy_pll_ranges[i].end_mbps) {
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hs_freq_sel = soc_mipi_csi_phy_pll_ranges[i].hs_freq_range_sel;
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break;
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}
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}
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s_mipi_csi_hal_phy_write_register(hal, 0x44, hs_freq_sel << 1);
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HAL_LOGD("csi_hal", "CSI-DPHY lane_rate: %d Hz, hs_freq: 0x%x, lane_num: 0x%x", csi_lane_rate, hs_freq_sel, config->lanes_num);
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mipi_csi_phy_ll_enable_shutdown_input(hal->host_dev, false);
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mipi_csi_phy_ll_enable_reset_output(hal->host_dev, false);
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mipi_csi_host_ll_enable_reset_output(hal->host_dev, false);
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// Configure the host controller.
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// Configure the number of active lanes.
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mipi_csi_host_ll_set_active_lanes_num(hal->host_dev, config->lanes_num);
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/**
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* We ignore the virtual channel and virtual channel extension info, there is only one virtual channel.
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* VC is by default there, VCX needs enable or disable.
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* So we disable VCX here.
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*/
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mipi_csi_host_ll_enable_virtual_channel_extension(hal->host_dev, false);
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// Set Scrambler.
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mipi_csi_host_ll_enable_scrambling(hal->host_dev, false);
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//CSI bridge
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//TODO: IDF-9126, make csi bridge updates into `mipi_csi_share_hw_ctrl.c` and share with ISP
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mipi_csi_brg_ll_set_intput_data_h_pixel_num(hal->bridge_dev, config->frame_height);
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mipi_csi_brg_ll_set_intput_data_v_row_num(hal->bridge_dev, config->frame_width);
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mipi_csi_brg_ll_set_flow_ctl_buf_afull_thrd(hal->bridge_dev, 960);
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mipi_csi_brg_ll_set_data_type_min(hal->bridge_dev, 0x12);
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mipi_csi_brg_ll_set_data_type_max(hal->bridge_dev, 0x2f);
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mipi_csi_brg_ll_set_byte_endian(hal->bridge_dev, config->byte_swap_en);
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}
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