kopia lustrzana https://github.com/espressif/esp-idf
256 wiersze
10 KiB
C
256 wiersze
10 KiB
C
/*
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* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdbool.h>
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#include <stdint.h>
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#include "sdkconfig.h"
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#include "soc/soc_caps.h"
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#include "soc/clk_tree_defs.h"
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#include "esp_attr.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief ADC unit
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*/
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typedef enum {
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ADC_UNIT_1, ///< SAR ADC 1
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ADC_UNIT_2, ///< SAR ADC 2
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} adc_unit_t;
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/**
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* @brief ADC channels
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*/
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typedef enum {
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ADC_CHANNEL_0, ///< ADC channel
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ADC_CHANNEL_1, ///< ADC channel
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ADC_CHANNEL_2, ///< ADC channel
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ADC_CHANNEL_3, ///< ADC channel
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ADC_CHANNEL_4, ///< ADC channel
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ADC_CHANNEL_5, ///< ADC channel
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ADC_CHANNEL_6, ///< ADC channel
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ADC_CHANNEL_7, ///< ADC channel
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ADC_CHANNEL_8, ///< ADC channel
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ADC_CHANNEL_9, ///< ADC channel
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} adc_channel_t;
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/**
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* @brief ADC attenuation parameter. Different parameters determine the range of the ADC.
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*/
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typedef enum {
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ADC_ATTEN_DB_0 = 0, ///<No input attenuation, ADC can measure up to approx.
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ADC_ATTEN_DB_2_5 = 1, ///<The input voltage of ADC will be attenuated extending the range of measurement by about 2.5 dB
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ADC_ATTEN_DB_6 = 2, ///<The input voltage of ADC will be attenuated extending the range of measurement by about 6 dB
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ADC_ATTEN_DB_12 = 3, ///<The input voltage of ADC will be attenuated extending the range of measurement by about 12 dB
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ADC_ATTEN_DB_11 __attribute__((deprecated)) = ADC_ATTEN_DB_12, ///<This is deprecated, it behaves the same as `ADC_ATTEN_DB_12`
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} adc_atten_t;
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typedef enum {
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ADC_BITWIDTH_DEFAULT = 0, ///< Default ADC output bits, max supported width will be selected
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ADC_BITWIDTH_9 = 9, ///< ADC output width is 9Bit
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ADC_BITWIDTH_10 = 10, ///< ADC output width is 10Bit
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ADC_BITWIDTH_11 = 11, ///< ADC output width is 11Bit
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ADC_BITWIDTH_12 = 12, ///< ADC output width is 12Bit
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ADC_BITWIDTH_13 = 13, ///< ADC output width is 13Bit
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} adc_bitwidth_t;
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typedef enum {
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ADC_ULP_MODE_DISABLE = 0, ///< ADC ULP mode is disabled
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ADC_ULP_MODE_FSM = 1, ///< ADC is controlled by ULP FSM
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ADC_ULP_MODE_RISCV = 2, ///< ADC is controlled by ULP RISCV
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} adc_ulp_mode_t;
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/**
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* @brief ADC digital controller (DMA mode) work mode.
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*/
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typedef enum {
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ADC_CONV_SINGLE_UNIT_1 = 1, ///< Only use ADC1 for conversion
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ADC_CONV_SINGLE_UNIT_2 = 2, ///< Only use ADC2 for conversion
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ADC_CONV_BOTH_UNIT = 3, ///< Use Both ADC1 and ADC2 for conversion simultaneously
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ADC_CONV_ALTER_UNIT = 7, ///< Use both ADC1 and ADC2 for conversion by turn. e.g. ADC1 -> ADC2 -> ADC1 -> ADC2 .....
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} adc_digi_convert_mode_t;
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/**
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* @brief ADC digital controller (DMA mode) output data format option.
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*/
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typedef enum {
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ADC_DIGI_OUTPUT_FORMAT_TYPE1, ///< See `adc_digi_output_data_t.type1`
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ADC_DIGI_OUTPUT_FORMAT_TYPE2, ///< See `adc_digi_output_data_t.type2`
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} adc_digi_output_format_t;
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#if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
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typedef soc_periph_adc_digi_clk_src_t adc_oneshot_clk_src_t; ///< Clock source type of oneshot mode which uses digital controller
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typedef soc_periph_adc_digi_clk_src_t adc_continuous_clk_src_t; ///< Clock source type of continuous mode which uses digital controller
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#elif SOC_ADC_RTC_CTRL_SUPPORTED
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typedef soc_periph_adc_rtc_clk_src_t adc_oneshot_clk_src_t; ///< Clock source type of oneshot mode which uses RTC controller
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typedef soc_periph_adc_digi_clk_src_t adc_continuous_clk_src_t; ///< Clock source type of continuous mode which uses digital controller
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#else
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typedef int adc_oneshot_clk_src_t; ///< Default type
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typedef int adc_continuous_clk_src_t; ///< Default type
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#endif
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/**
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* @brief ADC digital controller pattern configuration
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*/
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typedef struct {
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uint8_t atten; ///< Attenuation of this ADC channel
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uint8_t channel; ///< ADC channel
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uint8_t unit; ///< ADC unit
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uint8_t bit_width; ///< ADC output bit width
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} adc_digi_pattern_config_t;
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/**
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* @brief ADC IIR Filter ID
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*/
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typedef enum {
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ADC_DIGI_IIR_FILTER_0, ///< Filter 0
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ADC_DIGI_IIR_FILTER_1, ///< Filter 1
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} adc_digi_iir_filter_t;
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/**
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* @brief IIR Filter Coefficient
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*/
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typedef enum {
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ADC_DIGI_IIR_FILTER_COEFF_2, ///< The filter coefficient is 2
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ADC_DIGI_IIR_FILTER_COEFF_4, ///< The filter coefficient is 4
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ADC_DIGI_IIR_FILTER_COEFF_8, ///< The filter coefficient is 8
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ADC_DIGI_IIR_FILTER_COEFF_16, ///< The filter coefficient is 16
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ADC_DIGI_IIR_FILTER_COEFF_64, ///< The filter coefficient is 64
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} adc_digi_iir_filter_coeff_t;
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/*---------------------------------------------------------------
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ADC Monitor
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---------------------------------------------------------------*/
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/**
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* @brief ADC monitor (continuous mode) ID
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*/
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typedef enum {
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ADC_MONITOR_0, ///< The monitor index 0.
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ADC_MONITOR_1, ///< The monitor index 1.
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} adc_monitor_id_t;
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/**
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* @brief Monitor config/event mode type
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*/
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typedef enum {
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ADC_MONITOR_MODE_HIGH = 0, ///< ADC raw_result > threshold value, monitor interrupt will be generated.
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ADC_MONITOR_MODE_LOW, ///< ADC raw_result < threshold value, monitor interrupt will be generated.
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} adc_monitor_mode_t;
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/*---------------------------------------------------------------
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Output Format
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---------------------------------------------------------------*/
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#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2
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/**
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* @brief ADC digital controller (DMA mode) output data format.
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* Used to analyze the acquired ADC (DMA) data.
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* @note ESP32: Only `type1` is valid. ADC2 does not support DMA mode.
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* @note ESP32-S2: Member `channel` can be used to judge the validity of the ADC data,
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* because the role of the arbiter may get invalid ADC data.
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*/
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typedef struct {
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union {
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struct {
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uint16_t data: 12; /*!<ADC real output data info. Resolution: 12 bit. */
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uint16_t channel: 4; /*!<ADC channel index info. */
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} type1; /*!<ADC type1 */
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struct {
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uint16_t data: 11; /*!<ADC real output data info. Resolution: 11 bit. */
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uint16_t channel: 4; /*!<ADC channel index info. For ESP32-S2:
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If (channel < ADC_CHANNEL_MAX), The data is valid.
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If (channel > ADC_CHANNEL_MAX), The data is invalid. */
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uint16_t unit: 1; /*!<ADC unit index info. 0: ADC1; 1: ADC2. */
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} type2; /*!<When the configured output format is 11bit.*/
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uint16_t val; /*!<Raw data value */
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};
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} adc_digi_output_data_t;
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#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2
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/**
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* @brief ADC digital controller (DMA mode) output data format.
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* Used to analyze the acquired ADC (DMA) data.
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*/
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typedef struct {
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union {
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struct {
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uint32_t data: 12; /*!<ADC real output data info. Resolution: 12 bit. */
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uint32_t reserved12: 1; /*!<Reserved12. */
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uint32_t channel: 3; /*!<ADC channel index info.
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If (channel < ADC_CHANNEL_MAX), The data is valid.
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If (channel > ADC_CHANNEL_MAX), The data is invalid. */
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uint32_t unit: 1; /*!<ADC unit index info. 0: ADC1; 1: ADC2. */
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uint32_t reserved17_31: 15; /*!<Reserved17. */
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} type2; /*!<When the configured output format is 12bit. */
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uint32_t val; /*!<Raw data value */
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};
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} adc_digi_output_data_t;
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#elif CONFIG_IDF_TARGET_ESP32S3
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/**
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* @brief ADC digital controller (DMA mode) output data format.
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* Used to analyze the acquired ADC (DMA) data.
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*/
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typedef struct {
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union {
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struct {
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uint32_t data: 12; /*!<ADC real output data info. Resolution: 12 bit. */
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uint32_t reserved12: 1; /*!<Reserved12. */
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uint32_t channel: 4; /*!<ADC channel index info.
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If (channel < ADC_CHANNEL_MAX), The data is valid.
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If (channel > ADC_CHANNEL_MAX), The data is invalid. */
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uint32_t unit: 1; /*!<ADC unit index info. 0: ADC1; 1: ADC2. */
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uint32_t reserved17_31: 14; /*!<Reserved17. */
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} type2; /*!<When the configured output format is 12bit. */
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uint32_t val; /*!<Raw data value */
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};
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} adc_digi_output_data_t;
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#elif CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2
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/**
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* @brief ADC digital controller (DMA mode) output data format.
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* Used to analyze the acquired ADC (DMA) data.
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*/
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typedef struct {
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union {
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struct {
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uint32_t data: 12; /*!<ADC real output data info. Resolution: 12 bit. */
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uint32_t reserved12: 1; /*!<Reserved12. */
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uint32_t channel: 4; /*!<ADC channel index info.
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If (channel < ADC_CHANNEL_MAX), The data is valid.
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If (channel > ADC_CHANNEL_MAX), The data is invalid. */
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uint32_t reserved17_31: 15; /*!<Reserved 17-31. */
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} type2; /*!<When the configured output format is 12bit. */
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uint32_t val; /*!<Raw data value */
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};
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} adc_digi_output_data_t;
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#endif
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#if CONFIG_IDF_TARGET_ESP32S2
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/**
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* @brief ADC digital controller (DMA mode) clock system setting.
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* Calculation formula: controller_clk = (`APLL` or `APB`) / (div_num + div_a / div_b + 1).
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*
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* @note: The clocks of the DAC digital controller use the ADC digital controller clock divider.
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*/
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typedef struct {
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bool use_apll; /*!<true: use APLL clock; false: use APB clock. */
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uint32_t div_num; /*!<Division factor. Range: 0 ~ 255.
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Note: When a higher frequency clock is used (the division factor is less than 9),
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the ADC reading value will be slightly offset. */
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uint32_t div_b; /*!<Division factor. Range: 1 ~ 63. */
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uint32_t div_a; /*!<Division factor. Range: 0 ~ 63. */
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} adc_digi_clk_t;
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#endif
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#ifdef __cplusplus
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}
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#endif
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