kopia lustrzana https://github.com/espressif/esp-idf
248 wiersze
10 KiB
C
248 wiersze
10 KiB
C
/*
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "soc/soc_caps.h"
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#include "hal/assert.h"
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#include "hal/gdma_hal_ahb.h"
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#include "hal/ahb_dma_ll.h"
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static gdma_hal_priv_data_t gdma_ahb_hal_priv_data = {
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.m2m_free_periph_mask = AHB_DMA_LL_M2M_FREE_PERIPH_ID_MASK,
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};
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void gdma_ahb_hal_start_with_desc(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, intptr_t desc_base_addr)
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{
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if (dir == GDMA_CHANNEL_DIRECTION_RX) {
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ahb_dma_ll_rx_set_desc_addr(hal->ahb_dma_dev, chan_id, desc_base_addr);
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ahb_dma_ll_rx_start(hal->ahb_dma_dev, chan_id);
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} else {
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ahb_dma_ll_tx_set_desc_addr(hal->ahb_dma_dev, chan_id, desc_base_addr);
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ahb_dma_ll_tx_start(hal->ahb_dma_dev, chan_id);
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}
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}
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void gdma_ahb_hal_stop(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
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{
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if (dir == GDMA_CHANNEL_DIRECTION_RX) {
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ahb_dma_ll_rx_stop(hal->ahb_dma_dev, chan_id);
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} else {
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ahb_dma_ll_tx_stop(hal->ahb_dma_dev, chan_id);
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}
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}
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void gdma_ahb_hal_append(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
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{
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if (dir == GDMA_CHANNEL_DIRECTION_RX) {
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ahb_dma_ll_rx_restart(hal->ahb_dma_dev, chan_id);
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} else {
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ahb_dma_ll_tx_restart(hal->ahb_dma_dev, chan_id);
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}
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}
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void gdma_ahb_hal_reset(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
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{
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if (dir == GDMA_CHANNEL_DIRECTION_RX) {
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ahb_dma_ll_rx_reset_channel(hal->ahb_dma_dev, chan_id);
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} else {
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ahb_dma_ll_tx_reset_channel(hal->ahb_dma_dev, chan_id);
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}
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}
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void gdma_ahb_hal_set_priority(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t priority)
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{
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if (dir == GDMA_CHANNEL_DIRECTION_RX) {
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ahb_dma_ll_rx_set_priority(hal->ahb_dma_dev, chan_id, priority);
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} else {
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ahb_dma_ll_tx_set_priority(hal->ahb_dma_dev, chan_id, priority);
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}
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}
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void gdma_ahb_hal_connect_peri(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, gdma_trigger_peripheral_t periph, int periph_sub_id)
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{
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if (dir == GDMA_CHANNEL_DIRECTION_RX) {
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ahb_dma_ll_rx_reset_channel(hal->ahb_dma_dev, chan_id); // reset channel
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ahb_dma_ll_rx_connect_to_periph(hal->ahb_dma_dev, chan_id, periph, periph_sub_id);
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} else {
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ahb_dma_ll_tx_reset_channel(hal->ahb_dma_dev, chan_id); // reset channel
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ahb_dma_ll_tx_connect_to_periph(hal->ahb_dma_dev, chan_id, periph, periph_sub_id);
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}
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}
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void gdma_ahb_hal_disconnect_peri(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
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{
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if (dir == GDMA_CHANNEL_DIRECTION_RX) {
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ahb_dma_ll_rx_disconnect_from_periph(hal->ahb_dma_dev, chan_id);
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} else {
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ahb_dma_ll_tx_disconnect_from_periph(hal->ahb_dma_dev, chan_id);
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}
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}
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void gdma_ahb_hal_enable_burst(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool en_data_burst, bool en_desc_burst)
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{
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if (dir == GDMA_CHANNEL_DIRECTION_RX) {
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ahb_dma_ll_rx_enable_data_burst(hal->ahb_dma_dev, chan_id, en_data_burst);
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ahb_dma_ll_rx_enable_descriptor_burst(hal->ahb_dma_dev, chan_id, en_desc_burst);
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} else {
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ahb_dma_ll_tx_enable_data_burst(hal->ahb_dma_dev, chan_id, en_data_burst);
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ahb_dma_ll_tx_enable_descriptor_burst(hal->ahb_dma_dev, chan_id, en_desc_burst);
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}
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}
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void gdma_ahb_hal_set_strategy(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool en_owner_check, bool en_desc_write_back)
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{
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if (dir == GDMA_CHANNEL_DIRECTION_RX) {
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ahb_dma_ll_rx_enable_owner_check(hal->ahb_dma_dev, chan_id, en_owner_check);
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// RX direction always has the descriptor write-back feature enabled
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} else {
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ahb_dma_ll_tx_enable_owner_check(hal->ahb_dma_dev, chan_id, en_owner_check);
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ahb_dma_ll_tx_enable_auto_write_back(hal->ahb_dma_dev, chan_id, en_desc_write_back);
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}
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}
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void gdma_ahb_hal_enable_intr(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t intr_event_mask, bool en_or_dis)
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{
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if (dir == GDMA_CHANNEL_DIRECTION_RX) {
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ahb_dma_ll_rx_enable_interrupt(hal->ahb_dma_dev, chan_id, intr_event_mask, en_or_dis);
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} else {
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ahb_dma_ll_tx_enable_interrupt(hal->ahb_dma_dev, chan_id, intr_event_mask, en_or_dis);
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}
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}
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void gdma_ahb_hal_clear_intr(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, uint32_t intr_event_mask)
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{
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if (dir == GDMA_CHANNEL_DIRECTION_RX) {
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ahb_dma_ll_rx_clear_interrupt_status(hal->ahb_dma_dev, chan_id, intr_event_mask);
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} else {
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ahb_dma_ll_tx_clear_interrupt_status(hal->ahb_dma_dev, chan_id, intr_event_mask);
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}
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}
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uint32_t gdma_ahb_hal_read_intr_status(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool raw)
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{
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if (dir == GDMA_CHANNEL_DIRECTION_RX) {
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return ahb_dma_ll_rx_get_interrupt_status(hal->ahb_dma_dev, chan_id, raw);
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} else {
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return ahb_dma_ll_tx_get_interrupt_status(hal->ahb_dma_dev, chan_id, raw);
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}
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}
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uint32_t gdma_ahb_hal_get_intr_status_reg(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
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{
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if (dir == GDMA_CHANNEL_DIRECTION_RX) {
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return (uint32_t)ahb_dma_ll_rx_get_interrupt_status_reg(hal->ahb_dma_dev, chan_id);
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} else {
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return (uint32_t)ahb_dma_ll_tx_get_interrupt_status_reg(hal->ahb_dma_dev, chan_id);
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}
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}
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uint32_t gdma_ahb_hal_get_eof_desc_addr(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool is_success)
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{
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if (dir == GDMA_CHANNEL_DIRECTION_RX) {
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if (is_success) {
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return ahb_dma_ll_rx_get_success_eof_desc_addr(hal->ahb_dma_dev, chan_id);
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}
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return ahb_dma_ll_rx_get_error_eof_desc_addr(hal->ahb_dma_dev, chan_id);
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} else {
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// The TX direction only has success EOF, parameter 'is_success' is ignored
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return ahb_dma_ll_tx_get_eof_desc_addr(hal->ahb_dma_dev, chan_id);
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}
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}
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#if SOC_GDMA_SUPPORT_CRC
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void gdma_ahb_hal_clear_crc(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
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{
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if (dir == GDMA_CHANNEL_DIRECTION_RX) {
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ahb_dma_ll_rx_crc_clear(hal->ahb_dma_dev, chan_id);
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} else {
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ahb_dma_ll_tx_crc_clear(hal->ahb_dma_dev, chan_id);
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}
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}
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void gdma_ahb_hal_set_crc_poly(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, const gdma_hal_crc_config_t *config)
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{
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uint32_t init_value = config->init_value;
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uint32_t crc_bit_width = config->crc_bit_width;
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uint32_t poly_hex = config->poly_hex;
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// bit matrix for parallel CRC
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uint32_t lfsr_matrix[crc_bit_width];
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uint32_t data_matrix[GDMA_LL_PARALLEL_CRC_DATA_WIDTH];
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uint32_t lfsr_mask = 0;
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uint32_t data_mask = 0;
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// build the parallel CRC matrix first, later we will extract the control mask from it
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gdma_hal_build_parallel_crc_matrix(crc_bit_width, poly_hex, GDMA_LL_PARALLEL_CRC_DATA_WIDTH,
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lfsr_matrix, data_matrix);
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if (dir == GDMA_CHANNEL_DIRECTION_RX) {
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ahb_dma_ll_rx_crc_set_init_value(hal->ahb_dma_dev, chan_id, init_value);
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ahb_dma_ll_rx_crc_set_width(hal->ahb_dma_dev, chan_id, crc_bit_width);
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for (uint32_t i = 0; i < crc_bit_width; i++) {
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// extract the control mask from the matrix, for each CRC bit
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data_mask = gdma_hal_get_data_mask_from_matrix(data_matrix, GDMA_LL_PARALLEL_CRC_DATA_WIDTH, i);
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lfsr_mask = gdma_hal_get_lfsr_mask_from_matrix(lfsr_matrix, crc_bit_width, i);
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ahb_dma_ll_rx_crc_set_lfsr_data_mask(hal->ahb_dma_dev, chan_id, i, lfsr_mask, data_mask, config->reverse_data_mask);
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ahb_dma_ll_rx_crc_latch_config(hal->ahb_dma_dev, chan_id);
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}
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} else {
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ahb_dma_ll_tx_crc_set_init_value(hal->ahb_dma_dev, chan_id, init_value);
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ahb_dma_ll_tx_crc_set_width(hal->ahb_dma_dev, chan_id, crc_bit_width);
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for (uint32_t i = 0; i < crc_bit_width; i++) {
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// extract the control mask from the matrix, for each CRC bit
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data_mask = gdma_hal_get_data_mask_from_matrix(data_matrix, GDMA_LL_PARALLEL_CRC_DATA_WIDTH, i);
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lfsr_mask = gdma_hal_get_lfsr_mask_from_matrix(lfsr_matrix, crc_bit_width, i);
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ahb_dma_ll_tx_crc_set_lfsr_data_mask(hal->ahb_dma_dev, chan_id, i, lfsr_mask, data_mask, config->reverse_data_mask);
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ahb_dma_ll_tx_crc_latch_config(hal->ahb_dma_dev, chan_id);
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}
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}
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}
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uint32_t gdma_ahb_hal_get_crc_result(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir)
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{
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if (dir == GDMA_CHANNEL_DIRECTION_RX) {
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return ahb_dma_ll_rx_crc_get_result(hal->ahb_dma_dev, chan_id);
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} else {
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return ahb_dma_ll_tx_crc_get_result(hal->ahb_dma_dev, chan_id);
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}
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}
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#endif // SOC_GDMA_SUPPORT_CRC
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#if SOC_GDMA_SUPPORT_ETM
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void gdma_ahb_hal_enable_etm_task(gdma_hal_context_t *hal, int chan_id, gdma_channel_direction_t dir, bool en_or_dis)
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{
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if (dir == GDMA_CHANNEL_DIRECTION_RX) {
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ahb_dma_ll_rx_enable_etm_task(hal->ahb_dma_dev, chan_id, en_or_dis);
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} else {
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ahb_dma_ll_tx_enable_etm_task(hal->ahb_dma_dev, chan_id, en_or_dis);
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}
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}
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#endif // SOC_GDMA_SUPPORT_ETM
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void gdma_ahb_hal_init(gdma_hal_context_t *hal, const gdma_hal_config_t *config)
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{
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hal->ahb_dma_dev = AHB_DMA_LL_GET_HW(config->group_id - GDMA_LL_AHB_GROUP_START_ID);
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hal->priv_data = &gdma_ahb_hal_priv_data;
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hal->start_with_desc = gdma_ahb_hal_start_with_desc;
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hal->stop = gdma_ahb_hal_stop;
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hal->append = gdma_ahb_hal_append;
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hal->reset = gdma_ahb_hal_reset;
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hal->set_priority = gdma_ahb_hal_set_priority;
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hal->connect_peri = gdma_ahb_hal_connect_peri;
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hal->disconnect_peri = gdma_ahb_hal_disconnect_peri;
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hal->enable_burst = gdma_ahb_hal_enable_burst;
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hal->set_strategy = gdma_ahb_hal_set_strategy;
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hal->enable_intr = gdma_ahb_hal_enable_intr;
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hal->clear_intr = gdma_ahb_hal_clear_intr;
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hal->read_intr_status = gdma_ahb_hal_read_intr_status;
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hal->get_intr_status_reg = gdma_ahb_hal_get_intr_status_reg;
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hal->get_eof_desc_addr = gdma_ahb_hal_get_eof_desc_addr;
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#if SOC_GDMA_SUPPORT_CRC
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hal->clear_crc = gdma_ahb_hal_clear_crc;
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hal->set_crc_poly = gdma_ahb_hal_set_crc_poly;
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hal->get_crc_result = gdma_ahb_hal_get_crc_result;
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#endif // SOC_GDMA_SUPPORT_CRC
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#if SOC_GDMA_SUPPORT_ETM
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hal->enable_etm_task = gdma_ahb_hal_enable_etm_task;
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#endif // SOC_GDMA_SUPPORT_ETM
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}
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