kopia lustrzana https://github.com/espressif/esp-idf
76 wiersze
2.1 KiB
C
76 wiersze
2.1 KiB
C
/*
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "hal/clk_tree_hal.h"
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#include "hal/clk_tree_ll.h"
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#include "hal/assert.h"
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#include "hal/log.h"
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static const char *CLK_HAL_TAG = "clk_hal";
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uint32_t clk_hal_soc_root_get_freq_mhz(soc_cpu_clk_src_t cpu_clk_src)
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{
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switch (cpu_clk_src) {
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case SOC_CPU_CLK_SRC_XTAL:
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return clk_hal_xtal_get_freq_mhz();
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case SOC_CPU_CLK_SRC_PLL:
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return clk_ll_bbpll_get_freq_mhz();
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case SOC_CPU_CLK_SRC_RC_FAST:
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return SOC_CLK_RC_FAST_FREQ_APPROX / MHZ;
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default:
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// Unknown CPU_CLK mux input
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HAL_ASSERT(false);
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return 0;
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}
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}
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uint32_t clk_hal_cpu_get_freq_hz(void)
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{
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soc_cpu_clk_src_t source = clk_ll_cpu_get_src();
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uint32_t divider = (source == SOC_CPU_CLK_SRC_PLL) ? clk_ll_cpu_get_hs_divider() : clk_ll_cpu_get_ls_divider();
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return clk_hal_soc_root_get_freq_mhz(source) * MHZ / divider;
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}
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static uint32_t clk_hal_ahb_get_freq_hz(void)
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{
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soc_cpu_clk_src_t source = clk_ll_cpu_get_src();
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uint32_t divider = (source == SOC_CPU_CLK_SRC_PLL) ? clk_ll_ahb_get_hs_divider() : clk_ll_ahb_get_ls_divider();
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return clk_hal_soc_root_get_freq_mhz(source) * MHZ / divider;
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}
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uint32_t clk_hal_apb_get_freq_hz(void)
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{
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return clk_hal_ahb_get_freq_hz() / clk_ll_apb_get_divider();
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}
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uint32_t clk_hal_lp_slow_get_freq_hz(void)
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{
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switch (clk_ll_rtc_slow_get_src()) {
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case SOC_RTC_SLOW_CLK_SRC_RC_SLOW:
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return SOC_CLK_RC_SLOW_FREQ_APPROX;
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case SOC_RTC_SLOW_CLK_SRC_XTAL32K:
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return SOC_CLK_XTAL32K_FREQ_APPROX;
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case SOC_RTC_SLOW_CLK_SRC_OSC_SLOW:
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return SOC_CLK_OSC_SLOW_FREQ_APPROX;
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case SOC_RTC_SLOW_CLK_SRC_RC32K:
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return SOC_CLK_RC32K_FREQ_APPROX;
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default:
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// Unknown RTC_SLOW_CLK mux input
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HAL_ASSERT(false);
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return 0;
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}
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}
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uint32_t clk_hal_xtal_get_freq_mhz(void)
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{
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uint32_t freq = clk_ll_xtal_load_freq_mhz();
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if (freq == 0) {
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HAL_LOGW(CLK_HAL_TAG, "invalid RTC_XTAL_FREQ_REG value, assume 40MHz");
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return (uint32_t)SOC_XTAL_FREQ_40M;
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}
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return freq;
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}
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