kopia lustrzana https://github.com/espressif/esp-idf
186 wiersze
7.4 KiB
C
186 wiersze
7.4 KiB
C
/*
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* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include <stdio.h>
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#include <stdbool.h>
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#include "sdkconfig.h"
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#include "soc/soc_caps.h"
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#include "hal/wdt_hal.h"
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#include "hal/mwdt_ll.h"
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#include "hal/timer_ll.h"
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#include "freertos/FreeRTOS.h"
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#include "esp_cpu.h"
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#include "esp_err.h"
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#include "esp_attr.h"
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#include "esp_log.h"
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#include "esp_intr_alloc.h"
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#include "esp_chip_info.h"
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#include "esp_freertos_hooks.h"
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#include "esp_private/periph_ctrl.h"
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#include "esp_private/esp_int_wdt.h"
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#if SOC_TIMER_GROUPS > 1
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/* If we have two hardware timer groups, use the second one for interrupt watchdog. */
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#define WDT_LEVEL_INTR_SOURCE ETS_TG1_WDT_LEVEL_INTR_SOURCE
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#define IWDT_PRESCALER MWDT_LL_DEFAULT_CLK_PRESCALER // Tick period of 500us if WDT source clock is 80MHz
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#define IWDT_TICKS_PER_US 500
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#define IWDT_INSTANCE WDT_MWDT1
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#define IWDT_INITIAL_TIMEOUT_S 5
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#define IWDT_PERIPH PERIPH_TIMG1_MODULE
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#define IWDT_TIMER_GROUP 1
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#else
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#define WDT_LEVEL_INTR_SOURCE ETS_TG0_WDT_LEVEL_INTR_SOURCE
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#define IWDT_PRESCALER MWDT_LL_DEFAULT_CLK_PRESCALER // Tick period of 500us if WDT source clock is 80MHz
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#define IWDT_TICKS_PER_US 500
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#define IWDT_INSTANCE WDT_MWDT0
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#define IWDT_INITIAL_TIMEOUT_S 5
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#define IWDT_PERIPH PERIPH_TIMG0_MODULE
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#define IWDT_TIMER_GROUP 0
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#endif // SOC_TIMER_GROUPS > 1
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#if CONFIG_ESP_INT_WDT
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static wdt_hal_context_t iwdt_context;
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#if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
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/*
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* This parameter is used to indicate the response time of Interrupt watchdog to
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* identify the live lock.
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*/
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#define IWDT_LIVELOCK_TIMEOUT_MS (20)
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extern uint32_t _lx_intr_livelock_counter, _lx_intr_livelock_max;
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#endif
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#if CONFIG_ESP_INT_WDT_CHECK_CPU1
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volatile bool int_wdt_cpu1_ticked = false;
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#endif
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static void IRAM_ATTR tick_hook(void)
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{
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#if CONFIG_ESP_INT_WDT_CHECK_CPU1
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if (esp_cpu_get_core_id() != 0) {
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int_wdt_cpu1_ticked = true;
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} else {
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// Only feed wdt if app cpu also ticked.
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if (int_wdt_cpu1_ticked) {
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// Todo: Check if there's a way to avoid reconfiguring the stages on each feed.
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wdt_hal_write_protect_disable(&iwdt_context);
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// Reconfigure stage timeouts
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#if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
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_lx_intr_livelock_counter = 0;
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wdt_hal_config_stage(&iwdt_context, WDT_STAGE0,
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CONFIG_ESP_INT_WDT_TIMEOUT_MS * 1000 / IWDT_TICKS_PER_US / (_lx_intr_livelock_max + 1), WDT_STAGE_ACTION_INT); // Set timeout before interrupt
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#else
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wdt_hal_config_stage(&iwdt_context, WDT_STAGE0, CONFIG_ESP_INT_WDT_TIMEOUT_MS * 1000 / IWDT_TICKS_PER_US, WDT_STAGE_ACTION_INT); // Set timeout before interrupt
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#endif
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wdt_hal_config_stage(&iwdt_context, WDT_STAGE1, 2 * CONFIG_ESP_INT_WDT_TIMEOUT_MS * 1000 / IWDT_TICKS_PER_US, WDT_STAGE_ACTION_RESET_SYSTEM); // Set timeout before reset
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wdt_hal_feed(&iwdt_context);
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wdt_hal_write_protect_enable(&iwdt_context);
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int_wdt_cpu1_ticked = false;
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}
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}
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#else // CONFIG_ESP_INT_WDT_CHECK_CPU1
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if (esp_cpu_get_core_id() != 0) {
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return;
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} else {
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// Todo: Check if there's a way to avoid reconfiguring the stages on each feed.
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wdt_hal_write_protect_disable(&iwdt_context);
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// Reconfigure stage timeouts
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wdt_hal_config_stage(&iwdt_context, WDT_STAGE0, CONFIG_ESP_INT_WDT_TIMEOUT_MS * 1000 / IWDT_TICKS_PER_US, WDT_STAGE_ACTION_INT); // Set timeout before interrupt
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wdt_hal_config_stage(&iwdt_context, WDT_STAGE1, 2 * CONFIG_ESP_INT_WDT_TIMEOUT_MS * 1000 / IWDT_TICKS_PER_US, WDT_STAGE_ACTION_RESET_SYSTEM); // Set timeout before reset
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wdt_hal_feed(&iwdt_context);
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wdt_hal_write_protect_enable(&iwdt_context);
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}
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#endif // CONFIG_ESP_INT_WDT_CHECK_CPU1
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}
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void esp_int_wdt_init(void)
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{
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PERIPH_RCC_ACQUIRE_ATOMIC(IWDT_PERIPH, ref_count) {
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if (ref_count == 0) {
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timer_ll_enable_bus_clock(IWDT_TIMER_GROUP, true);
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timer_ll_reset_register(IWDT_TIMER_GROUP);
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}
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}
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/*
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* Initialize the WDT timeout stages. Note that the initial timeout is set to 5 seconds as variable startup times of
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* each CPU can lead to a timeout. The tick hooks will set the WDT timers to the actual timeout.
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* Todo: Fix this
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*/
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wdt_hal_init(&iwdt_context, IWDT_INSTANCE, IWDT_PRESCALER, true);
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wdt_hal_write_protect_disable(&iwdt_context);
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wdt_hal_config_stage(&iwdt_context, WDT_STAGE0, IWDT_INITIAL_TIMEOUT_S * 1000000 / IWDT_TICKS_PER_US, WDT_STAGE_ACTION_INT);
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wdt_hal_config_stage(&iwdt_context, WDT_STAGE1, IWDT_INITIAL_TIMEOUT_S * 1000000 / IWDT_TICKS_PER_US, WDT_STAGE_ACTION_RESET_SYSTEM);
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wdt_hal_enable(&iwdt_context);
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wdt_hal_write_protect_enable(&iwdt_context);
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#if (CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BTDM_CTRL_HLI)
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#define APB_DCRSET (0x200c)
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#define APB_ITCTRL (0x3f00)
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#define ERI_ADDR(APB) (0x100000 + (APB))
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#define _SYM2STR(x) # x
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#define SYM2STR(x) _SYM2STR(x)
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uint32_t eriadrs, scratch = 0, immediate = 0;
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if (soc_has_cache_lock_bug()) {
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if (xPortGetCoreID() != CONFIG_BTDM_CTRL_PINNED_TO_CORE) {
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__asm__ __volatile__(
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/* Enable Xtensa Debug Module Integration Mode */
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"movi %[ERI], " SYM2STR(ERI_ADDR(APB_ITCTRL)) "\n"
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"rer %[REG], %[ERI]\n"
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"movi %[IMM], 1\n"
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"or %[REG], %[IMM], %[REG]\n"
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"wer %[REG], %[ERI]\n"
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/* Enable Xtensa Debug Module BreakIn signal */
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"movi %[ERI], " SYM2STR(ERI_ADDR(APB_DCRSET)) "\n"
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"rer %[REG], %[ERI]\n"
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"movi %[IMM], 0x10000\n"
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"or %[REG], %[IMM], %[REG]\n"
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"wer %[REG], %[ERI]\n"
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: [ERI] "=r"(eriadrs), [REG] "+r"(scratch), [IMM] "+r"(immediate)
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);
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}
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}
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#endif // (CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BTDM_CTRL_HLI)
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}
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void esp_int_wdt_cpu_init(void)
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{
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assert((CONFIG_ESP_INT_WDT_TIMEOUT_MS >= (portTICK_PERIOD_MS << 1)) && "Interrupt watchdog timeout needs to be at least twice the RTOS tick period!");
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// Register tick hook for current CPU to feed the INT WDT
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esp_register_freertos_tick_hook_for_cpu(tick_hook, esp_cpu_get_core_id());
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/*
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* Register INT WDT interrupt for current CPU. We do this manually as the timeout interrupt should call an assembly
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* panic handler (see riscv/vector.S and xtensa_vectors.S).
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*/
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esp_intr_disable_source(ETS_INT_WDT_INUM);
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esp_rom_route_intr_matrix(esp_cpu_get_core_id(), WDT_LEVEL_INTR_SOURCE, ETS_INT_WDT_INUM);
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#if SOC_CPU_HAS_FLEXIBLE_INTC
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esp_cpu_intr_set_type(ETS_INT_WDT_INUM, INTR_TYPE_LEVEL);
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esp_cpu_intr_set_priority(ETS_INT_WDT_INUM, SOC_INTERRUPT_LEVEL_MEDIUM);
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#endif
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#if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
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/*
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* This is a workaround for issue 3.15 in "ESP32 ECO and workarounds for
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* Bugs" document.
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*/
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_lx_intr_livelock_counter = 0;
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if (soc_has_cache_lock_bug()) {
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assert((portTICK_PERIOD_MS << 1) <= IWDT_LIVELOCK_TIMEOUT_MS);
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assert(CONFIG_ESP_INT_WDT_TIMEOUT_MS >= (IWDT_LIVELOCK_TIMEOUT_MS * 3));
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_lx_intr_livelock_max = CONFIG_ESP_INT_WDT_TIMEOUT_MS / IWDT_LIVELOCK_TIMEOUT_MS - 1;
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}
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#endif
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esp_intr_enable_source(ETS_INT_WDT_INUM);
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}
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#endif // CONFIG_ESP_INT_WDT
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