kopia lustrzana https://github.com/espressif/esp-idf
112 wiersze
2.9 KiB
C
112 wiersze
2.9 KiB
C
/*
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* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "esp_attr.h"
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#include <stdint.h>
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#include "freertos/FreeRTOS.h"
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#include "freertos/semphr.h"
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#include "hal/regi2c_ctrl.h"
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#include "hal/regi2c_ctrl_ll.h"
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#include "esp_hw_log.h"
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static portMUX_TYPE mux = portMUX_INITIALIZER_UNLOCKED;
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static DRAM_ATTR __attribute__((unused)) const char *TAG = "REGI2C";
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uint8_t IRAM_ATTR regi2c_ctrl_read_reg(uint8_t block, uint8_t host_id, uint8_t reg_add)
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{
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portENTER_CRITICAL_SAFE(&mux);
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uint8_t value = regi2c_read_reg_raw(block, host_id, reg_add);
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portEXIT_CRITICAL_SAFE(&mux);
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return value;
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}
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uint8_t IRAM_ATTR regi2c_ctrl_read_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb)
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{
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portENTER_CRITICAL_SAFE(&mux);
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uint8_t value = regi2c_read_reg_mask_raw(block, host_id, reg_add, msb, lsb);
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portEXIT_CRITICAL_SAFE(&mux);
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return value;
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}
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void IRAM_ATTR regi2c_ctrl_write_reg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data)
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{
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portENTER_CRITICAL_SAFE(&mux);
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regi2c_write_reg_raw(block, host_id, reg_add, data);
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portEXIT_CRITICAL_SAFE(&mux);
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}
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void IRAM_ATTR regi2c_ctrl_write_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data)
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{
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portENTER_CRITICAL_SAFE(&mux);
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regi2c_write_reg_mask_raw(block, host_id, reg_add, msb, lsb, data);
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portEXIT_CRITICAL_SAFE(&mux);
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}
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void IRAM_ATTR regi2c_enter_critical(void)
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{
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portENTER_CRITICAL_SAFE(&mux);
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}
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void IRAM_ATTR regi2c_exit_critical(void)
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{
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portEXIT_CRITICAL_SAFE(&mux);
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}
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/**
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* Restore regi2c analog calibration related configuration registers.
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* This is a workaround, and is fixed on later chips
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*/
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#if REGI2C_ANA_CALI_PD_WORKAROUND
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#include "soc/regi2c_saradc.h"
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static DRAM_ATTR uint8_t reg_val[REGI2C_ANA_CALI_BYTE_NUM];
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void IRAM_ATTR regi2c_analog_cali_reg_read(void)
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{
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for (int i = 0; i < REGI2C_ANA_CALI_BYTE_NUM; i++) {
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reg_val[i] = regi2c_ctrl_read_reg(I2C_SAR_ADC, I2C_SAR_ADC_HOSTID, i);
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}
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}
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void IRAM_ATTR regi2c_analog_cali_reg_write(void)
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{
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for (int i = 0; i < REGI2C_ANA_CALI_BYTE_NUM; i++) {
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regi2c_ctrl_write_reg(I2C_SAR_ADC, I2C_SAR_ADC_HOSTID, i, reg_val[i]);
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}
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}
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#endif //#if ADC_CALI_PD_WORKAROUND
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/**
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* REGI2C_SARADC reference count
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*/
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static int s_i2c_saradc_enable_cnt;
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void regi2c_saradc_enable(void)
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{
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regi2c_enter_critical();
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s_i2c_saradc_enable_cnt++;
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if (s_i2c_saradc_enable_cnt == 1) {
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regi2c_ctrl_ll_i2c_saradc_enable();
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}
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regi2c_exit_critical();
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}
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void regi2c_saradc_disable(void)
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{
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regi2c_enter_critical();
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s_i2c_saradc_enable_cnt--;
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if (s_i2c_saradc_enable_cnt < 0){
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regi2c_exit_critical();
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ESP_HW_LOGE(TAG, "REGI2C_SARADC is already disabled");
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} else if (s_i2c_saradc_enable_cnt == 0) {
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regi2c_ctrl_ll_i2c_saradc_disable();
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}
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regi2c_exit_critical();
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}
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