kopia lustrzana https://github.com/espressif/esp-idf
258 wiersze
12 KiB
C
258 wiersze
12 KiB
C
/*
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* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include <stdatomic.h>
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#include <sys/queue.h>
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#include "esp_err.h"
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#include "driver/i2c_types.h"
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#include "hal/i2c_hal.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/semphr.h"
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#include "freertos/task.h"
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#include "freertos/ringbuf.h"
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#include "driver/i2c_slave.h"
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#include "esp_private/periph_ctrl.h"
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#include "esp_pm.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if SOC_PERIPH_CLK_CTRL_SHARED
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#define I2C_CLOCK_SRC_ATOMIC() PERIPH_RCC_ATOMIC()
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#else
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#define I2C_CLOCK_SRC_ATOMIC()
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#endif
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#if !SOC_RCC_IS_INDEPENDENT
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#define I2C_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
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#else
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#define I2C_RCC_ATOMIC()
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#endif
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#if SOC_LP_I2C_SUPPORTED
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#define LP_I2C_SRC_CLK_ATOMIC() PERIPH_RCC_ATOMIC()
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#define LP_I2C_BUS_CLK_ATOMIC() PERIPH_RCC_ATOMIC()
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#endif
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#if CONFIG_I2C_ISR_IRAM_SAFE
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#define I2C_MEM_ALLOC_CAPS (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT)
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#else
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#define I2C_MEM_ALLOC_CAPS (MALLOC_CAP_DEFAULT)
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#endif
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// I2C driver object is per-mode, the interrupt source is shared between modes
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#if CONFIG_I2C_ISR_IRAM_SAFE
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#define I2C_INTR_ALLOC_FLAG (ESP_INTR_FLAG_SHARED | ESP_INTR_FLAG_IRAM | ESP_INTR_FLAG_LOWMED)
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#else
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#define I2C_INTR_ALLOC_FLAG (ESP_INTR_FLAG_SHARED | ESP_INTR_FLAG_LOWMED)
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#endif
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#define I2C_ALLOW_INTR_PRIORITY_MASK ESP_INTR_FLAG_LOWMED
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#define I2C_PM_LOCK_NAME_LEN_MAX 16
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#define I2C_STATIC_OPERATION_ARRAY_MAX 6
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#define ACK_VAL 0
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#define NACK_VAL 1
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#define I2C_TRANS_READ_COMMAND(ack_value) {.ack_val = (ack_value), .op_code = I2C_LL_CMD_READ}
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#define I2C_TRANS_WRITE_COMMAND(ack_check) {.ack_en = (ack_check), .op_code = I2C_LL_CMD_WRITE}
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#define I2C_TRANS_STOP_COMMAND {.op_code = I2C_LL_CMD_STOP}
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#define I2C_TRANS_START_COMMAND {.op_code = I2C_LL_CMD_RESTART}
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typedef struct i2c_bus_t i2c_bus_t;
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typedef struct i2c_master_bus_t i2c_master_bus_t;
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typedef struct i2c_bus_t *i2c_bus_handle_t;
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typedef struct i2c_master_dev_t i2c_master_dev_t;
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typedef struct i2c_slave_dev_t i2c_slave_dev_t;
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typedef enum {
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I2C_BUS_MODE_MASTER = 0,
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I2C_BUS_MODE_SLAVE = 1,
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} i2c_bus_mode_t;
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typedef enum {
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I2C_SLAVE_FIFO = 0,
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I2C_SLAVE_NONFIFO = 1,
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} i2c_slave_fifo_mode_t;
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enum {
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I2C_TRANS_QUEUE_READY,
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I2C_TRANS_QUEUE_PROGRESS,
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I2C_TRANS_QUEUE_COMPLETE,
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I2C_TRANS_QUEUE_MAX,
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};
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typedef struct {
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i2c_ll_hw_cmd_t hw_cmd; // I2C command, defined by hardware
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uint8_t *data; // Pointer to data
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uint16_t bytes_used; // I2C data has been used
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size_t total_bytes; // Total bytes to be transferred
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} i2c_operation_t;
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typedef struct {
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uint32_t device_address; // Address of I2C device
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i2c_operation_t *ops; // Pointer to I2C operation structure
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size_t cmd_count; // Record how many I2C hardware commands in one transaction
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} i2c_transaction_t;
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struct i2c_bus_t {
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i2c_port_num_t port_num; // Port(Bus) ID, index from 0
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bool is_lp_i2c; // true if current port is lp_i2c. false is hp_i2c
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portMUX_TYPE spinlock; // To protect pre-group register level concurrency access
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i2c_hal_context_t hal; // Hal layer for each port(bus)
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soc_module_clk_t clk_src; // Record the port clock source
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uint32_t clk_src_freq_hz; // Record the clock source frequency
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int sda_num; // SDA pin number
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int scl_num; // SCL pin number
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bool pull_up_enable; // Enable pull-ups
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intr_handle_t intr_handle; // I2C interrupt handle
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esp_pm_lock_handle_t pm_lock; // power manage lock
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#if CONFIG_PM_ENABLE
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char pm_lock_name[I2C_PM_LOCK_NAME_LEN_MAX]; // pm lock name
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#endif
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i2c_bus_mode_t bus_mode; // I2C bus mode
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};
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typedef struct i2c_master_device_list {
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i2c_master_dev_t *device;
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SLIST_ENTRY(i2c_master_device_list) next;
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} i2c_master_device_list_t;
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struct i2c_master_bus_t {
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i2c_bus_t *base; // bus base class
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SemaphoreHandle_t bus_lock_mux; // semaphore to lock bus process
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int cmd_idx; //record current command index, for master mode
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_Atomic i2c_master_status_t status; // record current command status, for master mode
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i2c_master_event_t event; // record current i2c bus event
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int rx_cnt; // record current read index, for master mode
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i2c_transaction_t i2c_trans; // Pointer to I2C transfer structure
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i2c_operation_t i2c_ops[I2C_STATIC_OPERATION_ARRAY_MAX]; // I2C operation array
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_Atomic uint16_t trans_idx; // Index of I2C transaction command.
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SemaphoreHandle_t cmd_semphr; // Semaphore between task and interrupt, using for synchronizing ISR and I2C task.
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QueueHandle_t event_queue; // I2C event queue
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uint32_t read_buf_pos; // Read buffer position
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bool contains_read; // Whether command array includes read operation, true: yes, otherwise, false.
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uint32_t read_len_static; // Read static buffer length
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uint32_t w_r_size; // The size send/receive last time.
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bool trans_over_buffer; // Data length is more than hardware fifo length, needs interrupt.
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bool async_trans; // asynchronous transaction, true after callback is installed.
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bool ack_check_disable; // Disable ACK check
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volatile bool trans_done; // transaction command finish
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bool bypass_nack_log; // Bypass the error log. Sometimes the error is expected.
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SLIST_HEAD(i2c_master_device_list_head, i2c_master_device_list) device_list; // I2C device (instance) list
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// async trans members
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bool async_break; // break transaction loop flag.
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i2c_addr_bit_len_t addr_10bits_bus; // Slave address is 10 bits.
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size_t queue_size; // I2C transaction queue size.
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size_t num_trans_inflight; // Indicates the number of transactions that are undergoing but not recycled to ready_queue
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size_t num_trans_inqueue; // Indicates the number of transaction in queue transaction.
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void* queues_storage; // storage of transaction queues
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bool sent_all; // true if the queue transaction is sent
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bool in_progress; // true if current transaction is in progress
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bool trans_finish; // true if current command has been sent out.
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bool queue_trans; // true if current transaction is in queue
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bool new_queue; // true if allow a new queue transaction
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QueueHandle_t trans_queues[I2C_TRANS_QUEUE_MAX]; // transaction queues.
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StaticQueue_t trans_queue_structs[I2C_TRANS_QUEUE_MAX]; // memory to store the static structure for trans_queues
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i2c_operation_t (*i2c_async_ops)[I2C_STATIC_OPERATION_ARRAY_MAX]; // pointer to asynchronous operation(s).
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uint32_t ops_prepare_idx; // Index for the operations can be written into `i2c_async_ops` array.
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uint32_t ops_cur_size; // Indicates how many operations have already put in `i2c_async_ops`.
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i2c_transaction_t i2c_trans_pool[]; // I2C transaction pool.
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};
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struct i2c_master_dev_t {
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i2c_master_bus_t *master_bus; // I2C master bus base class
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uint16_t device_address; // I2C device address
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uint32_t scl_speed_hz; // SCL clock frequency
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uint32_t scl_wait_us; // SCL await time (unit:us)
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i2c_addr_bit_len_t addr_10bits; // Whether I2C device is a 10-bits address device.
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bool ack_check_disable; // Disable ACK check
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i2c_master_callback_t on_trans_done; // I2C master transaction done callback.
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void *user_ctx; // Callback user context
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};
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typedef struct {
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bool trans_complete; // Event of transaction complete
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bool slave_stretch; // Event of slave stretch happens
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bool addr_unmatch; // Event of address unmatched
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} i2c_slave_evt_t;
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typedef struct {
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uint8_t *buffer; // Pointer to the buffer need to be received in ISR
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uint32_t rcv_fifo_cnt; // receive fifo count.
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} i2c_slave_receive_t;
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struct i2c_slave_dev_t {
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i2c_bus_t *base; // bus base class
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SemaphoreHandle_t slv_rx_mux; // Mutex for slave rx direction
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SemaphoreHandle_t slv_tx_mux; // Mutex for slave tx direction
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RingbufHandle_t rx_ring_buf; // Handle for rx ringbuffer
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RingbufHandle_t tx_ring_buf; // Handle for tx ringbuffer
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uint8_t data_buf[SOC_I2C_FIFO_LEN]; // Data buffer for slave
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uint32_t trans_data_length; // Send data length
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i2c_slave_event_callbacks_t callbacks; // I2C slave callbacks
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void *user_ctx; // Callback user context
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i2c_slave_fifo_mode_t fifo_mode; // Slave fifo mode.
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QueueHandle_t slv_evt_queue; // Event Queue used in slave nonfifo mode.
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i2c_slave_evt_t slave_evt; // Slave event structure.
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i2c_slave_receive_t receive_desc; // Slave receive descriptor
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uint32_t already_receive_len; // Data length already received in ISR.
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};
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/**
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* @brief Acquire I2C bus handle
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*
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* @param port_num I2C port number.
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* @return
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* - ESP_OK: Acquire bus handle successfully.
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* - ESP_ERR_INVALID_ARG: Argument error.
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* - ESP_ERR_INVALID_STATE: Acquire bus invalid state because bus has already acquired.
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*/
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esp_err_t i2c_acquire_bus_handle(i2c_port_num_t port_num, i2c_bus_handle_t *i2c_new_bus, i2c_bus_mode_t mode);
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/**
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* @brief Release I2C bus handle
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*
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* @param i2c_bus I2C bus handle, returned from `i2c_acquire_bus_handle`
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* @return ESP_OK: If release successfully
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* ESP_ERR_INVALID_STATE: Release bus failed because same bus has been required several times.
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* Otherwise: Other reasons.
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*/
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esp_err_t i2c_release_bus_handle(i2c_bus_handle_t i2c_bus);
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/**
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* @brief Set clock source for I2C peripheral
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*
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* @param handle I2C bus handle
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* @param clk_src Clock source
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* @return
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* - ESP_OK: Set clock source successfully
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* - ESP_ERR_NOT_SUPPORTED: Set clock source failed because the clk_src is not supported
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* - ESP_ERR_INVALID_STATE: Set clock source failed because the clk_src is different from other I2C controller
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* - ESP_FAIL: Set clock source failed because of other error
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*/
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esp_err_t i2c_select_periph_clock(i2c_bus_handle_t handle, soc_module_clk_t clk_src);
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/**
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* @brief Set I2C SCL/SDA pins
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*
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* @param handle I2C bus handle
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* @return
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* - ESP_OK: I2C set SCL/SDA pins successfully.
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* - ESP_ERR_INVALID_ARG: Argument error.
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* - Otherwise: Set SCL/SDA IOs error.
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*/
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esp_err_t i2c_common_set_pins(i2c_bus_handle_t handle);
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#ifdef __cplusplus
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}
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#endif
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