kopia lustrzana https://github.com/espressif/esp-idf
92 wiersze
2.7 KiB
C
92 wiersze
2.7 KiB
C
/*
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* This file is a target specific for DAC DMA peripheral
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* Target: ESP32
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* DAC DMA peripheral (data source): I2S0 (i.e. use I2S DMA to transmit data)
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* DAC DMA interrupt source: I2S0
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* DAC digital controller clock source: I2S ws signal (root clock: D2PLL or APLL)
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*/
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#include "hal/i2s_types.h"
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#include "driver/i2s_types.h"
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#include "soc/i2s_periph.h"
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#include "esp_private/i2s_platform.h"
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#include "esp_private/adc_dma.h"
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#include "hal/i2s_ll.h"
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#define ADC_DMA_I2S_HOST ADC_HAL_DMA_I2S_HOST
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#define ADC_DMA_INTR_MASK BIT(9)
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static IRAM_ATTR void adc_dma_intr_handler(void *arg)
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{
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adc_continuous_ctx_t *ctx = (adc_continuous_ctx_t *)arg;
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bool need_yield = false;
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bool conversion_finish = i2s_ll_get_intr_status(ctx->adc_dma.adc_i2s_dev) & ADC_DMA_INTR_MASK;
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if (conversion_finish) {
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i2s_ll_clear_intr_status(ctx->adc_dma.adc_i2s_dev, ADC_DMA_INTR_MASK);
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uint32_t desc_addr;
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i2s_ll_rx_get_eof_des_addr(ctx->adc_dma.adc_i2s_dev, &desc_addr);
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ctx->rx_eof_desc_addr = (intptr_t)desc_addr;
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need_yield = ctx->adc_intr_func(ctx);
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}
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if (need_yield) {
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portYIELD_FROM_ISR();
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}
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}
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esp_err_t adc_dma_intr_event_init(adc_continuous_ctx_t *adc_ctx)
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{
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return (esp_intr_alloc(i2s_periph_signal[ADC_DMA_I2S_HOST].irq, ESP_INTR_FLAG_IRAM, adc_dma_intr_handler,
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(void *)adc_ctx, &adc_ctx->adc_dma.dma_intr_hdl));
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}
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esp_err_t adc_dma_init(adc_dma_t *adc_dma)
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{
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esp_err_t ret = ESP_OK;
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//ADC utilises I2S0 DMA on ESP32
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ret = i2s_platform_acquire_occupation(ADC_DMA_I2S_HOST, "adc");
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if (ret != ESP_OK) {
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return ESP_ERR_NOT_FOUND;
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}
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adc_dma->adc_i2s_dev = I2S_LL_GET_HW(ADC_DMA_I2S_HOST);
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return ESP_OK;
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}
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esp_err_t adc_dma_deinit(adc_dma_t adc_dma)
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{
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esp_intr_free(adc_dma.dma_intr_hdl);
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i2s_platform_release_occupation(ADC_DMA_I2S_HOST);
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return ESP_OK;
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}
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esp_err_t adc_dma_start(adc_dma_t adc_dma, dma_descriptor_t *addr)
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{
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i2s_ll_clear_intr_status(adc_dma.adc_i2s_dev, ADC_DMA_INTR_MASK);
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i2s_ll_enable_intr(adc_dma.adc_i2s_dev, ADC_DMA_INTR_MASK, true);
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i2s_ll_enable_dma(adc_dma.adc_i2s_dev, true);
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i2s_ll_rx_start_link(adc_dma.adc_i2s_dev, (uint32_t)addr);
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return ESP_OK;
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}
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esp_err_t adc_dma_stop(adc_dma_t adc_dma)
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{
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i2s_ll_enable_intr(adc_dma.adc_i2s_dev, ADC_DMA_INTR_MASK, false);
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i2s_ll_clear_intr_status(adc_dma.adc_i2s_dev, ADC_DMA_INTR_MASK);
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i2s_ll_rx_stop_link(adc_dma.adc_i2s_dev);
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return ESP_OK;
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}
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esp_err_t adc_dma_reset(adc_dma_t adc_dma)
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{
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i2s_ll_rx_reset_dma(adc_dma.adc_i2s_dev);
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return ESP_OK;
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}
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