This commit introduce SOC_MEM_NON_CONTIGUOUS_SRAM flag (that enebled for
esp32p4). If SOC_MEM_NON_CONTIGUOUS_SRAM is enabled:
- LDFLAGS+=--enable-non-contiguous-regions
- ldgen.py replaces "arrays[*]" from sections.ld.in with objects under
SURROUND keyword. (e.g. from linker.lf: data -> dram0_data SURROUND(foo))
- "mapping[*]" - refers to all other data
If SOC_MEM_NON_CONTIGUOUS_SRAM, sections.ld.in file should contain at
least one block of code like this (otherwise it does not make sense):
.dram0.bss (NOLOAD) :
{
arrays[dram0_bss]
mapping[dram0_bss]
} > sram_low
.dram1.bss (NOLOAD) :
{
/* do not place here arrays[dram0_bss] because it may be splited
* between segments */
mapping[dram0_bss]
} > sram_high
1st bootloader won't help to initialize the MSPI & cache properly as it
usually do when loading from flash. And the ram app doesn't have valid
headers.
Since there is no enough space in 2nd bootloader, we replace the
`bootloader_init_spi_flash` in the ram_app (!pure_ram_app), with an
customized alternative of it for the ram_app.
This alternative helps to initialize the MSPI & cache properly, without
the help of 1st bootloader or image headers.
This commit mainly targets the ESP32-P4. It adds supports for coprocessors on
RISC-V based targets. The coprocessor save area, describing the used coprocessors
is stored at the end of the stack of each task (highest address) whereas each
coprocessor save area is allocated at the beginning of the task (lowest address).
The context of each coprocessor is saved lazily, by the task that want to use it.
For RAM loadable ELF, entire firmware is running from RAM and hence the
IROM/DROM size must be treated as 0 (no cache mappings created for
code/rodata).
Memprot functions are no longer placed by default in IRAM,
selecting ESP_PANIC_HANDLER_IRAM will still force panic related memprot
functions to be placed in IRAM.
esp_rom_spiflash_attach is called in cpu_start.c when it's
CONFIG_APP_BUILD_TYPE_RAM && !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP.
This function will:
- reset MSPI
- configure MSPI IOs
- configure MSPI into slow read mode
Prior to this commit, this function is put quite late. It's OK for chips
earlier than C6. On C6 and H2, MMU registers are in SPI_MEM_x, so
resetting MSPI registers will also reset MMU registers.
After this commit, this funciton is called eariler, before
cpu_start.c: bootloader_init().
wanlei