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refactor(spi): use RCC functions to do DMA reset

pull/13550/head
morris 2024-03-29 10:51:28 +08:00
rodzic b55a0e015a
commit f29351b99a
2 zmienionych plików z 15 dodań i 9 usunięć
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8
components/esp_driver_spi/src/gpspi/spi_common.c
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@ -970,7 +970,9 @@ bool IRAM_ATTR spicommon_dmaworkaround_req_reset(int dmachan, dmaworkaround_cb_t
ret = false;
} else {
//Reset DMA
periph_module_reset(PERIPH_SPI_DMA_MODULE);
SPI_COMMON_RCC_CLOCK_ATOMIC() {
spi_dma_ll_reset_register(dmachan);
}
ret = true;
}
portEXIT_CRITICAL_ISR(&dmaworkaround_mux);
@ -988,7 +990,9 @@ void IRAM_ATTR spicommon_dmaworkaround_idle(int dmachan)
dmaworkaround_channels_busy[dmachan - 1] = 0;
if (dmaworkaround_waiting_for_chan == dmachan) {
//Reset DMA
periph_module_reset(PERIPH_SPI_DMA_MODULE);
SPI_COMMON_RCC_CLOCK_ATOMIC() {
spi_dma_ll_reset_register(dmachan);
}
dmaworkaround_waiting_for_chan = 0;
//Call callback
dmaworkaround_cb(dmaworkaround_cb_arg);

16
components/hal/esp32/include/hal/spi_ll.h
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -260,7 +260,7 @@ static inline void spi_ll_cpu_rx_fifo_reset(spi_dev_t *hw)
/**
* Reset SPI DMA TX FIFO
*
* On ESP32, this function is not seperated
* On ESP32, this function is not separated
*
* @param hw Beginning address of the peripheral registers.
*/
@ -273,7 +273,7 @@ static inline void spi_ll_dma_tx_fifo_reset(spi_dev_t *hw)
/**
* Reset SPI DMA RX FIFO
*
* On ESP32, this function is not seperated
* On ESP32, this function is not separated
*
* @param hw Beginning address of the peripheral registers.
*/
@ -626,7 +626,7 @@ static inline void spi_ll_master_set_clock_by_reg(spi_dev_t *hw, const spi_ll_cl
* Get the frequency of given dividers. Don't use in app.
*
* @param fapb APB clock of the system.
* @param pre Pre devider.
* @param pre Pre divider.
* @param n main divider.
*
* @return Frequency of given dividers.
@ -637,10 +637,10 @@ static inline int spi_ll_freq_for_pre_n(int fapb, int pre, int n)
}
/**
* Calculate the nearest frequency avaliable for master.
* Calculate the nearest frequency available for master.
*
* @param fapb APB clock of the system.
* @param hz Frequncy desired.
* @param hz Frequency desired.
* @param duty_cycle Duty cycle desired.
* @param out_reg Output address to store the calculated clock configurations for the return frequency.
*
@ -720,7 +720,7 @@ static inline int spi_ll_master_cal_clock(int fapb, int hz, int duty_cycle, spi_
*
* @param hw Beginning address of the peripheral registers.
* @param fapb APB clock of the system.
* @param hz Frequncy desired.
* @param hz Frequency desired.
* @param duty_cycle Duty cycle desired.
*
* @return Actual frequency that is used.
@ -1079,7 +1079,9 @@ static inline void spi_dma_ll_enable_bus_clock(spi_host_device_t host_id, bool e
*
* @param host_id Peripheral index number, see `spi_host_device_t`
*/
__attribute__((always_inline))
static inline void spi_dma_ll_reset_register(spi_host_device_t host_id) {
(void)host_id; // has only one spi_dma
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_DMA_RST);
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_DMA_RST);
}