diff --git a/components/esp_hw_support/esp_clock_output.c b/components/esp_hw_support/esp_clock_output.c
index 5c647ce610..e8e3179fa9 100644
--- a/components/esp_hw_support/esp_clock_output.c
+++ b/components/esp_hw_support/esp_clock_output.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -11,8 +11,9 @@
 #include "esp_clock_output.h"
 #include "esp_check.h"
 #include "esp_rom_gpio.h"
-#include "clkout_channel.h"
+#include "soc/clkout_channel.h"
 #include "hal/gpio_hal.h"
+#include "hal/clk_tree_hal.h"
 #include "hal/clk_tree_ll.h"
 #include "soc/soc_caps.h"
 #include "soc/io_mux_reg.h"
@@ -20,7 +21,7 @@
 typedef struct clkout_channel_handle {
     bool is_mapped;
     soc_clkout_sig_id_t mapped_clock;
-    uint8_t channel_id;
+    clock_out_channel_t channel_id;
     uint8_t ref_cnt;
     uint64_t mapped_io_bmap;
     portMUX_TYPE clkout_channel_lock;
@@ -87,13 +88,12 @@ static clkout_channel_handle_t* clkout_channel_alloc(soc_clkout_sig_id_t clk_sig
         allocated_channel->mapped_io_bmap |= BIT(gpio_num);
         allocated_channel->mapped_clock = clk_sig;
         allocated_channel->ref_cnt++;
-
         if (allocated_channel->ref_cnt == 1) {
             portENTER_CRITICAL(&s_clkout_lock);
 #if SOC_CLOCKOUT_HAS_SOURCE_GATE
             clk_ll_enable_clkout_source(clk_sig, true);
 #endif
-            gpio_ll_set_pin_ctrl(clk_sig, CLKOUT_CHANNEL_MASK(allocated_channel->channel_id), CLKOUT_CHANNEL_SHIFT(allocated_channel->channel_id));
+            clk_hal_clock_output_setup(clk_sig, allocated_channel->channel_id);
             portEXIT_CRITICAL(&s_clkout_lock);
         }
         portEXIT_CRITICAL(&allocated_channel->clkout_channel_lock);
@@ -150,7 +150,7 @@ static void clkout_channel_free(clkout_channel_handle_t *channel_hdl)
 #if SOC_CLOCKOUT_HAS_SOURCE_GATE
         clk_ll_enable_clkout_source(channel_hdl->mapped_clock, false);
 #endif
-        gpio_ll_set_pin_ctrl(0, CLKOUT_CHANNEL_MASK(channel_hdl->channel_id), CLKOUT_CHANNEL_SHIFT(channel_hdl->channel_id));
+        clk_hal_clock_output_teardown(channel_hdl->channel_id);
         portEXIT_CRITICAL(&s_clkout_lock);
         channel_hdl->mapped_clock = CLKOUT_SIG_INVALID;
         channel_hdl->is_mapped = false;
@@ -187,7 +187,11 @@ static void clkout_mapping_free(esp_clock_output_mapping_t *mapping_hdl)
 esp_err_t esp_clock_output_start(soc_clkout_sig_id_t clk_sig, gpio_num_t gpio_num, esp_clock_output_mapping_handle_t *clkout_mapping_ret_hdl)
 {
     ESP_RETURN_ON_FALSE((clkout_mapping_ret_hdl != NULL), ESP_ERR_INVALID_ARG, TAG, "Clock out mapping handle passed in is invalid");
+#if SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX
+    ESP_RETURN_ON_FALSE(GPIO_IS_VALID_GPIO(gpio_num), ESP_ERR_INVALID_ARG, TAG, "%s", "Output GPIO number error");
+#else
     ESP_RETURN_ON_FALSE(IS_VALID_CLKOUT_IO(gpio_num), ESP_ERR_INVALID_ARG, TAG, "%s", "Output GPIO number error");
+#endif
 
     esp_clock_output_mapping_t *hdl;
     SLIST_FOREACH(hdl, &s_mapping_list, next) {
@@ -214,6 +218,18 @@ esp_err_t esp_clock_output_stop(esp_clock_output_mapping_handle_t clkout_mapping
     return ESP_OK;
 }
 
+#if SOC_CLOCKOUT_SUPPORT_CHANNEL_DIVIDER
+esp_err_t esp_clock_output_set_divider(esp_clock_output_mapping_handle_t clkout_mapping_hdl, uint32_t div_num)
+{
+    ESP_RETURN_ON_FALSE(((div_num > 0) && (div_num <= 256)), ESP_ERR_INVALID_ARG, TAG, "Divider number must be in the range of [1,  256]");
+    ESP_RETURN_ON_FALSE((clkout_mapping_hdl != NULL), ESP_ERR_INVALID_ARG, TAG, "Clock out mapping handle passed in is invalid");
+    portENTER_CRITICAL(&clkout_mapping_hdl->clkout_mapping_lock);
+    clk_hal_clock_output_set_divider(clkout_mapping_hdl->clkout_channel_hdl->channel_id, div_num);
+    portEXIT_CRITICAL(&clkout_mapping_hdl->clkout_mapping_lock);
+    return ESP_OK;
+}
+#endif
+
 #if CONFIG_IDF_TARGET_ESP32
 // Due to a hardware bug, PIN_CTRL cannot select 0xf output, whereas 0xf is the default value.
 __attribute__((constructor))
diff --git a/components/esp_hw_support/include/esp_clock_output.h b/components/esp_hw_support/include/esp_clock_output.h
index 2acbb1377d..f4f21ea633 100644
--- a/components/esp_hw_support/include/esp_clock_output.h
+++ b/components/esp_hw_support/include/esp_clock_output.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -25,7 +25,7 @@ typedef struct esp_clock_output_mapping *esp_clock_output_mapping_handle_t;
  *
  * @param[in]   clk_src  The clock signal source to be mapped to GPIOs
  * @param[in]   gpio_num GPIO number to be mapped soc_root_clk signal source
- * @param[out]  clkout_mapping_ret_hdl Clock output controll handler
+ * @param[out]  clkout_mapping_ret_hdl Clock output control handler
  * @return
  *      - ESP_OK: Output specified clock signal to specified GPIO successfully
  *      - ESP_ERR_INVALID_ARG: Specified GPIO not supported to output internal clock
@@ -36,12 +36,26 @@ esp_err_t esp_clock_output_start(soc_clkout_sig_id_t clk_sig, gpio_num_t gpio_nu
 
 /**
  * @brief Stop clock signal to GPIO outputting
- * @param[in]  clkout_mapping_hdl Clock output mapping controll handle
+ * @param[in]  clkout_mapping_hdl Clock output mapping control handle
  * @return
  *     - ESP_OK: Disable the clock output on GPIO successfully
- *     - ESP_ERR_INVALID_STATE  The clock in handle is already in the disabled state
+ *     - ESP_ERR_INVALID_ARG  The clock mapping handle is not initialized yet
+ *     - ESP_ERR_INVALID_STATE  The clock mapping handle is already in the disabled state
  */
 esp_err_t esp_clock_output_stop(esp_clock_output_mapping_handle_t clkout_mapping_hdl);
+
+#if SOC_CLOCKOUT_SUPPORT_CHANNEL_DIVIDER
+/**
+ * @brief Output the mapped clock after frequency division
+ * @param  clkout_mapping_hdl clkout_mapping_hdl Clock output mapping control handle
+ * @param  div_num clock frequency division value, should be in the range of 1 ~ 256
+ * @return
+ *     - ESP_OK: Disable the clock output on GPIO successfully
+ *     - ESP_ERR_INVALID_ARG  The clock mapping handle is not initialized yet or the div_num is in bad range
+ */
+esp_err_t esp_clock_output_set_divider(esp_clock_output_mapping_handle_t clkout_mapping_hdl, uint32_t div_num);
+#endif
+
 #endif // SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX || SOC_GPIO_CLOCKOUT_BY_IO_MUX
 
 #ifdef __cplusplus
diff --git a/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_esp_clock_output.c b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_esp_clock_output.c
index e3e189283e..d4d5245450 100644
--- a/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_esp_clock_output.c
+++ b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_esp_clock_output.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Unlicense OR CC0-1.0
  */
@@ -20,6 +20,8 @@
 static const int test_clk_out_io[] = {0, 1, 3};
 #elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
 static const int test_clk_out_io[] = {18, 19, 20};
+#elif CONFIG_IDF_TARGET_ESP32P4
+static const int test_clk_out_io[] = {7, 8};
 #else
 static const int test_clk_out_io[] = {3, 4, 5, 6};
 #endif
@@ -33,6 +35,9 @@ void output_clock_1(void *pvParameter)
     esp_clock_output_mapping_handle_t clkout_mapping_hdl;
     for (int i = 0; i < TEST_LOOPS; ++i) {
         TEST_ESP_OK(esp_clock_output_start(test_clk_out_sig[0], test_clk_out_io[0], &clkout_mapping_hdl));
+#if SOC_CLOCKOUT_SUPPORT_CHANNEL_DIVIDER
+        TEST_ESP_OK(esp_clock_output_set_divider(clkout_mapping_hdl, 8));
+#endif
         vTaskDelay(3);
         TEST_ESP_OK(esp_clock_output_stop(clkout_mapping_hdl));
         vTaskDelay(7);
@@ -54,6 +59,7 @@ void output_clock_2(void *pvParameter)
     vTaskDelete(NULL);
 }
 
+#if SOC_GPIO_CLOCKOUT_CHANNEL_NUM >= 3
 void output_clock_3(void *pvParameter)
 {
     rtc_dig_clk8m_enable();
@@ -67,7 +73,7 @@ void output_clock_3(void *pvParameter)
     xSemaphoreGive(test_done_semphr);
     vTaskDelete(NULL);
 }
-
+#endif
 
 // This case is now tested only manually
 TEST_CASE("GPIO output internal clock", "[gpio_output_clock][ignore]")
@@ -75,10 +81,12 @@ TEST_CASE("GPIO output internal clock", "[gpio_output_clock][ignore]")
     test_done_semphr = xSemaphoreCreateCounting(3, 0);
     xTaskCreate(&output_clock_1, "output_clock_1", 4096, NULL, 4, NULL);
     xTaskCreate(&output_clock_2, "output_clock_2", 4096, NULL, 4, NULL);
+#if SOC_GPIO_CLOCKOUT_CHANNEL_NUM >= 3
     xTaskCreate(&output_clock_3, "output_clock_3", 4096, NULL, 4, NULL);
+#endif
 
     int cnt = 0;
-    while (cnt < 3) {
+    while (cnt < SOC_GPIO_CLOCKOUT_CHANNEL_NUM) {
         if (xSemaphoreTake(test_done_semphr, portMAX_DELAY) == pdTRUE) {
             cnt++;
         }
@@ -86,8 +94,13 @@ TEST_CASE("GPIO output internal clock", "[gpio_output_clock][ignore]")
     vTaskDelay(1);
 
     vSemaphoreDelete(test_done_semphr);
+
+#if CONFIG_IDF_TARGET_ESP32
+    /* ESP32 clock out channel pin reuses UART TX/RX pin, restore its default
+       configuration at the end of the test */
     gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_U0RXD_U, FUNC_U0RXD_U0RXD);
     gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_U0TXD_U, FUNC_U0TXD_U0TXD);
+#endif
 }
 
 #if SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX
diff --git a/components/hal/esp32/clk_tree_hal.c b/components/hal/esp32/clk_tree_hal.c
index f706121d89..1b5b676cea 100644
--- a/components/hal/esp32/clk_tree_hal.c
+++ b/components/hal/esp32/clk_tree_hal.c
@@ -4,9 +4,11 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include "soc/clkout_channel.h"
+#include "hal/assert.h"
 #include "hal/clk_tree_hal.h"
 #include "hal/clk_tree_ll.h"
-#include "hal/assert.h"
+#include "hal/gpio_ll.h"
 #include "hal/log.h"
 
 static const char *CLK_HAL_TAG = "clk_hal";
@@ -106,3 +108,13 @@ uint32_t clk_hal_apll_get_freq_hz(void)
     uint32_t apll_freq_hz = (uint32_t)((xtal_freq_hz * numerator) / denominator);
     return apll_freq_hz;
 }
+
+void clk_hal_clock_output_setup(soc_clkout_sig_id_t clk_sig, clock_out_channel_t channel_id)
+{
+    gpio_ll_set_pin_ctrl(clk_sig, CLKOUT_CHANNEL_MASK(channel_id), CLKOUT_CHANNEL_SHIFT(channel_id));
+}
+
+void clk_hal_clock_output_teardown(clock_out_channel_t channel_id)
+{
+    gpio_ll_set_pin_ctrl(0, CLKOUT_CHANNEL_MASK(channel_id), CLKOUT_CHANNEL_SHIFT(channel_id));
+}
diff --git a/components/hal/esp32c2/clk_tree_hal.c b/components/hal/esp32c2/clk_tree_hal.c
index b05e0abcdc..e7cdd87702 100644
--- a/components/hal/esp32c2/clk_tree_hal.c
+++ b/components/hal/esp32c2/clk_tree_hal.c
@@ -4,10 +4,12 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include "sdkconfig.h"
+#include "soc/clkout_channel.h"
+#include "hal/assert.h"
 #include "hal/clk_tree_hal.h"
 #include "hal/clk_tree_ll.h"
-#include "sdkconfig.h"
-#include "hal/assert.h"
+#include "hal/gpio_ll.h"
 #include "hal/log.h"
 
 static const char *CLK_HAL_TAG = "clk_hal";
@@ -81,3 +83,13 @@ uint32_t clk_hal_xtal_get_freq_mhz(void)
     }
     return freq;
 }
+
+void clk_hal_clock_output_setup(soc_clkout_sig_id_t clk_sig, clock_out_channel_t channel_id)
+{
+    gpio_ll_set_pin_ctrl(clk_sig, CLKOUT_CHANNEL_MASK(channel_id), CLKOUT_CHANNEL_SHIFT(channel_id));
+}
+
+void clk_hal_clock_output_teardown(clock_out_channel_t channel_id)
+{
+    gpio_ll_set_pin_ctrl(0, CLKOUT_CHANNEL_MASK(channel_id), CLKOUT_CHANNEL_SHIFT(channel_id));
+}
diff --git a/components/hal/esp32c3/clk_tree_hal.c b/components/hal/esp32c3/clk_tree_hal.c
index 23359d5246..6ce1f5a11a 100644
--- a/components/hal/esp32c3/clk_tree_hal.c
+++ b/components/hal/esp32c3/clk_tree_hal.c
@@ -4,9 +4,11 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include "soc/clkout_channel.h"
+#include "hal/assert.h"
 #include "hal/clk_tree_hal.h"
 #include "hal/clk_tree_ll.h"
-#include "hal/assert.h"
+#include "hal/gpio_ll.h"
 #include "hal/log.h"
 
 static const char *CLK_HAL_TAG = "clk_hal";
@@ -80,3 +82,13 @@ uint32_t clk_hal_xtal_get_freq_mhz(void)
     }
     return freq;
 }
+
+void clk_hal_clock_output_setup(soc_clkout_sig_id_t clk_sig, clock_out_channel_t channel_id)
+{
+    gpio_ll_set_pin_ctrl(clk_sig, CLKOUT_CHANNEL_MASK(channel_id), CLKOUT_CHANNEL_SHIFT(channel_id));
+}
+
+void clk_hal_clock_output_teardown(clock_out_channel_t channel_id)
+{
+    gpio_ll_set_pin_ctrl(0, CLKOUT_CHANNEL_MASK(channel_id), CLKOUT_CHANNEL_SHIFT(channel_id));
+}
diff --git a/components/hal/esp32c5/clk_tree_hal.c b/components/hal/esp32c5/clk_tree_hal.c
index 8d6fc467c4..d68db76ccd 100644
--- a/components/hal/esp32c5/clk_tree_hal.c
+++ b/components/hal/esp32c5/clk_tree_hal.c
@@ -4,10 +4,11 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include "sdkconfig.h"  // TODO: IDF-9197
+#include "soc/clkout_channel.h"
+#include "hal/assert.h"
 #include "hal/clk_tree_hal.h"
 #include "hal/clk_tree_ll.h"
-#include "hal/assert.h"
+#include "hal/gpio_ll.h"
 #include "hal/log.h"
 
 static const char *CLK_HAL_TAG = "clk_hal";
@@ -91,3 +92,13 @@ uint32_t clk_hal_xtal_get_freq_mhz(void)
     }
     return freq;
 }
+
+void clk_hal_clock_output_setup(soc_clkout_sig_id_t clk_sig, clock_out_channel_t channel_id)
+{
+    gpio_ll_set_pin_ctrl(clk_sig, CLKOUT_CHANNEL_MASK(channel_id), CLKOUT_CHANNEL_SHIFT(channel_id));
+}
+
+void clk_hal_clock_output_teardown(clock_out_channel_t channel_id)
+{
+    gpio_ll_set_pin_ctrl(0, CLKOUT_CHANNEL_MASK(channel_id), CLKOUT_CHANNEL_SHIFT(channel_id));
+}
diff --git a/components/hal/esp32c6/clk_tree_hal.c b/components/hal/esp32c6/clk_tree_hal.c
index 6ef025d025..432b75d7b3 100644
--- a/components/hal/esp32c6/clk_tree_hal.c
+++ b/components/hal/esp32c6/clk_tree_hal.c
@@ -4,9 +4,11 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include "soc/clkout_channel.h"
+#include "hal/assert.h"
 #include "hal/clk_tree_hal.h"
 #include "hal/clk_tree_ll.h"
-#include "hal/assert.h"
+#include "hal/gpio_ll.h"
 #include "hal/log.h"
 
 static const char *CLK_HAL_TAG = "clk_hal";
@@ -73,3 +75,13 @@ uint32_t clk_hal_xtal_get_freq_mhz(void)
     }
     return freq;
 }
+
+void clk_hal_clock_output_setup(soc_clkout_sig_id_t clk_sig, clock_out_channel_t channel_id)
+{
+    gpio_ll_set_pin_ctrl(clk_sig, CLKOUT_CHANNEL_MASK(channel_id), CLKOUT_CHANNEL_SHIFT(channel_id));
+}
+
+void clk_hal_clock_output_teardown(clock_out_channel_t channel_id)
+{
+    gpio_ll_set_pin_ctrl(0, CLKOUT_CHANNEL_MASK(channel_id), CLKOUT_CHANNEL_SHIFT(channel_id));
+}
diff --git a/components/hal/esp32h2/clk_tree_hal.c b/components/hal/esp32h2/clk_tree_hal.c
index 1c9281987c..006d63d261 100644
--- a/components/hal/esp32h2/clk_tree_hal.c
+++ b/components/hal/esp32h2/clk_tree_hal.c
@@ -4,9 +4,11 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include "soc/clkout_channel.h"
+#include "hal/assert.h"
 #include "hal/clk_tree_hal.h"
 #include "hal/clk_tree_ll.h"
-#include "hal/assert.h"
+#include "hal/gpio_ll.h"
 #include "hal/log.h"
 
 static const char *CLK_HAL_TAG = "clk_hal";
@@ -73,3 +75,13 @@ uint32_t clk_hal_xtal_get_freq_mhz(void)
     }
     return freq;
 }
+
+void clk_hal_clock_output_setup(soc_clkout_sig_id_t clk_sig, clock_out_channel_t channel_id)
+{
+    gpio_ll_set_pin_ctrl(clk_sig, CLKOUT_CHANNEL_MASK(channel_id), CLKOUT_CHANNEL_SHIFT(channel_id));
+}
+
+void clk_hal_clock_output_teardown(clock_out_channel_t channel_id)
+{
+    gpio_ll_set_pin_ctrl(0, CLKOUT_CHANNEL_MASK(channel_id), CLKOUT_CHANNEL_SHIFT(channel_id));
+}
diff --git a/components/hal/esp32p4/clk_tree_hal.c b/components/hal/esp32p4/clk_tree_hal.c
index a819e3c94b..b633752484 100644
--- a/components/hal/esp32p4/clk_tree_hal.c
+++ b/components/hal/esp32p4/clk_tree_hal.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -79,3 +79,20 @@ uint32_t clk_hal_xtal_get_freq_mhz(void)
     }
     return freq;
 }
+
+void clk_hal_clock_output_setup(soc_clkout_sig_id_t clk_sig, clock_out_channel_t channel_id)
+{
+    clk_ll_set_dbg_clk_ctrl(clk_sig, channel_id);
+    clk_ll_set_dbg_clk_channel_divider(channel_id, 1);
+    clk_ll_enable_dbg_clk_channel(channel_id, true);
+}
+
+void clk_hal_clock_output_set_divider(clock_out_channel_t channel_id, uint32_t div_num)
+{
+    clk_ll_set_dbg_clk_channel_divider(channel_id, div_num);
+}
+
+void clk_hal_clock_output_teardown(clock_out_channel_t channel_id)
+{
+    clk_ll_enable_dbg_clk_channel(channel_id, false);
+}
diff --git a/components/hal/esp32p4/include/hal/clk_tree_ll.h b/components/hal/esp32p4/include/hal/clk_tree_ll.h
index cc8675e3df..f504917fe7 100644
--- a/components/hal/esp32p4/include/hal/clk_tree_ll.h
+++ b/components/hal/esp32p4/include/hal/clk_tree_ll.h
@@ -7,6 +7,7 @@
 #pragma once
 
 #include <stdint.h>
+#include "soc/clkout_channel.h"
 #include "soc/soc.h"
 #include "soc/clk_tree_defs.h"
 #include "soc/hp_sys_clkrst_reg.h"
@@ -823,6 +824,53 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_rtc_slow_load_cal(v
     return REG_READ(RTC_SLOW_CLK_CAL_REG);
 }
 
+/**
+ * @brief Clock output channel configuration
+ * @param clk_sig    The clock signal source to be mapped to GPIOs
+ * @param channel_id The clock output channel to setup
+ */
+static inline __attribute__((always_inline)) void clk_ll_set_dbg_clk_ctrl(soc_clkout_sig_id_t clk_sig, clock_out_channel_t channel_id)
+{
+    if (channel_id == CLKOUT_CHANNEL_1) {
+        HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.dbg_clk_ctrl0, reg_dbg_ch0_sel, clk_sig);
+    } else if (channel_id == CLKOUT_CHANNEL_2) {
+        HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.dbg_clk_ctrl0, reg_dbg_ch1_sel, clk_sig);
+    } else {
+        abort();
+    }
+}
+
+/**
+ * @brief Enable the clock output channel
+ * @param  enable Enable or disable the clock output channel
+ */
+static inline __attribute__((always_inline)) void clk_ll_enable_dbg_clk_channel(clock_out_channel_t channel_id, bool enable)
+{
+    if (channel_id == CLKOUT_CHANNEL_1) {
+        HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.dbg_clk_ctrl1, reg_dbg_ch0_en, enable);
+    } else if (channel_id == CLKOUT_CHANNEL_2) {
+        HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.dbg_clk_ctrl1, reg_dbg_ch1_en, enable);
+    } else {
+        abort();
+    }
+}
+
+/**
+ * @brief Output the mapped clock after frequency division
+ * @param channel_id channel id that need to be configured with frequency division
+ * @param div_num  clock frequency division value
+ */
+static inline __attribute__((always_inline)) void clk_ll_set_dbg_clk_channel_divider(clock_out_channel_t channel_id, uint32_t div_num)
+{
+    if (channel_id == CLKOUT_CHANNEL_1) {
+        HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.dbg_clk_ctrl0, reg_dbg_ch0_div_num, div_num - 1);
+    } else if (channel_id == CLKOUT_CHANNEL_2) {
+        HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.dbg_clk_ctrl1, reg_dbg_ch1_div_num, div_num - 1);
+    } else {
+        abort();
+    }
+}
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/hal/esp32p4/include/hal/gpio_ll.h b/components/hal/esp32p4/include/hal/gpio_ll.h
index bc153f32b9..94a4df3918 100644
--- a/components/hal/esp32p4/include/hal/gpio_ll.h
+++ b/components/hal/esp32p4/include/hal/gpio_ll.h
@@ -124,7 +124,7 @@ static inline void gpio_ll_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num)
     // which should be checked is USB_INT_PHY0_DM_GPIO_NUM instead.
     // TODO: read the specific efuse with efuse_ll.h
 
-    // One more noticable point is P4 has two internal PHYs connecting to USJ and USB_WRAP(OTG1.1) seperately.
+    // One more noticeable point is P4 has two internal PHYs connecting to USJ and USB_WRAP(OTG1.1) separately.
     // We only consider the default connection here: PHY0 -> USJ, PHY1 -> USB_OTG
     if (gpio_num == USB_USJ_INT_PHY_DP_GPIO_NUM) {
         USB_SERIAL_JTAG.conf0.pad_pull_override = 1;
@@ -569,7 +569,7 @@ static inline void gpio_ll_iomux_in(gpio_dev_t *hw, uint32_t gpio, uint32_t sign
 static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func)
 {
     // Disable USB PHY configuration if pins (24, 25) (26, 27) needs to select an IOMUX function
-    // P4 has two internal PHYs connecting to USJ and USB_WRAP(OTG1.1) seperately.
+    // P4 has two internal PHYs connecting to USJ and USB_WRAP(OTG1.1) separately.
     // We only consider the default connection here: PHY0 -> USJ, PHY1 -> USB_OTG
     if (pin_name == IO_MUX_GPIO24_REG || pin_name == IO_MUX_GPIO25_REG) {
         USB_SERIAL_JTAG.conf0.usb_pad_enable = 0;
@@ -579,17 +579,6 @@ static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func)
     PIN_FUNC_SELECT(pin_name, func);
 }
 
-/**
- * @brief  Control the pin in the IOMUX
- *
- * @param  bmap   write mask of control value
- * @param  val    Control value
- * @param  shift  write mask shift of control value
- */
-static inline __attribute__((always_inline)) void gpio_ll_set_pin_ctrl(uint32_t val, uint32_t bmap, uint32_t shift)
-{
-    // TODO: IDF-8226
-}
 /**
  * @brief  Select a function for the pin in the IOMUX
  *
@@ -601,7 +590,7 @@ __attribute__((always_inline))
 static inline void gpio_ll_func_sel(gpio_dev_t *hw, uint8_t gpio_num, uint32_t func)
 {
     // Disable USB PHY configuration if pins (24, 25) (26, 27) needs to select an IOMUX function
-    // P4 has two internal PHYs connecting to USJ and USB_WRAP(OTG1.1) seperately.
+    // P4 has two internal PHYs connecting to USJ and USB_WRAP(OTG1.1) separately.
     // We only consider the default connection here: PHY0 -> USJ, PHY1 -> USB_OTG
     if (gpio_num == USB_USJ_INT_PHY_DM_GPIO_NUM || gpio_num == USB_USJ_INT_PHY_DP_GPIO_NUM) {
         USB_SERIAL_JTAG.conf0.usb_pad_enable = 0;
diff --git a/components/hal/esp32s2/clk_tree_hal.c b/components/hal/esp32s2/clk_tree_hal.c
index a301028c6c..b8deecb311 100644
--- a/components/hal/esp32s2/clk_tree_hal.c
+++ b/components/hal/esp32s2/clk_tree_hal.c
@@ -4,9 +4,11 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include "soc/clkout_channel.h"
+#include "hal/assert.h"
 #include "hal/clk_tree_hal.h"
 #include "hal/clk_tree_ll.h"
-#include "hal/assert.h"
+#include "hal/gpio_ll.h"
 #include "hal/log.h"
 
 static const char *CLK_HAL_TAG = "clk_hal";
@@ -111,3 +113,13 @@ uint32_t clk_hal_apll_get_freq_hz(void)
     uint32_t apll_freq_hz = (uint32_t)((xtal_freq_hz * numerator) / denominator);
     return apll_freq_hz;
 }
+
+void clk_hal_clock_output_setup(soc_clkout_sig_id_t clk_sig, clock_out_channel_t channel_id)
+{
+    gpio_ll_set_pin_ctrl(clk_sig, CLKOUT_CHANNEL_MASK(channel_id), CLKOUT_CHANNEL_SHIFT(channel_id));
+}
+
+void clk_hal_clock_output_teardown(clock_out_channel_t channel_id)
+{
+    gpio_ll_set_pin_ctrl(0, CLKOUT_CHANNEL_MASK(channel_id), CLKOUT_CHANNEL_SHIFT(channel_id));
+}
diff --git a/components/hal/esp32s3/clk_tree_hal.c b/components/hal/esp32s3/clk_tree_hal.c
index 7a79cbe2b8..f72f6f2dd7 100644
--- a/components/hal/esp32s3/clk_tree_hal.c
+++ b/components/hal/esp32s3/clk_tree_hal.c
@@ -4,9 +4,11 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include "soc/clkout_channel.h"
+#include "hal/assert.h"
 #include "hal/clk_tree_hal.h"
 #include "hal/clk_tree_ll.h"
-#include "hal/assert.h"
+#include "hal/gpio_ll.h"
 #include "hal/log.h"
 
 static const char *CLK_HAL_TAG = "clk_hal";
@@ -88,3 +90,13 @@ uint32_t clk_hal_xtal_get_freq_mhz(void)
     }
     return freq;
 }
+
+void clk_hal_clock_output_setup(soc_clkout_sig_id_t clk_sig, clock_out_channel_t channel_id)
+{
+    gpio_ll_set_pin_ctrl(clk_sig, CLKOUT_CHANNEL_MASK(channel_id), CLKOUT_CHANNEL_SHIFT(channel_id));
+}
+
+void clk_hal_clock_output_teardown(clock_out_channel_t channel_id)
+{
+    gpio_ll_set_pin_ctrl(0, CLKOUT_CHANNEL_MASK(channel_id), CLKOUT_CHANNEL_SHIFT(channel_id));
+}
diff --git a/components/hal/include/hal/clk_tree_hal.h b/components/hal/include/hal/clk_tree_hal.h
index 7a7d6ace9d..9e3cf888b6 100644
--- a/components/hal/include/hal/clk_tree_hal.h
+++ b/components/hal/include/hal/clk_tree_hal.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -8,6 +8,7 @@
 
 #include <stdint.h>
 #include "soc/clk_tree_defs.h"
+#include "soc/clkout_channel.h"
 #include "soc/soc_caps.h"
 
 #ifdef __cplusplus
@@ -60,6 +61,28 @@ uint32_t clk_hal_xtal_get_freq_mhz(void);
 uint32_t clk_hal_apll_get_freq_hz(void);
 #endif //SOC_CLK_APLL_SUPPORTED
 
+/**
+ * @brief Set up clock output channel
+ * @param clk_sig    The clock signal source to be mapped to GPIOs
+ * @param channel_id The clock output channel to setup
+ */
+void clk_hal_clock_output_setup(soc_clkout_sig_id_t clk_sig, clock_out_channel_t channel_id);
+
+#if SOC_CLOCKOUT_SUPPORT_CHANNEL_DIVIDER
+/**
+ * @brief Output the mapped clock after frequency division
+ * @param channel_id channel id that need to be configured with frequency division
+ * @param div_num  clock frequency division value
+ */
+void clk_hal_clock_output_set_divider(clock_out_channel_t channel_id, uint32_t div_num);
+#endif
+
+/**
+ * @brief Teardown clock output channel configuration
+ * @param channel_id The clock output channel to teardown
+ */
+void clk_hal_clock_output_teardown(clock_out_channel_t channel_id);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/soc/esp32/include/soc/Kconfig.soc_caps.in b/components/soc/esp32/include/soc/Kconfig.soc_caps.in
index 74c4785aa7..3723989bc7 100644
--- a/components/soc/esp32/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32/include/soc/Kconfig.soc_caps.in
@@ -351,6 +351,10 @@ config SOC_GPIO_CLOCKOUT_BY_IO_MUX
     bool
     default y
 
+config SOC_GPIO_CLOCKOUT_CHANNEL_NUM
+    int
+    default 3
+
 config SOC_I2C_NUM
     int
     default 2
diff --git a/components/soc/esp32/include/soc/clkout_channel.h b/components/soc/esp32/include/soc/clkout_channel.h
new file mode 100644
index 0000000000..b660ac1ac3
--- /dev/null
+++ b/components/soc/esp32/include/soc/clkout_channel.h
@@ -0,0 +1,52 @@
+/*
+ * SPDX-FileCopyrightText: 2010-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "esp_assert.h"
+#include "soc/soc_caps.h"
+#include "soc/io_mux_reg.h"
+#include "soc/gpio_sig_map.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum clock_out_channel {
+    CLKOUT_CHANNEL_1,
+    CLKOUT_CHANNEL_2,
+    CLKOUT_CHANNEL_3,
+    CLKOUT_CHANNEL_MAX,
+} clock_out_channel_t;
+
+#define CLKOUT_CHANNEL1_GPIO    GPIO_NUM_0
+#define CLKOUT_CHANNEL2_GPIO    GPIO_NUM_3
+#define CLKOUT_CHANNEL3_GPIO    GPIO_NUM_1
+#define FUNC_CLK_OUT1           FUNC_GPIO0_CLK_OUT1
+#define FUNC_CLK_OUT2           FUNC_U0RXD_CLK_OUT2
+#define FUNC_CLK_OUT3           FUNC_U0TXD_CLK_OUT3
+#define IONUM_TO_CLKOUT_CHANNEL(gpio_num)   ((gpio_num == CLKOUT_CHANNEL1_GPIO) ? CLKOUT_CHANNEL_1 : \
+                                             (gpio_num == CLKOUT_CHANNEL2_GPIO) ? CLKOUT_CHANNEL_2 : \
+                                             (gpio_num == CLKOUT_CHANNEL3_GPIO) ? CLKOUT_CHANNEL_3 : -1)
+#define CLKOUT_CHANNEL_TO_IOMUX_FUNC(channel)   ((channel == CLKOUT_CHANNEL_1) ? FUNC_CLK_OUT1 : \
+                                                 (channel == CLKOUT_CHANNEL_2) ? FUNC_CLK_OUT2 : \
+                                                 (channel == CLKOUT_CHANNEL_3) ? FUNC_CLK_OUT3 : -1)
+#define IS_VALID_CLKOUT_IO(gpio_num)    ((gpio_num == CLKOUT_CHANNEL1_GPIO) || (gpio_num == CLKOUT_CHANNEL2_GPIO) || (gpio_num == CLKOUT_CHANNEL3_GPIO))
+
+
+#define CLKOUT_CHANNEL_MASK(channel)    ((channel == CLKOUT_CHANNEL_1) ? CLK_OUT1 : \
+                                         (channel == CLKOUT_CHANNEL_2) ? CLK_OUT2 : \
+                                         (channel == CLKOUT_CHANNEL_3) ? CLK_OUT3 : 0)
+
+#define CLKOUT_CHANNEL_SHIFT(channel)   ((channel == CLKOUT_CHANNEL_1) ? CLK_OUT1_S : \
+                                         (channel == CLKOUT_CHANNEL_2) ? CLK_OUT2_S : \
+                                         (channel == CLKOUT_CHANNEL_3) ? CLK_OUT3_S : 0)
+
+ESP_STATIC_ASSERT(CLKOUT_CHANNEL_MAX == SOC_GPIO_CLOCKOUT_CHANNEL_NUM, "clock_out_channel enumeration mismatch");
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32/include/soc/soc_caps.h b/components/soc/esp32/include/soc/soc_caps.h
index 75f7c65f86..b1c18246f4 100644
--- a/components/soc/esp32/include/soc/soc_caps.h
+++ b/components/soc/esp32/include/soc/soc_caps.h
@@ -190,6 +190,7 @@
 
 // The Clock Out signal is binding to the pin's IO_MUX function
 #define SOC_GPIO_CLOCKOUT_BY_IO_MUX    (1)
+#define SOC_GPIO_CLOCKOUT_CHANNEL_NUM  (3)
 
 /*-------------------------- I2C CAPS ----------------------------------------*/
 // ESP32 has 2 I2C
diff --git a/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
index 8070cc1caa..285d91d292 100644
--- a/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
@@ -315,6 +315,10 @@ config SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX
     bool
     default y
 
+config SOC_GPIO_CLOCKOUT_CHANNEL_NUM
+    int
+    default 3
+
 config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
     int
     default 8
diff --git a/components/soc/esp32c2/include/soc/clkout_channel.h b/components/soc/esp32c2/include/soc/clkout_channel.h
new file mode 100644
index 0000000000..719893aee4
--- /dev/null
+++ b/components/soc/esp32c2/include/soc/clkout_channel.h
@@ -0,0 +1,42 @@
+/*
+ * SPDX-FileCopyrightText: 2010-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "esp_assert.h"
+#include "soc/soc_caps.h"
+#include "soc/io_mux_reg.h"
+#include "soc/gpio_sig_map.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum clock_out_channel {
+    CLKOUT_CHANNEL_1,
+    CLKOUT_CHANNEL_2,
+    CLKOUT_CHANNEL_3,
+    CLKOUT_CHANNEL_MAX,
+} clock_out_channel_t;
+
+#define CLKOUT_CHANNEL_TO_GPIO_SIG_ID(channel)  ((channel == CLKOUT_CHANNEL_1) ? CLK_OUT_OUT1_IDX : \
+                                                 (channel == CLKOUT_CHANNEL_2) ? CLK_OUT_OUT2_IDX : \
+                                                 (channel == CLKOUT_CHANNEL_3) ? CLK_OUT_OUT3_IDX : SIG_GPIO_OUT_IDX)
+
+
+#define CLKOUT_CHANNEL_MASK(channel)    ((channel == CLKOUT_CHANNEL_1) ? CLK_OUT1 : \
+                                         (channel == CLKOUT_CHANNEL_2) ? CLK_OUT2 : \
+                                         (channel == CLKOUT_CHANNEL_3) ? CLK_OUT3 : 0)
+
+#define CLKOUT_CHANNEL_SHIFT(channel)   ((channel == CLKOUT_CHANNEL_1) ? CLK_OUT1_S : \
+                                         (channel == CLKOUT_CHANNEL_2) ? CLK_OUT2_S : \
+                                         (channel == CLKOUT_CHANNEL_3) ? CLK_OUT3_S : 0)
+
+ESP_STATIC_ASSERT(CLKOUT_CHANNEL_MAX == SOC_GPIO_CLOCKOUT_CHANNEL_NUM, "clock_out_channel enumeration mismatch");
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c2/include/soc/soc_caps.h b/components/soc/esp32c2/include/soc/soc_caps.h
index fbc241ce76..46e90f108b 100644
--- a/components/soc/esp32c2/include/soc/soc_caps.h
+++ b/components/soc/esp32c2/include/soc/soc_caps.h
@@ -140,6 +140,7 @@
 
 // The Clock Out signal is route to the pin by GPIO matrix
 #define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX    (1)
+#define SOC_GPIO_CLOCKOUT_CHANNEL_NUM       (3)
 
 /*-------------------------- Dedicated GPIO CAPS -----------------------------*/
 #define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
diff --git a/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
index 114b541887..80a7732c89 100644
--- a/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
@@ -407,6 +407,10 @@ config SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX
     bool
     default y
 
+config SOC_GPIO_CLOCKOUT_CHANNEL_NUM
+    int
+    default 3
+
 config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
     int
     default 8
diff --git a/components/soc/esp32c3/include/soc/clkout_channel.h b/components/soc/esp32c3/include/soc/clkout_channel.h
new file mode 100644
index 0000000000..719893aee4
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/clkout_channel.h
@@ -0,0 +1,42 @@
+/*
+ * SPDX-FileCopyrightText: 2010-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "esp_assert.h"
+#include "soc/soc_caps.h"
+#include "soc/io_mux_reg.h"
+#include "soc/gpio_sig_map.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum clock_out_channel {
+    CLKOUT_CHANNEL_1,
+    CLKOUT_CHANNEL_2,
+    CLKOUT_CHANNEL_3,
+    CLKOUT_CHANNEL_MAX,
+} clock_out_channel_t;
+
+#define CLKOUT_CHANNEL_TO_GPIO_SIG_ID(channel)  ((channel == CLKOUT_CHANNEL_1) ? CLK_OUT_OUT1_IDX : \
+                                                 (channel == CLKOUT_CHANNEL_2) ? CLK_OUT_OUT2_IDX : \
+                                                 (channel == CLKOUT_CHANNEL_3) ? CLK_OUT_OUT3_IDX : SIG_GPIO_OUT_IDX)
+
+
+#define CLKOUT_CHANNEL_MASK(channel)    ((channel == CLKOUT_CHANNEL_1) ? CLK_OUT1 : \
+                                         (channel == CLKOUT_CHANNEL_2) ? CLK_OUT2 : \
+                                         (channel == CLKOUT_CHANNEL_3) ? CLK_OUT3 : 0)
+
+#define CLKOUT_CHANNEL_SHIFT(channel)   ((channel == CLKOUT_CHANNEL_1) ? CLK_OUT1_S : \
+                                         (channel == CLKOUT_CHANNEL_2) ? CLK_OUT2_S : \
+                                         (channel == CLKOUT_CHANNEL_3) ? CLK_OUT3_S : 0)
+
+ESP_STATIC_ASSERT(CLKOUT_CHANNEL_MAX == SOC_GPIO_CLOCKOUT_CHANNEL_NUM, "clock_out_channel enumeration mismatch");
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c3/include/soc/soc_caps.h b/components/soc/esp32c3/include/soc/soc_caps.h
index 721fa33383..de6c54a6ba 100644
--- a/components/soc/esp32c3/include/soc/soc_caps.h
+++ b/components/soc/esp32c3/include/soc/soc_caps.h
@@ -178,6 +178,7 @@
 
 // The Clock Out signal is route to the pin by GPIO matrix
 #define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX    (1)
+#define SOC_GPIO_CLOCKOUT_CHANNEL_NUM       (3)
 
 /*-------------------------- Dedicated GPIO CAPS -----------------------------*/
 #define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
diff --git a/components/soc/esp32c5/beta3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/beta3/include/soc/Kconfig.soc_caps.in
index 83d68c6dae..ec09df500b 100644
--- a/components/soc/esp32c5/beta3/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c5/beta3/include/soc/Kconfig.soc_caps.in
@@ -287,6 +287,10 @@ config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
     bool
     default y
 
+config SOC_GPIO_CLOCKOUT_CHANNEL_NUM
+    int
+    default 3
+
 config SOC_RTCIO_PIN_COUNT
     int
     default 0
diff --git a/components/soc/esp32c5/beta3/include/soc/clkout_channel.h b/components/soc/esp32c5/beta3/include/soc/clkout_channel.h
new file mode 100644
index 0000000000..719893aee4
--- /dev/null
+++ b/components/soc/esp32c5/beta3/include/soc/clkout_channel.h
@@ -0,0 +1,42 @@
+/*
+ * SPDX-FileCopyrightText: 2010-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "esp_assert.h"
+#include "soc/soc_caps.h"
+#include "soc/io_mux_reg.h"
+#include "soc/gpio_sig_map.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum clock_out_channel {
+    CLKOUT_CHANNEL_1,
+    CLKOUT_CHANNEL_2,
+    CLKOUT_CHANNEL_3,
+    CLKOUT_CHANNEL_MAX,
+} clock_out_channel_t;
+
+#define CLKOUT_CHANNEL_TO_GPIO_SIG_ID(channel)  ((channel == CLKOUT_CHANNEL_1) ? CLK_OUT_OUT1_IDX : \
+                                                 (channel == CLKOUT_CHANNEL_2) ? CLK_OUT_OUT2_IDX : \
+                                                 (channel == CLKOUT_CHANNEL_3) ? CLK_OUT_OUT3_IDX : SIG_GPIO_OUT_IDX)
+
+
+#define CLKOUT_CHANNEL_MASK(channel)    ((channel == CLKOUT_CHANNEL_1) ? CLK_OUT1 : \
+                                         (channel == CLKOUT_CHANNEL_2) ? CLK_OUT2 : \
+                                         (channel == CLKOUT_CHANNEL_3) ? CLK_OUT3 : 0)
+
+#define CLKOUT_CHANNEL_SHIFT(channel)   ((channel == CLKOUT_CHANNEL_1) ? CLK_OUT1_S : \
+                                         (channel == CLKOUT_CHANNEL_2) ? CLK_OUT2_S : \
+                                         (channel == CLKOUT_CHANNEL_3) ? CLK_OUT3_S : 0)
+
+ESP_STATIC_ASSERT(CLKOUT_CHANNEL_MAX == SOC_GPIO_CLOCKOUT_CHANNEL_NUM, "clock_out_channel enumeration mismatch");
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c5/beta3/include/soc/soc_caps.h b/components/soc/esp32c5/beta3/include/soc/soc_caps.h
index 0f5f9f6613..74df08b4f3 100644
--- a/components/soc/esp32c5/beta3/include/soc/soc_caps.h
+++ b/components/soc/esp32c5/beta3/include/soc/soc_caps.h
@@ -220,6 +220,7 @@
 
 // The Clock Out signal is route to the pin by GPIO matrix
 // #define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX    (1)
+#define SOC_GPIO_CLOCKOUT_CHANNEL_NUM           (3)
 
 /*-------------------------- RTCIO CAPS --------------------------------------*/
 #define SOC_RTCIO_PIN_COUNT                 0UL
diff --git a/components/soc/esp32c5/mp/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/mp/include/soc/Kconfig.soc_caps.in
index 036953edfa..347785282f 100644
--- a/components/soc/esp32c5/mp/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c5/mp/include/soc/Kconfig.soc_caps.in
@@ -127,6 +127,10 @@ config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
     bool
     default y
 
+config SOC_GPIO_CLOCKOUT_CHANNEL_NUM
+    int
+    default 3
+
 config SOC_RTCIO_PIN_COUNT
     int
     default 0
diff --git a/components/soc/esp32c5/mp/include/soc/clkout_channel.h b/components/soc/esp32c5/mp/include/soc/clkout_channel.h
new file mode 100644
index 0000000000..719893aee4
--- /dev/null
+++ b/components/soc/esp32c5/mp/include/soc/clkout_channel.h
@@ -0,0 +1,42 @@
+/*
+ * SPDX-FileCopyrightText: 2010-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "esp_assert.h"
+#include "soc/soc_caps.h"
+#include "soc/io_mux_reg.h"
+#include "soc/gpio_sig_map.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum clock_out_channel {
+    CLKOUT_CHANNEL_1,
+    CLKOUT_CHANNEL_2,
+    CLKOUT_CHANNEL_3,
+    CLKOUT_CHANNEL_MAX,
+} clock_out_channel_t;
+
+#define CLKOUT_CHANNEL_TO_GPIO_SIG_ID(channel)  ((channel == CLKOUT_CHANNEL_1) ? CLK_OUT_OUT1_IDX : \
+                                                 (channel == CLKOUT_CHANNEL_2) ? CLK_OUT_OUT2_IDX : \
+                                                 (channel == CLKOUT_CHANNEL_3) ? CLK_OUT_OUT3_IDX : SIG_GPIO_OUT_IDX)
+
+
+#define CLKOUT_CHANNEL_MASK(channel)    ((channel == CLKOUT_CHANNEL_1) ? CLK_OUT1 : \
+                                         (channel == CLKOUT_CHANNEL_2) ? CLK_OUT2 : \
+                                         (channel == CLKOUT_CHANNEL_3) ? CLK_OUT3 : 0)
+
+#define CLKOUT_CHANNEL_SHIFT(channel)   ((channel == CLKOUT_CHANNEL_1) ? CLK_OUT1_S : \
+                                         (channel == CLKOUT_CHANNEL_2) ? CLK_OUT2_S : \
+                                         (channel == CLKOUT_CHANNEL_3) ? CLK_OUT3_S : 0)
+
+ESP_STATIC_ASSERT(CLKOUT_CHANNEL_MAX == SOC_GPIO_CLOCKOUT_CHANNEL_NUM, "clock_out_channel enumeration mismatch");
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c5/mp/include/soc/soc_caps.h b/components/soc/esp32c5/mp/include/soc/soc_caps.h
index 74d6743bf5..e63311e1e9 100644
--- a/components/soc/esp32c5/mp/include/soc/soc_caps.h
+++ b/components/soc/esp32c5/mp/include/soc/soc_caps.h
@@ -210,6 +210,7 @@
 
 // The Clock Out signal is route to the pin by GPIO matrix
 // #define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX    (1)
+#define SOC_GPIO_CLOCKOUT_CHANNEL_NUM           (3)
 
 /*-------------------------- RTCIO CAPS --------------------------------------*/
 #define SOC_RTCIO_PIN_COUNT                 0UL
diff --git a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
index 3c1dd57518..986ac496d5 100644
--- a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
@@ -523,6 +523,10 @@ config SOC_CLOCKOUT_HAS_SOURCE_GATE
     bool
     default y
 
+config SOC_GPIO_CLOCKOUT_CHANNEL_NUM
+    int
+    default 3
+
 config SOC_RTCIO_PIN_COUNT
     int
     default 8
diff --git a/components/soc/esp32c6/include/soc/clkout_channel.h b/components/soc/esp32c6/include/soc/clkout_channel.h
new file mode 100644
index 0000000000..719893aee4
--- /dev/null
+++ b/components/soc/esp32c6/include/soc/clkout_channel.h
@@ -0,0 +1,42 @@
+/*
+ * SPDX-FileCopyrightText: 2010-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "esp_assert.h"
+#include "soc/soc_caps.h"
+#include "soc/io_mux_reg.h"
+#include "soc/gpio_sig_map.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum clock_out_channel {
+    CLKOUT_CHANNEL_1,
+    CLKOUT_CHANNEL_2,
+    CLKOUT_CHANNEL_3,
+    CLKOUT_CHANNEL_MAX,
+} clock_out_channel_t;
+
+#define CLKOUT_CHANNEL_TO_GPIO_SIG_ID(channel)  ((channel == CLKOUT_CHANNEL_1) ? CLK_OUT_OUT1_IDX : \
+                                                 (channel == CLKOUT_CHANNEL_2) ? CLK_OUT_OUT2_IDX : \
+                                                 (channel == CLKOUT_CHANNEL_3) ? CLK_OUT_OUT3_IDX : SIG_GPIO_OUT_IDX)
+
+
+#define CLKOUT_CHANNEL_MASK(channel)    ((channel == CLKOUT_CHANNEL_1) ? CLK_OUT1 : \
+                                         (channel == CLKOUT_CHANNEL_2) ? CLK_OUT2 : \
+                                         (channel == CLKOUT_CHANNEL_3) ? CLK_OUT3 : 0)
+
+#define CLKOUT_CHANNEL_SHIFT(channel)   ((channel == CLKOUT_CHANNEL_1) ? CLK_OUT1_S : \
+                                         (channel == CLKOUT_CHANNEL_2) ? CLK_OUT2_S : \
+                                         (channel == CLKOUT_CHANNEL_3) ? CLK_OUT3_S : 0)
+
+ESP_STATIC_ASSERT(CLKOUT_CHANNEL_MAX == SOC_GPIO_CLOCKOUT_CHANNEL_NUM, "clock_out_channel enumeration mismatch");
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c6/include/soc/soc_caps.h b/components/soc/esp32c6/include/soc/soc_caps.h
index 1d5380c8ff..07deaadfa0 100644
--- a/components/soc/esp32c6/include/soc/soc_caps.h
+++ b/components/soc/esp32c6/include/soc/soc_caps.h
@@ -215,7 +215,8 @@
 
 // The Clock Out signal is route to the pin by GPIO matrix
 #define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX    (1)
-#define SOC_CLOCKOUT_HAS_SOURCE_GATE         (1)
+#define SOC_CLOCKOUT_HAS_SOURCE_GATE        (1)
+#define SOC_GPIO_CLOCKOUT_CHANNEL_NUM       (3)
 
 /*-------------------------- RTCIO CAPS --------------------------------------*/
 #define SOC_RTCIO_PIN_COUNT                 8
diff --git a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
index 6b87a8e502..214bf3ec8d 100644
--- a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
@@ -199,9 +199,9 @@ config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
     bool
     default y
 
-config SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX
-    bool
-    default y
+config SOC_GPIO_CLOCKOUT_CHANNEL_NUM
+    int
+    default 3
 
 config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
     int
diff --git a/components/soc/esp32c61/include/soc/clkout_channel.h b/components/soc/esp32c61/include/soc/clkout_channel.h
new file mode 100644
index 0000000000..719893aee4
--- /dev/null
+++ b/components/soc/esp32c61/include/soc/clkout_channel.h
@@ -0,0 +1,42 @@
+/*
+ * SPDX-FileCopyrightText: 2010-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "esp_assert.h"
+#include "soc/soc_caps.h"
+#include "soc/io_mux_reg.h"
+#include "soc/gpio_sig_map.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum clock_out_channel {
+    CLKOUT_CHANNEL_1,
+    CLKOUT_CHANNEL_2,
+    CLKOUT_CHANNEL_3,
+    CLKOUT_CHANNEL_MAX,
+} clock_out_channel_t;
+
+#define CLKOUT_CHANNEL_TO_GPIO_SIG_ID(channel)  ((channel == CLKOUT_CHANNEL_1) ? CLK_OUT_OUT1_IDX : \
+                                                 (channel == CLKOUT_CHANNEL_2) ? CLK_OUT_OUT2_IDX : \
+                                                 (channel == CLKOUT_CHANNEL_3) ? CLK_OUT_OUT3_IDX : SIG_GPIO_OUT_IDX)
+
+
+#define CLKOUT_CHANNEL_MASK(channel)    ((channel == CLKOUT_CHANNEL_1) ? CLK_OUT1 : \
+                                         (channel == CLKOUT_CHANNEL_2) ? CLK_OUT2 : \
+                                         (channel == CLKOUT_CHANNEL_3) ? CLK_OUT3 : 0)
+
+#define CLKOUT_CHANNEL_SHIFT(channel)   ((channel == CLKOUT_CHANNEL_1) ? CLK_OUT1_S : \
+                                         (channel == CLKOUT_CHANNEL_2) ? CLK_OUT2_S : \
+                                         (channel == CLKOUT_CHANNEL_3) ? CLK_OUT3_S : 0)
+
+ESP_STATIC_ASSERT(CLKOUT_CHANNEL_MAX == SOC_GPIO_CLOCKOUT_CHANNEL_NUM, "clock_out_channel enumeration mismatch");
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c61/include/soc/soc_caps.h b/components/soc/esp32c61/include/soc/soc_caps.h
index c122828598..12b054b07d 100644
--- a/components/soc/esp32c61/include/soc/soc_caps.h
+++ b/components/soc/esp32c61/include/soc/soc_caps.h
@@ -213,7 +213,8 @@
 #define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP  (1)
 
 // The Clock Out signal is route to the pin by GPIO matrix
-#define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX    (1)
+// #define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX    (1)
+#define SOC_GPIO_CLOCKOUT_CHANNEL_NUM           (3)
 
 /*-------------------------- RTCIO CAPS --------------------------------------*/
 //TODO: [ESP32C61] IDF-9317
diff --git a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
index ffccb5477e..d9eec8f6fd 100644
--- a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
@@ -523,6 +523,10 @@ config SOC_CLOCKOUT_HAS_SOURCE_GATE
     bool
     default y
 
+config SOC_GPIO_CLOCKOUT_CHANNEL_NUM
+    int
+    default 3
+
 config SOC_RTCIO_PIN_COUNT
     int
     default 8
diff --git a/components/soc/esp32h2/include/soc/clkout_channel.h b/components/soc/esp32h2/include/soc/clkout_channel.h
new file mode 100644
index 0000000000..719893aee4
--- /dev/null
+++ b/components/soc/esp32h2/include/soc/clkout_channel.h
@@ -0,0 +1,42 @@
+/*
+ * SPDX-FileCopyrightText: 2010-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "esp_assert.h"
+#include "soc/soc_caps.h"
+#include "soc/io_mux_reg.h"
+#include "soc/gpio_sig_map.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum clock_out_channel {
+    CLKOUT_CHANNEL_1,
+    CLKOUT_CHANNEL_2,
+    CLKOUT_CHANNEL_3,
+    CLKOUT_CHANNEL_MAX,
+} clock_out_channel_t;
+
+#define CLKOUT_CHANNEL_TO_GPIO_SIG_ID(channel)  ((channel == CLKOUT_CHANNEL_1) ? CLK_OUT_OUT1_IDX : \
+                                                 (channel == CLKOUT_CHANNEL_2) ? CLK_OUT_OUT2_IDX : \
+                                                 (channel == CLKOUT_CHANNEL_3) ? CLK_OUT_OUT3_IDX : SIG_GPIO_OUT_IDX)
+
+
+#define CLKOUT_CHANNEL_MASK(channel)    ((channel == CLKOUT_CHANNEL_1) ? CLK_OUT1 : \
+                                         (channel == CLKOUT_CHANNEL_2) ? CLK_OUT2 : \
+                                         (channel == CLKOUT_CHANNEL_3) ? CLK_OUT3 : 0)
+
+#define CLKOUT_CHANNEL_SHIFT(channel)   ((channel == CLKOUT_CHANNEL_1) ? CLK_OUT1_S : \
+                                         (channel == CLKOUT_CHANNEL_2) ? CLK_OUT2_S : \
+                                         (channel == CLKOUT_CHANNEL_3) ? CLK_OUT3_S : 0)
+
+ESP_STATIC_ASSERT(CLKOUT_CHANNEL_MAX == SOC_GPIO_CLOCKOUT_CHANNEL_NUM, "clock_out_channel enumeration mismatch");
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32h2/include/soc/soc_caps.h b/components/soc/esp32h2/include/soc/soc_caps.h
index 7940868d6c..051657fa7b 100644
--- a/components/soc/esp32h2/include/soc/soc_caps.h
+++ b/components/soc/esp32h2/include/soc/soc_caps.h
@@ -216,7 +216,8 @@
 
 // The Clock Out signal is route to the pin by GPIO matrix
 #define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX    (1)
-#define SOC_CLOCKOUT_HAS_SOURCE_GATE         (1)
+#define SOC_CLOCKOUT_HAS_SOURCE_GATE        (1)
+#define SOC_GPIO_CLOCKOUT_CHANNEL_NUM       (3)
 
 /*-------------------------- RTCIO CAPS --------------------------------------*/
 /* No dedicated LP_IOMUX subsystem on ESP32-H2. LP functions are still supported
diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
index 26b48d5dae..1d24950af7 100644
--- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
@@ -555,6 +555,18 @@ config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
     hex
     default 0x007FFFFFFFFF0000
 
+config SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX
+    bool
+    default y
+
+config SOC_GPIO_CLOCKOUT_CHANNEL_NUM
+    int
+    default 2
+
+config SOC_CLOCKOUT_SUPPORT_CHANNEL_DIVIDER
+    bool
+    default y
+
 config SOC_GPIO_SUPPORT_FORCE_HOLD
     bool
     default y
diff --git a/components/soc/esp32p4/include/soc/clk_tree_defs.h b/components/soc/esp32p4/include/soc/clk_tree_defs.h
index 374efc01cc..5626e7f2b0 100644
--- a/components/soc/esp32p4/include/soc/clk_tree_defs.h
+++ b/components/soc/esp32p4/include/soc/clk_tree_defs.h
@@ -672,6 +672,27 @@ typedef enum {
     TEMPERATURE_SENSOR_CLK_SRC_DEFAULT = SOC_MOD_CLK_LP_PERI,    /*!< Select LP_PERI as the default choice */
 } soc_periph_temperature_sensor_clk_src_t;
 
+//////////////////////////////////////////////CLOCK OUTPUT///////////////////////////////////////////////////////////
+typedef enum {
+    CLKOUT_SIG_MPLL     = 0,    /*!< MPLL is from 40MHz XTAL oscillator frequency multipliers */
+    CLKOUT_SIG_SPLL     = 1,    /*!< SPLL is from 40MHz XTAL oscillator frequency multipliers, it has a "fixed" frequency of 480MHz */
+    CLKOUT_SIG_CPLL     = 2,    /*!< CPLL_CLK is the output of 40MHz crystal oscillator frequency multiplier, can be 320/360/400MHz */
+    CLKOUT_SIG_XTAL     = 3,    /*!< External 40MHz crystal */
+    CLKOUT_SIG_RC_FAST  = 4,    /*!< Internal 17.5MHz RC oscillator */
+    CLKOUT_SIG_RC_SLOW  = 5,    /*!< Internal 136kHz RC oscillator */
+    CLKOUT_SIG_RC_32K   = 6,    /*!< Internal 32kHz RC oscillator */
+    CLKOUT_SIG_XTAL32K  = 7,    /*!< External 32kHz crystal clock */
+    CLKOUT_SIG_I2S0     = 16,   /*!< I2S0 clock, depends on the i2s driver configuration */
+    CLKOUT_SIG_I2S1     = 17,   /*!< I2S1 clock, depends on the i2s driver configuration */
+    CLKOUT_SIG_I2S2     = 18,   /*!< I2S2 clock, depends on the i2s driver configuration */
+    CLKOUT_SIG_CPU      = 26,   /*!< CPU clock */
+    CLKOUT_SIG_MEM      = 27,   /*!< MEM clock */
+    CLKOUT_SIG_SYS      = 28,   /*!< SYS clock */
+    CLKOUT_SIG_APB      = 29,   /*!< APB clock */
+    CLKOUT_SIG_PLL_F80M = 105,  /*!< From PLL, usually be 80MHz */
+    CLKOUT_SIG_INVALID  = 0xFF,
+} soc_clkout_sig_id_t;
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/soc/esp32p4/include/soc/clkout_channel.h b/components/soc/esp32p4/include/soc/clkout_channel.h
new file mode 100644
index 0000000000..2099d5a582
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/clkout_channel.h
@@ -0,0 +1,32 @@
+/*
+ * SPDX-FileCopyrightText: 2010-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "esp_assert.h"
+#include "soc/soc_caps.h"
+#include "soc/io_mux_reg.h"
+#include "soc/gpio_sig_map.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum clock_out_channel {
+    CLKOUT_CHANNEL_1,
+    CLKOUT_CHANNEL_2,
+    CLKOUT_CHANNEL_MAX,
+} clock_out_channel_t;
+
+
+#define CLKOUT_CHANNEL_TO_GPIO_SIG_ID(channel)  ((channel == CLKOUT_CHANNEL_1) ? DBG_CH0_CLK_IDX : \
+                                                 (channel == CLKOUT_CHANNEL_2) ? DBG_CH1_CLK_IDX : SIG_GPIO_OUT_IDX)
+
+ESP_STATIC_ASSERT(CLKOUT_CHANNEL_MAX == SOC_GPIO_CLOCKOUT_CHANNEL_NUM, "clock_out_channel enumeration mismatch");
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/hp_sys_clkrst_reg.h b/components/soc/esp32p4/include/soc/hp_sys_clkrst_reg.h
index 8a7ad9c6af..500b59e2c2 100644
--- a/components/soc/esp32p4/include/soc/hp_sys_clkrst_reg.h
+++ b/components/soc/esp32p4/include/soc/hp_sys_clkrst_reg.h
@@ -1,5 +1,5 @@
 /**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
  *
  *  SPDX-License-Identifier: Apache-2.0
  */
@@ -4248,13 +4248,6 @@ extern "C" {
 #define HP_SYS_CLKRST_REG_DBG_CH1_SEL_M  (HP_SYS_CLKRST_REG_DBG_CH1_SEL_V << HP_SYS_CLKRST_REG_DBG_CH1_SEL_S)
 #define HP_SYS_CLKRST_REG_DBG_CH1_SEL_V  0x000000FFU
 #define HP_SYS_CLKRST_REG_DBG_CH1_SEL_S  8
-/** HP_SYS_CLKRST_REG_DBG_CH2_SEL : R/W; bitpos: [23:16]; default: 255;
- *  Reserved
- */
-#define HP_SYS_CLKRST_REG_DBG_CH2_SEL    0x000000FFU
-#define HP_SYS_CLKRST_REG_DBG_CH2_SEL_M  (HP_SYS_CLKRST_REG_DBG_CH2_SEL_V << HP_SYS_CLKRST_REG_DBG_CH2_SEL_S)
-#define HP_SYS_CLKRST_REG_DBG_CH2_SEL_V  0x000000FFU
-#define HP_SYS_CLKRST_REG_DBG_CH2_SEL_S  16
 /** HP_SYS_CLKRST_REG_DBG_CH0_DIV_NUM : R/W; bitpos: [31:24]; default: 3;
  *  Reserved
  */
@@ -4274,13 +4267,6 @@ extern "C" {
 #define HP_SYS_CLKRST_REG_DBG_CH1_DIV_NUM_M  (HP_SYS_CLKRST_REG_DBG_CH1_DIV_NUM_V << HP_SYS_CLKRST_REG_DBG_CH1_DIV_NUM_S)
 #define HP_SYS_CLKRST_REG_DBG_CH1_DIV_NUM_V  0x000000FFU
 #define HP_SYS_CLKRST_REG_DBG_CH1_DIV_NUM_S  0
-/** HP_SYS_CLKRST_REG_DBG_CH2_DIV_NUM : R/W; bitpos: [15:8]; default: 3;
- *  Reserved
- */
-#define HP_SYS_CLKRST_REG_DBG_CH2_DIV_NUM    0x000000FFU
-#define HP_SYS_CLKRST_REG_DBG_CH2_DIV_NUM_M  (HP_SYS_CLKRST_REG_DBG_CH2_DIV_NUM_V << HP_SYS_CLKRST_REG_DBG_CH2_DIV_NUM_S)
-#define HP_SYS_CLKRST_REG_DBG_CH2_DIV_NUM_V  0x000000FFU
-#define HP_SYS_CLKRST_REG_DBG_CH2_DIV_NUM_S  8
 /** HP_SYS_CLKRST_REG_DBG_CH0_EN : R/W; bitpos: [16]; default: 0;
  *  Reserved
  */
@@ -4295,13 +4281,6 @@ extern "C" {
 #define HP_SYS_CLKRST_REG_DBG_CH1_EN_M  (HP_SYS_CLKRST_REG_DBG_CH1_EN_V << HP_SYS_CLKRST_REG_DBG_CH1_EN_S)
 #define HP_SYS_CLKRST_REG_DBG_CH1_EN_V  0x00000001U
 #define HP_SYS_CLKRST_REG_DBG_CH1_EN_S  17
-/** HP_SYS_CLKRST_REG_DBG_CH2_EN : R/W; bitpos: [18]; default: 0;
- *  Reserved
- */
-#define HP_SYS_CLKRST_REG_DBG_CH2_EN    (BIT(18))
-#define HP_SYS_CLKRST_REG_DBG_CH2_EN_M  (HP_SYS_CLKRST_REG_DBG_CH2_EN_V << HP_SYS_CLKRST_REG_DBG_CH2_EN_S)
-#define HP_SYS_CLKRST_REG_DBG_CH2_EN_V  0x00000001U
-#define HP_SYS_CLKRST_REG_DBG_CH2_EN_S  18
 
 /** HP_SYS_CLKRST_HPCORE_WDT_RESET_SOURCE0_REG register
  *  Reserved
diff --git a/components/soc/esp32p4/include/soc/hp_sys_clkrst_struct.h b/components/soc/esp32p4/include/soc/hp_sys_clkrst_struct.h
index 2837628cd6..822ad73ecc 100644
--- a/components/soc/esp32p4/include/soc/hp_sys_clkrst_struct.h
+++ b/components/soc/esp32p4/include/soc/hp_sys_clkrst_struct.h
@@ -1,5 +1,5 @@
 /**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
  *
  *  SPDX-License-Identifier: Apache-2.0
  */
@@ -2859,10 +2859,7 @@ typedef union {
          *  Reserved
          */
         uint32_t reg_dbg_ch1_sel:8;
-        /** reg_dbg_ch2_sel : R/W; bitpos: [23:16]; default: 255;
-         *  Reserved
-         */
-        uint32_t reg_dbg_ch2_sel:8;
+        uint32_t reserved_16:8;
         /** reg_dbg_ch0_div_num : R/W; bitpos: [31:24]; default: 3;
          *  Reserved
          */
@@ -2880,10 +2877,7 @@ typedef union {
          *  Reserved
          */
         uint32_t reg_dbg_ch1_div_num:8;
-        /** reg_dbg_ch2_div_num : R/W; bitpos: [15:8]; default: 3;
-         *  Reserved
-         */
-        uint32_t reg_dbg_ch2_div_num:8;
+        uint32_t reserved_8:8;
         /** reg_dbg_ch0_en : R/W; bitpos: [16]; default: 0;
          *  Reserved
          */
@@ -2892,11 +2886,7 @@ typedef union {
          *  Reserved
          */
         uint32_t reg_dbg_ch1_en:1;
-        /** reg_dbg_ch2_en : R/W; bitpos: [18]; default: 0;
-         *  Reserved
-         */
-        uint32_t reg_dbg_ch2_en:1;
-        uint32_t reserved_19:13;
+        uint32_t reserved_18:14;
     };
     uint32_t val;
 } hp_sys_clkrst_dbg_clk_ctrl1_reg_t;
diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h
index 61ca9e53c5..c0606c49d8 100644
--- a/components/soc/esp32p4/include/soc/soc_caps.h
+++ b/components/soc/esp32p4/include/soc/soc_caps.h
@@ -231,6 +231,11 @@
 // digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_16~GPIO_NUM_54)
 #define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x007FFFFFFFFF0000ULL
 
+// The Clock Out signal is route to the pin by GPIO matrix
+#define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX         (1)
+#define SOC_GPIO_CLOCKOUT_CHANNEL_NUM            (2)
+#define SOC_CLOCKOUT_SUPPORT_CHANNEL_DIVIDER     (1)
+
 // Support to force hold all IOs
 #define SOC_GPIO_SUPPORT_FORCE_HOLD              (1)
 // Support to hold a single digital I/O when the digital domain is powered off
diff --git a/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in
index 17f43581b2..dc17829d64 100644
--- a/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in
@@ -399,6 +399,10 @@ config SOC_GPIO_CLOCKOUT_BY_IO_MUX
     bool
     default y
 
+config SOC_GPIO_CLOCKOUT_CHANNEL_NUM
+    int
+    default 3
+
 config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
     int
     default 8
diff --git a/components/esp_hw_support/clkout_channel.h b/components/soc/esp32s2/include/soc/clkout_channel.h
similarity index 66%
rename from components/esp_hw_support/clkout_channel.h
rename to components/soc/esp32s2/include/soc/clkout_channel.h
index 57169f0cc2..1c5ef2a2ee 100644
--- a/components/esp_hw_support/clkout_channel.h
+++ b/components/soc/esp32s2/include/soc/clkout_channel.h
@@ -6,8 +6,10 @@
 
 #pragma once
 
-#include "sdkconfig.h"
+#include "esp_assert.h"
 #include "soc/soc_caps.h"
+#include "soc/io_mux_reg.h"
+#include "soc/gpio_sig_map.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -20,35 +22,20 @@ typedef enum clock_out_channel {
     CLKOUT_CHANNEL_MAX,
 } clock_out_channel_t;
 
-#if SOC_GPIO_CLOCKOUT_BY_IO_MUX
-#if CONFIG_IDF_TARGET_ESP32
-#define CLKOUT_CHANNEL1_GPIO    GPIO_NUM_0
-#define CLKOUT_CHANNEL2_GPIO    GPIO_NUM_3
-#define CLKOUT_CHANNEL3_GPIO    GPIO_NUM_1
-#define FUNC_CLK_OUT1           FUNC_GPIO0_CLK_OUT1
-#define FUNC_CLK_OUT2           FUNC_U0RXD_CLK_OUT2
-#define FUNC_CLK_OUT3           FUNC_U0TXD_CLK_OUT3
-#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
 #define CLKOUT_CHANNEL1_GPIO    GPIO_NUM_20
 #define CLKOUT_CHANNEL2_GPIO    GPIO_NUM_19
 #define CLKOUT_CHANNEL3_GPIO    GPIO_NUM_18
 #define FUNC_CLK_OUT1           FUNC_GPIO20_CLK_OUT1
 #define FUNC_CLK_OUT2           FUNC_GPIO19_CLK_OUT2
 #define FUNC_CLK_OUT3           FUNC_DAC_2_CLK_OUT3
-#endif
+
 #define IONUM_TO_CLKOUT_CHANNEL(gpio_num)   ((gpio_num == CLKOUT_CHANNEL1_GPIO) ? CLKOUT_CHANNEL_1 : \
                                              (gpio_num == CLKOUT_CHANNEL2_GPIO) ? CLKOUT_CHANNEL_2 : \
-                                             (gpio_num == CLKOUT_CHANNEL3_GPIO) ? CLKOUT_CHANNEL_3 : 0)
+                                             (gpio_num == CLKOUT_CHANNEL3_GPIO) ? CLKOUT_CHANNEL_3 : -1)
 #define CLKOUT_CHANNEL_TO_IOMUX_FUNC(channel)   ((channel == CLKOUT_CHANNEL_1) ? FUNC_CLK_OUT1 : \
                                                  (channel == CLKOUT_CHANNEL_2) ? FUNC_CLK_OUT2 : \
-                                                 (channel == CLKOUT_CHANNEL_3) ? FUNC_CLK_OUT3 : 0)
+                                                 (channel == CLKOUT_CHANNEL_3) ? FUNC_CLK_OUT3 : -1)
 #define IS_VALID_CLKOUT_IO(gpio_num)    ((gpio_num == CLKOUT_CHANNEL1_GPIO) || (gpio_num == CLKOUT_CHANNEL2_GPIO) || (gpio_num == CLKOUT_CHANNEL3_GPIO))
-#elif SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX
-#define CLKOUT_CHANNEL_TO_GPIO_SIG_ID(channel)  ((channel == CLKOUT_CHANNEL_1) ? CLK_OUT_OUT1_IDX : \
-                                                 (channel == CLKOUT_CHANNEL_2) ? CLK_OUT_OUT2_IDX : \
-                                                 (channel == CLKOUT_CHANNEL_3) ? CLK_OUT_OUT3_IDX : SIG_GPIO_OUT_IDX)
-#define IS_VALID_CLKOUT_IO(gpio_num)    GPIO_IS_VALID_GPIO(gpio_num)
-#endif
 
 #define CLKOUT_CHANNEL_MASK(channel)    ((channel == CLKOUT_CHANNEL_1) ? CLK_OUT1 : \
                                          (channel == CLKOUT_CHANNEL_2) ? CLK_OUT2 : \
@@ -58,6 +45,8 @@ typedef enum clock_out_channel {
                                          (channel == CLKOUT_CHANNEL_2) ? CLK_OUT2_S : \
                                          (channel == CLKOUT_CHANNEL_3) ? CLK_OUT3_S : 0)
 
+ESP_STATIC_ASSERT(CLKOUT_CHANNEL_MAX == SOC_GPIO_CLOCKOUT_CHANNEL_NUM, "clock_out_channel enumeration mismatch");
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/soc/esp32s2/include/soc/soc_caps.h b/components/soc/esp32s2/include/soc/soc_caps.h
index dc1c29858f..a3405cddbc 100644
--- a/components/soc/esp32s2/include/soc/soc_caps.h
+++ b/components/soc/esp32s2/include/soc/soc_caps.h
@@ -179,6 +179,8 @@
 
 // The Clock Out signal is binding to the pin's IO_MUX function
 #define SOC_GPIO_CLOCKOUT_BY_IO_MUX    (1)
+#define SOC_GPIO_CLOCKOUT_CHANNEL_NUM  (3)
+
 
 /*-------------------------- Dedicated GPIO CAPS ---------------------------------------*/
 #define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
diff --git a/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
index 930d5ce20f..c736f41619 100644
--- a/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
@@ -475,6 +475,10 @@ config SOC_GPIO_CLOCKOUT_BY_IO_MUX
     bool
     default y
 
+config SOC_GPIO_CLOCKOUT_CHANNEL_NUM
+    int
+    default 3
+
 config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
     int
     default 8
diff --git a/components/soc/esp32s3/include/soc/clkout_channel.h b/components/soc/esp32s3/include/soc/clkout_channel.h
new file mode 100644
index 0000000000..ab104d7f13
--- /dev/null
+++ b/components/soc/esp32s3/include/soc/clkout_channel.h
@@ -0,0 +1,52 @@
+/*
+ * SPDX-FileCopyrightText: 2010-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "esp_assert.h"
+#include "soc/soc_caps.h"
+#include "soc/io_mux_reg.h"
+#include "soc/gpio_sig_map.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum clock_out_channel {
+    CLKOUT_CHANNEL_1,
+    CLKOUT_CHANNEL_2,
+    CLKOUT_CHANNEL_3,
+    CLKOUT_CHANNEL_MAX,
+} clock_out_channel_t;
+
+#define CLKOUT_CHANNEL1_GPIO    GPIO_NUM_20
+#define CLKOUT_CHANNEL2_GPIO    GPIO_NUM_19
+#define CLKOUT_CHANNEL3_GPIO    GPIO_NUM_18
+#define FUNC_CLK_OUT1           FUNC_GPIO20_CLK_OUT1
+#define FUNC_CLK_OUT2           FUNC_GPIO19_CLK_OUT2
+#define FUNC_CLK_OUT3           FUNC_DAC_2_CLK_OUT3
+
+#define IONUM_TO_CLKOUT_CHANNEL(gpio_num)   ((gpio_num == CLKOUT_CHANNEL1_GPIO) ? CLKOUT_CHANNEL_1 : \
+                                             (gpio_num == CLKOUT_CHANNEL2_GPIO) ? CLKOUT_CHANNEL_2 : \
+                                             (gpio_num == CLKOUT_CHANNEL3_GPIO) ? CLKOUT_CHANNEL_3 : -1)
+#define CLKOUT_CHANNEL_TO_IOMUX_FUNC(channel)   ((channel == CLKOUT_CHANNEL_1) ? FUNC_CLK_OUT1 : \
+                                                 (channel == CLKOUT_CHANNEL_2) ? FUNC_CLK_OUT2 : \
+                                                 (channel == CLKOUT_CHANNEL_3) ? FUNC_CLK_OUT3 : -1)
+#define IS_VALID_CLKOUT_IO(gpio_num)    ((gpio_num == CLKOUT_CHANNEL1_GPIO) || (gpio_num == CLKOUT_CHANNEL2_GPIO) || (gpio_num == CLKOUT_CHANNEL3_GPIO))
+
+#define CLKOUT_CHANNEL_MASK(channel)    ((channel == CLKOUT_CHANNEL_1) ? CLK_OUT1 : \
+                                         (channel == CLKOUT_CHANNEL_2) ? CLK_OUT2 : \
+                                         (channel == CLKOUT_CHANNEL_3) ? CLK_OUT3 : 0)
+
+#define CLKOUT_CHANNEL_SHIFT(channel)   ((channel == CLKOUT_CHANNEL_1) ? CLK_OUT1_S : \
+                                         (channel == CLKOUT_CHANNEL_2) ? CLK_OUT2_S : \
+                                         (channel == CLKOUT_CHANNEL_3) ? CLK_OUT3_S : 0)
+
+ESP_STATIC_ASSERT(CLKOUT_CHANNEL_MAX == SOC_GPIO_CLOCKOUT_CHANNEL_NUM, "clock_out_channel enumeration mismatch");
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s3/include/soc/soc_caps.h b/components/soc/esp32s3/include/soc/soc_caps.h
index 8816802a52..536560d2d1 100644
--- a/components/soc/esp32s3/include/soc/soc_caps.h
+++ b/components/soc/esp32s3/include/soc/soc_caps.h
@@ -187,6 +187,7 @@
 
 // The Clock Out signal is binding to the pin's IO_MUX function
 #define SOC_GPIO_CLOCKOUT_BY_IO_MUX    (1)
+#define SOC_GPIO_CLOCKOUT_CHANNEL_NUM  (3)
 
 /*-------------------------- Dedicated GPIO CAPS -----------------------------*/
 #define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */