diff --git a/components/esp_hw_support/CMakeLists.txt b/components/esp_hw_support/CMakeLists.txt index 4a2a96c8db..338602cc8a 100644 --- a/components/esp_hw_support/CMakeLists.txt +++ b/components/esp_hw_support/CMakeLists.txt @@ -150,7 +150,13 @@ if(NOT BOOTLOADER_BUILD) list(APPEND srcs "esp_clock_output.c") endif() - if(CONFIG_IDF_TARGET_ESP32C5) + if(CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION) + list(REMOVE_ITEM srcs + "sleep_gpio.c" # TODO: [ESP32C5] IDF-8638, IDF-8640 + "port/esp_clk_tree_common.c" # TODO: [ESP32C5] IDF-8638, IDF-8640 + ) + endif() + if(CONFIG_IDF_TARGET_ESP32C5_MP_VERSION) list(REMOVE_ITEM srcs "sleep_modes.c" # TODO: [ESP32C5] IDF-8638, IDF-8640 "sleep_modem.c" # TODO: [ESP32C5] IDF-8638, IDF-8640 diff --git a/components/esp_hw_support/lowpower/CMakeLists.txt b/components/esp_hw_support/lowpower/CMakeLists.txt index c951006ad2..6727506080 100644 --- a/components/esp_hw_support/lowpower/CMakeLists.txt +++ b/components/esp_hw_support/lowpower/CMakeLists.txt @@ -15,11 +15,6 @@ if(CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP) endif() endif() -if(CONFIG_IDF_TARGET_ESP32C5) - list(REMOVE_ITEM srcs "cpu_retention/port/${target}/sleep_cpu.c" # TODO: [ESP32C5] IDF-8638, IDF-8640 - ) -endif() - add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}") target_sources(${COMPONENT_LIB} PRIVATE "${srcs}") diff --git a/components/esp_hw_support/lowpower/cpu_retention/port/esp32c5/rvsleep-frames.h b/components/esp_hw_support/lowpower/cpu_retention/port/esp32c5/rvsleep-frames.h index 616a16469b..8496d2cd9f 100644 --- a/components/esp_hw_support/lowpower/cpu_retention/port/esp32c5/rvsleep-frames.h +++ b/components/esp_hw_support/lowpower/cpu_retention/port/esp32c5/rvsleep-frames.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -86,7 +86,7 @@ STRUCT_BEGIN STRUCT_FIELD (long, 4, RV_SLP_CTX_PMUFUNC, pmufunc) /* A field is used to identify whether it is going * to sleep or has just been awakened. We use the - * lowest 2 bits as indication infomation, 3 means + * lowest 2 bits as indication information, 3 means * being awakened, 1 means going to sleep */ #if CONFIG_PM_CHECK_SLEEP_RETENTION_FRAME STRUCT_FIELD (long, 4, RV_SLP_CSF_CTX_CRC, frame_crc) /* Used to check RvCoreCriticalSleepFrame integrity */ @@ -111,7 +111,6 @@ STRUCT_END(RvCoreCriticalSleepFrame) */ STRUCT_BEGIN STRUCT_FIELD (long, 4, RV_SLP_CTX_MSCRATCH, mscratch) - STRUCT_FIELD (long, 4, RV_SLP_CTX_MIDELEG, mideleg) STRUCT_FIELD (long, 4, RV_SLP_CTX_MISA, misa) STRUCT_FIELD (long, 4, RV_SLP_CTX_TSELECT, tselect) STRUCT_FIELD (long, 4, RV_SLP_CTX_TDATA1, tdata1) @@ -171,21 +170,16 @@ STRUCT_BEGIN STRUCT_FIELD (long, 4, RV_SLP_CTX_PMACFG14, pmacfg14) STRUCT_FIELD (long, 4, RV_SLP_CTX_PMACFG15, pmacfg15) - STRUCT_FIELD (long, 4, RV_SLP_CTX_UTVEC, utvec) - STRUCT_FIELD (long, 4, RV_SLP_CTX_USTATUS, ustatus) - STRUCT_FIELD (long, 4, RV_SLP_CTX_UEPC, uepc) - STRUCT_FIELD (long, 4, RV_SLP_CTX_UCAUSE, ucause) + STRUCT_FIELD (long, 4, RV_SLP_CTX_MCYCLE, mcycle) - STRUCT_FIELD (long, 4, RV_SLP_CTX_MPCER, mpcer) - STRUCT_FIELD (long, 4, RV_SLP_CTX_MPCMR, mpcmr) - STRUCT_FIELD (long, 4, RV_SLP_CTX_MPCCR, mpccr) - STRUCT_FIELD (long, 4, RV_SLP_CTX_CPU_TESTBUS_CTRL, cpu_testbus_ctrl) - STRUCT_FIELD (long, 4, RV_SLP_CTX_UPCER, upcer) - STRUCT_FIELD (long, 4, RV_SLP_CTX_UPCMR, upcmr) - STRUCT_FIELD (long, 4, RV_SLP_CTX_UPCCR, upccr) - STRUCT_FIELD (long, 4, RV_SLP_CTX_UGPIO_OEN, ugpio_oen) - STRUCT_FIELD (long, 4, RV_SLP_CTX_UGPIO_IN, ugpio_in) - STRUCT_FIELD (long, 4, RV_SLP_CTX_UGPIO_OUT, ugpio_out) + STRUCT_FIELD (long, 4, RV_SLP_CTX_MTVT, mtvt) + STRUCT_FIELD (long, 4, RV_SLP_CTX_MNXTI, mnxti) + STRUCT_FIELD (long, 4, RV_SLP_CTX_MINTSTATUS, mintstatus) + STRUCT_FIELD (long, 4, RV_SLP_CTX_MXSTATUS, mxstatus) + STRUCT_FIELD (long, 4, RV_SLP_CTX_MHCR, mhcr) + STRUCT_FIELD (long, 4, RV_SLP_CTX_MHINT, mhint) + STRUCT_FIELD (long, 4, RV_SLP_CTX_MEXSTATUS, mexstatus) + STRUCT_FIELD (long, 4, RV_SLP_CTX_JVT, jvt) #if CONFIG_PM_CHECK_SLEEP_RETENTION_FRAME STRUCT_FIELD (long, 4, RV_SLP_NCSF_CTX_CRC, frame_crc) /* Used to check RvCoreNonCriticalSleepFrame integrity */ #endif diff --git a/components/esp_hw_support/lowpower/cpu_retention/port/esp32c5/sleep_cpu.c b/components/esp_hw_support/lowpower/cpu_retention/port/esp32c5/sleep_cpu.c index daf0a99192..d12d2d47f8 100644 --- a/components/esp_hw_support/lowpower/cpu_retention/port/esp32c5/sleep_cpu.c +++ b/components/esp_hw_support/lowpower/cpu_retention/port/esp32c5/sleep_cpu.c @@ -59,28 +59,22 @@ typedef struct { struct { RvCoreCriticalSleepFrame *critical_frame; RvCoreNonCriticalSleepFrame *non_critical_frame; - cpu_domain_dev_sleep_frame_t *intpri_frame; cpu_domain_dev_sleep_frame_t *cache_config_frame; - cpu_domain_dev_sleep_frame_t *plic_frame; + cpu_domain_dev_sleep_frame_t *clic_frame; cpu_domain_dev_sleep_frame_t *clint_frame; } retent; } sleep_cpu_retention_t; static DRAM_ATTR __attribute__((unused)) sleep_cpu_retention_t s_cpu_retention; -#define CUSTOM_CSR_PCER_MACHINE 0x7e0 -#define CUSTOM_CSR_PCMR_MACHINE 0x7e1 -#define CUSTOM_CSR_PCCR_MACHINE 0x7e2 -#define CUSTOM_CSR_CPU_TESTBUS_CTRL 0x7e3 -#define CUSTOM_CSR_PCER_USER 0x800 -#define CUSTOM_CSR_PCMR_USER 0x801 -#define CUSTOM_CSR_PCCR_USER 0x802 -#define CUSTOM_CSR_GPIO_OEN_USER 0x803 -#define CUSTOM_CSR_GPIO_IN_USER 0x804 -#define CUSTOM_CSR_GPIO_OUT_USER 0x805 -#define CUSTOM_CSR_CO_EXCEPTION_CAUSE 0x7f0 -#define CUSTOM_CSR_CO_HWLP 0x7f1 -#define CUSTOM_CSR_CO_AIA 0x7f2 +#define CUSTOM_CSR_MTVT (0x307) +#define CUSTOM_CSR_MNXTI (0x345) +#define CUSTOM_CSR_MINTSTATUS (0x346) +#define CUSTOM_CSR_MXSTATUS (0x7c0) +#define CUSTOM_CSR_MHCR (0x7c1) +#define CUSTOM_CSR_MHINT (0x7c5) +#define CUSTOM_CSR_MEXSTATUS (0x7e1) +#define CUSTOM_CSR_JVT (0x017) extern RvCoreCriticalSleepFrame *rv_core_critical_regs_frame; @@ -106,14 +100,6 @@ static void * cpu_domain_dev_sleep_frame_alloc_and_init(const cpu_domain_dev_reg return frame; } -static inline void * cpu_domain_intpri_sleep_frame_alloc_and_init(void) -{ - const static cpu_domain_dev_regs_region_t regions[] = { - { .start = INTPRI_CORE0_CPU_INT_ENABLE_REG, .end = INTPRI_RND_ECO_LOW_REG + 4 }, - { .start = INTPRI_RND_ECO_HIGH_REG, .end = INTPRI_RND_ECO_HIGH_REG + 4 } - }; - return cpu_domain_dev_sleep_frame_alloc_and_init(regions, sizeof(regions) / sizeof(regions[0])); -} static inline void * cpu_domain_cache_config_sleep_frame_alloc_and_init(void) { @@ -124,22 +110,19 @@ static inline void * cpu_domain_cache_config_sleep_frame_alloc_and_init(void) return cpu_domain_dev_sleep_frame_alloc_and_init(regions, sizeof(regions) / sizeof(regions[0])); } -static inline void * cpu_domain_plic_sleep_frame_alloc_and_init(void) -{ - const static cpu_domain_dev_regs_region_t regions[] = { - { .start = PLIC_MXINT_ENABLE_REG, .end = PLIC_MXINT_CLAIM_REG + 4 }, - { .start = PLIC_MXINT_CONF_REG, .end = PLIC_MXINT_CONF_REG + 4 }, - { .start = PLIC_UXINT_ENABLE_REG, .end = PLIC_UXINT_CLAIM_REG + 4 }, - { .start = PLIC_UXINT_CONF_REG, .end = PLIC_UXINT_CONF_REG + 4 } - }; - return cpu_domain_dev_sleep_frame_alloc_and_init(regions, sizeof(regions) / sizeof(regions[0])); -} - static inline void * cpu_domain_clint_sleep_frame_alloc_and_init(void) { const static cpu_domain_dev_regs_region_t regions[] = { { .start = CLINT_MINT_SIP_REG, .end = CLINT_MINT_MTIMECMP_H_REG + 4 }, - { .start = CLINT_UINT_SIP_REG, .end = CLINT_UINT_UTIMECMP_H_REG + 4 } + }; + return cpu_domain_dev_sleep_frame_alloc_and_init(regions, sizeof(regions) / sizeof(regions[0])); +} + +static inline void * cpu_domain_clic_sleep_frame_alloc_and_init(void) +{ + const static cpu_domain_dev_regs_region_t regions[] = { + { .start = CLIC_INT_CONFIG_REG, .end = CLIC_INT_THRESH_REG + 4 }, + { .start = CLIC_INT_CTRL_REG(0), .end = CLIC_INT_CTRL_REG(47) + 4 }, }; return cpu_domain_dev_sleep_frame_alloc_and_init(regions, sizeof(regions) / sizeof(regions[0])); } @@ -161,13 +144,6 @@ static esp_err_t esp_sleep_cpu_retention_init_impl(void) } s_cpu_retention.retent.non_critical_frame = (RvCoreNonCriticalSleepFrame *)frame; } - if (s_cpu_retention.retent.intpri_frame == NULL) { - void *frame = cpu_domain_intpri_sleep_frame_alloc_and_init(); - if (frame == NULL) { - goto err; - } - s_cpu_retention.retent.intpri_frame = (cpu_domain_dev_sleep_frame_t *)frame; - } if (s_cpu_retention.retent.cache_config_frame == NULL) { void *frame = cpu_domain_cache_config_sleep_frame_alloc_and_init(); if (frame == NULL) { @@ -175,12 +151,12 @@ static esp_err_t esp_sleep_cpu_retention_init_impl(void) } s_cpu_retention.retent.cache_config_frame = (cpu_domain_dev_sleep_frame_t *)frame; } - if (s_cpu_retention.retent.plic_frame == NULL) { - void *frame = cpu_domain_plic_sleep_frame_alloc_and_init(); + if (s_cpu_retention.retent.clic_frame == NULL) { + void *frame = cpu_domain_clic_sleep_frame_alloc_and_init(); if (frame == NULL) { goto err; } - s_cpu_retention.retent.plic_frame = (cpu_domain_dev_sleep_frame_t *)frame; + s_cpu_retention.retent.clic_frame = (cpu_domain_dev_sleep_frame_t *)frame; } if (s_cpu_retention.retent.clint_frame == NULL) { void *frame = cpu_domain_clint_sleep_frame_alloc_and_init(); @@ -206,17 +182,13 @@ static esp_err_t esp_sleep_cpu_retention_deinit_impl(void) heap_caps_free((void *)s_cpu_retention.retent.non_critical_frame); s_cpu_retention.retent.non_critical_frame = NULL; } - if (s_cpu_retention.retent.intpri_frame) { - heap_caps_free((void *)s_cpu_retention.retent.intpri_frame); - s_cpu_retention.retent.intpri_frame = NULL; - } if (s_cpu_retention.retent.cache_config_frame) { heap_caps_free((void *)s_cpu_retention.retent.cache_config_frame); s_cpu_retention.retent.cache_config_frame = NULL; } - if (s_cpu_retention.retent.plic_frame) { - heap_caps_free((void *)s_cpu_retention.retent.plic_frame); - s_cpu_retention.retent.plic_frame = NULL; + if (s_cpu_retention.retent.clic_frame) { + heap_caps_free((void *)s_cpu_retention.retent.clic_frame); + s_cpu_retention.retent.clic_frame = NULL; } if (s_cpu_retention.retent.clint_frame) { heap_caps_free((void *)s_cpu_retention.retent.clint_frame); @@ -240,7 +212,6 @@ static IRAM_ATTR RvCoreNonCriticalSleepFrame * rv_core_noncritical_regs_save(voi assert(s_cpu_retention.retent.non_critical_frame); RvCoreNonCriticalSleepFrame *frame = s_cpu_retention.retent.non_critical_frame; frame->mscratch = RV_READ_CSR(mscratch); - frame->mideleg = RV_READ_CSR(mideleg); frame->misa = RV_READ_CSR(misa); frame->tselect = RV_READ_CSR(tselect); frame->tdata1 = RV_READ_CSR(tdata1); @@ -301,21 +272,16 @@ static IRAM_ATTR RvCoreNonCriticalSleepFrame * rv_core_noncritical_regs_save(voi frame->pmacfg14 = RV_READ_CSR(CSR_PMACFG(14)); frame->pmacfg15 = RV_READ_CSR(CSR_PMACFG(15)); - frame->utvec = RV_READ_CSR(utvec); - frame->ustatus = RV_READ_CSR(ustatus); - frame->uepc = RV_READ_CSR(uepc); - frame->ucause = RV_READ_CSR(ucause); + frame->mcycle = RV_READ_CSR(mcycle); - frame->mpcer = RV_READ_CSR(CUSTOM_CSR_PCER_MACHINE); - frame->mpcmr = RV_READ_CSR(CUSTOM_CSR_PCMR_MACHINE); - frame->mpccr = RV_READ_CSR(CUSTOM_CSR_PCCR_MACHINE); - frame->cpu_testbus_ctrl = RV_READ_CSR(CUSTOM_CSR_CPU_TESTBUS_CTRL); - frame->upcer = RV_READ_CSR(CUSTOM_CSR_PCER_USER); - frame->upcmr = RV_READ_CSR(CUSTOM_CSR_PCMR_USER); - frame->upccr = RV_READ_CSR(CUSTOM_CSR_PCCR_USER); - frame->ugpio_oen = RV_READ_CSR(CUSTOM_CSR_GPIO_OEN_USER); - frame->ugpio_in = RV_READ_CSR(CUSTOM_CSR_GPIO_IN_USER); - frame->ugpio_out = RV_READ_CSR(CUSTOM_CSR_GPIO_OUT_USER); + frame->mtvt = RV_READ_CSR(CUSTOM_CSR_MTVT); + frame->mnxti = RV_READ_CSR(CUSTOM_CSR_MNXTI); + frame->mintstatus = RV_READ_CSR(CUSTOM_CSR_MINTSTATUS); + frame->mxstatus = RV_READ_CSR(CUSTOM_CSR_MXSTATUS); + frame->mhcr = RV_READ_CSR(CUSTOM_CSR_MHCR); + frame->mhint = RV_READ_CSR(CUSTOM_CSR_MHINT); + frame->mexstatus = RV_READ_CSR(CUSTOM_CSR_MEXSTATUS); + frame->jvt = RV_READ_CSR(CUSTOM_CSR_JVT); return frame; } @@ -323,7 +289,6 @@ static IRAM_ATTR void rv_core_noncritical_regs_restore(RvCoreNonCriticalSleepFra { assert(frame); RV_WRITE_CSR(mscratch, frame->mscratch); - RV_WRITE_CSR(mideleg, frame->mideleg); RV_WRITE_CSR(misa, frame->misa); RV_WRITE_CSR(tselect, frame->tselect); RV_WRITE_CSR(tdata1, frame->tdata1); @@ -383,21 +348,16 @@ static IRAM_ATTR void rv_core_noncritical_regs_restore(RvCoreNonCriticalSleepFra RV_WRITE_CSR(CSR_PMACFG(14), frame->pmacfg14); RV_WRITE_CSR(CSR_PMACFG(15), frame->pmacfg15); - RV_WRITE_CSR(utvec, frame->utvec); - RV_WRITE_CSR(ustatus, frame->ustatus); - RV_WRITE_CSR(uepc, frame->uepc); - RV_WRITE_CSR(ucause, frame->ucause); + RV_WRITE_CSR(mcycle, frame->mcycle); - RV_WRITE_CSR(CUSTOM_CSR_PCER_MACHINE, frame->mpcer); - RV_WRITE_CSR(CUSTOM_CSR_PCMR_MACHINE, frame->mpcmr); - RV_WRITE_CSR(CUSTOM_CSR_PCCR_MACHINE, frame->mpccr); - RV_WRITE_CSR(CUSTOM_CSR_CPU_TESTBUS_CTRL, frame->cpu_testbus_ctrl); - RV_WRITE_CSR(CUSTOM_CSR_PCER_USER, frame->upcer); - RV_WRITE_CSR(CUSTOM_CSR_PCMR_USER, frame->upcmr); - RV_WRITE_CSR(CUSTOM_CSR_PCCR_USER, frame->upccr); - RV_WRITE_CSR(CUSTOM_CSR_GPIO_OEN_USER,frame->ugpio_oen); - RV_WRITE_CSR(CUSTOM_CSR_GPIO_IN_USER, frame->ugpio_in); - RV_WRITE_CSR(CUSTOM_CSR_GPIO_OUT_USER,frame->ugpio_out); + RV_WRITE_CSR(CUSTOM_CSR_MTVT, frame->mtvt); + RV_WRITE_CSR(CUSTOM_CSR_MNXTI, frame->mnxti); + RV_WRITE_CSR(CUSTOM_CSR_MINTSTATUS, frame->mintstatus); + RV_WRITE_CSR(CUSTOM_CSR_MXSTATUS, frame->mxstatus); + RV_WRITE_CSR(CUSTOM_CSR_MHCR, frame->mhcr); + RV_WRITE_CSR(CUSTOM_CSR_MHINT, frame->mhint); + RV_WRITE_CSR(CUSTOM_CSR_MEXSTATUS, frame->mexstatus); + RV_WRITE_CSR(CUSTOM_CSR_JVT, frame->jvt); } static IRAM_ATTR void cpu_domain_dev_regs_save(cpu_domain_dev_sleep_frame_t *frame) @@ -484,9 +444,8 @@ esp_err_t IRAM_ATTR esp_sleep_cpu_retention(uint32_t (*goto_sleep)(uint32_t, uin esp_sleep_execute_event_callbacks(SLEEP_EVENT_SW_CPU_TO_MEM_START, (void *)0); uint32_t mstatus = save_mstatus_and_disable_global_int(); - cpu_domain_dev_regs_save(s_cpu_retention.retent.plic_frame); + cpu_domain_dev_regs_save(s_cpu_retention.retent.clic_frame); cpu_domain_dev_regs_save(s_cpu_retention.retent.clint_frame); - cpu_domain_dev_regs_save(s_cpu_retention.retent.intpri_frame); cpu_domain_dev_regs_save(s_cpu_retention.retent.cache_config_frame); RvCoreNonCriticalSleepFrame *frame = rv_core_noncritical_regs_save(); @@ -503,9 +462,8 @@ esp_err_t IRAM_ATTR esp_sleep_cpu_retention(uint32_t (*goto_sleep)(uint32_t, uin rv_core_noncritical_regs_restore(frame); cpu_domain_dev_regs_restore(s_cpu_retention.retent.cache_config_frame); - cpu_domain_dev_regs_restore(s_cpu_retention.retent.intpri_frame); cpu_domain_dev_regs_restore(s_cpu_retention.retent.clint_frame); - cpu_domain_dev_regs_restore(s_cpu_retention.retent.plic_frame); + cpu_domain_dev_regs_restore(s_cpu_retention.retent.clic_frame); restore_mstatus(mstatus); return err; } @@ -524,9 +482,8 @@ bool cpu_domain_pd_allowed(void) { return (s_cpu_retention.retent.critical_frame != NULL) && \ (s_cpu_retention.retent.non_critical_frame != NULL) && \ - (s_cpu_retention.retent.intpri_frame != NULL) && \ (s_cpu_retention.retent.cache_config_frame != NULL) && \ - (s_cpu_retention.retent.plic_frame != NULL) && \ + (s_cpu_retention.retent.clic_frame != NULL) && \ (s_cpu_retention.retent.clint_frame != NULL); } diff --git a/components/esp_hw_support/port/esp32c5/CMakeLists.txt b/components/esp_hw_support/port/esp32c5/CMakeLists.txt index 39fe4c5d06..d14b5b2cf6 100644 --- a/components/esp_hw_support/port/esp32c5/CMakeLists.txt +++ b/components/esp_hw_support/port/esp32c5/CMakeLists.txt @@ -1,23 +1,27 @@ -set(srcs "rtc_clk_init.c" - "rtc_clk.c" - "rtc_time.c" - "pmu_init.c" - "pmu_param.c" - "chip_info.c" - ) +if(CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION) + set(srcs "rtc_clk_init.c" + "rtc_clk.c" + "rtc_time.c" + "pmu_init.c" + "pmu_sleep.c" + "pmu_param.c" + "chip_info.c" + ) +endif() +if(CONFIG_IDF_TARGET_ESP32C5_MP_VERSION) + set(srcs "rtc_clk_init.c" + "rtc_time.c" + "rtc_clk.c" + "chip_info.c" + ) +endif() + if(NOT BOOTLOADER_BUILD) list(APPEND srcs "sar_periph_ctrl.c" "esp_crypto_lock.c") endif() -# TODO: [ESP32C5] IDF-8667 -if(IDF_TARGET STREQUAL "esp32c5") - list(REMOVE_ITEM srcs "pmu_init.c" - "pmu_param.c" - "sar_periph_ctrl.c") -endif() - add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}") target_sources(${COMPONENT_LIB} PRIVATE "${srcs}") diff --git a/components/esp_hw_support/port/esp32c5/include/soc/rtc.h b/components/esp_hw_support/port/esp32c5/include/soc/rtc.h index 4e956d412b..b066b5032a 100644 --- a/components/esp_hw_support/port/esp32c5/include/soc/rtc.h +++ b/components/esp_hw_support/port/esp32c5/include/soc/rtc.h @@ -134,7 +134,9 @@ typedef enum { RTC_CAL_RC32K = SOC_RTC_SLOW_CLK_SRC_RC32K, //!< Internal 32kHz RC oscillator, as one type of 32k clock RTC_CAL_32K_XTAL = SOC_RTC_SLOW_CLK_SRC_XTAL32K, //!< External 32kHz XTAL, as one type of 32k clock RTC_CAL_32K_OSC_SLOW = SOC_RTC_SLOW_CLK_SRC_OSC_SLOW, //!< External slow clock signal input by lp_pad_gpio0, as one type of 32k clock - // RTC_CAL_RC_FAST //!< Internal 20MHz RC oscillator +#if CONFIG_IDF_TARGET_ESP32C5_MP_VERSION + RTC_CAL_RC_FAST //!< Internal 20MHz RC oscillator +#endif } rtc_cal_sel_t; /** diff --git a/components/esp_hw_support/port/esp32c5/pmu_sleep.c b/components/esp_hw_support/port/esp32c5/pmu_sleep.c new file mode 100644 index 0000000000..6d8e27faf3 --- /dev/null +++ b/components/esp_hw_support/port/esp32c5/pmu_sleep.c @@ -0,0 +1,294 @@ +/* + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include "sdkconfig.h" +#include "esp_err.h" +#include "esp_attr.h" +#include "soc/soc.h" +#include "soc/rtc.h" +#include "soc/pmu_struct.h" +#include "hal/lp_aon_hal.h" +#include "esp_private/esp_pmu.h" +#include "pmu_param.h" + +#define HP(state) (PMU_MODE_HP_ ## state) +#define LP(state) (PMU_MODE_LP_ ## state) + + +static bool s_pmu_sleep_regdma_backup_enabled; + +void pmu_sleep_enable_regdma_backup(void) +{ + if(!s_pmu_sleep_regdma_backup_enabled){ + assert(PMU_instance()->hal); + /* entry 0, 1, 2 is used by pmu HP_SLEEP and HP_ACTIVE, HP_SLEEP + * and HP_MODEM or HP_MODEM and HP_ACTIVE states switching, + * respectively. entry 3 is reserved, not used yet! */ + pmu_hal_hp_set_sleep_active_backup_enable(PMU_instance()->hal); + pmu_hal_hp_set_sleep_modem_backup_enable(PMU_instance()->hal); + pmu_hal_hp_set_modem_active_backup_enable(PMU_instance()->hal); + s_pmu_sleep_regdma_backup_enabled = true; + } +} + +void pmu_sleep_disable_regdma_backup(void) +{ + if(s_pmu_sleep_regdma_backup_enabled){ + assert(PMU_instance()->hal); + pmu_hal_hp_set_sleep_active_backup_disable(PMU_instance()->hal); + pmu_hal_hp_set_sleep_modem_backup_disable(PMU_instance()->hal); + pmu_hal_hp_set_modem_active_backup_disable(PMU_instance()->hal); + s_pmu_sleep_regdma_backup_enabled = false; + } +} + +uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t pd_flags, uint32_t slowclk_period, uint32_t fastclk_period) +{ + const pmu_sleep_machine_constant_t *mc = (pmu_sleep_machine_constant_t *)PMU_instance()->mc; + + /* LP core hardware wait time, microsecond */ + const int lp_wakeup_wait_time_us = rtc_time_slowclk_to_us(mc->lp.wakeup_wait_cycle, slowclk_period); + const int lp_clk_switch_time_us = rtc_time_slowclk_to_us(mc->lp.clk_switch_cycle, slowclk_period); + const int lp_clk_power_on_wait_time_us = (pd_flags & PMU_SLEEP_PD_XTAL) ? mc->lp.xtal_wait_stable_time_us \ + : rtc_time_slowclk_to_us(mc->lp.clk_power_on_wait_cycle, slowclk_period); + + const int lp_hw_wait_time_us = mc->lp.min_slp_time_us + mc->lp.analog_wait_time_us + lp_clk_power_on_wait_time_us \ + + lp_wakeup_wait_time_us + lp_clk_switch_time_us + mc->lp.power_supply_wait_time_us \ + + mc->lp.power_up_wait_time_us; + + /* HP core hardware wait time, microsecond */ + const int hp_digital_power_up_wait_time_us = mc->hp.power_supply_wait_time_us + mc->hp.power_up_wait_time_us; + const int hp_regdma_wait_time_us = MAX(mc->hp.regdma_s2m_work_time_us + mc->hp.regdma_m2a_work_time_us, mc->hp.regdma_s2a_work_time_us); + const int hp_clock_wait_time_us = mc->hp.xtal_wait_stable_time_us + mc->hp.pll_wait_stable_time_us; + + const int hp_hw_wait_time_us = mc->hp.analog_wait_time_us + MAX(hp_digital_power_up_wait_time_us + hp_regdma_wait_time_us, hp_clock_wait_time_us); + + /* When the SOC wakeup (lp timer or GPIO wakeup) and Modem wakeup (Beacon wakeup) complete, the soc + * wakeup will be delayed until the RF is turned on in Modem state. + * + * modem wakeup TBTT, RF on by HW + * | | + * \|/ \|/ + * PMU_HP_ACTIVE /------ + * PMU_HP_MODEM /------------////////////////// + * PMU_HP_SLEEP ----------------------////////////////// + * /|\ /|\ /|\ /|\ /|\ /|\ + * |<- some hw wait ->| | | |<- M2A switch ->| + * | slow cycles & | soc wakeup | | + * | FOSC cycles |<- S2M switch ->| | + * | | + * |<-- PMU guard time, also the maximum time for the SOC -->| + * | wake-up delay | + */ +#if SOC_PM_SUPPORT_PMU_MODEM_STATE && CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP + const int rf_on_protect_time_us = mc->hp.regdma_rf_on_work_time_us; + const int total_hw_wait_time_us = lp_hw_wait_time_us + hp_hw_wait_time_us + mc->hp.clock_domain_sync_time_us; +#else + const int rf_on_protect_time_us = 0; + const int total_hw_wait_time_us = lp_hw_wait_time_us + hp_hw_wait_time_us; +#endif + return total_hw_wait_time_us + rf_on_protect_time_us; +} + +#define rtc_time_us_to_fastclk(time_us, period) rtc_time_us_to_slowclk((time_us), (period)) + +static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default( + pmu_sleep_param_config_t *param, + pmu_sleep_power_config_t *power, /* We'll use the runtime power parameter to determine some hardware parameters */ + const uint32_t pd_flags, + const uint32_t adjustment, + const uint32_t slowclk_period, + const uint32_t fastclk_period + ) +{ + const pmu_sleep_machine_constant_t *mc = (pmu_sleep_machine_constant_t *)PMU_instance()->mc; + + param->hp_sys.min_slp_slow_clk_cycle = rtc_time_us_to_slowclk(mc->hp.min_slp_time_us, slowclk_period); + param->hp_sys.analog_wait_target_cycle = rtc_time_us_to_fastclk(mc->hp.analog_wait_time_us, fastclk_period); + param->hp_sys.digital_power_supply_wait_cycle = rtc_time_us_to_fastclk(mc->hp.power_supply_wait_time_us, fastclk_period); + param->hp_sys.digital_power_up_wait_cycle = rtc_time_us_to_fastclk(mc->hp.power_up_wait_time_us, fastclk_period); + param->hp_sys.pll_stable_wait_cycle = rtc_time_us_to_fastclk(mc->hp.pll_wait_stable_time_us, fastclk_period); + + const int hw_wait_time_us = pmu_sleep_calculate_hw_wait_time(pd_flags, slowclk_period, fastclk_period); + const int modem_state_skip_time_us = mc->hp.regdma_m2a_work_time_us + mc->hp.system_dfs_up_work_time_us + mc->lp.min_slp_time_us; + const int modem_wakeup_wait_time_us = adjustment - hw_wait_time_us + modem_state_skip_time_us + mc->hp.regdma_rf_on_work_time_us; + param->hp_sys.modem_wakeup_wait_cycle = rtc_time_us_to_fastclk(modem_wakeup_wait_time_us, fastclk_period); + + param->lp_sys.min_slp_slow_clk_cycle = rtc_time_us_to_slowclk(mc->lp.min_slp_time_us, slowclk_period); + param->lp_sys.analog_wait_target_cycle = rtc_time_us_to_slowclk(mc->lp.analog_wait_time_us, slowclk_period); + param->lp_sys.digital_power_supply_wait_cycle = rtc_time_us_to_fastclk(mc->lp.power_supply_wait_time_us, fastclk_period); + param->lp_sys.digital_power_up_wait_cycle = rtc_time_us_to_fastclk(mc->lp.power_up_wait_time_us, fastclk_period); + + if (power->hp_sys.xtal.xpd_xtal) { + param->hp_lp.xtal_stable_wait_slow_clk_cycle = rtc_time_us_to_slowclk(mc->lp.xtal_wait_stable_time_us, slowclk_period); + } else { + param->hp_lp.xtal_stable_wait_cycle = rtc_time_us_to_fastclk(mc->hp.xtal_wait_stable_time_us, fastclk_period); + } + return param; +} + +const pmu_sleep_config_t* pmu_sleep_config_default( + pmu_sleep_config_t *config, + uint32_t pd_flags, + uint32_t adjustment, + uint32_t slowclk_period, + uint32_t fastclk_period, + bool dslp + ) +{ + pmu_sleep_power_config_t power_default = PMU_SLEEP_POWER_CONFIG_DEFAULT(pd_flags); + + uint32_t iram_pd_flags = 0; + iram_pd_flags |= (pd_flags & PMU_SLEEP_PD_MEM_G0) ? BIT(0) : 0; + iram_pd_flags |= (pd_flags & PMU_SLEEP_PD_MEM_G1) ? BIT(1) : 0; + iram_pd_flags |= (pd_flags & PMU_SLEEP_PD_MEM_G2) ? BIT(2) : 0; + iram_pd_flags |= (pd_flags & PMU_SLEEP_PD_MEM_G3) ? BIT(3) : 0; + config->power = power_default; + + pmu_sleep_param_config_t param_default = PMU_SLEEP_PARAM_CONFIG_DEFAULT(pd_flags); + config->param = *pmu_sleep_param_config_default(¶m_default, &power_default, pd_flags, adjustment, slowclk_period, fastclk_period); + + if (dslp) { + config->param.lp_sys.analog_wait_target_cycle = rtc_time_us_to_slowclk(PMU_LP_ANALOG_WAIT_TARGET_TIME_DSLP_US, slowclk_period); + pmu_sleep_analog_config_t analog_default = PMU_SLEEP_ANALOG_DSLP_CONFIG_DEFAULT(pd_flags); + config->analog = analog_default; + } else { + pmu_sleep_digital_config_t digital_default = PMU_SLEEP_DIGITAL_LSLP_CONFIG_DEFAULT(pd_flags); + config->digital = digital_default; + + pmu_sleep_analog_config_t analog_default = PMU_SLEEP_ANALOG_LSLP_CONFIG_DEFAULT(pd_flags); + + if (!(pd_flags & PMU_SLEEP_PD_XTAL)){ + analog_default.hp_sys.analog.pd_cur = PMU_PD_CUR_SLEEP_ON; + analog_default.hp_sys.analog.bias_sleep = PMU_BIASSLP_SLEEP_ON; + analog_default.hp_sys.analog.dbias = HP_CALI_DBIAS; + + analog_default.lp_sys[LP(SLEEP)].analog.pd_cur = PMU_PD_CUR_SLEEP_ON; + analog_default.lp_sys[LP(SLEEP)].analog.bias_sleep = PMU_BIASSLP_SLEEP_ON; + analog_default.lp_sys[LP(SLEEP)].analog.dbias = LP_CALI_DBIAS; + } + + config->analog = analog_default; + } + return config; +} + +static void pmu_sleep_power_init(pmu_context_t *ctx, const pmu_sleep_power_config_t *power, bool dslp) +{ + pmu_ll_hp_set_dig_power(ctx->hal->dev, HP(SLEEP), power->hp_sys.dig_power.val); + pmu_ll_hp_set_clk_power(ctx->hal->dev, HP(SLEEP), power->hp_sys.clk_power.val); + pmu_ll_hp_set_xtal_xpd (ctx->hal->dev, HP(SLEEP), power->hp_sys.xtal.xpd_xtal); + + pmu_ll_lp_set_dig_power(ctx->hal->dev, LP(ACTIVE), power->lp_sys[LP(ACTIVE)].dig_power.val); + pmu_ll_lp_set_clk_power(ctx->hal->dev, LP(ACTIVE), power->lp_sys[LP(ACTIVE)].clk_power.val); + + pmu_ll_lp_set_dig_power(ctx->hal->dev, LP(SLEEP), power->lp_sys[LP(SLEEP)].dig_power.val); + pmu_ll_lp_set_clk_power(ctx->hal->dev, LP(SLEEP), power->lp_sys[LP(SLEEP)].clk_power.val); + pmu_ll_lp_set_xtal_xpd (ctx->hal->dev, LP(SLEEP), power->lp_sys[LP(SLEEP)].xtal.xpd_xtal); +} + +static void pmu_sleep_digital_init(pmu_context_t *ctx, const pmu_sleep_digital_config_t *dig) +{ + pmu_ll_hp_set_dig_pad_slp_sel (ctx->hal->dev, HP(SLEEP), dig->syscntl.dig_pad_slp_sel); +} + +static void pmu_sleep_analog_init(pmu_context_t *ctx, const pmu_sleep_analog_config_t *analog, bool dslp) +{ + assert(ctx->hal); + pmu_ll_hp_set_dbg_atten (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.dbg_atten); + pmu_ll_hp_set_current_power_off (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.pd_cur); + pmu_ll_hp_set_bias_sleep_enable (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.bias_sleep); + pmu_ll_hp_set_regulator_xpd (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.xpd); + pmu_ll_hp_set_regulator_dbias (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.dbias); + pmu_ll_hp_set_regulator_driver_bar (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.drv_b); + + pmu_ll_lp_set_dbg_atten (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.dbg_atten); + pmu_ll_lp_set_current_power_off (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.pd_cur); + pmu_ll_lp_set_bias_sleep_enable (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.bias_sleep); + pmu_ll_lp_set_regulator_slp_xpd (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.slp_xpd); + pmu_ll_lp_set_regulator_xpd (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.xpd); + pmu_ll_lp_set_regulator_sleep_dbias(ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.slp_dbias); + pmu_ll_lp_set_regulator_dbias (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.dbias); + pmu_ll_lp_set_regulator_driver_bar (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.drv_b); +} + +static void pmu_sleep_param_init(pmu_context_t *ctx, const pmu_sleep_param_config_t *param, bool dslp) +{ + assert(ctx->hal); + pmu_ll_hp_set_min_sleep_cycle(ctx->hal->dev, param->hp_sys.min_slp_slow_clk_cycle); + pmu_ll_lp_set_min_sleep_cycle(ctx->hal->dev, param->lp_sys.min_slp_slow_clk_cycle); + + pmu_ll_hp_set_analog_wait_target_cycle(ctx->hal->dev, param->hp_sys.analog_wait_target_cycle); + pmu_ll_lp_set_analog_wait_target_cycle(ctx->hal->dev, param->lp_sys.analog_wait_target_cycle); + + pmu_hal_hp_set_digital_power_up_wait_cycle(ctx->hal, param->hp_sys.digital_power_supply_wait_cycle, param->hp_sys.digital_power_up_wait_cycle); + pmu_hal_lp_set_digital_power_up_wait_cycle(ctx->hal, param->lp_sys.digital_power_supply_wait_cycle, param->lp_sys.digital_power_up_wait_cycle); + + pmu_ll_set_modem_wait_target_cycle(ctx->hal->dev, param->hp_sys.modem_wakeup_wait_cycle); + pmu_ll_set_xtal_stable_wait_cycle(ctx->hal->dev, param->hp_lp.xtal_stable_wait_slow_clk_cycle); + pmu_ll_set_pll_stable_wait_cycle(ctx->hal->dev, param->hp_sys.pll_stable_wait_cycle); +} + +bool pmu_sleep_pll_already_enabled(void) +{ + return (pmu_ll_get_sysclk_sleep_select_state(PMU_instance()->hal->dev) != 0); +} + +void pmu_sleep_init(const pmu_sleep_config_t *config, bool dslp) +{ + assert(PMU_instance()); + pmu_sleep_power_init(PMU_instance(), &config->power, dslp); + if(!dslp){ + pmu_sleep_digital_init(PMU_instance(), &config->digital); + } + pmu_sleep_analog_init(PMU_instance(), &config->analog, dslp); + pmu_sleep_param_init(PMU_instance(), &config->param, dslp); +} + +uint32_t pmu_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp_mem_inf_fpu, bool dslp) +{ + assert(PMU_instance()->hal); + + lp_aon_hal_inform_wakeup_type(dslp); + + pmu_ll_hp_set_wakeup_enable(PMU_instance()->hal->dev, wakeup_opt); + pmu_ll_hp_set_reject_enable(PMU_instance()->hal->dev, reject_opt); + + pmu_ll_hp_clear_wakeup_intr_status(PMU_instance()->hal->dev); + pmu_ll_hp_clear_reject_intr_status(PMU_instance()->hal->dev); + pmu_ll_hp_clear_reject_cause(PMU_instance()->hal->dev); + + /* Start entry into sleep mode */ + pmu_ll_hp_set_sleep_enable(PMU_instance()->hal->dev); + + /* In pd_cpu lightsleep and deepsleep mode, we never get here */ + while (!pmu_ll_hp_is_sleep_wakeup(PMU_instance()->hal->dev) && + !pmu_ll_hp_is_sleep_reject(PMU_instance()->hal->dev)) { + ; + } + + return pmu_sleep_finish(); +} + +bool pmu_sleep_finish(void) +{ + return pmu_ll_hp_is_sleep_reject(PMU_instance()->hal->dev); +} + +void pmu_sleep_enable_hp_sleep_sysclk(bool enable) +{ + pmu_ll_hp_set_icg_sysclk_enable(PMU_instance()->hal->dev, HP(SLEEP), enable); +} + +uint32_t pmu_sleep_get_wakup_retention_cost(void) +{ + const pmu_sleep_machine_constant_t *mc = (pmu_sleep_machine_constant_t *)PMU_instance()->mc; + return mc->hp.regdma_s2a_work_time_us; +} diff --git a/components/esp_hw_support/port/esp32c5/private_include/pmu_bit_defs.h b/components/esp_hw_support/port/esp32c5/private_include/pmu_bit_defs.h new file mode 100644 index 0000000000..390499371b --- /dev/null +++ b/components/esp_hw_support/port/esp32c5/private_include/pmu_bit_defs.h @@ -0,0 +1,27 @@ +/* + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#define PMU_EXT0_WAKEUP_EN BIT(0) +#define PMU_EXT1_WAKEUP_EN BIT(1) +#define PMU_GPIO_WAKEUP_EN BIT(2) +#define PMU_WIFI_BEACON_WAKEUP_EN BIT(3) +#define PMU_LP_TIMER_WAKEUP_EN BIT(4) +#define PMU_WIFI_SOC_WAKEUP_EN BIT(5) +#define PMU_UART0_WAKEUP_EN BIT(6) +#define PMU_UART1_WAKEUP_EN BIT(7) +#define PMU_BLE_SOC_WAKEUP_EN BIT(10) +#define PMU_LP_CORE_WAKEUP_EN BIT(11) +#define PMU_USB_WAKEUP_EN BIT(14) + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_hw_support/port/esp32c5/rtc_time.c b/components/esp_hw_support/port/esp32c5/rtc_time.c index 1dc1db72d6..65b2c3cb7f 100644 --- a/components/esp_hw_support/port/esp32c5/rtc_time.c +++ b/components/esp_hw_support/port/esp32c5/rtc_time.c @@ -245,10 +245,12 @@ uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period) uint64_t rtc_time_get(void) { - // TODO: [ESP32C5] IDF-8667 - // return lp_timer_hal_get_cycle_count(); - ESP_EARLY_LOGW(TAG, "rtc_time_get has not been implemented yet"); +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION + return lp_timer_hal_get_cycle_count(); +#else + ESP_EARLY_LOGW(TAG, "rtc_timer has not been implemented yet"); return 0; +#endif } void rtc_clk_wait_for_slow_cycle(void) //This function may not by useful any more diff --git a/components/esp_hw_support/port/esp32c5/sar_periph_ctrl.c b/components/esp_hw_support/port/esp32c5/sar_periph_ctrl.c index d6b9d50906..484b89be1b 100644 --- a/components/esp_hw_support/port/esp32c5/sar_periph_ctrl.c +++ b/components/esp_hw_support/port/esp32c5/sar_periph_ctrl.c @@ -17,9 +17,9 @@ #include "sdkconfig.h" #include "esp_log.h" #include "freertos/FreeRTOS.h" -// #include "esp_private/sar_periph_ctrl.h" -// #include "esp_private/esp_modem_clock.h" -// #include "hal/sar_ctrl_ll.h" +#include "esp_private/sar_periph_ctrl.h" +#include "esp_private/esp_modem_clock.h" +#include "hal/sar_ctrl_ll.h" static const char *TAG = "sar_periph_ctrl"; extern portMUX_TYPE rtc_spinlock; @@ -28,26 +28,23 @@ extern portMUX_TYPE rtc_spinlock; void sar_periph_ctrl_init(void) { - // sar_ctrl_ll_force_power_ctrl_from_pwdet(true); + sar_ctrl_ll_force_power_ctrl_from_pwdet(true); //Add other periph power control initialisation here - ESP_EARLY_LOGW(TAG, "sar_periph_ctrl_init has not implemented on C5 yet"); } void sar_periph_ctrl_power_enable(void) { - // portENTER_CRITICAL_SAFE(&rtc_spinlock); - // sar_ctrl_ll_force_power_ctrl_from_pwdet(true); - // portEXIT_CRITICAL_SAFE(&rtc_spinlock); - ESP_EARLY_LOGW(TAG, "sar_periph_ctrl_power_enable has not implemented on C5 yet"); + portENTER_CRITICAL_SAFE(&rtc_spinlock); + sar_ctrl_ll_force_power_ctrl_from_pwdet(true); + portEXIT_CRITICAL_SAFE(&rtc_spinlock); } void sar_periph_ctrl_power_disable(void) { - // portENTER_CRITICAL_SAFE(&rtc_spinlock); - // sar_ctrl_ll_force_power_ctrl_from_pwdet(false); - // portEXIT_CRITICAL_SAFE(&rtc_spinlock); - ESP_EARLY_LOGW(TAG, "sar_periph_ctrl_power_disable has not implemented on C5 yet"); + portENTER_CRITICAL_SAFE(&rtc_spinlock); + sar_ctrl_ll_force_power_ctrl_from_pwdet(false); + portEXIT_CRITICAL_SAFE(&rtc_spinlock); } /** @@ -60,14 +57,13 @@ static int s_pwdet_power_on_cnt; static void s_sar_power_acquire(void) { - // modem_clock_module_enable(PERIPH_MODEM_ADC_COMMON_FE_MODULE); + modem_clock_module_enable(PERIPH_MODEM_ADC_COMMON_FE_MODULE); portENTER_CRITICAL_SAFE(&rtc_spinlock); s_pwdet_power_on_cnt++; if (s_pwdet_power_on_cnt == 1) { - // sar_ctrl_ll_set_power_mode_from_pwdet(SAR_CTRL_LL_POWER_ON); + sar_ctrl_ll_set_power_mode_from_pwdet(SAR_CTRL_LL_POWER_ON); } portEXIT_CRITICAL_SAFE(&rtc_spinlock); - ESP_EARLY_LOGW(TAG, "s_sar_power_acquire has not implemented on C5 yet"); } static void s_sar_power_release(void) @@ -79,11 +75,10 @@ static void s_sar_power_release(void) ESP_LOGE(TAG, "%s called, but s_pwdet_power_on_cnt == 0", __func__); abort(); } else if (s_pwdet_power_on_cnt == 0) { - // sar_ctrl_ll_set_power_mode_from_pwdet(SAR_CTRL_LL_POWER_FSM); + sar_ctrl_ll_set_power_mode_from_pwdet(SAR_CTRL_LL_POWER_FSM); } portEXIT_CRITICAL_SAFE(&rtc_spinlock); - ESP_EARLY_LOGW(TAG, "s_sar_power_release has not implemented on C5 yet"); - // modem_clock_module_disable(PERIPH_MODEM_ADC_COMMON_FE_MODULE); + modem_clock_module_disable(PERIPH_MODEM_ADC_COMMON_FE_MODULE); } diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c index 027e7a675a..35136975d6 100644 --- a/components/esp_hw_support/sleep_modes.c +++ b/components/esp_hw_support/sleep_modes.c @@ -683,7 +683,11 @@ static IRAM_ATTR void sleep_low_power_clock_calibration(bool is_dslp) if ((s_lightsleep_cnt % CONFIG_PM_LIGHTSLEEP_RTC_OSC_CAL_INTERVAL == 0) || is_dslp) #endif { +#if !CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION s_config.fast_clk_cal_period = rtc_clk_cal(RTC_CAL_RC_FAST, FAST_CLK_SRC_CAL_CYCLES); +#else + s_config.fast_clk_cal_period = 0x8000; +#endif } #endif } @@ -886,7 +890,7 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t m esp_sleep_isolate_digital_gpio(); #endif -#if ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB +#if ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB && SOC_DEEP_SLEEP_SUPPORTED #if SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY esp_set_deep_sleep_wake_stub_default_entry(); #elif !CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP && SOC_RTC_FAST_MEM_SUPPORTED @@ -994,10 +998,12 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t m misc_modules_wake_prepare(); } +#if SOC_SPI_MEM_SUPPORT_TIMING_TUNING if (cpu_freq_config.source == SOC_CPU_CLK_SRC_PLL) { // Turn up MSPI speed if switch to PLL mspi_timing_change_speed_mode_cache_safe(false); } +#endif // re-enable UART output resume_uarts(); @@ -1585,7 +1591,11 @@ bool esp_sleep_is_valid_wakeup_gpio(gpio_num_t gpio_num) #if SOC_RTCIO_PIN_COUNT > 0 return RTC_GPIO_IS_VALID_GPIO(gpio_num); #else +#if !CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION // TODO: IDF-9673 return GPIO_IS_DEEP_SLEEP_WAKEUP_VALID_GPIO(gpio_num); +#else + return true; +#endif #endif } diff --git a/components/esp_rom/include/esp32c5/beta3/esp32c5/rom/rtc.h b/components/esp_rom/include/esp32c5/beta3/esp32c5/rom/rtc.h index 65e37dbf7c..d97ec2d83a 100644 --- a/components/esp_rom/include/esp32c5/beta3/esp32c5/rom/rtc.h +++ b/components/esp_rom/include/esp32c5/beta3/esp32c5/rom/rtc.h @@ -64,7 +64,7 @@ extern "C" { #define RTC_RESET_CAUSE_REG LP_AON_STORE6_REG #define RTC_MEMORY_CRC_REG LP_AON_STORE7_REG #define RTC_SLEEP_WAKE_STUB_ADDR_REG LP_AON_STORE8_REG -#define RTC_SLEEP_MODE_REG LP_AON_STORE9_REG +#define RTC_SLEEP_MODE_REG LP_AON_STORE8_REG #define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) //!< Disable logging from the ROM code. diff --git a/components/esp_rom/include/esp32c5/mp/esp32c5/rom/rtc.h b/components/esp_rom/include/esp32c5/mp/esp32c5/rom/rtc.h index 42559d7524..eb98a8ebc4 100644 --- a/components/esp_rom/include/esp32c5/mp/esp32c5/rom/rtc.h +++ b/components/esp_rom/include/esp32c5/mp/esp32c5/rom/rtc.h @@ -63,8 +63,8 @@ extern "C" { #define RTC_ENTRY_ADDR_REG LP_AON_STORE6_REG #define RTC_RESET_CAUSE_REG LP_AON_STORE6_REG #define RTC_MEMORY_CRC_REG LP_AON_STORE7_REG -#define LIGHT_SLEEP_WAKE_STUB_ADDR_REG LP_AON_STORE8_REG -#define SLEEP_MODE_REG LP_AON_STORE9_REG +#define RTC_SLEEP_WAKE_STUB_ADDR_REG LP_AON_STORE8_REG +#define RTC_SLEEP_MODE_REG LP_AON_STORE8_REG #define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) //!< Disable logging from the ROM code. diff --git a/components/esp_system/port/soc/esp32c5/clk.c b/components/esp_system/port/soc/esp32c5/clk.c index 9ed553e6b5..38aa5f9a6c 100644 --- a/components/esp_system/port/soc/esp32c5/clk.c +++ b/components/esp_system/port/soc/esp32c5/clk.c @@ -222,14 +222,13 @@ __attribute__((weak)) void esp_perip_clk_init(void) * oscillator (40 MHz) to provide the clock during the sleep process in some * scenarios), the module needs to switch to the required clock source by * itself. */ //TODO - WIFI-5233 - // soc_rtc_slow_clk_src_t rtc_slow_clk_src = rtc_clk_slow_src_get(); - // modem_clock_lpclk_src_t modem_lpclk_src = (modem_clock_lpclk_src_t)( - // (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) ? MODEM_CLOCK_LPCLK_SRC_RC_SLOW - // : (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) ? MODEM_CLOCK_LPCLK_SRC_XTAL32K - // : (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) ? MODEM_CLOCK_LPCLK_SRC_RC32K - // : (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) ? MODEM_CLOCK_LPCLK_SRC_EXT32K - // : SOC_RTC_SLOW_CLK_SRC_RC_SLOW); - // modem_clock_select_lp_clock_source(PERIPH_WIFI_MODULE, modem_lpclk_src, 0); + soc_rtc_slow_clk_src_t rtc_slow_clk_src = rtc_clk_slow_src_get(); + modem_clock_lpclk_src_t modem_lpclk_src = (modem_clock_lpclk_src_t)( + (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) ? MODEM_CLOCK_LPCLK_SRC_XTAL32K + : (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) ? MODEM_CLOCK_LPCLK_SRC_RC32K + : (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) ? MODEM_CLOCK_LPCLK_SRC_EXT32K + : MODEM_CLOCK_LPCLK_SRC_RC32K); + modem_clock_select_lp_clock_source(PERIPH_WIFI_MODULE, modem_lpclk_src, 0); ESP_EARLY_LOGW(TAG, "esp_perip_clk_init() has not been implemented yet"); #if 0 // TODO: [ESP32C5] IDF-8844 diff --git a/components/esp_system/port/soc/esp32c61/clk.c b/components/esp_system/port/soc/esp32c61/clk.c index 20826e1cd5..9eabae2593 100644 --- a/components/esp_system/port/soc/esp32c61/clk.c +++ b/components/esp_system/port/soc/esp32c61/clk.c @@ -186,12 +186,12 @@ __attribute__((weak)) void esp_perip_clk_init(void) * scenarios), the module needs to switch to the required clock source by * itself. */ //TODO - WIFI-5233 soc_rtc_slow_clk_src_t rtc_slow_clk_src = rtc_clk_slow_src_get(); - modem_clock_lpclk_src_t modem_lpclk_src = (modem_clock_lpclk_src_t)(\ - (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) ? MODEM_CLOCK_LPCLK_SRC_RC_SLOW \ - : (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) ? MODEM_CLOCK_LPCLK_SRC_XTAL32K \ - : (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) ? MODEM_CLOCK_LPCLK_SRC_RC32K \ - : (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) ? MODEM_CLOCK_LPCLK_SRC_EXT32K \ - : SOC_RTC_SLOW_CLK_SRC_RC_SLOW); + modem_clock_lpclk_src_t modem_lpclk_src = (modem_clock_lpclk_src_t)( + (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) ? MODEM_CLOCK_LPCLK_SRC_RC_SLOW + : (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) ? MODEM_CLOCK_LPCLK_SRC_XTAL32K + : (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) ? MODEM_CLOCK_LPCLK_SRC_RC32K + : (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) ? MODEM_CLOCK_LPCLK_SRC_EXT32K + : SOC_RTC_SLOW_CLK_SRC_RC_SLOW); modem_clock_select_lp_clock_source(PERIPH_WIFI_MODULE, modem_lpclk_src, 0); ESP_EARLY_LOGW(TAG, "esp_perip_clk_init() has not been implemented yet"); diff --git a/components/hal/esp32c5/include/hal/lp_aon_hal.h b/components/hal/esp32c5/include/hal/lp_aon_hal.h new file mode 100644 index 0000000000..2090a64928 --- /dev/null +++ b/components/hal/esp32c5/include/hal/lp_aon_hal.h @@ -0,0 +1,17 @@ +/* + * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "hal/lp_aon_ll.h" + +#define rtc_hal_ext1_get_wakeup_status() lp_aon_ll_ext1_get_wakeup_status() +#define rtc_hal_ext1_clear_wakeup_status() lp_aon_ll_ext1_clear_wakeup_status() +#define rtc_hal_ext1_set_wakeup_pins(io_mask, mode_mask) lp_aon_ll_ext1_set_wakeup_pins(io_mask, mode_mask) +#define rtc_hal_ext1_clear_wakeup_pins() lp_aon_ll_ext1_clear_wakeup_pins() +#define rtc_hal_ext1_get_wakeup_pins() lp_aon_ll_ext1_get_wakeup_pins() + +#define lp_aon_hal_inform_wakeup_type(dslp) lp_aon_ll_inform_wakeup_type(dslp) diff --git a/components/hal/esp32c5/include/hal/lp_aon_ll.h b/components/hal/esp32c5/include/hal/lp_aon_ll.h new file mode 100644 index 0000000000..dc65bb3225 --- /dev/null +++ b/components/hal/esp32c5/include/hal/lp_aon_ll.h @@ -0,0 +1,97 @@ +/* + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The LL layer for ESP32-C5 LP_AON register operations + +#pragma once + +#include +#include "soc/soc.h" +#include "soc/lp_aon_struct.h" +#include "hal/misc.h" +#include "esp32c5/rom/rtc.h" + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Get ext1 wakeup source status + * @return The lower 8 bits of the returned value are the bitmap of + * the wakeup source status, bit 0~7 corresponds to LP_IO 0~7 + */ +static inline uint32_t lp_aon_ll_ext1_get_wakeup_status(void) +{ + return HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_status); +} + +/** + * @brief Clear the ext1 wakeup source status + */ +static inline void lp_aon_ll_ext1_clear_wakeup_status(void) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_status_clr, 1); +} + +/** + * @brief Set the wake-up LP_IO of the ext1 wake-up source + * @param io_mask wakeup LP_IO bitmap, bit 0~7 corresponds to LP_IO 0~7 + * @param level_mask LP_IO wakeup level bitmap, bit 0~7 corresponds to LP_IO 0~7 wakeup level + * each bit's corresponding position is set to 0, the wakeup level will be low + * on the contrary, each bit's corresponding position is set to 1, the wakeup + * level will be high + */ +static inline void lp_aon_ll_ext1_set_wakeup_pins(uint32_t io_mask, uint32_t level_mask) +{ + uint32_t wakeup_sel_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel); + wakeup_sel_mask |= io_mask; + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel, wakeup_sel_mask); + + uint32_t wakeup_level_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_lv); + wakeup_level_mask |= io_mask & level_mask; + wakeup_level_mask &= ~(io_mask & ~level_mask); + + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_lv, wakeup_level_mask); +} + +/** + * @brief Clear all ext1 wakup-source setting + */ +static inline void lp_aon_ll_ext1_clear_wakeup_pins(void) +{ + HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel, 0); +} + +/** + * @brief Get ext1 wakeup source setting + * @return The lower 8 bits of the returned value are the bitmap of + * the wakeup source status, bit 0~7 corresponds to LP_IO 0~7 + */ +static inline uint32_t lp_aon_ll_ext1_get_wakeup_pins(void) +{ + return HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel); +} + + +/** + * @brief ROM obtains the wake-up type through LP_AON_STORE9_REG[0]. + * Set the flag to inform + * @param true: deepsleep false: lightsleep + */ +static inline void lp_aon_ll_inform_wakeup_type(bool dslp) +{ + if (dslp) { + REG_SET_BIT(RTC_SLEEP_MODE_REG, BIT(0)); /* Tell rom to run deep sleep wake stub */ + + } else { + REG_CLR_BIT(RTC_SLEEP_MODE_REG, BIT(0)); /* Tell rom to run light sleep wake stub */ + } +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c5/include/hal/lp_timer_ll.h b/components/hal/esp32c5/include/hal/lp_timer_ll.h new file mode 100644 index 0000000000..357a89b8a1 --- /dev/null +++ b/components/hal/esp32c5/include/hal/lp_timer_ll.h @@ -0,0 +1,181 @@ +/* + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The LL layer for ESP32-C5 LP_Timer register operations + +#pragma once + +#include +#include "soc/soc.h" +#include "soc/rtc.h" +#include "soc/lp_timer_struct.h" +#include "soc/lp_aon_reg.h" +#include "hal/assert.h" +#include "hal/lp_timer_types.h" +#include "esp_attr.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Set lp_timer alarm target + * + * @param dev lp_timer source + * @param timer_id lp_timer target num + * @param value next alarm value + * + * @return None + */ +FORCE_INLINE_ATTR void lp_timer_ll_set_alarm_target(lp_timer_dev_t *dev, uint8_t timer_id, uint64_t value) +{ +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION + dev->target[timer_id].hi.main_timer_tar_high = (value >> 32) & 0xFFFF; + dev->target[timer_id].lo.main_timer_tar_low = value & 0xFFFFFFFF; +#else + HAL_ASSERT(false && "lp_timer not supported yet"); +#endif +} + +/** + * @brief Enable lp_timer alarm + * + * @param dev lp_timer source + * @param timer_id lp_timer target num + * @param en enable bit + * + * @return None + */ +FORCE_INLINE_ATTR void lp_timer_ll_set_target_enable(lp_timer_dev_t *dev, uint8_t timer_id, bool en) +{ +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION + dev->target[timer_id].hi.main_timer_tar_en = en; +#else + HAL_ASSERT(false && "lp_timer not supported yet"); +#endif +} + +/** + * @brief Get lp_timer low bits value of counter + * + * @param dev lp_timer source + * @param buffer_id lp_timer counter buffer num + * + * @return The lp_timer low bits value of counter + */ +FORCE_INLINE_ATTR uint32_t lp_timer_ll_get_counter_value_low(lp_timer_dev_t *dev, uint8_t buffer_id) +{ +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION + return dev->counter[buffer_id].lo.main_timer_buf_low; +#else + HAL_ASSERT(false && "lp_timer not supported yet"); + return 0; +#endif +} + +/** + * @brief Get lp_timer high bits value of counter + * + * @param dev lp_timer source + * @param buffer_id lp_timer counter buffer num + * + * @return The lp_timer high bits value of counter + */ +FORCE_INLINE_ATTR uint32_t lp_timer_ll_get_counter_value_high(lp_timer_dev_t *dev, uint8_t buffer_id) +{ +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION + return dev->counter[buffer_id].hi.main_timer_buf_high; +#else + HAL_ASSERT(false && "lp_timer not supported yet"); + return 0; +#endif +} + +/** + * @brief Update lp_timer counter + * + * @param dev lp_timer source + * + * @return None + */ +FORCE_INLINE_ATTR void lp_timer_ll_counter_snapshot(lp_timer_dev_t *dev) +{ +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION + dev->update.main_timer_update = 1; +#else + HAL_ASSERT(false && "lp_timer not supported yet"); +#endif +} + +/** + * @brief Clear lp_timer alarm intr status + * + * @param dev lp_timer source + * + * @return None + */ +FORCE_INLINE_ATTR void lp_timer_ll_clear_alarm_intr_status(lp_timer_dev_t *dev) +{ +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION + dev->int_clr.soc_wakeup_int_clr = 1; +#else + HAL_ASSERT(false && "lp_timer not supported yet"); +#endif +} + +/** + * @brief Clear lp_timer overflow intr status + * + * @param dev lp_timer source + * + * @return None + */ +FORCE_INLINE_ATTR void lp_timer_ll_clear_overflow_intr_status(lp_timer_dev_t *dev) +{ +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION + dev->int_clr.overflow_clr = 1; +#else + HAL_ASSERT(false && "lp_timer not supported yet"); +#endif +} + +/** + * @brief Clear lp_timer lp_alarm intr status + * + * @param dev lp_timer source + * + * @return None + */ +FORCE_INLINE_ATTR void lp_timer_ll_clear_lp_alarm_intr_status(lp_timer_dev_t *dev) +{ +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION + dev->lp_int_clr.main_timer_lp_int_clr = 1; +#else + HAL_ASSERT(false && "lp_timer not supported yet"); +#endif +} + +/** + * @brief Convert lp_timer time to count + * + * @param time_in_us time in us + * + * @return lp_timer count + */ +FORCE_INLINE_ATTR uint64_t lp_timer_ll_time_to_count(uint64_t time_in_us) +{ +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION + uint32_t slow_clk_value = REG_READ(LP_AON_STORE1_REG); + return ((time_in_us * (1 << RTC_CLK_CAL_FRACT)) / slow_clk_value); +#else + HAL_ASSERT(false && "lp_timer not supported yet"); + return 0; +#endif +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c5/include/hal/pau_ll.h b/components/hal/esp32c5/include/hal/pau_ll.h new file mode 100644 index 0000000000..7294cfdefd --- /dev/null +++ b/components/hal/esp32c5/include/hal/pau_ll.h @@ -0,0 +1,265 @@ +/* + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The LL layer for ESP32-C5 PAU(Power Assist Unit) register operations + +#pragma once + +#include +#include +#include "soc/soc.h" +#include "soc/pau_reg.h" +#include "soc/pau_struct.h" +#include "hal/pau_types.h" +#include "hal/assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +static inline uint32_t pau_ll_get_regdma_backup_flow_error(pau_dev_t *dev) +{ +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION + return dev->regdma_conf.flow_err; +#else + HAL_ASSERT(false && "pau not supported yet"); + return 0; +#endif +} + +static inline void pau_ll_select_regdma_entry_link(pau_dev_t *dev, int link) +{ +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION + dev->regdma_conf.link_sel = link; +#else + HAL_ASSERT(false && "pau not supported yet"); +#endif +} + +static inline void pau_ll_set_regdma_entry_link_backup_direction(pau_dev_t *dev, bool to_mem) +{ +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION + dev->regdma_conf.to_mem = to_mem ? 1 : 0; +#else + HAL_ASSERT(false && "pau not supported yet"); +#endif +} + +static inline void pau_ll_set_regdma_entry_link_backup_start_enable(pau_dev_t *dev) +{ +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION + dev->regdma_conf.start = 1; +#else + HAL_ASSERT(false && "pau not supported yet"); +#endif +} + +static inline void pau_ll_set_regdma_entry_link_backup_start_disable(pau_dev_t *dev) +{ +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION + dev->regdma_conf.start = 0; +#else + HAL_ASSERT(false && "pau not supported yet"); +#endif +} + +static inline void pau_ll_set_regdma_select_wifimac_link(pau_dev_t *dev) +{ +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION + dev->regdma_conf.sel_mac = 1; +#else + HAL_ASSERT(false && "pau not supported yet"); +#endif +} + +static inline void pau_ll_set_regdma_deselect_wifimac_link(pau_dev_t *dev) +{ +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION + dev->regdma_conf.sel_mac = 0; +#else + HAL_ASSERT(false && "pau not supported yet"); +#endif +} + +static inline void pau_ll_set_regdma_wifimac_link_backup_direction(pau_dev_t *dev, bool to_mem) +{ +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION + dev->regdma_conf.to_mem_mac = to_mem ? 1 : 0; +#else + HAL_ASSERT(false && "pau not supported yet"); +#endif +} + +static inline void pau_ll_set_regdma_wifimac_link_backup_start_enable(pau_dev_t *dev) +{ +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION + dev->regdma_conf.start_mac = 1; +#else + HAL_ASSERT(false && "pau not supported yet"); +#endif +} + +static inline void pau_ll_set_regdma_wifimac_link_backup_start_disable(pau_dev_t *dev) +{ +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION + dev->regdma_conf.start_mac = 0; +#else + HAL_ASSERT(false && "pau not supported yet"); +#endif +} + +static inline void pau_ll_set_regdma_link0_addr(pau_dev_t *dev, void *link_addr) +{ +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION + dev->regdma_link_0_addr.val = (uint32_t)link_addr; +#else + HAL_ASSERT(false && "pau not supported yet"); +#endif +} + +static inline void pau_ll_set_regdma_link1_addr(pau_dev_t *dev, void *link_addr) +{ +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION + dev->regdma_link_1_addr.val = (uint32_t)link_addr; +#else + HAL_ASSERT(false && "pau not supported yet"); +#endif +} + +static inline void pau_ll_set_regdma_link2_addr(pau_dev_t *dev, void *link_addr) +{ +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION + dev->regdma_link_2_addr.val = (uint32_t)link_addr; +#else + HAL_ASSERT(false && "pau not supported yet"); +#endif +} + +static inline void pau_ll_set_regdma_link3_addr(pau_dev_t *dev, void *link_addr) +{ +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION + dev->regdma_link_3_addr.val = (uint32_t)link_addr; +#else + HAL_ASSERT(false && "pau not supported yet"); +#endif +} + +static inline void pau_ll_set_regdma_wifimac_link_addr(pau_dev_t *dev, void *link_addr) +{ +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION + dev->regdma_link_mac_addr.val = (uint32_t)link_addr; +#else + HAL_ASSERT(false && "pau not supported yet"); +#endif +} + +static inline uint32_t pau_ll_get_regdma_current_link_addr(pau_dev_t *dev) +{ +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION + return dev->regdma_current_link_addr.val; +#else + HAL_ASSERT(false && "pau not supported yet"); + return 0; +#endif +} + +static inline uint32_t pau_ll_get_regdma_backup_addr(pau_dev_t *dev) +{ +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION + return dev->regdma_backup_addr.val; +#else + HAL_ASSERT(false && "pau not supported yet"); + return 0; +#endif +} + +static inline uint32_t pau_ll_get_regdma_memory_addr(pau_dev_t *dev) +{ +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION + return dev->regdma_mem_addr.val; +#else + HAL_ASSERT(false && "pau not supported yet"); + return 0; +#endif +} + +static inline uint32_t pau_ll_get_regdma_intr_raw_signal(pau_dev_t *dev) +{ +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION + return dev->int_raw.val; +#else + HAL_ASSERT(false && "pau not supported yet"); + return 0; +#endif +} + +static inline uint32_t pau_ll_get_regdma_intr_status(pau_dev_t *dev) +{ +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION + return dev->int_st.val; +#else + HAL_ASSERT(false && "pau not supported yet"); + return 0; +#endif +} + +static inline void pau_ll_set_regdma_backup_done_intr_enable(pau_dev_t *dev) +{ +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION + dev->int_ena.done_int_ena = 1; +#else + HAL_ASSERT(false && "pau not supported yet"); +#endif +} + +static inline void pau_ll_set_regdma_backup_done_intr_disable(pau_dev_t *dev) +{ +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION + dev->int_ena.done_int_ena = 0; +#else + HAL_ASSERT(false && "pau not supported yet"); +#endif +} + +static inline void pau_ll_set_regdma_backup_error_intr_enable(pau_dev_t *dev) +{ +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION + dev->int_ena.error_int_ena = 1; +#else + HAL_ASSERT(false && "pau not supported yet"); +#endif +} + +static inline void pau_ll_set_regdma_backup_error_intr_disable(pau_dev_t *dev) +{ +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION + dev->int_ena.error_int_ena = 0; +#else + HAL_ASSERT(false && "pau not supported yet"); +#endif +} + +static inline void pau_ll_clear_regdma_backup_done_intr_state(pau_dev_t *dev) +{ +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION + dev->int_clr.done_int_clr = 1; +#else + HAL_ASSERT(false && "pau not supported yet"); +#endif +} + +static inline void pau_ll_clear_regdma_backup_error_intr_state(pau_dev_t *dev) +{ +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION + dev->int_clr.error_int_clr = 1; +#else + HAL_ASSERT(false && "pau not supported yet"); +#endif +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c5/include/hal/sar_ctrl_ll.h b/components/hal/esp32c5/include/hal/sar_ctrl_ll.h new file mode 100644 index 0000000000..e46a2f3f1e --- /dev/null +++ b/components/hal/esp32c5/include/hal/sar_ctrl_ll.h @@ -0,0 +1,73 @@ +/* + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * SAR related peripherals are interdependent. + * Related peripherals are: + * - ADC + * - PWDET + * + * All of above peripherals require SAR to work correctly. + * As SAR has some registers that will influence above mentioned peripherals. + * This file gives an abstraction for such registers + */ + +#pragma once + +#include +#include +#include "soc/soc.h" +#include "soc/apb_saradc_struct.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define PWDET_LL_SAR_POWER_FORCE_BIT BIT(24) +#define PWDET_LL_SAR_POWER_CNTL_BIT BIT(23) + + +typedef enum { + SAR_CTRL_LL_POWER_FSM, //SAR power controlled by FSM + SAR_CTRL_LL_POWER_ON, //SAR power on + SAR_CTRL_LL_POWER_OFF, //SAR power off +} sar_ctrl_ll_power_t; + +/*--------------------------------------------------------------- + SAR power control +---------------------------------------------------------------*/ +/** + * @brief Set SAR power mode when controlled by PWDET + * + * @param[in] mode See `sar_ctrl_ll_power_t` + */ +__attribute__((always_inline)) +static inline void sar_ctrl_ll_set_power_mode_from_pwdet(sar_ctrl_ll_power_t mode) +{ + if (mode == SAR_CTRL_LL_POWER_FSM) { + REG_CLR_BIT(PWDET_CONF_REG, PWDET_LL_SAR_POWER_FORCE_BIT); + } else if (mode == SAR_CTRL_LL_POWER_ON) { + REG_SET_BIT(PWDET_CONF_REG, PWDET_LL_SAR_POWER_FORCE_BIT); + REG_SET_BIT(PWDET_CONF_REG, PWDET_LL_SAR_POWER_CNTL_BIT); + } else if (mode == SAR_CTRL_LL_POWER_OFF) { + REG_SET_BIT(PWDET_CONF_REG, PWDET_LL_SAR_POWER_FORCE_BIT); + REG_CLR_BIT(PWDET_CONF_REG, PWDET_LL_SAR_POWER_CNTL_BIT); + } +} + +/** + * @brief Set SAR power ctrl source + * + * @param[in] force set PWDET as SAR power ctrl source when force is true + */ +static inline void sar_ctrl_ll_force_power_ctrl_from_pwdet(bool force) +{ + APB_SARADC.saradc_ctrl.saradc_saradc2_pwdet_drv = force; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c5/pau_hal.c b/components/hal/esp32c5/pau_hal.c new file mode 100644 index 0000000000..000a958b32 --- /dev/null +++ b/components/hal/esp32c5/pau_hal.c @@ -0,0 +1,56 @@ +/* + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/soc.h" +#include "esp_attr.h" +#include "hal/pau_hal.h" +#include "hal/pau_types.h" + +void pau_hal_set_regdma_entry_link_addr(pau_hal_context_t *hal, pau_regdma_link_addr_t *link_addr) +{ + pau_ll_set_regdma_link0_addr(hal->dev, (*link_addr)[0]); + pau_ll_set_regdma_link1_addr(hal->dev, (*link_addr)[1]); + pau_ll_set_regdma_link2_addr(hal->dev, (*link_addr)[2]); + /* The link 3 of REGDMA is reserved, PMU state switching will not use + * REGDMA link 3 */ +} + +void pau_hal_start_regdma_modem_link(pau_hal_context_t *hal, bool backup_or_restore) +{ + pau_ll_clear_regdma_backup_done_intr_state(hal->dev); + pau_ll_set_regdma_select_wifimac_link(hal->dev); + pau_ll_set_regdma_wifimac_link_backup_direction(hal->dev, backup_or_restore); + pau_ll_set_regdma_wifimac_link_backup_start_enable(hal->dev); + + while (!(pau_ll_get_regdma_intr_raw_signal(hal->dev) & PAU_DONE_INT_RAW)); +} + +void pau_hal_stop_regdma_modem_link(pau_hal_context_t *hal) +{ + pau_ll_set_regdma_wifimac_link_backup_start_disable(hal->dev); + pau_ll_set_regdma_deselect_wifimac_link(hal->dev); + pau_ll_clear_regdma_backup_done_intr_state(hal->dev); +} + +void pau_hal_start_regdma_extra_link(pau_hal_context_t *hal, bool backup_or_restore) +{ + pau_ll_clear_regdma_backup_done_intr_state(hal->dev); + /* The link 3 of REGDMA is reserved, we use it as an extra linked list to + * provide backup and restore services for BLE, IEEE802.15.4 and possibly + * other modules */ + pau_ll_select_regdma_entry_link(hal->dev, 3); + pau_ll_set_regdma_entry_link_backup_direction(hal->dev, backup_or_restore); + pau_ll_set_regdma_entry_link_backup_start_enable(hal->dev); + + while (!(pau_ll_get_regdma_intr_raw_signal(hal->dev) & PAU_DONE_INT_RAW)); +} + +void pau_hal_stop_regdma_extra_link(pau_hal_context_t *hal) +{ + pau_ll_set_regdma_entry_link_backup_start_disable(hal->dev); + pau_ll_select_regdma_entry_link(hal->dev, 0); /* restore link select to default */ + pau_ll_clear_regdma_backup_done_intr_state(hal->dev); +} diff --git a/components/hal/esp32c6/pau_hal.c b/components/hal/esp32c6/pau_hal.c index 53be6120c3..cc39004bae 100644 --- a/components/hal/esp32c6/pau_hal.c +++ b/components/hal/esp32c6/pau_hal.c @@ -4,8 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ -// The HAL layer for PAU (ESP32-C6 specific part) - #include "soc/soc.h" #include "esp_attr.h" #include "hal/pau_hal.h" diff --git a/components/hal/esp32p4/pau_hal.c b/components/hal/esp32p4/pau_hal.c index 958210f0c1..38b98ba4e1 100644 --- a/components/hal/esp32p4/pau_hal.c +++ b/components/hal/esp32p4/pau_hal.c @@ -4,8 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ -// The HAL layer for PAU (ESP32-C6 specific part) - #include "soc/soc.h" #include "soc/soc_caps.h" #include "esp_attr.h" diff --git a/components/soc/esp32c5/beta3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/beta3/include/soc/Kconfig.soc_caps.in index 63e8ec59c7..3a4882b451 100644 --- a/components/soc/esp32c5/beta3/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c5/beta3/include/soc/Kconfig.soc_caps.in @@ -99,6 +99,18 @@ config SOC_FLASH_ENC_SUPPORTED bool default y +config SOC_PMU_SUPPORTED + bool + default y + +config SOC_LP_TIMER_SUPPORTED + bool + default y + +config SOC_LP_AON_SUPPORTED + bool + default y + config SOC_LP_PERIPHERALS_SUPPORTED bool default y @@ -523,6 +535,14 @@ config SOC_SYSTIMER_ALARM_MISS_COMPENSATE bool default y +config SOC_LP_TIMER_BIT_WIDTH_LO + int + default 32 + +config SOC_LP_TIMER_BIT_WIDTH_HI + int + default 16 + config SOC_TIMER_GROUPS int default 2 @@ -643,6 +663,22 @@ config SOC_PM_SUPPORT_RTC_PERIPH_PD bool default y +config SOC_PM_SUPPORT_PMU_MODEM_STATE + bool + default n + +config SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY + bool + default y + +config SOC_PM_CPU_RETENTION_BY_SW + bool + default y + +config SOC_PM_PAU_LINK_NUM + int + default 4 + config SOC_CLK_RC_FAST_SUPPORT_CALIBRATION bool default y diff --git a/components/soc/esp32c5/beta3/include/soc/clint_reg.h b/components/soc/esp32c5/beta3/include/soc/clint_reg.h new file mode 100644 index 0000000000..ac96f4bb82 --- /dev/null +++ b/components/soc/esp32c5/beta3/include/soc/clint_reg.h @@ -0,0 +1,77 @@ +/* + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + + +/*CLINT MINT*/ +#define CLINT_MINT_SIP_REG (DR_REG_CLINT_M_BASE + 0x0) +/* CLINT_CPU_MINT_SIP : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: .*/ +#define CLINT_CPU_MINT_SIP BIT(0) +#define CLINT_CPU_MINT_SIP_M BIT(0) +#define CLINT_CPU_MINT_SIP_V 1 +#define CLINT_CPU_MINT_SIP_S 0 + +#define CLINT_MINT_MTIMECMP_L_REG (DR_REG_CLINT_M_BASE + 0x4000) +/* CLINT_CPU_MINT_MTIMECMP_L : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define CLINT_CPU_MINT_MTIMECMP_L 0xFFFFFFFF +#define CLINT_CPU_MINT_MTIMECMP_L_M ((CLINT_CPU_MINT_MTIMECMP_L_V)<<(CLINT_CPU_MINT_MTIMECMP_L_S)) +#define CLINT_CPU_MINT_MTIMECMP_L_V 0xFFFFFFFF +#define CLINT_CPU_MINT_MTIMECMP_L_S 0 + +#define CLINT_MINT_MTIMECMP_H_REG (DR_REG_CLINT_M_BASE + 0x4004) +/* CLINT_CPU_MINT_MTIMECMP_H : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define CLINT_CPU_MINT_MTIMECMP_H 0xFFFFFFFF +#define CLINT_CPU_MINT_MTIMECMP_H_M ((CLINT_CPU_MINT_MTIMECMP_H_V)<<(CLINT_CPU_MINT_MTIMECMP_H_S)) +#define CLINT_CPU_MINT_MTIMECMP_H_V 0xFFFFFFFF +#define CLINT_CPU_MINT_MTIMECMP_H_S 0 + +#define CLINT_MINT_TIMECTL_REG (DR_REG_CLINT_M_BASE + 0x4010) +/* CLINT_MINT_SAMPLING_MODE : R/W ;bitpos:[5:4] ;default: 2'b0 ; */ +/*description: .*/ +#define CLINT_MINT_SAMPLING_MODE 0x00000003 +#define CLINT_MINT_SAMPLING_MODE_M ((CLINT_CPU_MINT_TIMECTL_V)<<(CLINT_CPU_MINT_TIMECTL_S)) +#define CLINT_MINT_SAMPLING_MODE_V 0x3 +#define CLINT_MINT_SAMPLING_MODE_S 4 +/* CLINT_MINT_COUNTER_OVERFLOW : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define CLINT_MINT_COUNTER_OVERFLOW (BIT(3)) +#define CLINT_MINT_COUNTER_OVERFLOW_M (BIT(3)) +#define CLINT_MINT_COUNTER_OVERFLOW_V 0x1 +#define CLINT_MINT_COUNTER_OVERFLOW_S 3 +/* CLINT_MINT_COUNTER_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define CLINT_MINT_COUNTER_EN (BIT(0)) +#define CLINT_MINT_COUNTER_EN_M (BIT(0)) +#define CLINT_MINT_COUNTER_EN_V 0x1 +#define CLINT_MINT_COUNTER_EN_S 0 + +#define CLINT_MINT_MTIME_L_REG (DR_REG_CLINT_M_BASE + 0xBFF8) +/* CLINT_CPU_MINT_MTIME_L : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define CLINT_CPU_MINT_MTIME_L 0xFFFFFFFF +#define CLINT_CPU_MINT_MTIME_L_M ((CLINT_CPU_MINT_MTIME_L_V)<<(CLINT_CPU_MINT_MTIME_L_S)) +#define CLINT_CPU_MINT_MTIME_L_V 0xFFFFFFFF +#define CLINT_CPU_MINT_MTIME_L_S 0 + +#define CLINT_MINT_MTIME_H_REG (DR_REG_CLINT_M_BASE + 0xBFFC) +/* CLINT_CPU_MINT_MTIME_H : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: .*/ +#define CLINT_CPU_MINT_MTIME_H 0xFFFFFFFF +#define CLINT_CPU_MINT_MTIME_H_M ((CLINT_CPU_MINT_MTIME_H_V)<<(CLINT_CPU_MINT_MTIME_H_S)) +#define CLINT_CPU_MINT_MTIME_H_V 0xFFFFFFFF +#define CLINT_CPU_MINT_MTIME_H_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/beta3/include/soc/hp_system_reg.h b/components/soc/esp32c5/beta3/include/soc/hp_system_reg.h index d6bcde83a6..99acf2448e 100644 --- a/components/soc/esp32c5/beta3/include/soc/hp_system_reg.h +++ b/components/soc/esp32c5/beta3/include/soc/hp_system_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -71,7 +71,7 @@ extern "C" { * 0: anti-DPA disable. 1~3: anti-DPA enable with different security level. The larger * the number, the stronger the ability to resist DPA attacks and the higher the * security level, but it will increase the computational overhead of the hardware - * crypto-accelerators. Only avaliable if HP_SYS_SEC_DPA_CFG_SEL is 0. + * crypto-accelerators. Only available if HP_SYS_SEC_DPA_CFG_SEL is 0. */ #define HP_SYS_SEC_DPA_LEVEL 0x00000003U #define HP_SYS_SEC_DPA_LEVEL_M (HP_SYS_SEC_DPA_LEVEL_V << HP_SYS_SEC_DPA_LEVEL_S) diff --git a/components/soc/esp32c5/beta3/include/soc/periph_defs.h b/components/soc/esp32c5/beta3/include/soc/periph_defs.h index 4f874392d1..99aca9c24b 100644 --- a/components/soc/esp32c5/beta3/include/soc/periph_defs.h +++ b/components/soc/esp32c5/beta3/include/soc/periph_defs.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/components/soc/esp32c5/beta3/include/soc/pmu_struct.h b/components/soc/esp32c5/beta3/include/soc/pmu_struct.h index 5d06311895..2cd967c42c 100644 --- a/components/soc/esp32c5/beta3/include/soc/pmu_struct.h +++ b/components/soc/esp32c5/beta3/include/soc/pmu_struct.h @@ -554,7 +554,9 @@ typedef union { typedef union { struct { - uint32_t reserved0 : 26; + uint32_t reserved0 : 24; + uint32_t xpd_tc5g_i2c : 1; + uint32_t xpd_rx5g_i2c : 1; uint32_t perif_i2c_rstb: 1; uint32_t xpd_perif_i2c : 1; uint32_t xpd_txrf_i2c : 1; diff --git a/components/soc/esp32c5/beta3/include/soc/reg_base.h b/components/soc/esp32c5/beta3/include/soc/reg_base.h index a929799f1f..c3fed9c37f 100644 --- a/components/soc/esp32c5/beta3/include/soc/reg_base.h +++ b/components/soc/esp32c5/beta3/include/soc/reg_base.h @@ -72,6 +72,7 @@ #define DR_REG_MODEM_PWR_BASE 0x600AD000 #define DR_REG_I2C_ANA_MST_BASE 0x600AF800 +#define PWDET_CONF_REG 0x600A0810 /** * @brief LP System (RTC) Modules * @@ -101,3 +102,4 @@ #define DR_REG_ASSIST_DEBUG_BASE 0x600C2000 #define DR_REG_INTPRI_BASE 0x600C5000 #define DR_REG_CACHE_BASE 0x600C8000 // CACHE_CONFIG/EXTMEM +#define DR_REG_CLINT_M_BASE 0x20000000 diff --git a/components/soc/esp32c5/beta3/include/soc/soc_caps.h b/components/soc/esp32c5/beta3/include/soc/soc_caps.h index 54b70d0df7..029362a79d 100644 --- a/components/soc/esp32c5/beta3/include/soc/soc_caps.h +++ b/components/soc/esp32c5/beta3/include/soc/soc_caps.h @@ -59,10 +59,10 @@ // #define SOC_SECURE_BOOT_SUPPORTED 1 // TODO: [ESP32C5] IDF-8623 // #define SOC_BOD_SUPPORTED 1 // TODO: [ESP32C5] IDF-8647 // #define SOC_APM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8614, IDF-8615 -// #define SOC_PMU_SUPPORTED 1 // TODO: [ESP32C5] IDF-8667 +#define SOC_PMU_SUPPORTED 1 // TODO: [ESP32C5] IDF-8667 // #define SOC_PAU_SUPPORTED 1 // TODO: [ESP32C5] IDF-8638, IDF-8640 -// #define SOC_LP_TIMER_SUPPORTED 1 // TODO: [ESP32C5] IDF-8636 -// #define SOC_LP_AON_SUPPORTED 1 // TODO: [ESP32C5] IDF-8638, IDF-8640 +#define SOC_LP_TIMER_SUPPORTED 1 // TODO: [ESP32C5] IDF-8636 +#define SOC_LP_AON_SUPPORTED 1 // TODO: [ESP32C5] IDF-8638, IDF-8640 #define SOC_LP_PERIPHERALS_SUPPORTED 1 // #define SOC_LP_I2C_SUPPORTED 1 // TODO: [ESP32C5] IDF-8634 #define SOC_ULP_SUPPORTED 1 @@ -431,8 +431,8 @@ // #define SOC_SYSTIMER_SUPPORT_ETM 1 // Systimer comparator can generate ETM event /*-------------------------- LP_TIMER CAPS ----------------------------------*/ -// #define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part -// #define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part +#define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part +#define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part /*--------------------------- TIMER GROUP CAPS ---------------------------------------*/ #define SOC_TIMER_GROUPS (2) @@ -524,17 +524,17 @@ // #define SOC_PM_SUPPORT_MAC_BB_PD (1) #define SOC_PM_SUPPORT_RTC_PERIPH_PD (1) -// #define SOC_PM_SUPPORT_PMU_MODEM_STATE (1) +#define SOC_PM_SUPPORT_PMU_MODEM_STATE (0) /* macro redefine for pass esp_wifi headers md5sum check */ -// #define MAC_SUPPORT_PMU_MODEM_STATE SOC_PM_SUPPORT_PMU_MODEM_STATE +#define MAC_SUPPORT_PMU_MODEM_STATE SOC_PM_SUPPORT_PMU_MODEM_STATE -// #define SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY (1) /*!