From 535afdd7f45a7481b2483239abe594070cdb73e7 Mon Sep 17 00:00:00 2001 From: wanlei Date: Thu, 21 Mar 2024 14:32:55 +0800 Subject: [PATCH] feat(esp32c61): ci enable header check, fix c61 build --- .gitlab/ci/host-test.yml | 1 + components/driver/CMakeLists.txt | 6 +- .../deprecated/driver/adc_types_legacy.h | 2 +- .../efuse/esp32c61/esp_efuse_rtc_calib.c | 2 +- .../esp32c61/include/esp_efuse_rtc_calib.h | 2 +- components/esp_adc/CMakeLists.txt | 36 +- .../esp32c61/include/adc_cali_schemes.h | 16 + components/esp_driver_spi/CMakeLists.txt | 16 +- .../esp_driver_spi/src/gpspi/spi_common.c | 2 - .../include/esp_private/spi_share_hw_ctrl.h | 3 + .../port/esp32c61/CMakeLists.txt | 1 + .../port/esp32c61/esp_cpu_intr.c} | 0 .../esp32c61/include/soc/rtc.h} | 0 .../esp_hw_support/port/esp32c61/systimer.c | 0 components/esp_phy/CMakeLists.txt | 4 +- .../esp_rom/esp32c61/Kconfig.soc_caps.in | 4 - components/esp_rom/esp32c61/esp_rom_caps.h | 1 - .../esp_rom/esp32c61/ld/esp32c61.rom.api.ld | 2 +- .../esp_rom/include/esp32c61/rom/ecdsa.h | 2 +- components/espcoredump/CMakeLists.txt | 4 + .../hal/esp32c61/include/hal/timer_ll.h | 24 +- components/hal/include/hal/modem_clock_hal.h | 2 +- components/hal/include/hal/rtc_hal.h | 4 +- components/hal/include/hal/sha_types.h | 2 + .../esp32c61/include/soc/Kconfig.soc_caps.in | 112 +----- .../soc/esp32c61/include/soc/gdma_channel.h | 7 + .../soc/esp32c61/include/soc/gpio_num.h | 10 +- .../soc/esp32c61/include/soc/gpio_struct.h | 352 +----------------- .../soc/esp32c61/include/soc/sha_struct.h | 96 ++--- .../soc/esp32c61/include/soc/soc_caps.h | 78 ++-- .../soc/esp32c61/include/soc/soc_pins.h | 16 + .../include/soc/system_periph_retention.h | 102 ----- components/spi_flash/esp_flash_spi_init.c | 2 - .../env_caps/esp32c61/Kconfig.env_caps | 15 + tools/test_apps/.build-test-rules.yml | 2 +- .../test_apps/system/g0_components/README.md | 4 +- 36 files changed, 226 insertions(+), 706 deletions(-) create mode 100644 components/esp_adc/esp32c61/include/adc_cali_schemes.h rename components/{esp_adc/esp32c61/include/.gitkeep => esp_hw_support/port/esp32c61/esp_cpu_intr.c} (100%) rename components/esp_hw_support/{include/soc/esp32p4/.gitkeep => port/esp32c61/include/soc/rtc.h} (100%) create mode 100644 components/esp_hw_support/port/esp32c61/systimer.c create mode 100644 components/soc/esp32c61/include/soc/gdma_channel.h create mode 100644 components/soc/esp32c61/include/soc/soc_pins.h delete mode 100644 components/soc/esp32c61/include/soc/system_periph_retention.h create mode 100644 examples/common_components/env_caps/esp32c61/Kconfig.env_caps diff --git a/.gitlab/ci/host-test.yml b/.gitlab/ci/host-test.yml index 39a0863555..8f78b88a38 100644 --- a/.gitlab/ci/host-test.yml +++ b/.gitlab/ci/host-test.yml @@ -32,6 +32,7 @@ check_public_headers: - IDF_TARGET=esp32c5 python tools/ci/check_public_headers.py --jobs 4 --prefix riscv32-esp-elf- - IDF_TARGET=esp32h2 python tools/ci/check_public_headers.py --jobs 4 --prefix riscv32-esp-elf- - IDF_TARGET=esp32p4 python tools/ci/check_public_headers.py --jobs 4 --prefix riscv32-esp-elf- + - IDF_TARGET=esp32c61 python tools/ci/check_public_headers.py --jobs 4 --prefix riscv32-esp-elf- test_nvs_on_host: extends: .host_test_template diff --git a/components/driver/CMakeLists.txt b/components/driver/CMakeLists.txt index 4e09ae6c65..54f12d920d 100644 --- a/components/driver/CMakeLists.txt +++ b/components/driver/CMakeLists.txt @@ -19,10 +19,10 @@ set(ldfragments "") # ADC related source files (dprecated) if(CONFIG_SOC_ADC_SUPPORTED) list(APPEND srcs "deprecated/adc_legacy.c") -endif() -if(CONFIG_SOC_ADC_DMA_SUPPORTED) - list(APPEND srcs "deprecated/adc_dma_legacy.c") + if(CONFIG_SOC_ADC_DMA_SUPPORTED) + list(APPEND srcs "deprecated/adc_dma_legacy.c") + endif() endif() # DAC related source files diff --git a/components/driver/deprecated/driver/adc_types_legacy.h b/components/driver/deprecated/driver/adc_types_legacy.h index 06642a99cc..8ea32f9d47 100644 --- a/components/driver/deprecated/driver/adc_types_legacy.h +++ b/components/driver/deprecated/driver/adc_types_legacy.h @@ -70,7 +70,7 @@ typedef enum { ADC1_CHANNEL_4, /*!< ADC1 channel 4 is GPIO4 */ ADC1_CHANNEL_MAX, } adc1_channel_t; -#elif CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 +#elif CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61 typedef enum { ADC1_CHANNEL_0 = 0, /*!< ADC1 channel 0 is GPIO0 */ ADC1_CHANNEL_1, /*!< ADC1 channel 1 is GPIO1 */ diff --git a/components/efuse/esp32c61/esp_efuse_rtc_calib.c b/components/efuse/esp32c61/esp_efuse_rtc_calib.c index 1146540149..84b6e7db36 100644 --- a/components/efuse/esp32c61/esp_efuse_rtc_calib.c +++ b/components/efuse/esp32c61/esp_efuse_rtc_calib.c @@ -51,7 +51,7 @@ esp_err_t esp_efuse_rtc_calib_get_tsens_val(float* tsens_cal) { // TODO: [ESP32C61] IDF-9303 abort(); - // Currently calibration is not supported on ESP32-C5, IDF-5236 + // Currently calibration is not supported on ESP32-C61 *tsens_cal = 0; return ESP_OK; } diff --git a/components/efuse/esp32c61/include/esp_efuse_rtc_calib.h b/components/efuse/esp32c61/include/esp_efuse_rtc_calib.h index e6eea86d2d..dad36bb85c 100644 --- a/components/efuse/esp32c61/include/esp_efuse_rtc_calib.h +++ b/components/efuse/esp32c61/include/esp_efuse_rtc_calib.h @@ -51,7 +51,7 @@ int esp_efuse_rtc_calib_get_chan_compens(int version, uint32_t adc_unit, uint32_ * @brief Get the calibration digits stored in the efuse, and the corresponding voltage. * * @param version Version of the stored efuse - * @param adc_unit ADC unit (not used on ESP32C6, for compatibility) + * @param adc_unit ADC unit (not used on ESP32C61, for compatibility) * @param atten Attenuation to use * @param out_digi Output buffer of the digits * @param out_vol_mv Output of the voltage, in mV diff --git a/components/esp_adc/CMakeLists.txt b/components/esp_adc/CMakeLists.txt index e8a3e96aef..633c954959 100644 --- a/components/esp_adc/CMakeLists.txt +++ b/components/esp_adc/CMakeLists.txt @@ -6,25 +6,29 @@ endif() set(includes "include" "interface" "${target}/include" "deprecated/include") -set(srcs "adc_cali.c" - "adc_cali_curve_fitting.c" - "deprecated/esp_adc_cal_common_legacy.c") +set(srcs) if(CONFIG_SOC_ADC_SUPPORTED) - list(APPEND srcs "adc_oneshot.c" "adc_common.c") -endif() + list(APPEND srcs + "adc_oneshot.c" + "adc_common.c" + "adc_cali.c" + "adc_cali_curve_fitting.c" + "deprecated/esp_adc_cal_common_legacy.c" + ) -if(CONFIG_SOC_ADC_DMA_SUPPORTED) - list(APPEND srcs "adc_continuous.c") - if(CONFIG_SOC_ADC_MONITOR_SUPPORTED) - list(APPEND srcs "adc_monitor.c") - endif() - if(CONFIG_SOC_GDMA_SUPPORTED) - list(APPEND srcs "gdma/adc_dma.c") - elseif(${target} STREQUAL "esp32") - list(APPEND srcs "esp32/adc_dma.c") - elseif(${target} STREQUAL "esp32s2") - list(APPEND srcs "esp32s2/adc_dma.c") + if(CONFIG_SOC_ADC_DMA_SUPPORTED) + list(APPEND srcs "adc_continuous.c") + if(CONFIG_SOC_ADC_MONITOR_SUPPORTED) + list(APPEND srcs "adc_monitor.c") + endif() + if(CONFIG_SOC_GDMA_SUPPORTED) + list(APPEND srcs "gdma/adc_dma.c") + elseif(${target} STREQUAL "esp32") + list(APPEND srcs "esp32/adc_dma.c") + elseif(${target} STREQUAL "esp32s2") + list(APPEND srcs "esp32s2/adc_dma.c") + endif() endif() endif() diff --git a/components/esp_adc/esp32c61/include/adc_cali_schemes.h b/components/esp_adc/esp32c61/include/adc_cali_schemes.h new file mode 100644 index 0000000000..0961c48691 --- /dev/null +++ b/components/esp_adc/esp32c61/include/adc_cali_schemes.h @@ -0,0 +1,16 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +/** + * @file adc_cali_schemes.h + * + * @brief Supported calibration schemes + */ + +// TODO: [ESP32C61] IDF-9303 +// #define ADC_CALI_SCHEME_CURVE_FITTING_SUPPORTED 1 diff --git a/components/esp_driver_spi/CMakeLists.txt b/components/esp_driver_spi/CMakeLists.txt index a2c123ab76..0cf3680cac 100644 --- a/components/esp_driver_spi/CMakeLists.txt +++ b/components/esp_driver_spi/CMakeLists.txt @@ -9,14 +9,16 @@ set(srcs "") set(public_include "include") if(CONFIG_SOC_GPSPI_SUPPORTED) - list(APPEND srcs "src/gpspi/spi_common.c" - "src/gpspi/spi_master.c" - "src/gpspi/spi_slave.c" - "src/gpspi/spi_dma.c") -endif() + list(APPEND srcs + "src/gpspi/spi_common.c" + "src/gpspi/spi_master.c" + "src/gpspi/spi_slave.c" + "src/gpspi/spi_dma.c" + ) -if(CONFIG_SOC_SPI_SUPPORT_SLAVE_HD_VER2) - list(APPEND srcs "src/gpspi/spi_slave_hd.c") + if(CONFIG_SOC_SPI_SUPPORT_SLAVE_HD_VER2) + list(APPEND srcs "src/gpspi/spi_slave_hd.c") + endif() endif() idf_component_register(SRCS ${srcs} diff --git a/components/esp_driver_spi/src/gpspi/spi_common.c b/components/esp_driver_spi/src/gpspi/spi_common.c index f78559f925..1a06b8c0a2 100644 --- a/components/esp_driver_spi/src/gpspi/spi_common.c +++ b/components/esp_driver_spi/src/gpspi/spi_common.c @@ -771,8 +771,6 @@ void spicommon_cs_free_io(int cs_gpio_num) bool spicommon_bus_using_iomux(spi_host_device_t host) { -#define CHECK_IOMUX_PIN(HOST, PIN_NAME) if (GPIO.func_in_sel_cfg[spi_periph_signal[(HOST)].PIN_NAME##_in].sig_in_sel) return false - CHECK_IOMUX_PIN(host, spid); CHECK_IOMUX_PIN(host, spiq); CHECK_IOMUX_PIN(host, spiwp); diff --git a/components/esp_hw_support/include/esp_private/spi_share_hw_ctrl.h b/components/esp_hw_support/include/esp_private/spi_share_hw_ctrl.h index cc86465590..873bb74d24 100644 --- a/components/esp_hw_support/include/esp_private/spi_share_hw_ctrl.h +++ b/components/esp_hw_support/include/esp_private/spi_share_hw_ctrl.h @@ -9,6 +9,8 @@ #include "soc/soc_caps.h" #include "hal/spi_types.h" +#include "soc/spi_periph.h" +#include "soc/gpio_struct.h" #include "esp_private/periph_ctrl.h" #include "freertos/FreeRTOS.h" @@ -30,6 +32,7 @@ extern "C" { #define BUS_LOCK_DEBUG_EXECUTE_CHECK(x) #endif +#define CHECK_IOMUX_PIN(HOST, PIN_NAME) if (GPIO.func_in_sel_cfg[spi_periph_signal[(HOST)].PIN_NAME##_in].sig_in_sel) return false struct spi_bus_lock_t; struct spi_bus_lock_dev_t; diff --git a/components/esp_hw_support/port/esp32c61/CMakeLists.txt b/components/esp_hw_support/port/esp32c61/CMakeLists.txt index e69de29bb2..59051829f8 100644 --- a/components/esp_hw_support/port/esp32c61/CMakeLists.txt +++ b/components/esp_hw_support/port/esp32c61/CMakeLists.txt @@ -0,0 +1 @@ +target_include_directories(${COMPONENT_LIB} PUBLIC . include) diff --git a/components/esp_adc/esp32c61/include/.gitkeep b/components/esp_hw_support/port/esp32c61/esp_cpu_intr.c similarity index 100% rename from components/esp_adc/esp32c61/include/.gitkeep rename to components/esp_hw_support/port/esp32c61/esp_cpu_intr.c diff --git a/components/esp_hw_support/include/soc/esp32p4/.gitkeep b/components/esp_hw_support/port/esp32c61/include/soc/rtc.h similarity index 100% rename from components/esp_hw_support/include/soc/esp32p4/.gitkeep rename to components/esp_hw_support/port/esp32c61/include/soc/rtc.h diff --git a/components/esp_hw_support/port/esp32c61/systimer.c b/components/esp_hw_support/port/esp32c61/systimer.c new file mode 100644 index 0000000000..e69de29bb2 diff --git a/components/esp_phy/CMakeLists.txt b/components/esp_phy/CMakeLists.txt index 535a87dfc0..11c4b10e0c 100644 --- a/components/esp_phy/CMakeLists.txt +++ b/components/esp_phy/CMakeLists.txt @@ -4,8 +4,8 @@ if(${idf_target} STREQUAL "linux") return() # This component is not supported by the POSIX/Linux simulator endif() -if(IDF_TARGET STREQUAL "esp32p4" OR IDF_TARGET STREQUAL "esp32c5") - # TODO: IDF-7460, IDF-8851 +if(IDF_TARGET STREQUAL "esp32p4" OR IDF_TARGET STREQUAL "esp32c5" OR IDF_TARGET STREQUAL "esp32c61") + # TODO: IDF-7460, IDF-8851, IDF-9553 return() endif() diff --git a/components/esp_rom/esp32c61/Kconfig.soc_caps.in b/components/esp_rom/esp32c61/Kconfig.soc_caps.in index 9ea64682e7..edb2c52a3d 100644 --- a/components/esp_rom/esp32c61/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32c61/Kconfig.soc_caps.in @@ -71,10 +71,6 @@ config ESP_ROM_HAS_VERSION bool default y -config ESP_ROM_REV0_HAS_NO_ECDSA_INTERFACE - bool - default y - config ESP_ROM_WDT_INIT_PATCH bool default y diff --git a/components/esp_rom/esp32c61/esp_rom_caps.h b/components/esp_rom/esp32c61/esp_rom_caps.h index f7b73b796e..a5eea647ef 100644 --- a/components/esp_rom/esp32c61/esp_rom_caps.h +++ b/components/esp_rom/esp32c61/esp_rom_caps.h @@ -25,7 +25,6 @@ #define ESP_ROM_HAS_NEWLIB (1) // ROM has newlib (at least parts of it) functions included #define ESP_ROM_HAS_NEWLIB_NANO_FORMAT (1) // ROM has the newlib nano version of formatting functions #define ESP_ROM_HAS_VERSION (1) // ROM has version/eco information -#define ESP_ROM_REV0_HAS_NO_ECDSA_INTERFACE (1) // ECO 0 does not have ets_ecdsa_verify symbol, future revision will have it #define ESP_ROM_WDT_INIT_PATCH (1) // ROM version does not configure the clock #define ESP_ROM_RAM_APP_NEEDS_MMU_INIT (1) // ROM doesn't init cache MMU when it's a RAM APP, needs MMU hal to init #define ESP_ROM_HAS_SW_FLOAT (1) // ROM has libgcc software floating point emulation functions diff --git a/components/esp_rom/esp32c61/ld/esp32c61.rom.api.ld b/components/esp_rom/esp32c61/ld/esp32c61.rom.api.ld index 421134e7c2..a222538a09 100644 --- a/components/esp_rom/esp32c61/ld/esp32c61.rom.api.ld +++ b/components/esp_rom/esp32c61/ld/esp32c61.rom.api.ld @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/components/esp_rom/include/esp32c61/rom/ecdsa.h b/components/esp_rom/include/esp32c61/rom/ecdsa.h index fbf5b06905..eb6f8bc602 100644 --- a/components/esp_rom/include/esp32c61/rom/ecdsa.h +++ b/components/esp_rom/include/esp32c61/rom/ecdsa.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/components/espcoredump/CMakeLists.txt b/components/espcoredump/CMakeLists.txt index d4d0686c7f..fb87a68e40 100644 --- a/components/espcoredump/CMakeLists.txt +++ b/components/espcoredump/CMakeLists.txt @@ -4,6 +4,10 @@ if(${target} STREQUAL "linux") return() # This component is not supported by the POSIX/Linux simulator endif() +if(${target} STREQUAL "esp32c61") + return() # TODO: [ESP32C61] IDF-9268 +endif() + set(srcs "src/core_dump_init.c" "src/core_dump_common.c" "src/core_dump_flash.c" diff --git a/components/hal/esp32c61/include/hal/timer_ll.h b/components/hal/esp32c61/include/hal/timer_ll.h index eee8f5ea94..f1158a6b5f 100644 --- a/components/hal/esp32c61/include/hal/timer_ll.h +++ b/components/hal/esp32c61/include/hal/timer_ll.h @@ -29,27 +29,27 @@ extern "C" { #define TIMER_LL_ETM_TASK_TABLE(group, timer, task) \ (uint32_t [2][1][GPTIMER_ETM_TASK_MAX]){{{ \ - [GPTIMER_ETM_TASK_START_COUNT] = TIMER0_TASK_CNT_START_TIMER0, \ - [GPTIMER_ETM_TASK_STOP_COUNT] = TIMER0_TASK_CNT_STOP_TIMER0, \ - [GPTIMER_ETM_TASK_EN_ALARM] = TIMER0_TASK_ALARM_START_TIMER0, \ - [GPTIMER_ETM_TASK_RELOAD] = TIMER0_TASK_CNT_RELOAD_TIMER0, \ - [GPTIMER_ETM_TASK_CAPTURE] = TIMER0_TASK_CNT_CAP_TIMER0, \ + [GPTIMER_ETM_TASK_START_COUNT] = TG0_TASK_CNT_START_TIMER0, \ + [GPTIMER_ETM_TASK_STOP_COUNT] = TG0_TASK_CNT_STOP_TIMER0, \ + [GPTIMER_ETM_TASK_EN_ALARM] = TG0_TASK_ALARM_START_TIMER0, \ + [GPTIMER_ETM_TASK_RELOAD] = TG0_TASK_CNT_RELOAD_TIMER0, \ + [GPTIMER_ETM_TASK_CAPTURE] = TG0_TASK_CNT_CAP_TIMER0, \ }}, \ {{ \ - [GPTIMER_ETM_TASK_START_COUNT] = TIMER1_TASK_CNT_START_TIMER0, \ - [GPTIMER_ETM_TASK_STOP_COUNT] = TIMER1_TASK_CNT_STOP_TIMER0, \ - [GPTIMER_ETM_TASK_EN_ALARM] = TIMER1_TASK_ALARM_START_TIMER0, \ - [GPTIMER_ETM_TASK_RELOAD] = TIMER1_TASK_CNT_RELOAD_TIMER0, \ - [GPTIMER_ETM_TASK_CAPTURE] = TIMER1_TASK_CNT_CAP_TIMER0, \ + [GPTIMER_ETM_TASK_START_COUNT] = TG1_TASK_CNT_START_TIMER0, \ + [GPTIMER_ETM_TASK_STOP_COUNT] = TG1_TASK_CNT_STOP_TIMER0, \ + [GPTIMER_ETM_TASK_EN_ALARM] = TG1_TASK_ALARM_START_TIMER0, \ + [GPTIMER_ETM_TASK_RELOAD] = TG1_TASK_CNT_RELOAD_TIMER0, \ + [GPTIMER_ETM_TASK_CAPTURE] = TG1_TASK_CNT_CAP_TIMER0, \ }}, \ }[group][timer][task] #define TIMER_LL_ETM_EVENT_TABLE(group, timer, event) \ (uint32_t [2][1][GPTIMER_ETM_EVENT_MAX]){{{ \ - [GPTIMER_ETM_EVENT_ALARM_MATCH] = TIMER0_EVT_CNT_CMP_TIMER0, \ + [GPTIMER_ETM_EVENT_ALARM_MATCH] = TG0_EVT_CNT_CMP_TIMER0, \ }}, \ {{ \ - [GPTIMER_ETM_EVENT_ALARM_MATCH] = TIMER1_EVT_CNT_CMP_TIMER0, \ + [GPTIMER_ETM_EVENT_ALARM_MATCH] = TG1_EVT_CNT_CMP_TIMER0, \ }}, \ }[group][timer][event] diff --git a/components/hal/include/hal/modem_clock_hal.h b/components/hal/include/hal/modem_clock_hal.h index 910d0809f6..713e458ca6 100644 --- a/components/hal/include/hal/modem_clock_hal.h +++ b/components/hal/include/hal/modem_clock_hal.h @@ -52,4 +52,4 @@ void modem_clock_hal_enable_wifipwr_clock(modem_clock_hal_context_t *hal, bool e } #endif -#endif // SOC_MODEM_CLOCK_IS_INDEPENDENT +#endif // SOC_MODEM_CLOCK_IS_INDEPENDENT && SOC_MODEM_CLOCK_SUPPORTED diff --git a/components/hal/include/hal/rtc_hal.h b/components/hal/include/hal/rtc_hal.h index e78a9451b3..fb87e889f8 100644 --- a/components/hal/include/hal/rtc_hal.h +++ b/components/hal/include/hal/rtc_hal.h @@ -11,11 +11,11 @@ #include "hal/gpio_types.h" #include "sdkconfig.h" -#if !CONFIG_IDF_TARGET_ESP32P4 && ! CONFIG_IDF_TARGET_ESP32C5 //TODO: IDF-7532, [ESP32C5] IDF-8636 +#if !CONFIG_IDF_TARGET_ESP32P4 && !CONFIG_IDF_TARGET_ESP32C5 && !CONFIG_IDF_TARGET_ESP32C61 //TODO: IDF-7532, [ESP32C5] IDF-8636, [ESP32C61] IDF-9244 #if !SOC_LP_TIMER_SUPPORTED #include "hal/rtc_cntl_ll.h" #endif -#endif //#if !CONFIG_IDF_TARGET_ESP32P4 && ! CONFIG_IDF_TARGET_ESP32C5 +#endif //#if !CONFIG_IDF_TARGET_ESP32P4 && !CONFIG_IDF_TARGET_ESP32C5 && !CONFIG_IDF_TARGET_ESP32C61 #if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED #include "hal/rtc_io_ll.h" #endif diff --git a/components/hal/include/hal/sha_types.h b/components/hal/include/hal/sha_types.h index 921660e594..8f76005096 100644 --- a/components/hal/include/hal/sha_types.h +++ b/components/hal/include/hal/sha_types.h @@ -21,6 +21,8 @@ #include "esp32c2/rom/sha.h" #elif CONFIG_IDF_TARGET_ESP32C6 #include "esp32c6/rom/sha.h" +#elif CONFIG_IDF_TARGET_ESP32C61 +#include "esp32c61/rom/sha.h" #elif CONFIG_IDF_TARGET_ESP32C5 #include "esp32c5/rom/sha.h" #elif CONFIG_IDF_TARGET_ESP32H2 diff --git a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in index a1b016f302..92502615ee 100644 --- a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in @@ -59,22 +59,6 @@ config SOC_AES_SUPPORT_AES_256 bool default y -config SOC_ADC_DIG_CTRL_SUPPORTED - bool - default y - -config SOC_ADC_DIG_IIR_FILTER_SUPPORTED - bool - default y - -config SOC_ADC_MONITOR_SUPPORTED - bool - default y - -config SOC_ADC_DMA_SUPPORTED - bool - default y - config SOC_ADC_PERIPH_NUM int default 1 @@ -83,78 +67,10 @@ config SOC_ADC_MAX_CHANNEL_NUM int default 7 -config SOC_ADC_ATTEN_NUM - int - default 4 - -config SOC_ADC_DIGI_CONTROLLER_NUM - int - default 1 - -config SOC_ADC_PATT_LEN_MAX - int - default 8 - -config SOC_ADC_DIGI_MAX_BITWIDTH - int - default 12 - -config SOC_ADC_DIGI_MIN_BITWIDTH - int - default 12 - -config SOC_ADC_DIGI_IIR_FILTER_NUM - int - default 2 - -config SOC_ADC_DIGI_MONITOR_NUM - int - default 2 - -config SOC_ADC_DIGI_RESULT_BYTES - int - default 4 - -config SOC_ADC_DIGI_DATA_BYTES_PER_CONV - int - default 4 - -config SOC_ADC_SAMPLE_FREQ_THRES_HIGH - int - default 83333 - -config SOC_ADC_SAMPLE_FREQ_THRES_LOW - int - default 611 - -config SOC_ADC_RTC_MIN_BITWIDTH - int - default 12 - -config SOC_ADC_RTC_MAX_BITWIDTH - int - default 12 - -config SOC_ADC_CALIBRATION_V1_SUPPORTED - bool - default y - -config SOC_ADC_SELF_HW_CALI_SUPPORTED - bool - default y - -config SOC_ADC_CALIB_CHAN_COMPENS_SUPPORTED - bool - default y - config SOC_ADC_TEMPERATURE_SHARE_INTR bool default y -config SOC_ADC_SHARED_POWER - bool - default y - config SOC_APB_BACKUP_DMA bool default n @@ -231,22 +147,6 @@ config SOC_DS_KEY_CHECK_MAX_WAIT_US int default 1100 -config SOC_AHB_GDMA_VERSION - int - default 1 - -config SOC_GDMA_NUM_GROUPS_MAX - int - default 1 - -config SOC_GDMA_PAIRS_PER_GROUP_MAX - int - default 3 - -config SOC_GDMA_SUPPORT_ETM - bool - default y - config SOC_ETM_GROUPS int default 1 @@ -261,7 +161,7 @@ config SOC_GPIO_PORT config SOC_GPIO_PIN_COUNT int - default 31 + default 25 config SOC_GPIO_ETM_EVENTS_PER_GROUP int @@ -277,11 +177,11 @@ config SOC_GPIO_SUPPORT_RTC_INDEPENDENT config SOC_GPIO_IN_RANGE_MAX int - default 30 + default 21 config SOC_GPIO_OUT_RANGE_MAX int - default 30 + default 21 config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK int @@ -945,11 +845,7 @@ config SOC_UART_NUM config SOC_UART_HP_NUM int - default 2 - -config SOC_UART_LP_NUM - int - default 1 + default 3 config SOC_UART_FIFO_LEN int diff --git a/components/soc/esp32c61/include/soc/gdma_channel.h b/components/soc/esp32c61/include/soc/gdma_channel.h new file mode 100644 index 0000000000..dd3f635e54 --- /dev/null +++ b/components/soc/esp32c61/include/soc/gdma_channel.h @@ -0,0 +1,7 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once diff --git a/components/soc/esp32c61/include/soc/gpio_num.h b/components/soc/esp32c61/include/soc/gpio_num.h index 4b574a3bfb..25ad0c0982 100644 --- a/components/soc/esp32c61/include/soc/gpio_num.h +++ b/components/soc/esp32c61/include/soc/gpio_num.h @@ -38,13 +38,9 @@ typedef enum { GPIO_NUM_19 = 19, /*!< GPIO19, input and output */ GPIO_NUM_20 = 20, /*!< GPIO20, input and output */ GPIO_NUM_21 = 21, /*!< GPIO21, input and output */ - GPIO_NUM_22 = 22, /*!< GPIO22, input and output */ - GPIO_NUM_23 = 23, /*!< GPIO23, input and output */ - GPIO_NUM_24 = 24, /*!< GPIO24, input and output */ - GPIO_NUM_25 = 25, /*!< GPIO25, input and output */ - GPIO_NUM_26 = 26, /*!< GPIO26, input and output */ - GPIO_NUM_27 = 27, /*!< GPIO27, input and output */ - GPIO_NUM_28 = 28, /*!< GPIO28, input and output */ + GPIO_NUM_22 = 22, /*!< GPIO22, NC */ + GPIO_NUM_23 = 23, /*!< GPIO23, NC */ + GPIO_NUM_24 = 24, /*!< GPIO24, NC */ GPIO_NUM_MAX, } gpio_num_t; diff --git a/components/soc/esp32c61/include/soc/gpio_struct.h b/components/soc/esp32c61/include/soc/gpio_struct.h index 18bb9e7566..0a6da97411 100644 --- a/components/soc/esp32c61/include/soc/gpio_struct.h +++ b/components/soc/esp32c61/include/soc/gpio_struct.h @@ -585,7 +585,7 @@ typedef union { */ typedef union { struct { - /** func0_in_sel : R/W; bitpos: [5:0]; default: 48; + /** func_in_sel : R/W; bitpos: [5:0]; default: 48; * Configures to select a pin from the 25 GPIO pins to connect the input signal 0.\\ * 0: Select GPIO0\\ * 1: Select GPIO1\\ @@ -596,340 +596,24 @@ typedef union { * 0x20: A constantly high input\\ * 0x30: A constantly low input\\ */ - uint32_t func0_in_sel:6; - /** func0_in_inv_sel : R/W; bitpos: [6]; default: 0; + uint32_t func_in_sel:6; + /** func_in_inv_sel : R/W; bitpos: [6]; default: 0; * Configures whether or not to invert the input value.\\ * 0: Not invert\\ * 1: Invert\\ */ - uint32_t func0_in_inv_sel:1; - /** sig0_in_sel : R/W; bitpos: [7]; default: 0; + uint32_t func_in_inv_sel:1; + /** sig_in_sel : R/W; bitpos: [7]; default: 0; * Configures whether or not to route signals via GPIO matrix.\\ * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in * IO MUX.\\ * 1: Route signals via GPIO matrix.\\ */ - uint32_t sig0_in_sel:1; + uint32_t sig_in_sel:1; uint32_t reserved_8:24; }; uint32_t val; -} gpio_func0_in_sel_cfg_reg_t; - -/** Type of funcb_in_sel_cfg register - * Configuration register for input signal b - */ -typedef union { - struct { - /** funcb_in_sel : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal b.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ - */ - uint32_t funcb_in_sel:6; - /** funcb_in_inv_sel : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ - */ - uint32_t funcb_in_inv_sel:1; - /** sigb_in_sel : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ - */ - uint32_t sigb_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_funcb_in_sel_cfg_reg_t; - -/** Type of funcc_in_sel_cfg register - * Configuration register for input signal c - */ -typedef union { - struct { - /** funcc_in_sel : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal c.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ - */ - uint32_t funcc_in_sel:6; - /** funcc_in_inv_sel : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ - */ - uint32_t funcc_in_inv_sel:1; - /** sigc_in_sel : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ - */ - uint32_t sigc_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_funcc_in_sel_cfg_reg_t; - -/** Type of funcd_in_sel_cfg register - * Configuration register for input signal d - */ -typedef union { - struct { - /** funcd_in_sel : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal d.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ - */ - uint32_t funcd_in_sel:6; - /** funcd_in_inv_sel : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ - */ - uint32_t funcd_in_inv_sel:1; - /** sigd_in_sel : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ - */ - uint32_t sigd_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_funcd_in_sel_cfg_reg_t; - -/** Type of funce_in_sel_cfg register - * Configuration register for input signal e - */ -typedef union { - struct { - /** funce_in_sel : R/W; bitpos: [5:0]; default: 32; - * Configures to select a pin from the 25 GPIO pins to connect the input signal e.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ - */ - uint32_t funce_in_sel:6; - /** funce_in_inv_sel : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ - */ - uint32_t funce_in_inv_sel:1; - /** sige_in_sel : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ - */ - uint32_t sige_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_funce_in_sel_cfg_reg_t; - -/** Type of funcf_in_sel_cfg register - * Configuration register for input signal f - */ -typedef union { - struct { - /** funcf_in_sel : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal f.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ - */ - uint32_t funcf_in_sel:6; - /** funcf_in_inv_sel : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ - */ - uint32_t funcf_in_inv_sel:1; - /** sigf_in_sel : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ - */ - uint32_t sigf_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_funcf_in_sel_cfg_reg_t; - -/** Type of funcg_in_sel_cfg register - * Configuration register for input signal g - */ -typedef union { - struct { - /** funcg_in_sel : R/W; bitpos: [5:0]; default: 32; - * Configures to select a pin from the 25 GPIO pins to connect the input signal g.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ - */ - uint32_t funcg_in_sel:6; - /** funcg_in_inv_sel : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ - */ - uint32_t funcg_in_inv_sel:1; - /** sigg_in_sel : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ - */ - uint32_t sigg_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_funcg_in_sel_cfg_reg_t; - -/** Type of funch_in_sel_cfg register - * Configuration register for input signal h - */ -typedef union { - struct { - /** funch_in_sel : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal h.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ - */ - uint32_t funch_in_sel:6; - /** funch_in_inv_sel : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ - */ - uint32_t funch_in_inv_sel:1; - /** sigh_in_sel : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ - */ - uint32_t sigh_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_funch_in_sel_cfg_reg_t; - -/** Type of funci_in_sel_cfg register - * Configuration register for input signal i - */ -typedef union { - struct { - /** funci_in_sel : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal i.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ - */ - uint32_t funci_in_sel:6; - /** funci_in_inv_sel : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ - */ - uint32_t funci_in_inv_sel:1; - /** sigi_in_sel : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ - */ - uint32_t sigi_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_funci_in_sel_cfg_reg_t; - -/** Type of funcj_in_sel_cfg register - * Configuration register for input signal j - */ -typedef union { - struct { - /** funcj_in_sel : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal j.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ - */ - uint32_t funcj_in_sel:6; - /** funcj_in_inv_sel : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ - */ - uint32_t funcj_in_inv_sel:1; - /** sigj_in_sel : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ - */ - uint32_t sigj_in_sel:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpio_funcj_in_sel_cfg_reg_t; - +} gpio_func_in_sel_cfg_reg_t; /** Group: Output Configuration Registers */ /** Type of funcn_out_sel_cfg register @@ -1218,26 +902,8 @@ typedef struct { volatile gpio_pin27_reg_t pin27; volatile gpio_pin28_reg_t pin28; uint32_t reserved_138[99]; - volatile gpio_func0_in_sel_cfg_reg_t func0_in_sel_cfg; - uint32_t reserved_2c8[5]; - volatile gpio_funcb_in_sel_cfg_reg_t funcb_in_sel_cfg[12]; - uint32_t reserved_30c[9]; - volatile gpio_funcc_in_sel_cfg_reg_t funcc_in_sel_cfg[9]; - uint32_t reserved_354[5]; - volatile gpio_funcd_in_sel_cfg_reg_t funcd_in_sel_cfg[3]; - uint32_t reserved_374[2]; - volatile gpio_funce_in_sel_cfg_reg_t funce_in_sel_cfg[2]; - uint32_t reserved_384[16]; - volatile gpio_funcf_in_sel_cfg_reg_t funcf_in_sel_cfg[6]; - uint32_t reserved_3dc[2]; - volatile gpio_funcg_in_sel_cfg_reg_t funcg_in_sel_cfg[3]; - uint32_t reserved_3f0[7]; - volatile gpio_funch_in_sel_cfg_reg_t funch_in_sel_cfg[2]; - uint32_t reserved_414[13]; - volatile gpio_funci_in_sel_cfg_reg_t funci_in_sel_cfg[4]; - uint32_t reserved_458[17]; - volatile gpio_funcj_in_sel_cfg_reg_t funcj_in_sel_cfg[4]; - uint32_t reserved_4ac[390]; + volatile gpio_func_in_sel_cfg_reg_t func_in_sel_cfg[256]; //0-255. reserved: 1-5, 18-26, 36-40, 44-45, 48-63, 70-71, 75-81, 84-96, 101-117, 122-255; + uint32_t reserved_4ac[256]; volatile gpio_funcn_out_sel_cfg_reg_t funcn_out_sel_cfg[25]; volatile gpio_func25_out_sel_cfg_reg_t func25_out_sel_cfg; volatile gpio_func26_out_sel_cfg_reg_t func26_out_sel_cfg; diff --git a/components/soc/esp32c61/include/soc/sha_struct.h b/components/soc/esp32c61/include/soc/sha_struct.h index 4cc4ad7d4b..a297423e8f 100644 --- a/components/soc/esp32c61/include/soc/sha_struct.h +++ b/components/soc/esp32c61/include/soc/sha_struct.h @@ -65,7 +65,7 @@ typedef union { /** continue : RO; bitpos: [31:1]; default: 0; * Write 1 to continue Typical SHA calculation. */ - uint32_t continue:31; + uint32_t conti:31; }; uint32_t val; } sha_continue_reg_t; @@ -127,113 +127,113 @@ typedef union { uint32_t val; } sha_t_length_reg_t; -/** Type of 3_mode register +/** Type of mode_3 register * Initial configuration register 0. */ typedef union { struct { - /** 3_mode : R/W; bitpos: [2:0]; default: 0; + /** mode_3 : R/W; bitpos: [2:0]; default: 0; * Sha3 mode */ - uint32_t 3_mode:3; + uint32_t mode_3:3; uint32_t reserved_3:29; }; uint32_t val; } sha_3_mode_reg_t; -/** Type of 3_clean_m register +/** Type of clean_m_3 register * Initial configuration register 1. */ typedef union { struct { - /** 3_clean_m : WO; bitpos: [0]; default: 0; + /** clean_m_3 : WO; bitpos: [0]; default: 0; * Clean Message. */ - uint32_t 3_clean_m:1; + uint32_t clean_m_3:1; uint32_t reserved_1:31; }; uint32_t val; } sha_3_clean_m_reg_t; -/** Type of 3_dma_block_num register +/** Type of dma_block_num_3 register * DMA configuration register 0. */ typedef union { struct { - /** 3_dma_block_num : R/W; bitpos: [5:0]; default: 0; + /** dma_block_num_3 : R/W; bitpos: [5:0]; default: 0; * DMA-SHA3 block number. */ - uint32_t 3_dma_block_num:6; + uint32_t dma_block_num_3:6; uint32_t reserved_6:26; }; uint32_t val; } sha_3_dma_block_num_reg_t; -/** Type of 3_start register +/** Type of start_3 register * Typical SHA3 configuration register 0. */ typedef union { struct { - /** 3_start : WO; bitpos: [0]; default: 0; + /** start_3 : WO; bitpos: [0]; default: 0; * Start typical sha3. */ - uint32_t 3_start:1; + uint32_t start_3:1; uint32_t reserved_1:31; }; uint32_t val; } sha_3_start_reg_t; -/** Type of 3_continue register +/** Type of continue_3 register * Typical SHA3 configuration register 1. */ typedef union { struct { - /** 3_continue : WO; bitpos: [0]; default: 0; + /** continue_3 : WO; bitpos: [0]; default: 0; * Continue typical sha3. */ - uint32_t 3_continue:1; + uint32_t continue_3:1; uint32_t reserved_1:31; }; uint32_t val; } sha_3_continue_reg_t; -/** Type of 3_dma_start register +/** Type of dma_start_3 register * DMA configuration register 1. */ typedef union { struct { - /** 3_dma_start : WO; bitpos: [0]; default: 0; + /** dma_start_3 : WO; bitpos: [0]; default: 0; * Start dma-sha3. */ - uint32_t 3_dma_start:1; + uint32_t dma_start_3:1; uint32_t reserved_1:31; }; uint32_t val; } sha_3_dma_start_reg_t; -/** Type of 3_dma_continue register +/** Type of dma_continue_3 register * DMA configuration register 2. */ typedef union { struct { - /** 3_dma_continue : WO; bitpos: [0]; default: 0; + /** dma_continue_3 : WO; bitpos: [0]; default: 0; * Continue dma-sha3. */ - uint32_t 3_dma_continue:1; + uint32_t dma_continue_3:1; uint32_t reserved_1:31; }; uint32_t val; } sha_3_dma_continue_reg_t; -/** Type of 3_shake_length register +/** Type of shake_length_3 register * DMA configuration register 3. */ typedef union { struct { - /** 3_shake_length : WO; bitpos: [10:0]; default: 50; + /** shake_length_3 : WO; bitpos: [10:0]; default: 50; * SHAKE output hash word length */ - uint32_t 3_shake_length:11; + uint32_t shake_length_3:11; uint32_t reserved_11:21; }; uint32_t val; @@ -307,15 +307,15 @@ typedef union { /** Group: memory type */ /** Group: Status Register */ -/** Type of 3_busy register +/** Type of busy_3 register * Busy register. */ typedef union { struct { - /** 3_busy_reg : RO; bitpos: [0]; default: 0; + /** busy_reg_3 : RO; bitpos: [0]; default: 0; * Sha3 busy state. 1'b0: idle. 1'b1: busy. */ - uint32_t 3_busy_reg:1; + uint32_t busy_reg_3:1; uint32_t reserved_1:31; }; uint32_t val; @@ -323,29 +323,29 @@ typedef union { /** Group: Interrupt Register */ -/** Type of 3_clear_int register +/** Type of clear_int_3 register * Interrupt clear register. */ typedef union { struct { - /** 3_clear_int : WO; bitpos: [0]; default: 0; + /** clear_int_3 : WO; bitpos: [0]; default: 0; * Clear sha3 interrupt. */ - uint32_t 3_clear_int:1; + uint32_t clear_int_3:1; uint32_t reserved_1:31; }; uint32_t val; } sha_3_clear_int_reg_t; -/** Type of 3_int_ena register +/** Type of int_ena_3 register * Interrupt enable register. */ typedef union { struct { - /** 3_int_ena : R/W; bitpos: [0]; default: 0; + /** int_ena_3 : R/W; bitpos: [0]; default: 0; * Sha3 interrupt enable register. 1'b0: disable(default). 1'b1:enable */ - uint32_t 3_int_ena:1; + uint32_t int_ena_3:1; uint32_t reserved_1:31; }; uint32_t val; @@ -358,7 +358,7 @@ typedef struct { volatile sha_t_length_reg_t t_length; volatile sha_dma_block_num_reg_t dma_block_num; volatile sha_start_reg_t start; - volatile sha_continue_reg_t continue; + volatile sha_continue_reg_t conti; volatile sha_busy_reg_t busy; volatile sha_dma_start_reg_t dma_start; volatile sha_dma_continue_reg_t dma_continue; @@ -369,22 +369,22 @@ typedef struct { volatile uint32_t h[16]; volatile uint32_t m[16]; uint32_t reserved_0c0[464]; - volatile sha_3_mode_reg_t 3_mode; - volatile sha_3_clean_m_reg_t 3_clean_m; + volatile sha_3_mode_reg_t mode_3; + volatile sha_3_clean_m_reg_t clean_m_3; uint32_t reserved_808; - volatile sha_3_dma_block_num_reg_t 3_dma_block_num; - volatile sha_3_start_reg_t 3_start; - volatile sha_3_continue_reg_t 3_continue; - volatile sha_3_busy_reg_t 3_busy; - volatile sha_3_dma_start_reg_t 3_dma_start; - volatile sha_3_dma_continue_reg_t 3_dma_continue; - volatile sha_3_clear_int_reg_t 3_clear_int; - volatile sha_3_int_ena_reg_t 3_int_ena; - volatile sha_3_shake_length_reg_t 3_shake_length; + volatile sha_3_dma_block_num_reg_t dma_block_num_3; + volatile sha_3_start_reg_t start_3; + volatile sha_3_continue_reg_t continue_3; + volatile sha_3_busy_reg_t busy_3; + volatile sha_3_dma_start_reg_t dma_start_3; + volatile sha_3_dma_continue_reg_t dma_continue_3; + volatile sha_3_clear_int_reg_t clear_int_3; + volatile sha_3_int_ena_reg_t int_ena_3; + volatile sha_3_shake_length_reg_t shake_length_3; uint32_t reserved_830[52]; - volatile uint32_t 3_m_out[50]; + volatile uint32_t m_out_3[50]; uint32_t reserved_9c8[14]; - volatile uint32_t 3_m[50]; + volatile uint32_t m_3[50]; } sha_dev_t; extern sha_dev_t SHA; diff --git a/components/soc/esp32c61/include/soc/soc_caps.h b/components/soc/esp32c61/include/soc/soc_caps.h index a718ee08da..35c2fa3403 100644 --- a/components/soc/esp32c61/include/soc/soc_caps.h +++ b/components/soc/esp32c61/include/soc/soc_caps.h @@ -51,7 +51,7 @@ // #define SOC_SECURE_BOOT_SUPPORTED 1 //TODO: [ESP32C61] IDF-9233 // #define SOC_BOD_SUPPORTED 1 //TODO: [ESP32C61] IDF-9254 // #define SOC_APM_SUPPORTED 1 //TODO: [ESP32C61] IDF-9230 -// #define SOC_PMU_SUPPORTED 1 +// #define SOC_PMU_SUPPORTED 1 //TODO: [ESP32C61] IDf-9250 // #define SOC_LP_TIMER_SUPPORTED 1 //TODO: [ESP32C61] IDF-9244 // #define SOC_LP_AON_SUPPORTED 1 // #define SOC_LP_PERIPHERALS_SUPPORTED 1 @@ -88,45 +88,46 @@ #define SOC_AES_SUPPORT_AES_128 (1) #define SOC_AES_SUPPORT_AES_256 (1) +//TODO: [ESP32C61] IDF-9302, IDF-9303, IDF-9304 /*-------------------------- ADC CAPS -------------------------------*/ /*!< SAR ADC Module*/ -#define SOC_ADC_DIG_CTRL_SUPPORTED 1 -#define SOC_ADC_DIG_IIR_FILTER_SUPPORTED 1 -#define SOC_ADC_MONITOR_SUPPORTED 1 -#define SOC_ADC_DIG_SUPPORTED_UNIT(UNIT) 1 //Digital controller supported ADC unit -#define SOC_ADC_DMA_SUPPORTED 1 +// #define SOC_ADC_DIG_CTRL_SUPPORTED 1 +// #define SOC_ADC_DIG_IIR_FILTER_SUPPORTED 1 +// #define SOC_ADC_MONITOR_SUPPORTED 1 +// #define SOC_ADC_DIG_SUPPORTED_UNIT(UNIT) 1 //Digital controller supported ADC unit +// #define SOC_ADC_DMA_SUPPORTED 1 #define SOC_ADC_PERIPH_NUM (1U) -#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (7) #define SOC_ADC_MAX_CHANNEL_NUM (7) -#define SOC_ADC_ATTEN_NUM (4) +// #define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (7) +// #define SOC_ADC_ATTEN_NUM (4) -/*!< Digital */ -#define SOC_ADC_DIGI_CONTROLLER_NUM (1U) -#define SOC_ADC_PATT_LEN_MAX (8) /*!< Two pattern tables, each contains 4 items. Each item takes 1 byte */ -#define SOC_ADC_DIGI_MAX_BITWIDTH (12) -#define SOC_ADC_DIGI_MIN_BITWIDTH (12) -#define SOC_ADC_DIGI_IIR_FILTER_NUM (2) -#define SOC_ADC_DIGI_MONITOR_NUM (2) -#define SOC_ADC_DIGI_RESULT_BYTES (4) -#define SOC_ADC_DIGI_DATA_BYTES_PER_CONV (4) -/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval <= 4095 */ -#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333 -#define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611 +// /*!< Digital */ +// #define SOC_ADC_DIGI_CONTROLLER_NUM (1U) +// #define SOC_ADC_PATT_LEN_MAX (8) /*!< Two pattern tables, each contains 4 items. Each item takes 1 byte */ +// #define SOC_ADC_DIGI_MAX_BITWIDTH (12) +// #define SOC_ADC_DIGI_MIN_BITWIDTH (12) +// #define SOC_ADC_DIGI_IIR_FILTER_NUM (2) +// #define SOC_ADC_DIGI_MONITOR_NUM (2) +// #define SOC_ADC_DIGI_RESULT_BYTES (4) +// #define SOC_ADC_DIGI_DATA_BYTES_PER_CONV (4) +// /*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval <= 4095 */ +// #define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333 +// #define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611 -/*!< RTC */ -#define SOC_ADC_RTC_MIN_BITWIDTH (12) -#define SOC_ADC_RTC_MAX_BITWIDTH (12) +// /*!< RTC */ +// #define SOC_ADC_RTC_MIN_BITWIDTH (12) +// #define SOC_ADC_RTC_MAX_BITWIDTH (12) -/*!< Calibration */ -#define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/ -#define SOC_ADC_SELF_HW_CALI_SUPPORTED (1) /*!< support HW offset self calibration */ -#define SOC_ADC_CALIB_CHAN_COMPENS_SUPPORTED (1) /*!< support channel compensation to the HW offset calibration */ +// /*!< Calibration */ // TODO: [ESP32C61] IDF-9303 +// #define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/ +// #define SOC_ADC_SELF_HW_CALI_SUPPORTED (1) /*!< support HW offset self calibration */ +// #define SOC_ADC_CALIB_CHAN_COMPENS_SUPPORTED (1) /*!< support channel compensation to the HW offset calibration */ /*!< Interrupt */ #define SOC_ADC_TEMPERATURE_SHARE_INTR (1) /*!< ADC power control is shared by PWDET */ -#define SOC_ADC_SHARED_POWER 1 +// #define SOC_ADC_SHARED_POWER 1 /*-------------------------- APB BACKUP DMA CAPS -------------------------------*/ #define SOC_APB_BACKUP_DMA (0) @@ -166,11 +167,12 @@ See TRM DS chapter for more details */ #define SOC_DS_KEY_CHECK_MAX_WAIT_US (1100) +//TODO: [ESP32C61] IDF-9310 /*-------------------------- GDMA CAPS -------------------------------------*/ -#define SOC_AHB_GDMA_VERSION 1U -#define SOC_GDMA_NUM_GROUPS_MAX 1U -#define SOC_GDMA_PAIRS_PER_GROUP_MAX 3 -#define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule +// #define SOC_AHB_GDMA_VERSION 1U +// #define SOC_GDMA_NUM_GROUPS_MAX 1U +// #define SOC_GDMA_PAIRS_PER_GROUP_MAX 3 +// #define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule /*-------------------------- ETM CAPS --------------------------------------*/ #define SOC_ETM_GROUPS 1U // Number of ETM groups @@ -179,7 +181,7 @@ /*-------------------------- GPIO CAPS ---------------------------------------*/ // ESP32-C61 has 1 GPIO peripheral #define SOC_GPIO_PORT 1U -#define SOC_GPIO_PIN_COUNT 31 +#define SOC_GPIO_PIN_COUNT 25 // #define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1 //TODO: [ESP32C61] IDF-9340 // #define SOC_GPIO_FLEX_GLITCH_FILTER_NUM 8 //TODO: [ESP32C61] IDF-9340 @@ -197,8 +199,8 @@ #define SOC_GPIO_VALID_GPIO_MASK ((1U< -#include "soc/soc_caps.h" -#include "soc/regdma.h" - -#ifdef __cplusplus -extern "C" -{ -#endif - -/** - * @brief Provide access to interrupt matrix configuration registers retention - * context defination. - * - * This is an internal function of the sleep retention driver, and is not - * useful for external use. - */ -#define INT_MTX_RETENTION_LINK_LEN 1 -extern const regdma_entries_config_t intr_matrix_regs_retention[INT_MTX_RETENTION_LINK_LEN]; - -/** - * @brief Provide access to hp_system configuration registers retention - * context defination. - * - * This is an internal function of the sleep retention driver, and is not - * useful for external use. - */ -#define HP_SYSTEM_RETENTION_LINK_LEN 1 -extern const regdma_entries_config_t hp_system_regs_retention[HP_SYSTEM_RETENTION_LINK_LEN]; - -/** - * @brief Provide access to TEE_APM configuration registers retention - * context defination. - * - * This is an internal function of the sleep retention driver, and is not - * useful for external use. - */ -#define TEE_APM_RETENTION_LINK_LEN 2 -extern const regdma_entries_config_t tee_apm_regs_retention[TEE_APM_RETENTION_LINK_LEN]; -#define TEE_APM_HIGH_PRI_RETENTION_LINK_LEN 1 -extern const regdma_entries_config_t tee_apm_highpri_regs_retention[TEE_APM_HIGH_PRI_RETENTION_LINK_LEN]; - -/** - * @brief Provide access to uart configuration registers retention - * context defination. - * - * This is an internal function of the sleep retention driver, and is not - * useful for external use. - */ -#define UART_RETENTION_LINK_LEN 3 -extern const regdma_entries_config_t uart_regs_retention[UART_RETENTION_LINK_LEN]; - -/** - * @brief Provide access to timer group configuration registers retention - * context defination. - * - * This is an internal function of the sleep retention driver, and is not - * useful for external use. - */ -#define TIMG_RETENTION_LINK_LEN 8 -extern const regdma_entries_config_t tg_regs_retention[TIMG_RETENTION_LINK_LEN]; - -/** - * @brief Provide access to IOMUX configuration registers retention - * context defination. - * - * This is an internal function of the sleep retention driver, and is not - * useful for external use. - */ -#define IOMUX_RETENTION_LINK_LEN 4 -extern const regdma_entries_config_t iomux_regs_retention[IOMUX_RETENTION_LINK_LEN]; - -/** - * @brief Provide access to spimem configuration registers retention - * context defination. - * - * This is an internal function of the sleep retention driver, and is not - * useful for external use. - */ -#define SPIMEM_RETENTION_LINK_LEN 8 -extern const regdma_entries_config_t spimem_regs_retention[SPIMEM_RETENTION_LINK_LEN]; - -/** - * @brief Provide access to systimer configuration registers retention - * context defination. - * - * This is an internal function of the sleep retention driver, and is not - * useful for external use. - */ -#define SYSTIMER_RETENTION_LINK_LEN 19 -extern const regdma_entries_config_t systimer_regs_retention[SYSTIMER_RETENTION_LINK_LEN]; - -#ifdef __cplusplus -} -#endif diff --git a/components/spi_flash/esp_flash_spi_init.c b/components/spi_flash/esp_flash_spi_init.c index aee5da0c8a..8ba9a8d9f1 100644 --- a/components/spi_flash/esp_flash_spi_init.c +++ b/components/spi_flash/esp_flash_spi_init.c @@ -168,8 +168,6 @@ static bool use_bus_lock(int host_id) static bool bus_using_iomux(spi_host_device_t host) { -#define CHECK_IOMUX_PIN(HOST, PIN_NAME) if (GPIO.func_in_sel_cfg[spi_periph_signal[(HOST)].PIN_NAME##_in].sig_in_sel) return false - CHECK_IOMUX_PIN(host, spid); CHECK_IOMUX_PIN(host, spiq); CHECK_IOMUX_PIN(host, spiwp); diff --git a/examples/common_components/env_caps/esp32c61/Kconfig.env_caps b/examples/common_components/env_caps/esp32c61/Kconfig.env_caps new file mode 100644 index 0000000000..9b197021c9 --- /dev/null +++ b/examples/common_components/env_caps/esp32c61/Kconfig.env_caps @@ -0,0 +1,15 @@ +config ENV_GPIO_RANGE_MIN + int + default 0 + +config ENV_GPIO_RANGE_MAX + int + default 21 + +config ENV_GPIO_IN_RANGE_MAX + int + default ENV_GPIO_RANGE_MAX + +config ENV_GPIO_OUT_RANGE_MAX + int + default ENV_GPIO_RANGE_MAX diff --git a/tools/test_apps/.build-test-rules.yml b/tools/test_apps/.build-test-rules.yml index 58c9378d86..49d07fc0a9 100644 --- a/tools/test_apps/.build-test-rules.yml +++ b/tools/test_apps/.build-test-rules.yml @@ -165,7 +165,7 @@ tools/test_apps/system/eh_frame: tools/test_apps/system/g0_components: enable: - - if: INCLUDE_DEFAULT == 1 or IDF_TARGET in ["esp32p4", "esp32c5"] # preview targets + - if: INCLUDE_DEFAULT == 1 or IDF_TARGET in ["esp32p4", "esp32c5", "esp32c61"] # preview targets tools/test_apps/system/g1_components: diff --git a/tools/test_apps/system/g0_components/README.md b/tools/test_apps/system/g0_components/README.md index 5c05ed3a70..7bcd7e6211 100644 --- a/tools/test_apps/system/g0_components/README.md +++ b/tools/test_apps/system/g0_components/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | # "G0"-components-only app