diff --git a/components/bootloader_support/src/esp32c2/bootloader_esp32c2.c b/components/bootloader_support/src/esp32c2/bootloader_esp32c2.c
index c54da7eb74..a19fa85443 100644
--- a/components/bootloader_support/src/esp32c2/bootloader_esp32c2.c
+++ b/components/bootloader_support/src/esp32c2/bootloader_esp32c2.c
@@ -39,6 +39,7 @@
 #include "esp_efuse.h"
 #include "hal/mmu_hal.h"
 #include "hal/cache_hal.h"
+#include "hal/rwdt_ll.h"
 
 static const char *TAG = "boot.esp32c2";
 
diff --git a/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c b/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c
index 0a6a5925fc..0160b921f1 100644
--- a/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c
+++ b/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c
@@ -44,6 +44,7 @@
 #include "hal/mmu_hal.h"
 #include "hal/cache_hal.h"
 #include "hal/efuse_hal.h"
+#include "hal/rwdt_ll.h"
 
 static const char *TAG = "boot.esp32c3";
 
diff --git a/components/bootloader_support/src/esp32c6/bootloader_esp32c6.c b/components/bootloader_support/src/esp32c6/bootloader_esp32c6.c
index 1e2b4ce501..76fd0b90b3 100644
--- a/components/bootloader_support/src/esp32c6/bootloader_esp32c6.c
+++ b/components/bootloader_support/src/esp32c6/bootloader_esp32c6.c
@@ -44,6 +44,7 @@
 #include "hal/clk_tree_ll.h"
 #include "soc/lp_wdt_reg.h"
 #include "hal/efuse_hal.h"
+#include "hal/lpwdt_ll.h"
 #include "modem/modem_lpcon_reg.h"
 
 static const char *TAG = "boot.esp32c6";
diff --git a/components/bootloader_support/src/esp32h2/bootloader_esp32h2.c b/components/bootloader_support/src/esp32h2/bootloader_esp32h2.c
index 022f796892..e5b23acfe3 100644
--- a/components/bootloader_support/src/esp32h2/bootloader_esp32h2.c
+++ b/components/bootloader_support/src/esp32h2/bootloader_esp32h2.c
@@ -41,6 +41,7 @@
 #include "esp_efuse.h"
 #include "hal/mmu_hal.h"
 #include "hal/cache_hal.h"
+#include "hal/lpwdt_ll.h"
 #include "soc/lp_wdt_reg.h"
 #include "hal/efuse_hal.h"
 #include "modem/modem_lpcon_reg.h"
diff --git a/components/bootloader_support/src/esp32p4/bootloader_esp32p4.c b/components/bootloader_support/src/esp32p4/bootloader_esp32p4.c
index 65b45600da..ddab8547e1 100644
--- a/components/bootloader_support/src/esp32p4/bootloader_esp32p4.c
+++ b/components/bootloader_support/src/esp32p4/bootloader_esp32p4.c
@@ -41,6 +41,7 @@
 #include "hal/mmu_hal.h"
 #include "hal/cache_hal.h"
 #include "hal/clk_tree_ll.h"
+#include "hal/lpwdt_ll.h"
 #include "soc/lp_wdt_reg.h"
 #include "hal/efuse_hal.h"
 
diff --git a/components/bootloader_support/src/esp32s3/bootloader_esp32s3.c b/components/bootloader_support/src/esp32s3/bootloader_esp32s3.c
index 71f499351c..06b4825a3a 100644
--- a/components/bootloader_support/src/esp32s3/bootloader_esp32s3.c
+++ b/components/bootloader_support/src/esp32s3/bootloader_esp32s3.c
@@ -38,6 +38,7 @@
 #include "esp_efuse.h"
 #include "hal/mmu_hal.h"
 #include "hal/cache_hal.h"
+#include "hal/rwdt_ll.h"
 #include "xtensa/config/core.h"
 #include "xt_instr_macros.h"
 
diff --git a/components/esp_hw_support/rtc_wdt.c b/components/esp_hw_support/rtc_wdt.c
index d1074073fb..43ee972868 100644
--- a/components/esp_hw_support/rtc_wdt.c
+++ b/components/esp_hw_support/rtc_wdt.c
@@ -7,6 +7,7 @@
 #include "rtc_wdt.h"
 #include "soc/rtc.h"
 #include "hal/efuse_ll.h"
+#include "hal/rwdt_ll.h"
 
 #if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2
 
diff --git a/components/esp_hw_support/sleep_system_peripheral.c b/components/esp_hw_support/sleep_system_peripheral.c
index 17fca8cc5f..df558b9594 100644
--- a/components/esp_hw_support/sleep_system_peripheral.c
+++ b/components/esp_hw_support/sleep_system_peripheral.c
@@ -28,6 +28,7 @@
 #include "soc/gpio_reg.h"
 #include "soc/io_mux_reg.h"
 #include "soc/interrupt_matrix_reg.h"
+#include "hal/mwdt_ll.h"
 
 static __attribute__((unused)) const char *TAG = "sleep_sys_periph";
 
diff --git a/components/esp_system/port/soc/esp32/highint_hdl.S b/components/esp_system/port/soc/esp32/highint_hdl.S
index 65f9eaebcf..a27f0e6bfd 100644
--- a/components/esp_system/port/soc/esp32/highint_hdl.S
+++ b/components/esp_system/port/soc/esp32/highint_hdl.S
@@ -70,6 +70,7 @@ Interrupt , a high-priority interrupt, is used for several things:
 #define TIMG1_WDT_STG1_HOLD_OFFSET          TIMG1_REG_OFFSET(TIMG_WDTCONFIG3_REG(1))
 #define TIMG1_WDT_FEED_OFFSET               TIMG1_REG_OFFSET(TIMG_WDTFEED_REG(1))
 #define UART0_DATA_REG                      (0x3FF40078)
+#define TIMG_WDT_WKEY_VALUE                 0x50D83AA1
 #define ETS_TG1_WDT_LEVEL_INTR_SOURCE       20
 
     .macro wdt_clr_intr_status  dev
diff --git a/components/hal/esp32/include/hal/mwdt_ll.h b/components/hal/esp32/include/hal/mwdt_ll.h
index 2741c47057..c60c16d510 100644
--- a/components/hal/esp32/include/hal/mwdt_ll.h
+++ b/components/hal/esp32/include/hal/mwdt_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -26,6 +26,25 @@ extern "C" {
 /* Pre-calculated prescaler to achieve 500 ticks/us (MWDT1_TICKS_PER_US) when using default clock (MWDT_CLK_SRC_DEFAULT ) */
 #define MWDT_LL_DEFAULT_CLK_PRESCALER 40000
 
+/* The value that needs to be written to TIMG_WDT_WKEY to write-enable the wdt registers */
+#define TIMG_WDT_WKEY_VALUE 0x50D83AA1
+
+/* Possible values for TIMG_WDT_STGx */
+#define TIMG_WDT_STG_SEL_OFF 0
+#define TIMG_WDT_STG_SEL_INT 1
+#define TIMG_WDT_STG_SEL_RESET_CPU 2
+#define TIMG_WDT_STG_SEL_RESET_SYSTEM 3
+
+/* Possible values for TIMG_WDT_CPU_RESET_LENGTH and TIMG_WDT_SYS_RESET_LENGTH */
+#define TIMG_WDT_RESET_LENGTH_100_NS    0
+#define TIMG_WDT_RESET_LENGTH_200_NS    1
+#define TIMG_WDT_RESET_LENGTH_300_NS    2
+#define TIMG_WDT_RESET_LENGTH_400_NS    3
+#define TIMG_WDT_RESET_LENGTH_500_NS    4
+#define TIMG_WDT_RESET_LENGTH_800_NS    5
+#define TIMG_WDT_RESET_LENGTH_1600_NS   6
+#define TIMG_WDT_RESET_LENGTH_3200_NS   7
+
 //Type check wdt_stage_action_t
 ESP_STATIC_ASSERT(WDT_STAGE_ACTION_OFF == TIMG_WDT_STG_SEL_OFF, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
 ESP_STATIC_ASSERT(WDT_STAGE_ACTION_INT == TIMG_WDT_STG_SEL_INT, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
diff --git a/components/hal/esp32/include/hal/rwdt_ll.h b/components/hal/esp32/include/hal/rwdt_ll.h
index bf83efcb81..7047858bd8 100644
--- a/components/hal/esp32/include/hal/rwdt_ll.h
+++ b/components/hal/esp32/include/hal/rwdt_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -21,6 +21,19 @@ extern "C" {
 #include "esp_attr.h"
 #include "esp_assert.h"
 
+/* The value that needs to be written to RTC_CNTL_WDT_WKEY to write-enable the wdt registers */
+#define RTC_CNTL_WDT_WKEY_VALUE 0x50D83AA1
+
+/* Possible values for RTC_CNTL_WDT_CPU_RESET_LENGTH and RTC_CNTL_WDT_SYS_RESET_LENGTH */
+#define RTC_WDT_RESET_LENGTH_100_NS    0
+#define RTC_WDT_RESET_LENGTH_200_NS    1
+#define RTC_WDT_RESET_LENGTH_300_NS    2
+#define RTC_WDT_RESET_LENGTH_400_NS    3
+#define RTC_WDT_RESET_LENGTH_500_NS    4
+#define RTC_WDT_RESET_LENGTH_800_NS    5
+#define RTC_WDT_RESET_LENGTH_1600_NS   6
+#define RTC_WDT_RESET_LENGTH_3200_NS   7
+
 //Type check wdt_stage_action_t
 ESP_STATIC_ASSERT(WDT_STAGE_ACTION_OFF == RTC_WDT_STG_SEL_OFF, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
 ESP_STATIC_ASSERT(WDT_STAGE_ACTION_INT == RTC_WDT_STG_SEL_INT, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
diff --git a/components/hal/esp32c2/include/hal/mwdt_ll.h b/components/hal/esp32c2/include/hal/mwdt_ll.h
index 4841116fa3..1fe9d77d6c 100644
--- a/components/hal/esp32c2/include/hal/mwdt_ll.h
+++ b/components/hal/esp32c2/include/hal/mwdt_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -26,6 +26,25 @@ extern "C" {
 /* Pre-calculated prescaler to achieve 500 ticks/us (MWDT1_TICKS_PER_US) when using default clock (MWDT_CLK_SRC_DEFAULT ) */
 #define MWDT_LL_DEFAULT_CLK_PRESCALER 20000
 
+/* The value that needs to be written to TIMG_WDT_WKEY to write-enable the wdt registers */
+#define TIMG_WDT_WKEY_VALUE 0x50D83AA1
+
+/* Possible values for TIMG_WDT_STGx */
+#define TIMG_WDT_STG_SEL_OFF 0
+#define TIMG_WDT_STG_SEL_INT 1
+#define TIMG_WDT_STG_SEL_RESET_CPU 2
+#define TIMG_WDT_STG_SEL_RESET_SYSTEM 3
+
+/* Possible values for TIMG_WDT_CPU_RESET_LENGTH and TIMG_WDT_SYS_RESET_LENGTH */
+#define TIMG_WDT_RESET_LENGTH_100_NS    0
+#define TIMG_WDT_RESET_LENGTH_200_NS    1
+#define TIMG_WDT_RESET_LENGTH_300_NS    2
+#define TIMG_WDT_RESET_LENGTH_400_NS    3
+#define TIMG_WDT_RESET_LENGTH_500_NS    4
+#define TIMG_WDT_RESET_LENGTH_800_NS    5
+#define TIMG_WDT_RESET_LENGTH_1600_NS   6
+#define TIMG_WDT_RESET_LENGTH_3200_NS   7
+
 //Type check wdt_stage_action_t
 STATIC_HAL_REG_CHECK("mwdt", WDT_STAGE_ACTION_OFF, TIMG_WDT_STG_SEL_OFF);
 STATIC_HAL_REG_CHECK("mwdt", WDT_STAGE_ACTION_INT, TIMG_WDT_STG_SEL_INT);
diff --git a/components/hal/esp32c2/include/hal/rwdt_ll.h b/components/hal/esp32c2/include/hal/rwdt_ll.h
index d782b59754..cd210ea501 100644
--- a/components/hal/esp32c2/include/hal/rwdt_ll.h
+++ b/components/hal/esp32c2/include/hal/rwdt_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -21,6 +21,21 @@ extern "C" {
 #include "esp_attr.h"
 #include "esp_assert.h"
 
+/* The value that needs to be written to RTC_CNTL_WDT_WKEY to write-enable the wdt registers */
+#define RTC_CNTL_WDT_WKEY_VALUE 0x50D83AA1
+/* The value that needs to be written to RTC_CNTL_SWD_WPROTECT_REG to write-enable the wdt registers */
+#define RTC_CNTL_SWD_WKEY_VALUE 0x8F1D312A
+
+/* Possible values for RTC_CNTL_WDT_CPU_RESET_LENGTH and RTC_CNTL_WDT_SYS_RESET_LENGTH */
+#define RTC_WDT_RESET_LENGTH_100_NS    0
+#define RTC_WDT_RESET_LENGTH_200_NS    1
+#define RTC_WDT_RESET_LENGTH_300_NS    2
+#define RTC_WDT_RESET_LENGTH_400_NS    3
+#define RTC_WDT_RESET_LENGTH_500_NS    4
+#define RTC_WDT_RESET_LENGTH_800_NS    5
+#define RTC_WDT_RESET_LENGTH_1600_NS   6
+#define RTC_WDT_RESET_LENGTH_3200_NS   7
+
 //Type check wdt_stage_action_t
 ESP_STATIC_ASSERT(WDT_STAGE_ACTION_OFF == RTC_WDT_STG_SEL_OFF, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
 ESP_STATIC_ASSERT(WDT_STAGE_ACTION_INT == RTC_WDT_STG_SEL_INT, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
diff --git a/components/hal/esp32c3/include/hal/mwdt_ll.h b/components/hal/esp32c3/include/hal/mwdt_ll.h
index 89b441c47d..de2e795f04 100644
--- a/components/hal/esp32c3/include/hal/mwdt_ll.h
+++ b/components/hal/esp32c3/include/hal/mwdt_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -26,6 +26,25 @@ extern "C" {
 /* Pre-calculated prescaler to achieve 500 ticks/us (MWDT1_TICKS_PER_US) when using default clock (MWDT_CLK_SRC_DEFAULT ) */
 #define MWDT_LL_DEFAULT_CLK_PRESCALER 40000
 
+/* The value that needs to be written to TIMG_WDT_WKEY to write-enable the wdt registers */
+#define TIMG_WDT_WKEY_VALUE 0x50D83AA1
+
+/* Possible values for TIMG_WDT_STGx */
+#define TIMG_WDT_STG_SEL_OFF 0
+#define TIMG_WDT_STG_SEL_INT 1
+#define TIMG_WDT_STG_SEL_RESET_CPU 2
+#define TIMG_WDT_STG_SEL_RESET_SYSTEM 3
+
+/* Possible values for TIMG_WDT_CPU_RESET_LENGTH and TIMG_WDT_SYS_RESET_LENGTH */
+#define TIMG_WDT_RESET_LENGTH_100_NS    0
+#define TIMG_WDT_RESET_LENGTH_200_NS    1
+#define TIMG_WDT_RESET_LENGTH_300_NS    2
+#define TIMG_WDT_RESET_LENGTH_400_NS    3
+#define TIMG_WDT_RESET_LENGTH_500_NS    4
+#define TIMG_WDT_RESET_LENGTH_800_NS    5
+#define TIMG_WDT_RESET_LENGTH_1600_NS   6
+#define TIMG_WDT_RESET_LENGTH_3200_NS   7
+
 //Type check wdt_stage_action_t
 ESP_STATIC_ASSERT(WDT_STAGE_ACTION_OFF == TIMG_WDT_STG_SEL_OFF, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
 ESP_STATIC_ASSERT(WDT_STAGE_ACTION_INT == TIMG_WDT_STG_SEL_INT, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
diff --git a/components/hal/esp32c3/include/hal/rwdt_ll.h b/components/hal/esp32c3/include/hal/rwdt_ll.h
index d943530773..fbbab7706b 100644
--- a/components/hal/esp32c3/include/hal/rwdt_ll.h
+++ b/components/hal/esp32c3/include/hal/rwdt_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -23,6 +23,21 @@ extern "C" {
 #include "esp_attr.h"
 #include "esp_assert.h"
 
+/* The value that needs to be written to RTC_CNTL_WDT_WKEY to write-enable the wdt registers */
+#define RTC_CNTL_WDT_WKEY_VALUE 0x50D83AA1
+/* The value that needs to be written to RTC_CNTL_SWD_WPROTECT_REG to write-enable the wdt registers */
+#define RTC_CNTL_SWD_WKEY_VALUE 0x8F1D312A
+
+/* Possible values for RTC_CNTL_WDT_CPU_RESET_LENGTH and RTC_CNTL_WDT_SYS_RESET_LENGTH */
+#define RTC_WDT_RESET_LENGTH_100_NS    0
+#define RTC_WDT_RESET_LENGTH_200_NS    1
+#define RTC_WDT_RESET_LENGTH_300_NS    2
+#define RTC_WDT_RESET_LENGTH_400_NS    3
+#define RTC_WDT_RESET_LENGTH_500_NS    4
+#define RTC_WDT_RESET_LENGTH_800_NS    5
+#define RTC_WDT_RESET_LENGTH_1600_NS   6
+#define RTC_WDT_RESET_LENGTH_3200_NS   7
+
 //Type check wdt_stage_action_t
 ESP_STATIC_ASSERT(WDT_STAGE_ACTION_OFF == RTC_WDT_STG_SEL_OFF, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
 ESP_STATIC_ASSERT(WDT_STAGE_ACTION_INT == RTC_WDT_STG_SEL_INT, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
diff --git a/components/hal/esp32c6/include/hal/lpwdt_ll.h b/components/hal/esp32c6/include/hal/lpwdt_ll.h
index 0b5e954c2f..46e83e9cde 100644
--- a/components/hal/esp32c6/include/hal/lpwdt_ll.h
+++ b/components/hal/esp32c6/include/hal/lpwdt_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -24,6 +24,22 @@ extern "C" {
 
 #include "esp32c6/rom/ets_sys.h"
 
+// TODO: IDF-5730 (better to rename and move to wdt_types.h?)
+/* The value that needs to be written to LP_WDT_WPROTECT_REG to write-enable the wdt registers */
+#define LP_WDT_WKEY_VALUE 0x50D83AA1
+/* The value that needs to be written to LP_WDT_SWD_WPROTECT_REG to write-enable the swd registers */
+#define LP_WDT_SWD_WKEY_VALUE 0x50D83AA1
+
+/* Possible values for RTC_CNTL_WDT_CPU_RESET_LENGTH and RTC_CNTL_WDT_SYS_RESET_LENGTH */
+#define RTC_WDT_RESET_LENGTH_100_NS    0
+#define RTC_WDT_RESET_LENGTH_200_NS    1
+#define RTC_WDT_RESET_LENGTH_300_NS    2
+#define RTC_WDT_RESET_LENGTH_400_NS    3
+#define RTC_WDT_RESET_LENGTH_500_NS    4
+#define RTC_WDT_RESET_LENGTH_800_NS    5
+#define RTC_WDT_RESET_LENGTH_1600_NS   6
+#define RTC_WDT_RESET_LENGTH_3200_NS   7
+
 // TODO: IDF-5717
 // //Type check wdt_stage_action_t
 // ESP_STATIC_ASSERT(WDT_STAGE_ACTION_OFF == RTC_WDT_STG_SEL_OFF, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
@@ -268,7 +284,7 @@ FORCE_INLINE_ATTR void lpwdt_ll_write_protect_enable(lp_wdt_dev_t *hw)
  */
 FORCE_INLINE_ATTR void lpwdt_ll_write_protect_disable(lp_wdt_dev_t *hw)
 {
-    hw->wprotect.val = RTC_CNTL_WDT_WKEY_VALUE;
+    hw->wprotect.val = LP_WDT_WKEY_VALUE;
 }
 
 /**
diff --git a/components/hal/esp32c6/include/hal/mwdt_ll.h b/components/hal/esp32c6/include/hal/mwdt_ll.h
index 4f447dbd79..aad994a1f8 100644
--- a/components/hal/esp32c6/include/hal/mwdt_ll.h
+++ b/components/hal/esp32c6/include/hal/mwdt_ll.h
@@ -27,6 +27,24 @@ extern "C" {
 /* Pre-calculated prescaler to achieve 500 ticks/us (MWDT1_TICKS_PER_US) when using default clock (MWDT_CLK_SRC_DEFAULT ) */
 #define MWDT_LL_DEFAULT_CLK_PRESCALER 40000
 
+/* The value that needs to be written to TIMG_WDT_WKEY to write-enable the wdt registers */
+#define TIMG_WDT_WKEY_VALUE 0x50D83AA1
+
+/* Possible values for TIMG_WDT_STGx */
+#define TIMG_WDT_STG_SEL_OFF 0
+#define TIMG_WDT_STG_SEL_INT 1
+#define TIMG_WDT_STG_SEL_RESET_CPU 2
+#define TIMG_WDT_STG_SEL_RESET_SYSTEM 3
+
+#define TIMG_WDT_RESET_LENGTH_100_NS 0
+#define TIMG_WDT_RESET_LENGTH_200_NS 1
+#define TIMG_WDT_RESET_LENGTH_300_NS 2
+#define TIMG_WDT_RESET_LENGTH_400_NS 3
+#define TIMG_WDT_RESET_LENGTH_500_NS 4
+#define TIMG_WDT_RESET_LENGTH_800_NS 5
+#define TIMG_WDT_RESET_LENGTH_1600_NS 6
+#define TIMG_WDT_RESET_LENGTH_3200_NS 7
+
 //Type check wdt_stage_action_t
 ESP_STATIC_ASSERT(WDT_STAGE_ACTION_OFF == TIMG_WDT_STG_SEL_OFF, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
 ESP_STATIC_ASSERT(WDT_STAGE_ACTION_INT == TIMG_WDT_STG_SEL_INT, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
diff --git a/components/hal/esp32h2/include/hal/lpwdt_ll.h b/components/hal/esp32h2/include/hal/lpwdt_ll.h
index b6009dbc7b..d3faacde5d 100644
--- a/components/hal/esp32h2/include/hal/lpwdt_ll.h
+++ b/components/hal/esp32h2/include/hal/lpwdt_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -23,6 +23,21 @@ extern "C" {
 
 #include "esp32h2/rom/ets_sys.h"
 
+/* The value that needs to be written to RTC_CNTL_WDT_WKEY to write-enable the wdt registers */
+#define RTC_CNTL_WDT_WKEY_VALUE 0x50D83AA1
+/* The value that needs to be written to LP_WDT_SWD_WPROTECT_REG to write-enable the swd registers */
+#define LP_WDT_SWD_WKEY_VALUE 0x50D83AA1
+
+/* Possible values for RTC_CNTL_WDT_CPU_RESET_LENGTH and RTC_CNTL_WDT_SYS_RESET_LENGTH */
+#define RTC_WDT_RESET_LENGTH_100_NS    0
+#define RTC_WDT_RESET_LENGTH_200_NS    1
+#define RTC_WDT_RESET_LENGTH_300_NS    2
+#define RTC_WDT_RESET_LENGTH_400_NS    3
+#define RTC_WDT_RESET_LENGTH_500_NS    4
+#define RTC_WDT_RESET_LENGTH_800_NS    5
+#define RTC_WDT_RESET_LENGTH_1600_NS   6
+#define RTC_WDT_RESET_LENGTH_3200_NS   7
+
 /**
  * @brief Enable the RWDT
  *
diff --git a/components/hal/esp32h2/include/hal/mwdt_ll.h b/components/hal/esp32h2/include/hal/mwdt_ll.h
index 7e903cf138..a09f16d6a8 100644
--- a/components/hal/esp32h2/include/hal/mwdt_ll.h
+++ b/components/hal/esp32h2/include/hal/mwdt_ll.h
@@ -26,6 +26,24 @@ extern "C" {
 /* Pre-calculated prescaler to achieve 500 ticks/us (MWDT1_TICKS_PER_US) when using default clock (MWDT_CLK_SRC_DEFAULT ) */
 #define MWDT_LL_DEFAULT_CLK_PRESCALER 24000
 
+/* The value that needs to be written to TIMG_WDT_WKEY to write-enable the wdt registers */
+#define TIMG_WDT_WKEY_VALUE 0x50D83AA1
+
+/* Possible values for TIMG_WDT_STGx */
+#define TIMG_WDT_STG_SEL_OFF 0
+#define TIMG_WDT_STG_SEL_INT 1
+#define TIMG_WDT_STG_SEL_RESET_CPU 2
+#define TIMG_WDT_STG_SEL_RESET_SYSTEM 3
+
+#define TIMG_WDT_RESET_LENGTH_100_NS 0
+#define TIMG_WDT_RESET_LENGTH_200_NS 1
+#define TIMG_WDT_RESET_LENGTH_300_NS 2
+#define TIMG_WDT_RESET_LENGTH_400_NS 3
+#define TIMG_WDT_RESET_LENGTH_500_NS 4
+#define TIMG_WDT_RESET_LENGTH_800_NS 5
+#define TIMG_WDT_RESET_LENGTH_1600_NS 6
+#define TIMG_WDT_RESET_LENGTH_3200_NS 7
+
 //Type check wdt_stage_action_t
 ESP_STATIC_ASSERT(WDT_STAGE_ACTION_OFF == TIMG_WDT_STG_SEL_OFF, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
 ESP_STATIC_ASSERT(WDT_STAGE_ACTION_INT == TIMG_WDT_STG_SEL_INT, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
diff --git a/components/hal/esp32p4/include/hal/lpwdt_ll.h b/components/hal/esp32p4/include/hal/lpwdt_ll.h
index 3b8d61613b..be64f2ca74 100644
--- a/components/hal/esp32p4/include/hal/lpwdt_ll.h
+++ b/components/hal/esp32p4/include/hal/lpwdt_ll.h
@@ -24,6 +24,24 @@ extern "C" {
 
 #include "esp32p4/rom/ets_sys.h"
 
+
+// TODO: IDF-5730 (better to rename and move to wdt_types.h?)
+/* The value that needs to be written to LP_WDT_WPROTECT_REG to write-enable the wdt registers */
+#define RTC_CNTL_WDT_WKEY_VALUE 0x50D83AA1
+/* The value that needs to be written to LP_WDT_SWD_WPROTECT_REG to write-enable the swd registers */
+#define LP_WDT_SWD_WKEY_VALUE 0x50D83AA1
+
+/* Possible values for RTC_CNTL_WDT_CPU_RESET_LENGTH and RTC_CNTL_WDT_SYS_RESET_LENGTH */
+#define RTC_WDT_RESET_LENGTH_100_NS    0
+#define RTC_WDT_RESET_LENGTH_200_NS    1
+#define RTC_WDT_RESET_LENGTH_300_NS    2
+#define RTC_WDT_RESET_LENGTH_400_NS    3
+#define RTC_WDT_RESET_LENGTH_500_NS    4
+#define RTC_WDT_RESET_LENGTH_800_NS    5
+#define RTC_WDT_RESET_LENGTH_1600_NS   6
+#define RTC_WDT_RESET_LENGTH_3200_NS   7
+
+
 // TODO: IDF-7539
 // //Type check wdt_stage_action_t
 // ESP_STATIC_ASSERT(WDT_STAGE_ACTION_OFF == RTC_WDT_STG_SEL_OFF, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
diff --git a/components/hal/esp32p4/include/hal/mwdt_ll.h b/components/hal/esp32p4/include/hal/mwdt_ll.h
index 956988d19d..892e592787 100644
--- a/components/hal/esp32p4/include/hal/mwdt_ll.h
+++ b/components/hal/esp32p4/include/hal/mwdt_ll.h
@@ -27,6 +27,23 @@ extern "C" {
 /* Pre-calculated prescaler to achieve 500 ticks/us (MWDT1_TICKS_PER_US) when using default clock (MWDT_CLK_SRC_DEFAULT ) */
 #define MWDT_LL_DEFAULT_CLK_PRESCALER 20000
 
+/* The value that needs to be written to TIMG_WDT_WKEY to write-enable the wdt registers */
+#define TIMG_WDT_WKEY_VALUE 0x50D83AA1
+
+/* Possible values for TIMG_WDT_STGx */
+#define TIMG_WDT_STG_SEL_OFF 0
+#define TIMG_WDT_STG_SEL_INT 1
+#define TIMG_WDT_STG_SEL_RESET_CPU 2
+#define TIMG_WDT_STG_SEL_RESET_SYSTEM 3
+
+#define TIMG_WDT_RESET_LENGTH_100_NS 0
+#define TIMG_WDT_RESET_LENGTH_200_NS 1
+#define TIMG_WDT_RESET_LENGTH_300_NS 2
+#define TIMG_WDT_RESET_LENGTH_400_NS 3
+#define TIMG_WDT_RESET_LENGTH_500_NS 4
+#define TIMG_WDT_RESET_LENGTH_800_NS 5
+#define TIMG_WDT_RESET_LENGTH_1600_NS 6
+#define TIMG_WDT_RESET_LENGTH_3200_NS 7
 
 // //Type check wdt_stage_action_t
 ESP_STATIC_ASSERT(WDT_STAGE_ACTION_OFF == TIMG_WDT_STG_SEL_OFF, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
diff --git a/components/hal/esp32s2/include/hal/mwdt_ll.h b/components/hal/esp32s2/include/hal/mwdt_ll.h
index 2803fe1f2e..0caf6bd864 100644
--- a/components/hal/esp32s2/include/hal/mwdt_ll.h
+++ b/components/hal/esp32s2/include/hal/mwdt_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -26,6 +26,25 @@ extern "C" {
 /* Pre-calculated prescaler to achieve 500 ticks/us (MWDT1_TICKS_PER_US) when using default clock (MWDT_CLK_SRC_DEFAULT ) */
 #define MWDT_LL_DEFAULT_CLK_PRESCALER 40000
 
+/* The value that needs to be written to TIMG_WDT_WKEY to write-enable the wdt registers */
+#define TIMG_WDT_WKEY_VALUE 0x50D83AA1
+
+/* Possible values for TIMG_WDT_STGx */
+#define TIMG_WDT_STG_SEL_OFF 0
+#define TIMG_WDT_STG_SEL_INT 1
+#define TIMG_WDT_STG_SEL_RESET_CPU 2
+#define TIMG_WDT_STG_SEL_RESET_SYSTEM 3
+
+/* Possible values for TIMG_WDT_CPU_RESET_LENGTH and TIMG_WDT_SYS_RESET_LENGTH */
+#define TIMG_WDT_RESET_LENGTH_100_NS    0
+#define TIMG_WDT_RESET_LENGTH_200_NS    1
+#define TIMG_WDT_RESET_LENGTH_300_NS    2
+#define TIMG_WDT_RESET_LENGTH_400_NS    3
+#define TIMG_WDT_RESET_LENGTH_500_NS    4
+#define TIMG_WDT_RESET_LENGTH_800_NS    5
+#define TIMG_WDT_RESET_LENGTH_1600_NS   6
+#define TIMG_WDT_RESET_LENGTH_3200_NS   7
+
 //Type check wdt_stage_action_t
 ESP_STATIC_ASSERT(WDT_STAGE_ACTION_OFF == TIMG_WDT_STG_SEL_OFF, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
 ESP_STATIC_ASSERT(WDT_STAGE_ACTION_INT == TIMG_WDT_STG_SEL_INT, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
diff --git a/components/hal/esp32s2/include/hal/rwdt_ll.h b/components/hal/esp32s2/include/hal/rwdt_ll.h
index c326370a8e..fe963a6f77 100644
--- a/components/hal/esp32s2/include/hal/rwdt_ll.h
+++ b/components/hal/esp32s2/include/hal/rwdt_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -23,6 +23,19 @@ extern "C" {
 #include "esp_attr.h"
 #include "esp_assert.h"
 
+/* The value that needs to be written to RTC_CNTL_WDT_WKEY to write-enable the wdt registers */
+#define RTC_CNTL_WDT_WKEY_VALUE 0x50D83AA1
+
+/* Possible values for RTC_CNTL_WDT_CPU_RESET_LENGTH and RTC_CNTL_WDT_SYS_RESET_LENGTH */
+#define RTC_WDT_RESET_LENGTH_100_NS    0
+#define RTC_WDT_RESET_LENGTH_200_NS    1
+#define RTC_WDT_RESET_LENGTH_300_NS    2
+#define RTC_WDT_RESET_LENGTH_400_NS    3
+#define RTC_WDT_RESET_LENGTH_500_NS    4
+#define RTC_WDT_RESET_LENGTH_800_NS    5
+#define RTC_WDT_RESET_LENGTH_1600_NS   6
+#define RTC_WDT_RESET_LENGTH_3200_NS   7
+
 //Type check wdt_stage_action_t
 ESP_STATIC_ASSERT(WDT_STAGE_ACTION_OFF == RTC_WDT_STG_SEL_OFF, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
 ESP_STATIC_ASSERT(WDT_STAGE_ACTION_INT == RTC_WDT_STG_SEL_INT, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
diff --git a/components/soc/esp32/include/soc/rtc_cntl_reg.h b/components/soc/esp32/include/soc/rtc_cntl_reg.h
index 6cad811552..7313106a58 100644
--- a/components/soc/esp32/include/soc/rtc_cntl_reg.h
+++ b/components/soc/esp32/include/soc/rtc_cntl_reg.h
@@ -1,24 +1,11 @@
 /*
- * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 #ifndef _SOC_RTC_CNTL_REG_H_
 #define _SOC_RTC_CNTL_REG_H_
 
-/* The value that needs to be written to RTC_CNTL_WDT_WKEY to write-enable the wdt registers */
-#define RTC_CNTL_WDT_WKEY_VALUE 0x50D83AA1
-
-/* Possible values for RTC_CNTL_WDT_CPU_RESET_LENGTH and RTC_CNTL_WDT_SYS_RESET_LENGTH */
-#define RTC_WDT_RESET_LENGTH_100_NS    0
-#define RTC_WDT_RESET_LENGTH_200_NS    1
-#define RTC_WDT_RESET_LENGTH_300_NS    2
-#define RTC_WDT_RESET_LENGTH_400_NS    3
-#define RTC_WDT_RESET_LENGTH_500_NS    4
-#define RTC_WDT_RESET_LENGTH_800_NS    5
-#define RTC_WDT_RESET_LENGTH_1600_NS   6
-#define RTC_WDT_RESET_LENGTH_3200_NS   7
-
 #include "soc.h"
 #define RTC_CNTL_OPTIONS0_REG          (DR_REG_RTCCNTL_BASE + 0x0)
 /* RTC_CNTL_SW_SYS_RST : WO ;bitpos:[31] ;default: 1'd0 ; */
diff --git a/components/soc/esp32/include/soc/timer_group_reg.h b/components/soc/esp32/include/soc/timer_group_reg.h
index d8b07fe407..e0566a1b94 100644
--- a/components/soc/esp32/include/soc/timer_group_reg.h
+++ b/components/soc/esp32/include/soc/timer_group_reg.h
@@ -1,5 +1,5 @@
 /**
- * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
  *
  *  SPDX-License-Identifier: Apache-2.0
  */
@@ -12,25 +12,6 @@
 extern "C" {
 #endif
 
-/* The value that needs to be written to TIMG_WDT_WKEY to write-enable the wdt registers */
-#define TIMG_WDT_WKEY_VALUE 0x50D83AA1
-
-/* Possible values for TIMG_WDT_STGx */
-#define TIMG_WDT_STG_SEL_OFF 0
-#define TIMG_WDT_STG_SEL_INT 1
-#define TIMG_WDT_STG_SEL_RESET_CPU 2
-#define TIMG_WDT_STG_SEL_RESET_SYSTEM 3
-
-/* Possible values for TIMG_WDT_CPU_RESET_LENGTH and TIMG_WDT_SYS_RESET_LENGTH */
-#define TIMG_WDT_RESET_LENGTH_100_NS    0
-#define TIMG_WDT_RESET_LENGTH_200_NS    1
-#define TIMG_WDT_RESET_LENGTH_300_NS    2
-#define TIMG_WDT_RESET_LENGTH_400_NS    3
-#define TIMG_WDT_RESET_LENGTH_500_NS    4
-#define TIMG_WDT_RESET_LENGTH_800_NS    5
-#define TIMG_WDT_RESET_LENGTH_1600_NS   6
-#define TIMG_WDT_RESET_LENGTH_3200_NS   7
-
 #define REG_TIMG_BASE(i)       (DR_REG_TIMERGROUP0_BASE + i*0x1000)
 #define TIMG_T0CONFIG_REG(i)          (REG_TIMG_BASE(i) + 0x0000)
 /* TIMG_T0_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
diff --git a/components/soc/esp32c2/include/soc/rtc_cntl_reg.h b/components/soc/esp32c2/include/soc/rtc_cntl_reg.h
index e70fb47603..e5ce9bff06 100644
--- a/components/soc/esp32c2/include/soc/rtc_cntl_reg.h
+++ b/components/soc/esp32c2/include/soc/rtc_cntl_reg.h
@@ -1,27 +1,11 @@
 /*
- * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 #ifndef _SOC_RTC_CNTL_REG_H_
 #define _SOC_RTC_CNTL_REG_H_
 
-/* The value that needs to be written to RTC_CNTL_WDT_WKEY to write-enable the wdt registers */
-#define RTC_CNTL_WDT_WKEY_VALUE 0x50D83AA1
-/* The value that needs to be written to RTC_CNTL_SWD_WPROTECT_REG to write-enable the wdt registers */
-#define RTC_CNTL_SWD_WKEY_VALUE 0x8F1D312A
-
-/* Possible values for RTC_CNTL_WDT_CPU_RESET_LENGTH and RTC_CNTL_WDT_SYS_RESET_LENGTH */
-#define RTC_WDT_RESET_LENGTH_100_NS    0
-#define RTC_WDT_RESET_LENGTH_200_NS    1
-#define RTC_WDT_RESET_LENGTH_300_NS    2
-#define RTC_WDT_RESET_LENGTH_400_NS    3
-#define RTC_WDT_RESET_LENGTH_500_NS    4
-#define RTC_WDT_RESET_LENGTH_800_NS    5
-#define RTC_WDT_RESET_LENGTH_1600_NS   6
-#define RTC_WDT_RESET_LENGTH_3200_NS   7
-
-
 #ifdef __cplusplus
 extern "C" {
 #endif
diff --git a/components/soc/esp32c2/include/soc/timer_group_reg.h b/components/soc/esp32c2/include/soc/timer_group_reg.h
index f92a355c66..67cf62862a 100644
--- a/components/soc/esp32c2/include/soc/timer_group_reg.h
+++ b/components/soc/esp32c2/include/soc/timer_group_reg.h
@@ -1,5 +1,5 @@
 /**
- * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
  *
  *  SPDX-License-Identifier: Apache-2.0
  */
@@ -13,24 +13,6 @@ extern "C" {
 
 #define DR_REG_TIMG_BASE(i) REG_TIMG_BASE(i)
 
-/* The value that needs to be written to TIMG_WDT_WKEY to write-enable the wdt registers */
-#define TIMG_WDT_WKEY_VALUE 0x50D83AA1
-
-/* Possible values for TIMG_WDT_STGx */
-#define TIMG_WDT_STG_SEL_OFF 0
-#define TIMG_WDT_STG_SEL_INT 1
-#define TIMG_WDT_STG_SEL_RESET_CPU 2
-#define TIMG_WDT_STG_SEL_RESET_SYSTEM 3
-
-/* Possible values for TIMG_WDT_CPU_RESET_LENGTH and TIMG_WDT_SYS_RESET_LENGTH */
-#define TIMG_WDT_RESET_LENGTH_100_NS    0
-#define TIMG_WDT_RESET_LENGTH_200_NS    1
-#define TIMG_WDT_RESET_LENGTH_300_NS    2
-#define TIMG_WDT_RESET_LENGTH_400_NS    3
-#define TIMG_WDT_RESET_LENGTH_500_NS    4
-#define TIMG_WDT_RESET_LENGTH_800_NS    5
-#define TIMG_WDT_RESET_LENGTH_1600_NS   6
-#define TIMG_WDT_RESET_LENGTH_3200_NS   7
 
 /** TIMG_T0CONFIG_REG register
  *  Timer 0 configuration register
diff --git a/components/soc/esp32c3/include/soc/rtc_cntl_reg.h b/components/soc/esp32c3/include/soc/rtc_cntl_reg.h
index 55c8cc2cb5..433ca196b3 100644
--- a/components/soc/esp32c3/include/soc/rtc_cntl_reg.h
+++ b/components/soc/esp32c3/include/soc/rtc_cntl_reg.h
@@ -1,27 +1,11 @@
 /*
- * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 #ifndef _SOC_RTC_CNTL_REG_H_
 #define _SOC_RTC_CNTL_REG_H_
 
-/* The value that needs to be written to RTC_CNTL_WDT_WKEY to write-enable the wdt registers */
-#define RTC_CNTL_WDT_WKEY_VALUE 0x50D83AA1
-/* The value that needs to be written to RTC_CNTL_SWD_WPROTECT_REG to write-enable the wdt registers */
-#define RTC_CNTL_SWD_WKEY_VALUE 0x8F1D312A
-
-/* Possible values for RTC_CNTL_WDT_CPU_RESET_LENGTH and RTC_CNTL_WDT_SYS_RESET_LENGTH */
-#define RTC_WDT_RESET_LENGTH_100_NS    0
-#define RTC_WDT_RESET_LENGTH_200_NS    1
-#define RTC_WDT_RESET_LENGTH_300_NS    2
-#define RTC_WDT_RESET_LENGTH_400_NS    3
-#define RTC_WDT_RESET_LENGTH_500_NS    4
-#define RTC_WDT_RESET_LENGTH_800_NS    5
-#define RTC_WDT_RESET_LENGTH_1600_NS   6
-#define RTC_WDT_RESET_LENGTH_3200_NS   7
-
-
 #ifdef __cplusplus
 extern "C" {
 #endif
diff --git a/components/soc/esp32c3/include/soc/timer_group_reg.h b/components/soc/esp32c3/include/soc/timer_group_reg.h
index 4d591035fc..907d4e2c53 100644
--- a/components/soc/esp32c3/include/soc/timer_group_reg.h
+++ b/components/soc/esp32c3/include/soc/timer_group_reg.h
@@ -1,5 +1,5 @@
 /**
- *  SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
  *
  *  SPDX-License-Identifier: Apache-2.0
  */
@@ -13,25 +13,6 @@ extern "C" {
 
 #define DR_REG_TIMG_BASE(i) REG_TIMG_BASE(i)
 
-/* The value that needs to be written to TIMG_WDT_WKEY to write-enable the wdt registers */
-#define TIMG_WDT_WKEY_VALUE 0x50D83AA1
-
-/* Possible values for TIMG_WDT_STGx */
-#define TIMG_WDT_STG_SEL_OFF 0
-#define TIMG_WDT_STG_SEL_INT 1
-#define TIMG_WDT_STG_SEL_RESET_CPU 2
-#define TIMG_WDT_STG_SEL_RESET_SYSTEM 3
-
-/* Possible values for TIMG_WDT_CPU_RESET_LENGTH and TIMG_WDT_SYS_RESET_LENGTH */
-#define TIMG_WDT_RESET_LENGTH_100_NS    0
-#define TIMG_WDT_RESET_LENGTH_200_NS    1
-#define TIMG_WDT_RESET_LENGTH_300_NS    2
-#define TIMG_WDT_RESET_LENGTH_400_NS    3
-#define TIMG_WDT_RESET_LENGTH_500_NS    4
-#define TIMG_WDT_RESET_LENGTH_800_NS    5
-#define TIMG_WDT_RESET_LENGTH_1600_NS   6
-#define TIMG_WDT_RESET_LENGTH_3200_NS   7
-
 /** TIMG_T0CONFIG_REG register
  *  Timer 0 configuration register
  */
diff --git a/components/soc/esp32c6/include/soc/lp_wdt_reg.h b/components/soc/esp32c6/include/soc/lp_wdt_reg.h
index 4b0071c223..f47fa3942f 100644
--- a/components/soc/esp32c6/include/soc/lp_wdt_reg.h
+++ b/components/soc/esp32c6/include/soc/lp_wdt_reg.h
@@ -1,5 +1,5 @@
 /**
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
  *
  *  SPDX-License-Identifier: Apache-2.0
  */
@@ -11,22 +11,6 @@
 extern "C" {
 #endif
 
-// TODO: IDF-5730 (better to rename and move to wdt_types.h?)
-/* The value that needs to be written to LP_WDT_WPROTECT_REG to write-enable the wdt registers */
-#define RTC_CNTL_WDT_WKEY_VALUE 0x50D83AA1
-/* The value that needs to be written to LP_WDT_SWD_WPROTECT_REG to write-enable the swd registers */
-#define LP_WDT_SWD_WKEY_VALUE 0x50D83AA1
-
-/* Possible values for RTC_CNTL_WDT_CPU_RESET_LENGTH and RTC_CNTL_WDT_SYS_RESET_LENGTH */
-#define RTC_WDT_RESET_LENGTH_100_NS    0
-#define RTC_WDT_RESET_LENGTH_200_NS    1
-#define RTC_WDT_RESET_LENGTH_300_NS    2
-#define RTC_WDT_RESET_LENGTH_400_NS    3
-#define RTC_WDT_RESET_LENGTH_500_NS    4
-#define RTC_WDT_RESET_LENGTH_800_NS    5
-#define RTC_WDT_RESET_LENGTH_1600_NS   6
-#define RTC_WDT_RESET_LENGTH_3200_NS   7
-
 /** LP_WDT_CONFIG0_REG register
  *  need_des
  */
diff --git a/components/soc/esp32c6/include/soc/timer_group_reg.h b/components/soc/esp32c6/include/soc/timer_group_reg.h
index 549ad77714..451ee04195 100644
--- a/components/soc/esp32c6/include/soc/timer_group_reg.h
+++ b/components/soc/esp32c6/include/soc/timer_group_reg.h
@@ -11,23 +11,6 @@
 extern "C" {
 #endif
 
-/* The value that needs to be written to TIMG_WDT_WKEY to write-enable the wdt registers */
-#define TIMG_WDT_WKEY_VALUE 0x50D83AA1
-
-/* Possible values for TIMG_WDT_STGx */
-#define TIMG_WDT_STG_SEL_OFF 0
-#define TIMG_WDT_STG_SEL_INT 1
-#define TIMG_WDT_STG_SEL_RESET_CPU 2
-#define TIMG_WDT_STG_SEL_RESET_SYSTEM 3
-
-#define TIMG_WDT_RESET_LENGTH_100_NS 0
-#define TIMG_WDT_RESET_LENGTH_200_NS 1
-#define TIMG_WDT_RESET_LENGTH_300_NS 2
-#define TIMG_WDT_RESET_LENGTH_400_NS 3
-#define TIMG_WDT_RESET_LENGTH_500_NS 4
-#define TIMG_WDT_RESET_LENGTH_800_NS 5
-#define TIMG_WDT_RESET_LENGTH_1600_NS 6
-#define TIMG_WDT_RESET_LENGTH_3200_NS 7
 
 /** TIMG_T0CONFIG_REG register
  *  Timer 0 configuration register
diff --git a/components/soc/esp32h2/include/soc/lp_wdt_reg.h b/components/soc/esp32h2/include/soc/lp_wdt_reg.h
index 6ae1949037..a42bdaec7d 100644
--- a/components/soc/esp32h2/include/soc/lp_wdt_reg.h
+++ b/components/soc/esp32h2/include/soc/lp_wdt_reg.h
@@ -1,5 +1,5 @@
 /**
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
  *
  *  SPDX-License-Identifier: Apache-2.0
  */
@@ -11,22 +11,6 @@
 extern "C" {
 #endif
 
-// ESP32H2-TODO: IDF-5730 better to move to wdt_types.h
-/* The value that needs to be written to RTC_CNTL_WDT_WKEY to write-enable the wdt registers */
-#define RTC_CNTL_WDT_WKEY_VALUE 0x50D83AA1
-/* The value that needs to be written to LP_WDT_SWD_WPROTECT_REG to write-enable the swd registers */
-#define LP_WDT_SWD_WKEY_VALUE 0x50D83AA1
-
-/* Possible values for RTC_CNTL_WDT_CPU_RESET_LENGTH and RTC_CNTL_WDT_SYS_RESET_LENGTH */
-#define RTC_WDT_RESET_LENGTH_100_NS    0
-#define RTC_WDT_RESET_LENGTH_200_NS    1
-#define RTC_WDT_RESET_LENGTH_300_NS    2
-#define RTC_WDT_RESET_LENGTH_400_NS    3
-#define RTC_WDT_RESET_LENGTH_500_NS    4
-#define RTC_WDT_RESET_LENGTH_800_NS    5
-#define RTC_WDT_RESET_LENGTH_1600_NS   6
-#define RTC_WDT_RESET_LENGTH_3200_NS   7
-
 /** LP_WDT_CONFIG0_REG register
  *  need_des
  */
diff --git a/components/soc/esp32h2/include/soc/timer_group_reg.h b/components/soc/esp32h2/include/soc/timer_group_reg.h
index 549ad77714..451ee04195 100644
--- a/components/soc/esp32h2/include/soc/timer_group_reg.h
+++ b/components/soc/esp32h2/include/soc/timer_group_reg.h
@@ -11,23 +11,6 @@
 extern "C" {
 #endif
 
-/* The value that needs to be written to TIMG_WDT_WKEY to write-enable the wdt registers */
-#define TIMG_WDT_WKEY_VALUE 0x50D83AA1
-
-/* Possible values for TIMG_WDT_STGx */
-#define TIMG_WDT_STG_SEL_OFF 0
-#define TIMG_WDT_STG_SEL_INT 1
-#define TIMG_WDT_STG_SEL_RESET_CPU 2
-#define TIMG_WDT_STG_SEL_RESET_SYSTEM 3
-
-#define TIMG_WDT_RESET_LENGTH_100_NS 0
-#define TIMG_WDT_RESET_LENGTH_200_NS 1
-#define TIMG_WDT_RESET_LENGTH_300_NS 2
-#define TIMG_WDT_RESET_LENGTH_400_NS 3
-#define TIMG_WDT_RESET_LENGTH_500_NS 4
-#define TIMG_WDT_RESET_LENGTH_800_NS 5
-#define TIMG_WDT_RESET_LENGTH_1600_NS 6
-#define TIMG_WDT_RESET_LENGTH_3200_NS 7
 
 /** TIMG_T0CONFIG_REG register
  *  Timer 0 configuration register
diff --git a/components/soc/esp32p4/include/soc/timer_group_reg.h b/components/soc/esp32p4/include/soc/timer_group_reg.h
index c1b81b2793..53679d5b04 100644
--- a/components/soc/esp32p4/include/soc/timer_group_reg.h
+++ b/components/soc/esp32p4/include/soc/timer_group_reg.h
@@ -11,24 +11,6 @@
 extern "C" {
 #endif
 
-/* The value that needs to be written to TIMG_WDT_WKEY to write-enable the wdt registers */
-#define TIMG_WDT_WKEY_VALUE 0x50D83AA1
-
-/* Possible values for TIMG_WDT_STGx */
-#define TIMG_WDT_STG_SEL_OFF 0
-#define TIMG_WDT_STG_SEL_INT 1
-#define TIMG_WDT_STG_SEL_RESET_CPU 2
-#define TIMG_WDT_STG_SEL_RESET_SYSTEM 3
-
-#define TIMG_WDT_RESET_LENGTH_100_NS 0
-#define TIMG_WDT_RESET_LENGTH_200_NS 1
-#define TIMG_WDT_RESET_LENGTH_300_NS 2
-#define TIMG_WDT_RESET_LENGTH_400_NS 3
-#define TIMG_WDT_RESET_LENGTH_500_NS 4
-#define TIMG_WDT_RESET_LENGTH_800_NS 5
-#define TIMG_WDT_RESET_LENGTH_1600_NS 6
-#define TIMG_WDT_RESET_LENGTH_3200_NS 7
-
 /** TIMG_T0CONFIG_REG register
  *  Timer 0 configuration register
  */
diff --git a/components/soc/esp32s2/include/soc/rtc_cntl_reg.h b/components/soc/esp32s2/include/soc/rtc_cntl_reg.h
index bd747d13aa..6e78e06977 100644
--- a/components/soc/esp32s2/include/soc/rtc_cntl_reg.h
+++ b/components/soc/esp32s2/include/soc/rtc_cntl_reg.h
@@ -1,24 +1,11 @@
 /*
- * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 #ifndef _SOC_RTC_CNTL_REG_H_
 #define _SOC_RTC_CNTL_REG_H_
 
-/* The value that needs to be written to RTC_CNTL_WDT_WKEY to write-enable the wdt registers */
-#define RTC_CNTL_WDT_WKEY_VALUE 0x50D83AA1
-
-/* Possible values for RTC_CNTL_WDT_CPU_RESET_LENGTH and RTC_CNTL_WDT_SYS_RESET_LENGTH */
-#define RTC_WDT_RESET_LENGTH_100_NS    0
-#define RTC_WDT_RESET_LENGTH_200_NS    1
-#define RTC_WDT_RESET_LENGTH_300_NS    2
-#define RTC_WDT_RESET_LENGTH_400_NS    3
-#define RTC_WDT_RESET_LENGTH_500_NS    4
-#define RTC_WDT_RESET_LENGTH_800_NS    5
-#define RTC_WDT_RESET_LENGTH_1600_NS   6
-#define RTC_WDT_RESET_LENGTH_3200_NS   7
-
 #ifdef __cplusplus
 extern "C" {
 #endif
diff --git a/components/soc/esp32s2/include/soc/timer_group_reg.h b/components/soc/esp32s2/include/soc/timer_group_reg.h
index a74c3e2e5e..a2a7310164 100644
--- a/components/soc/esp32s2/include/soc/timer_group_reg.h
+++ b/components/soc/esp32s2/include/soc/timer_group_reg.h
@@ -1,5 +1,5 @@
 /**
- *  SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
  *
  *  SPDX-License-Identifier: Apache-2.0
  */
@@ -13,24 +13,6 @@ extern "C" {
 
 #define DR_REG_TIMG_BASE(i) REG_TIMG_BASE(i)
 
-/* The value that needs to be written to TIMG_WDT_WKEY to write-enable the wdt registers */
-#define TIMG_WDT_WKEY_VALUE 0x50D83AA1
-
-/* Possible values for TIMG_WDT_STGx */
-#define TIMG_WDT_STG_SEL_OFF 0
-#define TIMG_WDT_STG_SEL_INT 1
-#define TIMG_WDT_STG_SEL_RESET_CPU 2
-#define TIMG_WDT_STG_SEL_RESET_SYSTEM 3
-
-/* Possible values for TIMG_WDT_CPU_RESET_LENGTH and TIMG_WDT_SYS_RESET_LENGTH */
-#define TIMG_WDT_RESET_LENGTH_100_NS    0
-#define TIMG_WDT_RESET_LENGTH_200_NS    1
-#define TIMG_WDT_RESET_LENGTH_300_NS    2
-#define TIMG_WDT_RESET_LENGTH_400_NS    3
-#define TIMG_WDT_RESET_LENGTH_500_NS    4
-#define TIMG_WDT_RESET_LENGTH_800_NS    5
-#define TIMG_WDT_RESET_LENGTH_1600_NS   6
-#define TIMG_WDT_RESET_LENGTH_3200_NS   7
 
 /** TIMG_T0CONFIG_REG register
  *  Timer 0 configuration register