kopia lustrzana https://github.com/espressif/esp-idf
fix(rmt): DMA descriptor alignment respect the cache line size
morris
rodzic
86707a3af6
commit
d97a46160d
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@ -9,6 +9,6 @@ endif()
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idf_component_register(SRCS ${srcs}
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INCLUDE_DIRS ${public_include}
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PRIV_REQUIRES "esp_pm" "esp_driver_gpio"
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PRIV_REQUIRES "esp_pm" "esp_driver_gpio" "esp_mm"
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LDFRAGMENTS "linker.lf"
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)
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@ -66,7 +66,7 @@ static size_t IRAM_ATTR rmt_encode_bytes(rmt_encoder_t *encoder, rmt_channel_han
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// where to put the encoded symbols? DMA buffer or RMT HW memory
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rmt_symbol_word_t *mem_to_nc = NULL;
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if (channel->dma_chan) {
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mem_to_nc = (rmt_symbol_word_t *)RMT_GET_NON_CACHE_ADDR(channel->dma_mem_base);
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mem_to_nc = tx_chan->dma_mem_base_nc;
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} else {
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mem_to_nc = channel->hw_mem_base;
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}
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@ -176,7 +176,7 @@ static size_t IRAM_ATTR rmt_encode_copy(rmt_encoder_t *encoder, rmt_channel_hand
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// where to put the encoded symbols? DMA buffer or RMT HW memory
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rmt_symbol_word_t *mem_to_nc = NULL;
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if (channel->dma_chan) {
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mem_to_nc = (rmt_symbol_word_t *)RMT_GET_NON_CACHE_ADDR(channel->dma_mem_base);
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mem_to_nc = tx_chan->dma_mem_base_nc;
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} else {
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mem_to_nc = channel->hw_mem_base;
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}
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@ -127,7 +127,6 @@ struct rmt_channel_t {
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_Atomic rmt_fsm_t fsm; // channel life cycle specific FSM
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rmt_channel_direction_t direction; // channel direction
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rmt_symbol_word_t *hw_mem_base; // base address of RMT channel hardware memory
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rmt_symbol_word_t *dma_mem_base; // base address of RMT channel DMA buffer
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gdma_channel_handle_t dma_chan; // DMA channel
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esp_pm_lock_handle_t pm_lock; // power management lock
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#if CONFIG_PM_ENABLE
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@ -157,6 +156,8 @@ typedef struct {
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struct rmt_tx_channel_t {
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rmt_channel_t base; // channel base class
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rmt_symbol_word_t *dma_mem_base; // base address of RMT channel DMA buffer
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rmt_symbol_word_t *dma_mem_base_nc; // base address of RMT channel DMA buffer, accessed in non-cached way
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size_t mem_off; // runtime argument, indicating the next writing position in the RMT hardware memory
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size_t mem_end; // runtime argument, indicating the end of current writing region
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size_t ping_pong_symbols; // ping-pong size (half of the RMT channel memory)
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -17,6 +17,7 @@
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#include "esp_log.h"
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#include "esp_check.h"
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#include "esp_memory_utils.h"
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#include "esp_cache.h"
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#include "esp_rom_gpio.h"
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#include "soc/rmt_periph.h"
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#include "soc/rtc.h"
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@ -26,7 +27,6 @@
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#include "driver/gpio.h"
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#include "driver/rmt_rx.h"
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#include "rmt_private.h"
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#include "rom/cache.h"
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#define ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1))
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#define ALIGN_DOWN(num, align) ((num) & ~((align) - 1))
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@ -199,7 +199,10 @@ esp_err_t rmt_new_rx_channel(const rmt_rx_channel_config_t *config, rmt_channel_
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num_dma_nodes = config->mem_block_symbols * sizeof(rmt_symbol_word_t) / RMT_DMA_DESC_BUF_MAX_SIZE + 1;
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num_dma_nodes = MAX(2, num_dma_nodes); // at least 2 DMA nodes for ping-pong
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// DMA descriptors must be placed in internal SRAM
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rx_channel->dma_nodes = heap_caps_aligned_calloc(RMT_DMA_DESC_ALIGN, num_dma_nodes, sizeof(rmt_dma_descriptor_t), mem_caps);
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uint32_t data_cache_line_size = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_INT_MEM, CACHE_TYPE_DATA);
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// the alignment should meet both the DMA and cache requirement
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size_t alignment = MAX(data_cache_line_size, RMT_DMA_DESC_ALIGN);
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rx_channel->dma_nodes = heap_caps_aligned_calloc(alignment, num_dma_nodes, sizeof(rmt_dma_descriptor_t), mem_caps);
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ESP_GOTO_ON_FALSE(rx_channel->dma_nodes, ESP_ERR_NO_MEM, err, TAG, "no mem for rx channel DMA nodes");
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// we will use the non-cached address to manipulate the DMA descriptor, for simplicity
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rx_channel->dma_nodes_nc = (rmt_dma_descriptor_t *)RMT_GET_NON_CACHE_ADDR(rx_channel->dma_nodes);
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@ -345,13 +348,14 @@ esp_err_t rmt_receive(rmt_channel_handle_t channel, void *buffer, size_t buffer_
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size_t last_dma_block_size = 0;
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if (channel->dma_chan) {
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ESP_RETURN_ON_FALSE_ISR(esp_ptr_internal(buffer), ESP_ERR_INVALID_ARG, TAG, "buffer must locate in internal RAM for DMA use");
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#if CONFIG_IDF_TARGET_ESP32P4
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uint32_t data_cache_line_mask = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_INT_MEM, CACHE_TYPE_DATA) - 1;
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ESP_RETURN_ON_FALSE_ISR(((uintptr_t)buffer & data_cache_line_mask) == 0, ESP_ERR_INVALID_ARG, TAG, "buffer must be aligned to cache line size");
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ESP_RETURN_ON_FALSE_ISR((buffer_size & data_cache_line_mask) == 0, ESP_ERR_INVALID_ARG, TAG, "buffer size must be aligned to cache line size");
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#endif
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// Currently we assume the user buffer is allocated from internal RAM, PSRAM is not supported yet.
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ESP_RETURN_ON_FALSE_ISR(esp_ptr_internal(buffer), ESP_ERR_INVALID_ARG, TAG, "user buffer not allocated from internal RAM");
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uint32_t data_cache_line_size = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_INT_MEM, CACHE_TYPE_DATA);
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// DMA doesn't have alignment requirement for SRAM buffer if the burst mode is not enabled,
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// but we need to make sure the buffer is aligned to cache line size
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uint32_t align_mask = data_cache_line_size ? (data_cache_line_size - 1) : 0;
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ESP_RETURN_ON_FALSE_ISR(((uintptr_t)buffer & align_mask) == 0, ESP_ERR_INVALID_ARG, TAG, "buffer address not aligned");
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ESP_RETURN_ON_FALSE_ISR((buffer_size & align_mask) == 0, ESP_ERR_INVALID_ARG, TAG, "buffer size not aligned");
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ESP_RETURN_ON_FALSE_ISR(buffer_size <= rx_chan->num_dma_nodes * RMT_DMA_DESC_BUF_MAX_SIZE,
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ESP_ERR_INVALID_ARG, TAG, "buffer size exceeds DMA capacity");
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per_dma_block_size = buffer_size / rx_chan->num_dma_nodes;
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@ -752,13 +756,11 @@ static bool IRAM_ATTR rmt_dma_rx_one_block_cb(gdma_channel_handle_t dma_chan, gd
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rmt_rx_trans_desc_t *trans_desc = &rx_chan->trans_desc;
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uint32_t channel_id = channel->channel_id;
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#if CONFIG_IDF_TARGET_ESP32P4
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int invalidate_map = CACHE_MAP_L1_DCACHE;
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if (esp_ptr_external_ram((const void *)trans_desc->buffer)) {
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invalidate_map |= CACHE_MAP_L2_CACHE;
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uint32_t data_cache_line_size = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_INT_MEM, CACHE_TYPE_DATA);
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if (data_cache_line_size) {
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// invalidate the user buffer, so that the DMA modified data can be seen by CPU
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esp_cache_msync(trans_desc->buffer, trans_desc->buffer_size, ESP_CACHE_MSYNC_FLAG_DIR_M2C);
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}
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Cache_Invalidate_Addr(invalidate_map, (uint32_t)trans_desc->buffer, trans_desc->buffer_size);
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#endif
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if (event_data->flags.normal_eof) {
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// if the DMA received an EOF, it means the RMT peripheral has received an "end marker"
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -21,6 +21,8 @@
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#include "soc/rtc.h"
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#include "hal/rmt_ll.h"
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#include "hal/gpio_hal.h"
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#include "hal/cache_hal.h"
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#include "hal/cache_ll.h"
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#include "driver/gpio.h"
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#include "driver/rmt_tx.h"
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#include "rmt_private.h"
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@ -47,10 +49,16 @@ static bool rmt_dma_tx_eof_cb(gdma_channel_handle_t dma_chan, gdma_event_data_t
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static esp_err_t rmt_tx_init_dma_link(rmt_tx_channel_t *tx_channel, const rmt_tx_channel_config_t *config)
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{
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rmt_symbol_word_t *dma_mem_base = heap_caps_calloc(1, sizeof(rmt_symbol_word_t) * config->mem_block_symbols,
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RMT_MEM_ALLOC_CAPS | MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL);
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// For simplicity, the encoder will access the dma_mem_base in a non-cached way
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// and we allocate the dma_mem_base from the internal SRAM for performance
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uint32_t data_cache_line_size = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_INT_MEM, CACHE_TYPE_DATA);
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// the alignment should meet both the DMA and cache requirement
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size_t alignment = MAX(data_cache_line_size, sizeof(rmt_symbol_word_t));
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rmt_symbol_word_t *dma_mem_base = heap_caps_aligned_calloc(alignment, config->mem_block_symbols, sizeof(rmt_symbol_word_t),
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RMT_MEM_ALLOC_CAPS | MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL);
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ESP_RETURN_ON_FALSE(dma_mem_base, ESP_ERR_NO_MEM, TAG, "no mem for tx DMA buffer");
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tx_channel->base.dma_mem_base = dma_mem_base;
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tx_channel->dma_mem_base = dma_mem_base;
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tx_channel->dma_mem_base_nc = (rmt_symbol_word_t *)RMT_GET_NON_CACHE_ADDR(dma_mem_base);
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for (int i = 0; i < RMT_DMA_NODES_PING_PONG; i++) {
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// each descriptor shares half of the DMA buffer
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tx_channel->dma_nodes_nc[i].buffer = dma_mem_base + tx_channel->ping_pong_symbols * i;
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@ -193,8 +201,8 @@ static esp_err_t rmt_tx_destroy(rmt_tx_channel_t *tx_channel)
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vQueueDeleteWithCaps(tx_channel->trans_queues[i]);
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}
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}
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if (tx_channel->base.dma_mem_base) {
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free(tx_channel->base.dma_mem_base);
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if (tx_channel->dma_mem_base) {
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free(tx_channel->dma_mem_base);
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}
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if (tx_channel->base.group) {
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// de-register channel from RMT group
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@ -239,9 +247,12 @@ esp_err_t rmt_new_tx_channel(const rmt_tx_channel_config_t *config, rmt_channel_
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ESP_GOTO_ON_FALSE(tx_channel, ESP_ERR_NO_MEM, err, TAG, "no mem for tx channel");
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// create DMA descriptors
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if (config->flags.with_dma) {
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// DMA descriptors must be placed in internal SRAM
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mem_caps |= MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA;
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tx_channel->dma_nodes = heap_caps_aligned_calloc(RMT_DMA_DESC_ALIGN, RMT_DMA_NODES_PING_PONG, sizeof(rmt_dma_descriptor_t), mem_caps);
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// DMA descriptors must be placed in internal SRAM
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uint32_t data_cache_line_size = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_INT_MEM, CACHE_TYPE_DATA);
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// the alignment should meet both the DMA and cache requirement
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size_t alignment = MAX(data_cache_line_size, RMT_DMA_DESC_ALIGN);
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tx_channel->dma_nodes = heap_caps_aligned_calloc(alignment, RMT_DMA_NODES_PING_PONG, sizeof(rmt_dma_descriptor_t), mem_caps);
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ESP_GOTO_ON_FALSE(tx_channel->dma_nodes, ESP_ERR_NO_MEM, err, TAG, "no mem for tx DMA nodes");
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// we will use the non-cached address to manipulate the DMA descriptor, for simplicity
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tx_channel->dma_nodes_nc = (rmt_dma_descriptor_t *)RMT_GET_NON_CACHE_ADDR(tx_channel->dma_nodes);
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@ -327,9 +338,9 @@ esp_err_t rmt_new_tx_channel(const rmt_tx_channel_config_t *config, rmt_channel_
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tx_channel->base.disable = rmt_tx_disable;
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// return general channel handle
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*ret_chan = &tx_channel->base;
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ESP_LOGD(TAG, "new tx channel(%d,%d) at %p, gpio=%d, res=%"PRIu32"Hz, hw_mem_base=%p, dma_mem_base=%p, dma_nodes_nc=%p,ping_pong_size=%zu, queue_depth=%zu",
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ESP_LOGD(TAG, "new tx channel(%d,%d) at %p, gpio=%d, res=%"PRIu32"Hz, hw_mem_base=%p, dma_mem_base=%p, dma_nodes=%p, ping_pong_size=%zu, queue_depth=%zu",
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group_id, channel_id, tx_channel, config->gpio_num, tx_channel->base.resolution_hz,
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tx_channel->base.hw_mem_base, tx_channel->base.dma_mem_base, tx_channel->dma_nodes_nc, tx_channel->ping_pong_symbols, tx_channel->queue_size);
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tx_channel->base.hw_mem_base, tx_channel->dma_mem_base, tx_channel->dma_nodes, tx_channel->ping_pong_symbols, tx_channel->queue_size);
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return ESP_OK;
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err:
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@ -569,7 +580,7 @@ static void IRAM_ATTR rmt_tx_mark_eof(rmt_tx_channel_t *tx_chan)
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rmt_tx_trans_desc_t *cur_trans = tx_chan->cur_trans;
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rmt_dma_descriptor_t *desc_nc = NULL;
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if (channel->dma_chan) {
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mem_to_nc = (rmt_symbol_word_t *)RMT_GET_NON_CACHE_ADDR(channel->dma_mem_base);
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mem_to_nc = tx_chan->dma_mem_base_nc;
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} else {
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mem_to_nc = channel->hw_mem_base;
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}
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@ -646,7 +657,7 @@ static void IRAM_ATTR rmt_tx_do_transaction(rmt_tx_channel_t *tx_chan, rmt_tx_tr
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tx_chan->dma_nodes_nc[i].next = &tx_chan->dma_nodes[i + 1]; // note, we must use the cache address for the next pointer
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tx_chan->dma_nodes_nc[i].dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_CPU;
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}
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tx_chan->dma_nodes_nc[1].next = &tx_chan->dma_nodes[0];
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tx_chan->dma_nodes_nc[RMT_DMA_NODES_PING_PONG - 1].next = &tx_chan->dma_nodes[0];
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}
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#endif // SOC_RMT_SUPPORT_DMA
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@ -3,9 +3,5 @@
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components/esp_driver_rmt/test_apps/rmt:
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disable:
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- if: SOC_RMT_SUPPORTED != 1
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disable_test:
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- if: IDF_TARGET == "esp32p4"
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temporary: true
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reason: test not passing, should be re-enabled # TODO: IDF-8961
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depends_components:
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- esp_driver_rmt
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -107,7 +107,8 @@ typedef struct {
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TaskHandle_t task_to_notify;
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size_t received_symbol_num;
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rmt_receive_config_t rx_config;
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rmt_symbol_word_t remote_codes[128];
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rmt_symbol_word_t* remote_codes;
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size_t remote_codes_mem_size;
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} test_rx_user_data_t;
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IRAM_ATTR
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@ -121,7 +122,7 @@ static bool test_rmt_rx_done_callback(rmt_channel_handle_t channel, const rmt_rx
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if (test_user_data->received_symbol_num == TEST_RMT_SYMBOLS) {
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vTaskNotifyGiveFromISR(test_user_data->task_to_notify, &high_task_wakeup);
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} else {
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rmt_receive(channel, test_user_data->remote_codes, sizeof(test_user_data->remote_codes), &test_user_data->rx_config);
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rmt_receive(channel, test_user_data->remote_codes, test_user_data->remote_codes_mem_size, &test_user_data->rx_config);
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}
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}
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return high_task_wakeup == pdTRUE;
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@ -129,6 +130,11 @@ static bool test_rmt_rx_done_callback(rmt_channel_handle_t channel, const rmt_rx
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static void test_rmt_rx_iram_safe(size_t mem_block_symbols, bool with_dma, rmt_clock_source_t clk_src)
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{
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uint32_t const test_rx_buffer_symbols = 128;
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rmt_symbol_word_t *remote_codes = heap_caps_aligned_calloc(64, test_rx_buffer_symbols, sizeof(rmt_symbol_word_t),
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MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA);
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TEST_ASSERT_NOT_NULL(remote_codes);
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rmt_rx_channel_config_t rx_channel_cfg = {
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.clk_src = clk_src,
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.resolution_hz = 1000000, // 1MHz, 1 tick = 1us
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@ -155,6 +161,8 @@ static void test_rmt_rx_iram_safe(size_t mem_block_symbols, bool with_dma, rmt_c
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.signal_range_min_ns = 1250,
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.signal_range_max_ns = 12000000,
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},
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.remote_codes = remote_codes,
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.remote_codes_mem_size = test_rx_buffer_symbols * sizeof(rmt_symbol_word_t),
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};
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TEST_ESP_OK(rmt_rx_register_event_callbacks(rx_channel, &cbs, &test_user_data));
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@ -162,7 +170,7 @@ static void test_rmt_rx_iram_safe(size_t mem_block_symbols, bool with_dma, rmt_c
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TEST_ESP_OK(rmt_enable(rx_channel));
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// ready to receive
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TEST_ESP_OK(rmt_receive(rx_channel, test_user_data.remote_codes, sizeof(test_user_data.remote_codes), &test_user_data.rx_config));
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TEST_ESP_OK(rmt_receive(rx_channel, remote_codes, test_user_data.remote_codes_mem_size, &test_user_data.rx_config));
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// disable the flash cache, and simulate input signal by GPIO
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unity_utils_run_cache_disable_stub(test_simulate_input_post_cache_disable, TEST_RMT_GPIO_NUM_A);
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@ -174,6 +182,7 @@ static void test_rmt_rx_iram_safe(size_t mem_block_symbols, bool with_dma, rmt_c
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TEST_ESP_OK(rmt_disable(rx_channel));
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printf("delete channels and encoder\r\n");
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TEST_ESP_OK(rmt_del_channel(rx_channel));
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free(remote_codes);
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}
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TEST_CASE("rmt rx iram safe", "[rmt]")
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@ -10,6 +10,7 @@ from pytest_embedded import Dut
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@pytest.mark.esp32c3
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||||
@pytest.mark.esp32c6
|
||||
@pytest.mark.esp32h2
|
||||
@pytest.mark.esp32p4
|
||||
@pytest.mark.generic
|
||||
@pytest.mark.parametrize(
|
||||
'config',
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
|
@ -214,11 +214,7 @@ typedef enum {
|
|||
/**
|
||||
* @brief Array initializer for all supported clock sources of RMT
|
||||
*/
|
||||
#if SOC_CLK_TREE_SUPPORTED
|
||||
#define SOC_RMT_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL}
|
||||
#else
|
||||
#define SOC_RMT_CLKS {SOC_MOD_CLK_XTAL}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Type of RMT clock source
|
||||
|
|
@ -227,11 +223,7 @@ typedef enum {
|
|||
RMT_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */
|
||||
RMT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
|
||||
RMT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
|
||||
#if SOC_CLK_TREE_SUPPORTED
|
||||
RMT_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default choice */
|
||||
#else
|
||||
RMT_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default choice */
|
||||
#endif
|
||||
} soc_periph_rmt_clk_src_t;
|
||||
|
||||
/**
|
||||
|
|
@ -240,11 +232,7 @@ typedef enum {
|
|||
typedef enum {
|
||||
RMT_BASECLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< RMT source clock is PLL_F80M */
|
||||
RMT_BASECLK_XTAL = SOC_MOD_CLK_XTAL, /*!< RMT source clock is XTAL */
|
||||
#if SOC_CLK_TREE_SUPPORTED
|
||||
RMT_BASECLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< RMT source clock default choice is PLL_F80M */
|
||||
#else
|
||||
RMT_BASECLK_DEFAULT = SOC_MOD_CLK_XTAL, /*!< RMT source clock default choice is XTAL */
|
||||
#endif
|
||||
} soc_periph_rmt_clk_src_legacy_t;
|
||||
|
||||
//////////////////////////////////////////////////Temp Sensor///////////////////////////////////////////////////////////
|
||||
|
|
|
|||
Ładowanie…
Reference in New Issue