kopia lustrzana https://github.com/espressif/esp-idf
ci: add flash psram test under different configs on esp32s3
Armando
rodzic
4cafdbd83b
commit
d6caf142d3
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@ -303,6 +303,11 @@ example_test_ESP32C3_SDSPI:
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- .test_app_template
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- .rules:test:custom_test-esp32c3
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.test_app_esp32s3_template:
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extends:
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- .test_app_template
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- .rules:test:custom_test-esp32s3
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test_app_test_001:
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extends: .test_app_esp32_template
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tags:
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@ -345,6 +350,24 @@ test_app_test_esp32_generic:
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variables:
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SETUP_TOOLS: "1"
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test_app_test_flash_psram_f4r4:
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extends: .test_app_esp32s3_template
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tags:
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- ESP32S3
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- MSPI_F4R4
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test_app_test_flash_psram_f4r8:
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extends: .test_app_esp32s3_template
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tags:
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- ESP32S3
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- MSPI_F4R8
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test_app_test_flash_psram_f8r8:
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extends: .test_app_esp32s3_template
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tags:
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- ESP32S3
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- MSPI_F8R8
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.component_ut_template:
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extends: .target_test_job_template
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variables:
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@ -0,0 +1,6 @@
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# The following lines of boilerplate have to be in your project's
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# CMakeLists in this exact order for cmake to work correctly
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cmake_minimum_required(VERSION 3.5)
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include($ENV{IDF_PATH}/tools/cmake/project.cmake)
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project(test_flash_psram)
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@ -0,0 +1,7 @@
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| Supported Targets | ESP32-S3 |
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| ----------------- | -------- |
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This project tests if Flash and PSRAM can work under different configurations.
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To add new configuration, create one more sdkconfig.ci.NAME file in this directory.
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If you need to test for anything other than flash and psram, create another test project.
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@ -0,0 +1,54 @@
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# SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
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# SPDX-License-Identifier: Apache-2.0
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import glob
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import os
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from typing import Any
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import ttfw_idf
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from tiny_test_fw import Utility
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def test_loop(env, config_names): # type: (Any, Any) -> None
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for name in config_names:
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Utility.console_log("Checking config \"{}\"... ".format(name), end='')
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dut = env.get_dut('flash_psram', 'tools/test_apps/system/flash_psram', app_config_name=name)
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dut.start_app()
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dut.expect('flash psram test success')
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env.close_dut(dut.name)
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Utility.console_log('done')
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# For F8R8 board (Octal Flash and Octal PSRAM)
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@ttfw_idf.idf_custom_test(env_tag='MSPI_F8R8', target=['esp32s3'])
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def test_flash8_psram8(env, _): # type: (Any, Any) -> None
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config_files = glob.glob(os.path.join(os.path.dirname(__file__), 'sdkconfig.ci.f8r8*'))
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config_names = [os.path.basename(s).replace('sdkconfig.ci.', '') for s in config_files]
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test_loop(env, config_names)
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# For F4R8 board (Quad Flash and Octal PSRAM)
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@ttfw_idf.idf_custom_test(env_tag='MSPI_F4R8', target=['esp32s3'])
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def test_flash4_psram8(env, _): # type: (Any, Any) -> None
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config_files = glob.glob(os.path.join(os.path.dirname(__file__), 'sdkconfig.ci.f4r8*'))
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config_names = [os.path.basename(s).replace('sdkconfig.ci.', '') for s in config_files]
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test_loop(env, config_names)
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# For F4R4 board (Quad Flash and Quad PSRAM)
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@ttfw_idf.idf_custom_test(env_tag='MSPI_F4R4', target=['esp32s3'])
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def test_flash4_psram4(env, _): # type: (Any, Any) -> None
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config_files = glob.glob(os.path.join(os.path.dirname(__file__), 'sdkconfig.ci.f4r4*'))
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config_names = [os.path.basename(s).replace('sdkconfig.ci.', '') for s in config_files]
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test_loop(env, config_names)
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if __name__ == '__main__':
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test_flash8_psram8()
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test_flash4_psram8()
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test_flash4_psram4()
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@ -0,0 +1,2 @@
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idf_component_register(SRCS "test_flash_psram.c"
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INCLUDE_DIRS ".")
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@ -0,0 +1,160 @@
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/*
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* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdio.h>
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#include <string.h>
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#include "sdkconfig.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "esp_system.h"
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#include "esp_check.h"
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#include "esp_attr.h"
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#if CONFIG_IDF_TARGET_ESP32S3
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#include "esp32s3/rom/spi_flash.h"
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#include "esp32s3/rom/opi_flash.h"
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#endif
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const static char *TAG = "SPI0";
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//-----------------------------------------SPI0 PSRAM TEST-----------------------------------------------//
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#if CONFIG_SPIRAM
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#if CONFIG_SPIRAM_MODE_OCT
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#define SPI0_PSRAM_TEST_LEN (512 * 1024)
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#define LENGTH_PER_TIME 1024
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#else
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#define SPI0_PSRAM_TEST_LEN (128 * 1024)
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#define LENGTH_PER_TIME 1024
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#endif
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static esp_err_t spi0_psram_test(void)
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{
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printf("----------SPI0 PSRAM Test----------\n");
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uint8_t *psram_wr_buf = (uint8_t *)heap_caps_malloc(LENGTH_PER_TIME, MALLOC_CAP_32BIT | MALLOC_CAP_SPIRAM);
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if (!psram_wr_buf) {
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printf("no memory\n");
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abort();
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}
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uint32_t *psram_rd_buf = (uint32_t *)heap_caps_malloc(SPI0_PSRAM_TEST_LEN, MALLOC_CAP_32BIT | MALLOC_CAP_SPIRAM);
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if (!psram_rd_buf) {
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printf("no memory\n");
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abort();
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}
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srand(399);
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for (int i = 0; i < SPI0_PSRAM_TEST_LEN / LENGTH_PER_TIME; i++) {
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for (int j = 0; j < sizeof(psram_wr_buf); j++) {
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psram_wr_buf[j] = rand();
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}
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memcpy(psram_rd_buf + i * LENGTH_PER_TIME, psram_wr_buf, LENGTH_PER_TIME);
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if (memcmp(psram_rd_buf + i * LENGTH_PER_TIME, psram_wr_buf, LENGTH_PER_TIME) != 0) {
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printf("Fail\n");
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free(psram_rd_buf);
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free(psram_wr_buf);
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return ESP_FAIL;
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}
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}
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free(psram_rd_buf);
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free(psram_wr_buf);
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printf(DRAM_STR("----------SPI0 PSRAM Test Success----------\n\n"));
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return ESP_OK;
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}
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#endif
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//-----------------------------------------SPI1 FLASH TEST-----------------------------------------------//
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#define SPI1_FLASH_TEST_LEN 512
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#define SECTOR_LEN 4096
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#define SPI1_FLASH_TEST_NUM (SECTOR_LEN / SPI1_FLASH_TEST_LEN)
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#define SPI1_FLASH_TEST_ADDR 0x200000
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extern void spi_flash_disable_interrupts_caches_and_other_cpu(void);
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extern void spi_flash_enable_interrupts_caches_and_other_cpu(void);
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static DRAM_ATTR uint8_t rd_buf[SPI1_FLASH_TEST_LEN];
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static DRAM_ATTR uint8_t wr_buf[SPI1_FLASH_TEST_LEN];
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static IRAM_ATTR esp_err_t spi1_flash_test(void)
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{
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printf(DRAM_STR("----------SPI1 Flash Test----------\n"));
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//We need to use SPI1
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spi_flash_disable_interrupts_caches_and_other_cpu();
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uint32_t sector_num = SPI1_FLASH_TEST_ADDR / SECTOR_LEN;
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esp_rom_spiflash_erase_sector(sector_num);
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spi_flash_enable_interrupts_caches_and_other_cpu();
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for (int i = 0; i < SPI1_FLASH_TEST_NUM; i++) {
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for (int j = i + 10; j < SPI1_FLASH_TEST_LEN; j++) {
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wr_buf[j] = j;
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}
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spi_flash_disable_interrupts_caches_and_other_cpu();
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uint32_t test_flash_addr = SPI1_FLASH_TEST_ADDR + i * SPI1_FLASH_TEST_LEN;
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esp_rom_spiflash_write(test_flash_addr, (uint32_t*)wr_buf, SPI1_FLASH_TEST_LEN);
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esp_rom_spiflash_read(test_flash_addr, (uint32_t*)rd_buf, SPI1_FLASH_TEST_LEN);
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spi_flash_enable_interrupts_caches_and_other_cpu();
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if (memcmp(wr_buf, rd_buf, SPI1_FLASH_TEST_LEN) != 0) {
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printf(DRAM_STR("error happened between 0x%x and 0x%x!!!!\n"), test_flash_addr, test_flash_addr + SPI1_FLASH_TEST_LEN);
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for (int i = 0; i < SPI1_FLASH_TEST_LEN; i++) {
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if (wr_buf[i] != rd_buf[i]) {
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printf(DRAM_STR("err: wr[%d]: 0x%02x -- rd[%d]: 0x%02x\n"), i, wr_buf[i], i, rd_buf[i]);
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}
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}
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return ESP_FAIL;
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}
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memset(rd_buf, 0x0, SPI1_FLASH_TEST_LEN);
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}
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printf(DRAM_STR("----------SPI1 Flash Test Success----------\n\n"));
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return ESP_OK;
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}
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//-----------------------------------------SPI0 FLASH TEST-----------------------------------------------//
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#define SPI0_FLASH_TEST_LEN 32
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#define SPI0_FLASH_TEST_BUF {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, \
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0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}
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uint8_t flash_rd_buf[SPI0_FLASH_TEST_LEN] __attribute__((section (".flash.rodata"))) = SPI0_FLASH_TEST_BUF;
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extern int _flash_rodata_start;
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extern int _rodata_reserved_end;
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static IRAM_ATTR esp_err_t spi0_flash_test(void)
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{
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printf("----------SPI0 Flash Test----------\n");
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//Check if the flash_rd_buf is in .rodata
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ESP_RETURN_ON_ERROR(((intptr_t)flash_rd_buf >= (intptr_t)_flash_rodata_start) && ((intptr_t)flash_rd_buf < (intptr_t)_rodata_reserved_end), TAG, "psram_rd_buf not in rodata");
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uint8_t cmp_buf[SPI0_FLASH_TEST_LEN] = SPI0_FLASH_TEST_BUF;
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for (int i = 0; i < SPI0_FLASH_TEST_LEN; i++) {
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if (flash_rd_buf[i] != cmp_buf[i]) {
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return ESP_FAIL;
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}
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}
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printf(DRAM_STR("----------SPI0 Flash Test Success----------\n\n"));
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return ESP_OK;
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}
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void app_main(void)
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{
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ESP_ERROR_CHECK(spi0_flash_test());
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#if CONFIG_SPIRAM
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ESP_ERROR_CHECK(spi0_psram_test());
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#endif
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ESP_ERROR_CHECK(spi1_flash_test());
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printf("flash psram test success\n");
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}
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@ -0,0 +1,2 @@
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CONFIG_IDF_TARGET="esp32s3"
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CONFIG_IDF_TARGET_ESP32S3=y
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@ -0,0 +1,5 @@
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# Legacy, F4R4, Flash 120M SDR, PSRAM disable
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CONFIG_SPI_FLASH_USE_LEGACY_IMPL=y
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CONFIG_ESPTOOLPY_FLASHFREQ_120M=y
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CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
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@ -0,0 +1,7 @@
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# Legacy, F4R4, Flash 120M SDR, PSRAM 120M SDR
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CONFIG_SPI_FLASH_USE_LEGACY_IMPL=y
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CONFIG_ESPTOOLPY_FLASHFREQ_120M=y
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CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
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CONFIG_ESP32S3_SPIRAM_SUPPORT=y
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CONFIG_SPIRAM_SPEED_120M=y
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@ -0,0 +1,7 @@
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# Legacy, F4R4, Flash 120M SDR, PSRAM 40M SDR
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CONFIG_SPI_FLASH_USE_LEGACY_IMPL=y
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CONFIG_ESPTOOLPY_FLASHFREQ_120M=y
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CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
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CONFIG_ESP32S3_SPIRAM_SUPPORT=y
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CONFIG_SPIRAM_SPEED_40M=y
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@ -0,0 +1,7 @@
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# Legacy, F4R4, Flash 40M SDR, PSRAM 120M SDR
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CONFIG_SPI_FLASH_USE_LEGACY_IMPL=y
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CONFIG_ESPTOOLPY_FLASHFREQ_40M=y
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CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
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CONFIG_ESP32S3_SPIRAM_SUPPORT=y
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CONFIG_SPIRAM_SPEED_120M=y
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@ -0,0 +1,7 @@
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# Legacy, F4R4, Flash 80M SDR, PSRAM 80M SDR
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CONFIG_SPI_FLASH_USE_LEGACY_IMPL=y
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CONFIG_ESPTOOLPY_FLASHFREQ_80M=y
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CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
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CONFIG_ESP32S3_SPIRAM_SUPPORT=y
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CONFIG_SPIRAM_SPEED_80M=y
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@ -0,0 +1,5 @@
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# Legacy, F4R8, Flash 120M SDR, PSRAM disable
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CONFIG_SPI_FLASH_USE_LEGACY_IMPL=y
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CONFIG_ESPTOOLPY_FLASHFREQ_120M=y
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CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
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@ -0,0 +1,8 @@
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# Legacy, F4R8, Flash 80M SDR, PSRAM 40M DDR
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CONFIG_SPI_FLASH_USE_LEGACY_IMPL=y
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CONFIG_ESPTOOLPY_FLASHFREQ_80M=y
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CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
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CONFIG_ESP32S3_SPIRAM_SUPPORT=y
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CONFIG_SPIRAM_MODE_OCT=y
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CONFIG_SPIRAM_SPEED_40M=y
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# Legacy, F4R8, Flash 80M SDR, PSRAM 80M DDR
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CONFIG_SPI_FLASH_USE_LEGACY_IMPL=y
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CONFIG_ESPTOOLPY_FLASHFREQ_80M=y
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CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
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CONFIG_ESP32S3_SPIRAM_SUPPORT=y
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CONFIG_SPIRAM_MODE_OCT=y
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CONFIG_SPIRAM_SPEED_80M=y
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@ -0,0 +1,8 @@
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# Legacy, F8R8, Flash 120M SDR, PSRAM disable
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CONFIG_SPI_FLASH_USE_LEGACY_IMPL=y
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CONFIG_ESPTOOLPY_OCT_FLASH=y
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CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_STR=y
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CONFIG_ESPTOOLPY_FLASHFREQ_120M=y
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CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
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CONFIG_ESP32S3_SPIRAM_SUPPORT=n
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@ -0,0 +1,10 @@
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# Legacy, F8R8, Flash 40M DDR, PSRAM 40M DDR
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CONFIG_SPI_FLASH_USE_LEGACY_IMPL=y
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CONFIG_ESPTOOLPY_OCT_FLASH=y
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CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_DTR=y
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CONFIG_ESPTOOLPY_FLASHFREQ_40M=y
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CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
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CONFIG_ESP32S3_SPIRAM_SUPPORT=y
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CONFIG_SPIRAM_MODE_OCT=y
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CONFIG_SPIRAM_SPEED_40M=y
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@ -0,0 +1,10 @@
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# Legacy, F8R8, Flash 40M DDR, PSRAM 80M DDR
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CONFIG_SPI_FLASH_USE_LEGACY_IMPL=y
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CONFIG_ESPTOOLPY_OCT_FLASH=y
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CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_DTR=y
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CONFIG_ESPTOOLPY_FLASHFREQ_40M=y
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CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
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CONFIG_ESP32S3_SPIRAM_SUPPORT=y
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CONFIG_SPIRAM_MODE_OCT=y
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CONFIG_SPIRAM_SPEED_80M=y
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# Legacy, F8R8, Flash 80M DDR, PSRAM 40M DDR
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CONFIG_SPI_FLASH_USE_LEGACY_IMPL=y
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CONFIG_ESPTOOLPY_OCT_FLASH=y
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CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_DTR=y
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CONFIG_ESPTOOLPY_FLASHFREQ_80M=y
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CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
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CONFIG_ESP32S3_SPIRAM_SUPPORT=y
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CONFIG_SPIRAM_MODE_OCT=y
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CONFIG_SPIRAM_SPEED_40M=y
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@ -0,0 +1,10 @@
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# Legacy, F8R8, Flash 80M DDR, PSRAM 80M DDR
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CONFIG_SPI_FLASH_USE_LEGACY_IMPL=y
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CONFIG_ESPTOOLPY_OCT_FLASH=y
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CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_DTR=y
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CONFIG_ESPTOOLPY_FLASHFREQ_80M=y
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CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
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CONFIG_ESP32S3_SPIRAM_SUPPORT=y
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CONFIG_SPIRAM_MODE_OCT=y
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CONFIG_SPIRAM_SPEED_80M=y
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
# Legacy, F8R8, Flash 80M SDR, PSRAM 80M DDR
|
||||
|
||||
CONFIG_SPI_FLASH_USE_LEGACY_IMPL=y
|
||||
CONFIG_ESPTOOLPY_OCT_FLASH=y
|
||||
CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_STR=y
|
||||
CONFIG_ESPTOOLPY_FLASHFREQ_80M=y
|
||||
CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
|
||||
CONFIG_ESP32S3_SPIRAM_SUPPORT=y
|
||||
CONFIG_SPIRAM_MODE_OCT=y
|
||||
CONFIG_SPIRAM_SPEED_80M=y
|
||||
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Reference in New Issue