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hw_support: fixed regi2c not protected by lock on ESP32S2

pull/8572/head
Michael (XIAO Xufeng) 2022-01-05 06:08:37 +00:00
rodzic c6aeb86485
commit d5bdf95580
69 zmienionych plików z 421 dodań i 646 usunięć
Pokaż statystyki Ściągnij plik aktualizacji Ściągnij plik porównania Expand all files Collapse all files

1
components/bootloader/subproject/main/ld/esp32s2/bootloader.ld
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@ -57,6 +57,7 @@ SECTIONS
*libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*)
*libesp_hw_support.a:regi2c_ctrl.*(.literal .text .literal.* .text.*)
*libefuse.a:*.*(.literal .text .literal.* .text.*)
*libesp_rom.a:esp_rom_regi2c.*(.literal .text .literal.* .text.*)
*(.fini.literal)
*(.fini)
*(.gnu.version)

2
components/bootloader_support/src/bootloader_random_esp32c2.c
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@ -10,7 +10,7 @@
#include "soc/rtc_cntl_reg.h"
#include "soc/apb_saradc_reg.h"
#include "soc/system_reg.h"
#include "regi2c_ctrl.h"
#include "esp_private/regi2c_ctrl.h"
void bootloader_random_enable(void)
{

3
components/bootloader_support/src/bootloader_random_esp32c3.c
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@ -10,7 +10,8 @@
#include "soc/rtc_cntl_reg.h"
#include "soc/apb_saradc_reg.h"
#include "soc/system_reg.h"
#include "regi2c_ctrl.h"
#include "esp_private/regi2c_ctrl.h"
#include "regi2c_saradc.h"
void bootloader_random_enable(void)
{

2
components/bootloader_support/src/bootloader_random_esp32h2.c
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@ -10,7 +10,7 @@
#include "soc/rtc_cntl_reg.h"
#include "soc/apb_saradc_reg.h"
#include "soc/system_reg.h"
#include "regi2c_ctrl.h"
#include "esp_private/regi2c_ctrl.h"
// ESP32H2-TODO: IDF-3381
void bootloader_random_enable(void)

2
components/bootloader_support/src/bootloader_random_esp32s2.c
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@ -13,7 +13,7 @@
#include "esp_log.h"
#include "soc/io_mux_reg.h"
#include "soc/apb_saradc_reg.h"
#include "regi2c_ctrl.h"
#include "esp_private/regi2c_ctrl.h"
#include "hal/adc_ll.h"
#ifndef BOOTLOADER_BUILD

2
components/bootloader_support/src/bootloader_random_esp32s3.c
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@ -11,7 +11,7 @@
#include "soc/apb_saradc_reg.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/sens_reg.h"
#include "regi2c_ctrl.h"
#include "esp_private/regi2c_ctrl.h"
#include "regi2c_saradc.h"
void bootloader_random_enable(void)

1
components/bootloader_support/src/esp32c2/bootloader_esp32c2.c
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@ -33,7 +33,6 @@
#include "bootloader_clock.h"
#include "bootloader_flash_config.h"
#include "bootloader_mem.h"
#include "regi2c_ctrl.h"
#include "bootloader_console.h"
#include "bootloader_flash_priv.h"
#include "esp_efuse.h"

4
components/bootloader_support/src/esp32c3/bootloader_esp32c3.c
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@ -32,7 +32,9 @@
#include "bootloader_clock.h"
#include "bootloader_flash_config.h"
#include "bootloader_mem.h"
#include "regi2c_ctrl.h"
#include "esp_private/regi2c_ctrl.h"
#include "regi2c_lp_bias.h"
#include "regi2c_bias.h"
#include "bootloader_console.h"
#include "bootloader_flash_priv.h"
#include "bootloader_soc.h"

1
components/bootloader_support/src/esp32h2/bootloader_esp32h2.c
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@ -32,7 +32,6 @@
#include "bootloader_clock.h"
#include "bootloader_flash_config.h"
#include "bootloader_mem.h"
#include "regi2c_ctrl.h"
#include "bootloader_console.h"
#include "bootloader_flash_priv.h"
#include "bootloader_soc.h"

3
components/driver/rtc_temperature_legacy.c
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@ -11,7 +11,8 @@
#include "esp_log.h"
#include "esp_check.h"
#include "soc/rtc_cntl_reg.h"
#include "regi2c_ctrl.h"
#include "esp_private/regi2c_ctrl.h"
#include "regi2c_saradc.h"
#include "esp_log.h"
#include "esp_efuse_rtc_calib.h"
#include "hal/temperature_sensor_ll.h"

5
components/driver/test/test_adc.c
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@ -398,7 +398,10 @@ TEST_CASE("test_adc_single_cali_time", "[adc][ignore][manual]")
********************************************************************************/
#include <inttypes.h>
#include "esp_sleep.h"
#include "regi2c_ctrl.h"
#include "esp_private/regi2c_ctrl.h"
#if REGI2C_ANA_CALI_PD_WORKAROUND
#include "regi2c_saradc.h"
#endif
//ADC Channels
#if CONFIG_IDF_TARGET_ESP32

2
components/esp_hw_support/CMakeLists.txt
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@ -33,7 +33,7 @@ endif()
idf_component_register(SRCS ${srcs}
INCLUDE_DIRS include include/soc include/soc/${target}
PRIV_INCLUDE_DIRS port/include
PRIV_INCLUDE_DIRS port/include include/esp_private
REQUIRES ${requires}
PRIV_REQUIRES "${priv_requires}"
LDFRAGMENTS linker.lf)

47
components/esp_hw_support/port/esp32/regi2c_ctrl.h → components/esp_hw_support/include/esp_private/regi2c_ctrl.h
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -7,46 +7,33 @@
#pragma once
#include <stdint.h>
#include "regi2c_apll.h"
#include "regi2c_bbpll.h"
#include "sdkconfig.h"
#include "esp_rom_regi2c.h"
#include "soc/regi2c_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
/* Analog function control register */
#define ANA_CONFIG_REG 0x6000E044
#define ANA_CONFIG_S (8)
#define ANA_CONFIG_M (0x3FF)
/* Clear to enable APLL */
#define I2C_APLL_M (BIT(14))
/* Clear to enable BBPLL */
#define I2C_BBPLL_M (BIT(17))
/* ROM functions which read/write internal control bus */
uint8_t rom_i2c_readReg(uint8_t block, uint8_t host_id, uint8_t reg_add);
uint8_t rom_i2c_readReg_Mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb);
void rom_i2c_writeReg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data);
void rom_i2c_writeReg_Mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data);
#define regi2c_read_reg_raw esp_rom_regi2c_read
#define regi2c_read_reg_mask_raw esp_rom_regi2c_read_mask
#define regi2c_write_reg_raw esp_rom_regi2c_write
#define regi2c_write_reg_mask_raw esp_rom_regi2c_write_mask
#ifdef BOOTLOADER_BUILD
/**
* If compiling for the bootloader, ROM functions can be called directly,
* without the need of a lock.
*/
#define regi2c_ctrl_read_reg rom_i2c_readReg
#define regi2c_ctrl_read_reg_mask rom_i2c_readReg_Mask
#define regi2c_ctrl_write_reg rom_i2c_writeReg
#define regi2c_ctrl_write_reg_mask rom_i2c_writeReg_Mask
#define regi2c_ctrl_read_reg regi2c_read_reg_raw
#define regi2c_ctrl_read_reg_mask regi2c_read_reg_mask_raw
#define regi2c_ctrl_write_reg regi2c_write_reg_raw
#define regi2c_ctrl_write_reg_mask regi2c_write_reg_mask_raw
#else
#define i2c_read_reg_raw rom_i2c_readReg
#define i2c_read_reg_mask_raw rom_i2c_readReg_Mask
#define i2c_write_reg_raw rom_i2c_writeReg
#define i2c_write_reg_mask_raw rom_i2c_writeReg_Mask
uint8_t regi2c_ctrl_read_reg(uint8_t block, uint8_t host_id, uint8_t reg_add);
uint8_t regi2c_ctrl_read_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb);
void regi2c_ctrl_write_reg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data);
@ -69,6 +56,14 @@ void regi2c_ctrl_write_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_add,
#define REGI2C_READ(block, reg_add) \
regi2c_ctrl_read_reg(block, block##_HOSTID, reg_add)
/**
* Restore regi2c analog calibration related configuration registers.
* This is a workaround, and is fixed on later chips
*/
#if REGI2C_ANA_CALI_PD_WORKAROUND
void regi2c_analog_cali_reg_read(void);
void regi2c_analog_cali_reg_write(void);
#endif //#if ADC_CALI_PD_WORKAROUND
#ifdef __cplusplus
}

2
components/esp_hw_support/linker.lf
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@ -2,8 +2,6 @@
archive: libesp_hw_support.a
entries:
cpu_util (noflash_text)
if IDF_TARGET_ESP32S2 = y:
regi2c_ctrl (noflash)
rtc_clk (noflash)
rtc_init:rtc_vddsdio_set_config (noflash)
rtc_pm (noflash_text)

14
components/esp_hw_support/port/esp32/rtc_clk.c
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@ -8,9 +8,6 @@
#include <stdint.h>
#include <stddef.h>
#include <stdlib.h>
#include "esp32/rom/ets_sys.h" // for ets_update_cpu_frequency
#include "esp32/rom/rtc.h"
#include "esp_rom_gpio.h"
#include "soc/rtc.h"
#include "soc/rtc_periph.h"
#include "soc/sens_periph.h"
@ -22,12 +19,19 @@
#include "soc/gpio_struct.h"
#include "hal/cpu_hal.h"
#include "hal/gpio_ll.h"
#include "esp_rom_sys.h"
#include "regi2c_ctrl.h"
#include "esp_hw_log.h"
#include "sdkconfig.h"
#include "rtc_clk_common.h"
#include "esp_rom_sys.h"
#include "esp_rom_gpio.h"
#include "esp32/rom/ets_sys.h" // for ets_update_cpu_frequency
#include "esp32/rom/rtc.h"
#include "regi2c_ctrl.h"
#include "regi2c_apll.h"
#include "regi2c_bbpll.h"
/* Frequency of the 8M oscillator is 8.5MHz +/- 5%, at the default DCAP setting */
#define RTC_FAST_CLK_FREQ_8M 8500000
#define RTC_SLOW_CLK_FREQ_150K 150000

7
components/esp_hw_support/port/esp32c2/private_include/regi2c_saradc.h
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@ -77,10 +77,3 @@
#define I2C_SARADC_TSENS_DAC 0x6
#define I2C_SARADC_TSENS_DAC_MSB 3
#define I2C_SARADC_TSENS_DAC_LSB 0
/**
* Restore regi2c analog calibration related configuration registers.
* This is a workaround, and is fixed on later chips
*/
#define REGI2C_ANA_CALI_PD_WORKAROUND 1
#define REGI2C_ANA_CALI_BYTE_NUM 8

98
components/esp_hw_support/port/esp32c2/regi2c_ctrl.h
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@ -1,98 +0,0 @@
/*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "regi2c_bbpll.h"
#include "regi2c_lp_bias.h"
#include "regi2c_dig_reg.h"
#include "regi2c_bias.h"
#include "regi2c_saradc.h"
#ifdef __cplusplus
extern "C" {
#endif
/* Analog function control register */
#define I2C_MST_ANA_CONF0_REG 0x6000E040
#define I2C_MST_BBPLL_STOP_FORCE_HIGH (BIT(2))
#define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3))
#define ANA_CONFIG_REG 0x6000E044
#define ANA_CONFIG_S (8)
#define ANA_CONFIG_M (0x3FF)
#define ANA_I2C_SAR_FORCE_PD BIT(18)
#define ANA_I2C_BBPLL_M BIT(17) /* Clear to enable BBPLL */
#define ANA_I2C_APLL_M BIT(14) /* Clear to enable APLL */
#define ANA_CONFIG2_REG 0x6000E048
#define ANA_CONFIG2_M BIT(18)
#define ANA_I2C_SAR_FORCE_PU BIT(16)
/* ROM functions which read/write internal control bus */
uint8_t rom_i2c_readReg(uint8_t block, uint8_t host_id, uint8_t reg_add);
uint8_t rom_i2c_readReg_Mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb);
void rom_i2c_writeReg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data);
void rom_i2c_writeReg_Mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data);
#ifdef BOOTLOADER_BUILD
/**
* If compiling for the bootloader, ROM functions can be called directly,
* without the need of a lock.
*/
#define regi2c_ctrl_read_reg rom_i2c_readReg
#define regi2c_ctrl_read_reg_mask rom_i2c_readReg_Mask
#define regi2c_ctrl_write_reg rom_i2c_writeReg
#define regi2c_ctrl_write_reg_mask rom_i2c_writeReg_Mask
#else
#define i2c_read_reg_raw rom_i2c_readReg
#define i2c_read_reg_mask_raw rom_i2c_readReg_Mask
#define i2c_write_reg_raw rom_i2c_writeReg
#define i2c_write_reg_mask_raw rom_i2c_writeReg_Mask
uint8_t regi2c_ctrl_read_reg(uint8_t block, uint8_t host_id, uint8_t reg_add);
uint8_t regi2c_ctrl_read_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb);
void regi2c_ctrl_write_reg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data);
void regi2c_ctrl_write_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data);
#endif // BOOTLOADER_BUILD
/* Convenience macros for the above functions, these use register definitions
* from regi2c_bbpll.h/regi2c_dig_reg.h/regi2c_lp_bias.h/regi2c_bias.h header files.
*/
#define REGI2C_WRITE_MASK(block, reg_add, indata) \
regi2c_ctrl_write_reg_mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB, indata)
#define REGI2C_READ_MASK(block, reg_add) \
regi2c_ctrl_read_reg_mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB)
#define REGI2C_WRITE(block, reg_add, indata) \
regi2c_ctrl_write_reg(block, block##_HOSTID, reg_add, indata)
#define REGI2C_READ(block, reg_add) \
regi2c_ctrl_read_reg(block, block##_HOSTID, reg_add)
/**
* Restore regi2c analog calibration related configuration registers.
* This is a workaround, and is fixed on later chips
*/
#if REGI2C_ANA_CALI_PD_WORKAROUND
void regi2c_analog_cali_reg_read(void);
void regi2c_analog_cali_reg_write(void);
#endif //#if ADC_CALI_PD_WORKAROUND
#ifdef __cplusplus
}
#endif

1
components/esp_hw_support/port/esp32c2/rtc_clk.c
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@ -20,6 +20,7 @@
#include "soc/syscon_reg.h"
#include "soc/system_reg.h"
#include "regi2c_ctrl.h"
#include "regi2c_bbpll.h"
#include "esp_hw_log.h"
#include "rtc_clk_common.h"
#include "esp_rom_sys.h"

2
components/esp_hw_support/port/esp32c2/rtc_init.c
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@ -15,6 +15,8 @@
#include "soc/extmem_reg.h"
#include "soc/system_reg.h"
#include "regi2c_ctrl.h"
#include "regi2c_dig_reg.h"
#include "regi2c_lp_bias.h"
#include "esp_hw_log.h"
#include "esp_efuse.h"
#include "esp_efuse_table.h"

2
components/esp_hw_support/port/esp32c2/rtc_sleep.c
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@ -20,6 +20,8 @@
#include "esp32c2/rom/ets_sys.h"
#include "esp32c2/rom/rtc.h"
#include "regi2c_ctrl.h"
#include "regi2c_lp_bias.h"
#include "regi2c_dig_reg.h"
#include "esp_efuse.h"
/**

7
components/esp_hw_support/port/esp32c3/private_include/regi2c_saradc.h
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@ -77,10 +77,3 @@
#define I2C_SARADC_TSENS_DAC 0x6
#define I2C_SARADC_TSENS_DAC_MSB 3
#define I2C_SARADC_TSENS_DAC_LSB 0
/**
* Restore regi2c analog calibration related configuration registers.
* This is a workaround, and is fixed on later chips
*/
#define REGI2C_ANA_CALI_PD_WORKAROUND 1
#define REGI2C_ANA_CALI_BYTE_NUM 8

97
components/esp_hw_support/port/esp32c3/regi2c_ctrl.h
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@ -1,97 +0,0 @@
/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "regi2c_bbpll.h"
#include "regi2c_lp_bias.h"
#include "regi2c_dig_reg.h"
#include "regi2c_bias.h"
#include "regi2c_saradc.h"
#ifdef __cplusplus
extern "C" {
#endif
/* Analog function control register */
#define I2C_MST_ANA_CONF0_REG 0x6000E040
#define I2C_MST_BBPLL_STOP_FORCE_HIGH (BIT(2))
#define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3))
#define ANA_CONFIG_REG 0x6000E044
#define ANA_CONFIG_S (8)
#define ANA_CONFIG_M (0x3FF)
#define ANA_I2C_SAR_FORCE_PD BIT(18)
#define ANA_I2C_BBPLL_M BIT(17) /* Clear to enable BBPLL */
#define ANA_I2C_APLL_M BIT(14) /* Clear to enable APLL */
#define ANA_CONFIG2_REG 0x6000E048
#define ANA_CONFIG2_M BIT(18)
#define ANA_I2C_SAR_FORCE_PU BIT(16)
/* ROM functions which read/write internal control bus */
uint8_t rom_i2c_readReg(uint8_t block, uint8_t host_id, uint8_t reg_add);
uint8_t rom_i2c_readReg_Mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb);
void rom_i2c_writeReg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data);
void rom_i2c_writeReg_Mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data);
#ifdef BOOTLOADER_BUILD
/**
* If compiling for the bootloader, ROM functions can be called directly,
* without the need of a lock.
*/
#define regi2c_ctrl_read_reg rom_i2c_readReg
#define regi2c_ctrl_read_reg_mask rom_i2c_readReg_Mask
#define regi2c_ctrl_write_reg rom_i2c_writeReg
#define regi2c_ctrl_write_reg_mask rom_i2c_writeReg_Mask
#else
#define i2c_read_reg_raw rom_i2c_readReg
#define i2c_read_reg_mask_raw rom_i2c_readReg_Mask
#define i2c_write_reg_raw rom_i2c_writeReg
#define i2c_write_reg_mask_raw rom_i2c_writeReg_Mask
uint8_t regi2c_ctrl_read_reg(uint8_t block, uint8_t host_id, uint8_t reg_add);
uint8_t regi2c_ctrl_read_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb);
void regi2c_ctrl_write_reg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data);
void regi2c_ctrl_write_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data);
#endif // BOOTLOADER_BUILD
/* Convenience macros for the above functions, these use register definitions
* from regi2c_bbpll.h/regi2c_dig_reg.h/regi2c_lp_bias.h/regi2c_bias.h header files.
*/
#define REGI2C_WRITE_MASK(block, reg_add, indata) \
regi2c_ctrl_write_reg_mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB, indata)
#define REGI2C_READ_MASK(block, reg_add) \
regi2c_ctrl_read_reg_mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB)
#define REGI2C_WRITE(block, reg_add, indata) \
regi2c_ctrl_write_reg(block, block##_HOSTID, reg_add, indata)
#define REGI2C_READ(block, reg_add) \
regi2c_ctrl_read_reg(block, block##_HOSTID, reg_add)
/**
* Restore regi2c analog calibration related configuration registers.
* This is a workaround, and is fixed on later chips
*/
#if REGI2C_ANA_CALI_PD_WORKAROUND
void regi2c_analog_cali_reg_read(void);
void regi2c_analog_cali_reg_write(void);
#endif //#if ADC_CALI_PD_WORKAROUND
#ifdef __cplusplus
}
#endif

1
components/esp_hw_support/port/esp32c3/rtc_clk.c
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@ -20,6 +20,7 @@
#include "soc/syscon_reg.h"
#include "soc/system_reg.h"
#include "regi2c_ctrl.h"
#include "regi2c_bbpll.h"
#include "esp_hw_log.h"
#include "rtc_clk_common.h"
#include "esp_rom_sys.h"

2
components/esp_hw_support/port/esp32c3/rtc_init.c
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@ -15,6 +15,8 @@
#include "soc/extmem_reg.h"
#include "soc/system_reg.h"
#include "regi2c_ctrl.h"
#include "regi2c_dig_reg.h"
#include "regi2c_lp_bias.h"
#include "esp_hw_log.h"
#include "esp_efuse.h"
#include "esp_efuse_table.h"

2
components/esp_hw_support/port/esp32c3/rtc_sleep.c
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@ -21,6 +21,8 @@
#include "esp32c3/rom/ets_sys.h"
#include "esp32c3/rom/rtc.h"
#include "regi2c_ctrl.h"
#include "regi2c_dig_reg.h"
#include "regi2c_lp_bias.h"
#include "esp_efuse.h"
/**

101
components/esp_hw_support/port/esp32h2/regi2c_ctrl.h
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@ -1,101 +0,0 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#include <stdint.h>
#include "regi2c_bbpll.h"
#include "regi2c_lp_bias.h"
#include "regi2c_dig_reg.h"
#include "regi2c_bias.h"
#include "regi2c_saradc.h"
#ifdef __cplusplus
extern "C" {
#endif
/* Analog function control register */
#define I2C_MST_ANA_CONF0_REG 0x6000E040
#define I2C_MST_BBPLL_STOP_FORCE_HIGH (BIT(2))
#define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3))
#define ANA_CONFIG_REG 0x6000E044
#define ANA_CONFIG_S (8)
#define ANA_CONFIG_M (0x3FF)
#define ANA_I2C_SAR_FORCE_PD BIT(18)
#define ANA_I2C_BBPLL_M BIT(17) /* Clear to enable BBPLL */
#define ANA_I2C_APLL_M BIT(14) /* Clear to enable APLL */
#define ANA_CONFIG2_REG 0x6000E048
#define ANA_CONFIG2_M BIT(18)
#define ANA_I2C_SAR_FORCE_PU BIT(16)
/* ROM functions which read/write internal control bus */
uint8_t rom_i2c_readReg(uint8_t block, uint8_t host_id, uint8_t reg_add);
uint8_t rom_i2c_readReg_Mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb);
void rom_i2c_writeReg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data);
void rom_i2c_writeReg_Mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data);
#ifdef BOOTLOADER_BUILD
/**
* If compiling for the bootloader, ROM functions can be called directly,
* without the need of a lock.
*/
#define regi2c_ctrl_read_reg rom_i2c_readReg
#define regi2c_ctrl_read_reg_mask rom_i2c_readReg_Mask
#define regi2c_ctrl_write_reg rom_i2c_writeReg
#define regi2c_ctrl_write_reg_mask rom_i2c_writeReg_Mask
#else
#define i2c_read_reg_raw rom_i2c_readReg
#define i2c_read_reg_mask_raw rom_i2c_readReg_Mask
#define i2c_write_reg_raw rom_i2c_writeReg
#define i2c_write_reg_mask_raw rom_i2c_writeReg_Mask
uint8_t regi2c_ctrl_read_reg(uint8_t block, uint8_t host_id, uint8_t reg_add);
uint8_t regi2c_ctrl_read_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb);
void regi2c_ctrl_write_reg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data);
void regi2c_ctrl_write_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data);
#endif // BOOTLOADER_BUILD
/* Convenience macros for the above functions, these use register definitions
* from regi2c_bbpll.h/regi2c_dig_reg.h/regi2c_lp_bias.h/regi2c_bias.h header files.
*/
#define REGI2C_WRITE_MASK(block, reg_add, indata) \
regi2c_ctrl_write_reg_mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB, indata)
#define REGI2C_READ_MASK(block, reg_add) \
regi2c_ctrl_read_reg_mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB)
#define REGI2C_WRITE(block, reg_add, indata) \
regi2c_ctrl_write_reg(block, block##_HOSTID, reg_add, indata)
#define REGI2C_READ(block, reg_add) \
regi2c_ctrl_read_reg(block, block##_HOSTID, reg_add)
#ifdef __cplusplus
}
#endif

2
components/esp_hw_support/port/esp32h2/rtc_sleep.c
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@ -19,6 +19,8 @@
#include "esp32h2/rom/ets_sys.h"
#include "esp32h2/rom/rtc.h"
#include "regi2c_ctrl.h"
#include "regi2c_bias.h"
#include "regi2c_ulp.h"
#include "esp_efuse.h"
#include "i2c_pmu.h"
#include "esp_hw_log.h"

1
components/esp_hw_support/port/esp32s2/CMakeLists.txt
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@ -8,7 +8,6 @@ set(srcs
"rtc_pm.c"
"rtc_sleep.c"
"rtc_time.c"
"regi2c_ctrl.c"
"chip_info.c"
)

7
components/esp_hw_support/port/esp32s2/private_include/regi2c_saradc.h
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@ -73,10 +73,3 @@
#define I2C_SARADC_TSENS_DAC 0x6
#define I2C_SARADC_TSENS_DAC_MSB 3
#define I2C_SARADC_TSENS_DAC_LSB 0
/**
* Restore regi2c analog calibration related configuration registers.
* This is a workaround, and is fixed on later chips
*/
#define REGI2C_ANA_CALI_PD_WORKAROUND 1
#define REGI2C_ANA_CALI_BYTE_NUM 8

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components/esp_hw_support/port/esp32s2/regi2c_ctrl.h
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@ -1,92 +0,0 @@
/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "regi2c_apll.h"
#include "regi2c_bbpll.h"
#include "regi2c_ulp.h"
#include "regi2c_saradc.h"
#ifdef __cplusplus
extern "C" {
#endif
/* Analog function control register */
#define ANA_CONFIG_REG 0x6000E044
#define ANA_CONFIG_S (8)
#define ANA_CONFIG_M (0x3FF)
/* Clear to enable APLL */
#define I2C_APLL_M (BIT(14))
/* Clear to enable BBPLL */
#define I2C_BBPLL_M (BIT(17))
/* Clear to enable SAR */
#define I2C_SAR_M (BIT(18))
#define ANA_CONFIG2_REG 0x6000E048
#define ANA_SAR_CFG2_M (BIT(16))
/* Read/Write internal control bus */
uint8_t i2c_rtc_read_reg(uint8_t block, uint8_t host_id, uint8_t reg_add);
uint8_t i2c_rtc_read_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb);
void i2c_rtc_write_reg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data);
void i2c_rtc_write_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data);
void i2c_rtc_init(void);
#ifdef BOOTLOADER_BUILD
/**
* If compiling for the bootloader, internal functions can be called directly,
* without the need of a lock.
*/
#define regi2c_ctrl_read_reg i2c_rtc_read_reg
#define regi2c_ctrl_read_reg_mask i2c_rtc_read_reg_mask
#define regi2c_ctrl_write_reg i2c_rtc_write_reg
#define regi2c_ctrl_write_reg_mask i2c_rtc_write_reg_mask
#else
#define i2c_read_reg_raw i2c_rtc_read_reg
#define i2c_read_reg_mask_raw i2c_rtc_read_reg_mask
#define i2c_write_reg_raw i2c_rtc_write_reg
#define i2c_write_reg_mask_raw i2c_rtc_write_reg_mask
uint8_t regi2c_ctrl_read_reg(uint8_t block, uint8_t host_id, uint8_t reg_add);
uint8_t regi2c_ctrl_read_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb);
void regi2c_ctrl_write_reg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data);
void regi2c_ctrl_write_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data);
#endif // BOOTLOADER_BUILD
/* Convenience macros for the above functions, these use register definitions
* from regi2c_apll.h/regi2c_bbpll.h header files.
*/
#define REGI2C_WRITE_MASK(block, reg_add, indata) \
regi2c_ctrl_write_reg_mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB, indata)
#define REGI2C_READ_MASK(block, reg_add) \
regi2c_ctrl_read_reg_mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB)
#define REGI2C_WRITE(block, reg_add, indata) \
regi2c_ctrl_write_reg(block, block##_HOSTID, reg_add, indata)
#define REGI2C_READ(block, reg_add) \
regi2c_ctrl_read_reg(block, block##_HOSTID, reg_add)
/**
* Restore regi2c analog calibration related configuration registers.
* This is a workaround, and is fixed on later chips
*/
#if REGI2C_ANA_CALI_PD_WORKAROUND
void regi2c_analog_cali_reg_read(void);
void regi2c_analog_cali_reg_write(void);
#endif //#if ADC_CALI_PD_WORKAROUND
#ifdef __cplusplus
}
#endif

5
components/esp_hw_support/port/esp32s2/rtc_clk.c
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@ -21,11 +21,14 @@
#include "soc/efuse_reg.h"
#include "soc/syscon_reg.h"
#include "esp_rom_sys.h"
#include "regi2c_ctrl.h"
#include "esp_hw_log.h"
#include "rtc_clk_common.h"
#include "sdkconfig.h"
#include "regi2c_ctrl.h"
#include "regi2c_apll.h"
#include "regi2c_bbpll.h"
static const char *TAG = "rtc_clk";
#define RTC_PLL_FREQ_320M 320

7
components/esp_hw_support/port/esp32s3/private_include/regi2c_saradc.h
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@ -73,10 +73,3 @@
#define I2C_SARADC_TSENS_DAC 0x6
#define I2C_SARADC_TSENS_DAC_MSB 3
#define I2C_SARADC_TSENS_DAC_LSB 0
/**
* Restore regi2c analog calibration related configuration registers.
* This is a workaround, and is fixed on later chips
*/
#define REGI2C_ANA_CALI_PD_WORKAROUND 1
#define REGI2C_ANA_CALI_BYTE_NUM 8

95
components/esp_hw_support/port/esp32s3/regi2c_ctrl.h
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@ -1,95 +0,0 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "regi2c_bbpll.h"
#include "regi2c_dig_reg.h"
#include "regi2c_lp_bias.h"
#include "regi2c_saradc.h"
#ifdef __cplusplus
extern "C" {
#endif
/* Analog function control register */
#define I2C_MST_ANA_CONF0_REG 0x6000E040
#define I2C_MST_BBPLL_STOP_FORCE_HIGH (BIT(2))
#define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3))
#define ANA_CONFIG_REG 0x6000E044
#define ANA_CONFIG_S (8)
#define ANA_CONFIG_M (0x3FF)
/* Clear to enable APLL */
#define I2C_APLL_M (BIT(14))
/* Clear to enable BBPLL */
#define I2C_BBPLL_M (BIT(17))
/* Clear to enable SAR */
#define I2C_SAR_M (BIT(18))
#define ANA_CONFIG2_REG 0x6000E048
#define ANA_SAR_CFG2_M (BIT(16))
/* ROM functions which read/write internal control bus */
uint8_t rom_i2c_readReg(uint8_t block, uint8_t host_id, uint8_t reg_add);
uint8_t rom_i2c_readReg_Mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb);
void rom_i2c_writeReg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data);
void rom_i2c_writeReg_Mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data);
#ifdef BOOTLOADER_BUILD
/**
* If compiling for the bootloader, ROM functions can be called directly,
* without the need of a lock.
*/
#define regi2c_ctrl_read_reg rom_i2c_readReg
#define regi2c_ctrl_read_reg_mask rom_i2c_readReg_Mask
#define regi2c_ctrl_write_reg rom_i2c_writeReg
#define regi2c_ctrl_write_reg_mask rom_i2c_writeReg_Mask
#else
#define i2c_read_reg_raw rom_i2c_readReg
#define i2c_read_reg_mask_raw rom_i2c_readReg_Mask
#define i2c_write_reg_raw rom_i2c_writeReg
#define i2c_write_reg_mask_raw rom_i2c_writeReg_Mask
uint8_t regi2c_ctrl_read_reg(uint8_t block, uint8_t host_id, uint8_t reg_add);
uint8_t regi2c_ctrl_read_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb);
void regi2c_ctrl_write_reg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data);
void regi2c_ctrl_write_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data);
#endif // BOOTLOADER_BUILD
/* Convenience macros for the above functions, these use register definitions
* from regi2c_bbpll.h/regi2c_dig_reg.h/regi2c_ulp.h header files.
*/
#define REGI2C_WRITE_MASK(block, reg_add, indata) \
regi2c_ctrl_write_reg_mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB, indata)
#define REGI2C_READ_MASK(block, reg_add) \
regi2c_ctrl_read_reg_mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB)
#define REGI2C_WRITE(block, reg_add, indata) \
regi2c_ctrl_write_reg(block, block##_HOSTID, reg_add, indata)
#define REGI2C_READ(block, reg_add) \
regi2c_ctrl_read_reg(block, block##_HOSTID, reg_add)
/**
* Restore regi2c analog calibration related configuration registers.
* This is a workaround, and is fixed on later chips
*/
#if REGI2C_ANA_CALI_PD_WORKAROUND
void regi2c_analog_cali_reg_read(void);
void regi2c_analog_cali_reg_write(void);
#endif //#if ADC_CALI_PD_WORKAROUND
#ifdef __cplusplus
}
#endif

2
components/esp_hw_support/port/esp32s3/rtc_clk.c
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@ -22,6 +22,8 @@
#include "soc/system_reg.h"
#include "esp_rom_sys.h"
#include "regi2c_ctrl.h"
#include "regi2c_dig_reg.h"
#include "regi2c_bbpll.h"
#include "esp_hw_log.h"
#include "rtc_clk_common.h"
#include "hal/usb_serial_jtag_ll.h"

2
components/esp_hw_support/port/esp32s3/rtc_init.c
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@ -15,7 +15,9 @@
#include "soc/extmem_reg.h"
#include "soc/syscon_reg.h"
#include "regi2c_ctrl.h"
#include "regi2c_lp_bias.h"
#include "regi2c_ulp.h"
#include "regi2c_dig_reg.h"
#include "esp_hw_log.h"
#include "esp_err.h"
#include "esp_attr.h"

1
components/esp_hw_support/port/esp32s3/rtc_sleep.c
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@ -18,6 +18,7 @@
#include "soc/fe_reg.h"
#include "soc/rtc.h"
#include "regi2c_ctrl.h"
#include "regi2c_dig_reg.h"
#include "soc/rtc.h"
#define RTC_CNTL_MEM_FOLW_CPU (RTC_CNTL_SLOWMEM_FOLW_CPU | RTC_CNTL_FASTMEM_FOLW_CPU)

16
components/esp_hw_support/regi2c_ctrl.c
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@ -4,18 +4,19 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "regi2c_ctrl.h"
#include "esp_attr.h"
#include <stdint.h>
#include <freertos/FreeRTOS.h>
#include <freertos/semphr.h>
#include "freertos/FreeRTOS.h"
#include "freertos/semphr.h"
#include "regi2c_ctrl.h"
static portMUX_TYPE mux = portMUX_INITIALIZER_UNLOCKED;
uint8_t IRAM_ATTR regi2c_ctrl_read_reg(uint8_t block, uint8_t host_id, uint8_t reg_add)
{
portENTER_CRITICAL_ISR(&mux);
uint8_t value = i2c_read_reg_raw(block, host_id, reg_add);
uint8_t value = regi2c_read_reg_raw(block, host_id, reg_add);
portEXIT_CRITICAL_ISR(&mux);
return value;
}
@ -23,7 +24,7 @@ uint8_t IRAM_ATTR regi2c_ctrl_read_reg(uint8_t block, uint8_t host_id, uint8_t r
uint8_t IRAM_ATTR regi2c_ctrl_read_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb)
{
portENTER_CRITICAL_ISR(&mux);
uint8_t value = i2c_read_reg_mask_raw(block, host_id, reg_add, msb, lsb);
uint8_t value = regi2c_read_reg_mask_raw(block, host_id, reg_add, msb, lsb);
portEXIT_CRITICAL_ISR(&mux);
return value;
}
@ -31,14 +32,14 @@ uint8_t IRAM_ATTR regi2c_ctrl_read_reg_mask(uint8_t block, uint8_t host_id, uint
void IRAM_ATTR regi2c_ctrl_write_reg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data)
{
portENTER_CRITICAL_ISR(&mux);
i2c_write_reg_raw(block, host_id, reg_add, data);
regi2c_write_reg_raw(block, host_id, reg_add, data);
portEXIT_CRITICAL_ISR(&mux);
}
void IRAM_ATTR regi2c_ctrl_write_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data)
{
portENTER_CRITICAL_ISR(&mux);
i2c_write_reg_mask_raw(block, host_id, reg_add, msb, lsb, data);
regi2c_write_reg_mask_raw(block, host_id, reg_add, msb, lsb, data);
portEXIT_CRITICAL_ISR(&mux);
}
@ -47,6 +48,7 @@ void IRAM_ATTR regi2c_ctrl_write_reg_mask(uint8_t block, uint8_t host_id, uint8_
* This is a workaround, and is fixed on later chips
*/
#if REGI2C_ANA_CALI_PD_WORKAROUND
#include "regi2c_saradc.h"
static DRAM_ATTR uint8_t reg_val[REGI2C_ANA_CALI_BYTE_NUM];

3
components/esp_rom/CMakeLists.txt
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@ -17,7 +17,8 @@ else()
"patches/esp_rom_sys.c"
"patches/esp_rom_uart.c"
"patches/esp_rom_spiflash.c"
"patches/esp_rom_tjpgd.c")
"patches/esp_rom_tjpgd.c"
"patches/esp_rom_regi2c.c")
list(APPEND private_required_comp soc hal)
endif()

5
components/esp_rom/esp32/ld/esp32.rom.api.ld
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@ -48,3 +48,8 @@ PROVIDE ( esp_rom_get_cpu_ticks_per_us = ets_get_cpu_frequency );
PROVIDE ( esp_rom_spiflash_set_bp = esp_rom_spiflash_lock );
PROVIDE ( esp_rom_spiflash_write_enable = SPI_write_enable);
PROVIDE ( esp_rom_regi2c_read = rom_i2c_readReg );
PROVIDE ( esp_rom_regi2c_read_mask = rom_i2c_readReg_Mask );
PROVIDE ( esp_rom_regi2c_write = rom_i2c_writeReg );
PROVIDE ( esp_rom_regi2c_write_mask = rom_i2c_writeReg_Mask );

5
components/esp_rom/esp32c2/ld/esp32c2.rom.api.ld
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@ -43,3 +43,8 @@ PROVIDE ( esp_rom_get_cpu_ticks_per_us = ets_get_cpu_frequency );
PROVIDE( esp_rom_spiflash_attach = spi_flash_attach );
PROVIDE ( esp_rom_spiflash_clear_bp = esp_rom_spiflash_unlock );
PROVIDE ( esp_rom_spiflash_write_enable = SPI_write_enable);
PROVIDE ( esp_rom_regi2c_read = rom_i2c_readReg );
PROVIDE ( esp_rom_regi2c_read_mask = rom_i2c_readReg_Mask );
PROVIDE ( esp_rom_regi2c_write = rom_i2c_writeReg );
PROVIDE ( esp_rom_regi2c_write_mask = rom_i2c_writeReg_Mask );

7
components/esp_rom/esp32c3/ld/esp32c3.rom.api.ld
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@ -44,4 +44,9 @@ PROVIDE ( esp_rom_route_intr_matrix = intr_matrix_set );
PROVIDE ( esp_rom_get_cpu_ticks_per_us = ets_get_cpu_frequency );
PROVIDE ( esp_rom_spiflash_clear_bp = esp_rom_spiflash_unlock );
PROVIDE ( esp_rom_spiflash_write_enable = SPI_write_enable);
PROVIDE ( esp_rom_spiflash_write_enable = SPI_write_enable );
PROVIDE ( esp_rom_regi2c_read = rom_i2c_readReg );
PROVIDE ( esp_rom_regi2c_read_mask = rom_i2c_readReg_Mask );
PROVIDE ( esp_rom_regi2c_write = rom_i2c_writeReg );
PROVIDE ( esp_rom_regi2c_write_mask = rom_i2c_writeReg_Mask );

5
components/esp_rom/esp32h2/ld/rev1/esp32h2.rom.api.ld
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@ -48,3 +48,8 @@ PROVIDE ( esp_rom_get_cpu_ticks_per_us = ets_get_cpu_frequency );
PROVIDE ( esp_rom_spiflash_clear_bp = esp_rom_spiflash_unlock );
PROVIDE ( esp_rom_spiflash_write_enable = SPI_write_enable);
PROVIDE ( esp_rom_regi2c_read = rom_i2c_readReg );
PROVIDE ( esp_rom_regi2c_read_mask = rom_i2c_readReg_Mask );
PROVIDE ( esp_rom_regi2c_write = rom_i2c_writeReg );
PROVIDE ( esp_rom_regi2c_write_mask = rom_i2c_writeReg_Mask );

5
components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.api.ld
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@ -48,3 +48,8 @@ PROVIDE ( esp_rom_get_cpu_ticks_per_us = ets_get_cpu_frequency );
PROVIDE ( esp_rom_spiflash_clear_bp = esp_rom_spiflash_unlock );
PROVIDE ( esp_rom_spiflash_write_enable = SPI_write_enable);
PROVIDE ( esp_rom_regi2c_read = rom_i2c_readReg );
PROVIDE ( esp_rom_regi2c_read_mask = rom_i2c_readReg_Mask );
PROVIDE ( esp_rom_regi2c_write = rom_i2c_writeReg );
PROVIDE ( esp_rom_regi2c_write_mask = rom_i2c_writeReg_Mask );

5
components/esp_rom/esp32s3/ld/esp32s3.rom.api.ld
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@ -49,3 +49,8 @@ PROVIDE ( esp_rom_get_cpu_ticks_per_us = ets_get_cpu_frequency );
PROVIDE( esp_rom_spiflash_attach = spi_flash_attach );
PROVIDE ( esp_rom_spiflash_clear_bp = esp_rom_spiflash_unlock );
PROVIDE ( esp_rom_spiflash_write_enable = SPI_write_enable);
PROVIDE ( esp_rom_regi2c_read = rom_i2c_readReg );
PROVIDE ( esp_rom_regi2c_read_mask = rom_i2c_readReg_Mask );
PROVIDE ( esp_rom_regi2c_write = rom_i2c_writeReg );
PROVIDE ( esp_rom_regi2c_write_mask = rom_i2c_writeReg_Mask );

63
components/esp_rom/include/esp_rom_regi2c.h 100644
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@ -0,0 +1,63 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* Espressif private functions. Not for peripherals. Don't use it in your app.
*/
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Read internal register
*
* @param block Block of the register
* @param host_id Host of the register
* @param reg_add Address of the register
* @return uint8_t Register value
*/
uint8_t esp_rom_regi2c_read(uint8_t block, uint8_t host_id, uint8_t reg_add);
/**
* @brief Read internal register, in bits
*
* @param block Block of the register
* @param host_id Host of the register
* @param reg_add Address of the register
* @param msb MSB of the register
* @param lsb LSB of the register
* @return uint8_t Register value
*/
uint8_t esp_rom_regi2c_read_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb);
/**
* @brief Write internal register
*
* @param block Block of the register
* @param host_id Host of the register
* @param reg_add Address of the register
* @param data Value to write
*/
void esp_rom_regi2c_write(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data);
/**
* @brief Write internal register, in bits
*
* @param block Block of the register
* @param host_id Host of the register
* @param reg_add Address of the register
* @param msb MSB of the register
* @param lsb LSB of the register
* @param data Value to write
*/
void esp_rom_regi2c_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data);
#ifdef __cplusplus
}
#endif

1
components/esp_rom/linker.lf
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@ -2,3 +2,4 @@
archive: libesp_rom.a
entries:
esp_rom_spiflash (noflash)
esp_rom_regi2c (noflash)

25
components/esp_hw_support/port/esp32s2/regi2c_ctrl.c → components/esp_rom/patches/esp_rom_regi2c.c
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@ -1,13 +1,16 @@
/*
* SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/soc.h"
#include <stdlib.h>
#include "esp_bit_defs.h"
#include "soc/syscon_reg.h"
#include "regi2c_ctrl.h"
#include "regi2c_brownout.h"
#include "esp_rom_caps.h"
#include "sdkconfig.h"
#if CONFIG_IDF_TARGET_ESP32S2
#define I2C_RTC_WIFI_CLK_EN (SYSCON_WIFI_CLK_EN_REG)
@ -79,6 +82,11 @@
#define I2C_RTC_MAGIC_DEFAULT (0x1c40)
#define I2C_BOD 0x61
#define I2C_BBPLL 0x66
#define I2C_SAR_ADC 0X69
#define I2C_APLL 0X6D
static void i2c_rtc_enable_block(uint8_t block)
{
REG_SET_FIELD(I2C_RTC_CONFIG0, I2C_RTC_MAGIC_CTRL, I2C_RTC_MAGIC_DEFAULT);
@ -100,7 +108,7 @@ static void i2c_rtc_enable_block(uint8_t block)
}
}
uint8_t i2c_rtc_read_reg(uint8_t block, uint8_t host_id, uint8_t reg_add)
uint8_t esp_rom_regi2c_read(uint8_t block, uint8_t host_id, uint8_t reg_add)
{
i2c_rtc_enable_block(block);
@ -111,7 +119,7 @@ uint8_t i2c_rtc_read_reg(uint8_t block, uint8_t host_id, uint8_t reg_add)
return REG_GET_FIELD(I2C_RTC_CONFIG2, I2C_RTC_DATA);
}
uint8_t i2c_rtc_read_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb)
uint8_t esp_rom_regi2c_read_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb)
{
assert(msb - lsb < 8);
i2c_rtc_enable_block(block);
@ -124,7 +132,7 @@ uint8_t i2c_rtc_read_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, u
return (uint8_t)((data >> lsb) & (~(0xFFFFFFFF << (msb - lsb + 1))));
}
void i2c_rtc_write_reg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data)
void esp_rom_regi2c_write(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data)
{
i2c_rtc_enable_block(block);
@ -136,7 +144,7 @@ void i2c_rtc_write_reg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t
while (REG_GET_BIT(I2C_RTC_CONFIG2, I2C_RTC_BUSY));
}
void i2c_rtc_write_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data)
void esp_rom_regi2c_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data)
{
assert(msb - lsb < 8);
i2c_rtc_enable_block(block);
@ -157,3 +165,4 @@ void i2c_rtc_write_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uin
REG_WRITE(I2C_RTC_CONFIG2, temp);
while (REG_GET_BIT(I2C_RTC_CONFIG2, I2C_RTC_BUSY));
}
#endif //CONFIG_IDF_TARGET_ESP32S2

2
components/hal/esp32c2/brownout_hal.c
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@ -8,7 +8,7 @@
#include "hal/brownout_hal.h"
#include "soc/rtc_cntl_struct.h"
#include "soc/rtc_cntl_reg.h"
#include "regi2c_ctrl.h"
#include "esp_private/regi2c_ctrl.h"
#include "regi2c_brownout.h"

4
components/hal/esp32c2/include/hal/adc_ll.h
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@ -7,7 +7,6 @@
#include <stdbool.h>
#include <stdlib.h>
#include "regi2c_ctrl.h"
#include "esp_attr.h"
#include "soc/adc_periph.h"
@ -18,6 +17,9 @@
#include "hal/misc.h"
#include "hal/adc_types.h"
#include "esp_private/regi2c_ctrl.h"
#include "regi2c_saradc.h"
#ifdef __cplusplus
extern "C" {
#endif

20
components/hal/esp32c3/brownout_hal.c
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@ -1,22 +1,14 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "hal/brownout_hal.h"
#include "soc/rtc_cntl_struct.h"
#include "soc/rtc_cntl_reg.h"
#include "regi2c_ctrl.h"
#include "esp_private/regi2c_ctrl.h"
#include "regi2c_brownout.h"

4
components/hal/esp32c3/include/hal/adc_ll.h
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@ -7,7 +7,6 @@
#include <stdbool.h>
#include <stdlib.h>
#include "regi2c_ctrl.h"
#include "esp_attr.h"
#include "soc/adc_periph.h"
@ -18,6 +17,9 @@
#include "hal/misc.h"
#include "hal/adc_types.h"
#include "esp_private/regi2c_ctrl.h"
#include "regi2c_saradc.h"
#ifdef __cplusplus
extern "C" {
#endif

3
components/hal/esp32c3/include/hal/temperature_sensor_ll.h
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@ -16,7 +16,8 @@
#include <stdbool.h>
#include <stdlib.h>
#include "regi2c_ctrl.h"
#include "esp_private/regi2c_ctrl.h"
#include "regi2c_saradc.h"
#include "soc/apb_saradc_struct.h"
#include "soc/soc.h"
#include "soc/soc_caps.h"

20
components/hal/esp32h2/brownout_hal.c
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@ -1,23 +1,15 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "hal/brownout_hal.h"
#include "soc/rtc_cntl_struct.h"
#include "soc/rtc_cntl_reg.h"
#include "regi2c_ctrl.h"
#include "i2c_pmu.h"
#include "esp_private/regi2c_ctrl.h"
#include "regi2c_brownout.h"

4
components/hal/esp32h2/include/hal/adc_ll.h
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@ -7,7 +7,6 @@
#include <stdbool.h>
#include <stdlib.h>
#include "regi2c_ctrl.h"
#include "esp_attr.h"
#include "soc/adc_periph.h"
@ -18,6 +17,9 @@
#include "soc/rtc_cntl_reg.h"
#include "hal/misc.h"
#include "esp_private/regi2c_ctrl.h"
#include "regi2c_saradc.h"
#ifdef __cplusplus
extern "C" {
#endif

3
components/hal/esp32h2/include/hal/temperature_sensor_ll.h
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@ -16,7 +16,8 @@
#include <stdbool.h>
#include <stdlib.h>
#include "regi2c_ctrl.h"
#include "esp_private/regi2c_ctrl.h"
#include "regi2c_saradc.h"
#include "soc/apb_saradc_struct.h"
#include "soc/soc.h"
#include "soc/soc_caps.h"

20
components/hal/esp32s2/brownout_hal.c
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@ -1,22 +1,14 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "hal/brownout_hal.h"
#include "soc/rtc_cntl_struct.h"
#include "soc/rtc_cntl_reg.h"
#include "regi2c_ctrl.h"
#include "esp_private/regi2c_ctrl.h"
#include "regi2c_brownout.h"

5
components/hal/esp32s2/include/hal/adc_ll.h
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -15,7 +15,8 @@
#include "soc/apb_saradc_reg.h"
#include "soc/rtc_cntl_struct.h"
#include "soc/rtc_cntl_reg.h"
#include "regi2c_ctrl.h"
#include "esp_private/regi2c_ctrl.h"
#include "regi2c_saradc.h"
#ifdef __cplusplus
extern "C" {

3
components/hal/esp32s2/include/hal/temperature_sensor_ll.h
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@ -15,7 +15,8 @@
#pragma once
#include <stdbool.h>
#include "regi2c_ctrl.h"
#include "esp_private/regi2c_ctrl.h"
#include "regi2c_saradc.h"
#include "soc/apb_saradc_struct.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/sens_struct.h"

20
components/hal/esp32s3/brownout_hal.c
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@ -1,22 +1,14 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "hal/brownout_hal.h"
#include "soc/rtc_cntl_struct.h"
#include "soc/rtc_cntl_reg.h"
#include "regi2c_ctrl.h"
#include "esp_private/regi2c_ctrl.h"
#include "regi2c_brownout.h"

4
components/hal/esp32s3/include/hal/adc_ll.h
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@ -7,7 +7,6 @@
#include <stdio.h>
#include <stdbool.h>
#include "regi2c_ctrl.h"
#include "soc/adc_periph.h"
#include "hal/adc_types.h"
@ -18,6 +17,9 @@
#include "soc/rtc_cntl_reg.h"
#include "hal/misc.h"
#include "esp_private/regi2c_ctrl.h"
#include "regi2c_saradc.h"
#ifdef __cplusplus
extern "C" {
#endif

3
components/hal/esp32s3/include/hal/temperature_sensor_ll.h
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@ -15,7 +15,8 @@
#pragma once
#include <stdbool.h>
#include "regi2c_ctrl.h"
#include "esp_private/regi2c_ctrl.h"
#include "regi2c_saradc.h"
#include "soc/apb_saradc_struct.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/sens_struct.h"

18
components/soc/esp32/include/soc/regi2c_defs.h 100644
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@ -0,0 +1,18 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "esp_bit_defs.h"
/* Analog function control register */
#define ANA_CONFIG_REG 0x6000E044
#define ANA_CONFIG_S (8)
#define ANA_CONFIG_M (0x3FF)
/* Clear to enable APLL */
#define I2C_APLL_M (BIT(14))
/* Clear to enable BBPLL */
#define I2C_BBPLL_M (BIT(17))

36
components/soc/esp32c2/include/soc/regi2c_defs.h 100644
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@ -0,0 +1,36 @@
/*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "esp_bit_defs.h"
/* Analog function control register */
#define I2C_MST_ANA_CONF0_REG 0x6000E040
#define I2C_MST_BBPLL_STOP_FORCE_HIGH (BIT(2))
#define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3))
#define ANA_CONFIG_REG 0x6000E044
#define ANA_CONFIG_S (8)
#define ANA_CONFIG_M (0x3FF)
#define ANA_I2C_SAR_FORCE_PD BIT(18)
#define ANA_I2C_BBPLL_M BIT(17) /* Clear to enable BBPLL */
#define ANA_I2C_APLL_M BIT(14) /* Clear to enable APLL */
#define ANA_CONFIG2_REG 0x6000E048
#define ANA_CONFIG2_M BIT(18)
#define ANA_I2C_SAR_FORCE_PU BIT(16)
/**
* Restore regi2c analog calibration related configuration registers.
* This is a workaround, and is fixed on later chips
*/
#define REGI2C_ANA_CALI_PD_WORKAROUND 1
#define REGI2C_ANA_CALI_BYTE_NUM 8

35
components/soc/esp32c3/include/soc/regi2c_defs.h 100644
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@ -0,0 +1,35 @@
/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "esp_bit_defs.h"
/* Analog function control register */
#define I2C_MST_ANA_CONF0_REG 0x6000E040
#define I2C_MST_BBPLL_STOP_FORCE_HIGH (BIT(2))
#define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3))
#define ANA_CONFIG_REG 0x6000E044
#define ANA_CONFIG_S (8)
#define ANA_CONFIG_M (0x3FF)
#define ANA_I2C_SAR_FORCE_PD BIT(18)
#define ANA_I2C_BBPLL_M BIT(17) /* Clear to enable BBPLL */
#define ANA_I2C_APLL_M BIT(14) /* Clear to enable APLL */
#define ANA_CONFIG2_REG 0x6000E048
#define ANA_CONFIG2_M BIT(18)
#define ANA_I2C_SAR_FORCE_PU BIT(16)
/**
* Restore regi2c analog calibration related configuration registers.
* This is a workaround, and is fixed on later chips
*/
#define REGI2C_ANA_CALI_PD_WORKAROUND 1
#define REGI2C_ANA_CALI_BYTE_NUM 8

29
components/soc/esp32h2/include/soc/regi2c_defs.h 100644
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@ -0,0 +1,29 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "esp_bit_defs.h"
/* Analog function control register */
#define I2C_MST_ANA_CONF0_REG 0x6000E040
#define I2C_MST_BBPLL_STOP_FORCE_HIGH (BIT(2))
#define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3))
#define ANA_CONFIG_REG 0x6000E044
#define ANA_CONFIG_S (8)
#define ANA_CONFIG_M (0x3FF)
#define ANA_I2C_SAR_FORCE_PD BIT(18)
#define ANA_I2C_BBPLL_M BIT(17) /* Clear to enable BBPLL */
#define ANA_I2C_APLL_M BIT(14) /* Clear to enable APLL */
#define ANA_CONFIG2_REG 0x6000E048
#define ANA_CONFIG2_M BIT(18)
#define ANA_I2C_SAR_FORCE_PU BIT(16)

30
components/soc/esp32s2/include/soc/regi2c_defs.h 100644
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@ -0,0 +1,30 @@
/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "esp_bit_defs.h"
/* Analog function control register */
#define ANA_CONFIG_REG 0x6000E044
#define ANA_CONFIG_S (8)
#define ANA_CONFIG_M (0x3FF)
/* Clear to enable APLL */
#define I2C_APLL_M (BIT(14))
/* Clear to enable BBPLL */
#define I2C_BBPLL_M (BIT(17))
/* Clear to enable SAR */
#define I2C_SAR_M (BIT(18))
#define ANA_CONFIG2_REG 0x6000E048
#define ANA_SAR_CFG2_M (BIT(16))
/**
* Restore regi2c analog calibration related configuration registers.
* This is a workaround, and is fixed on later chips
*/
#define REGI2C_ANA_CALI_PD_WORKAROUND 1
#define REGI2C_ANA_CALI_BYTE_NUM 8

34
components/soc/esp32s3/include/soc/regi2c_defs.h 100644
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@ -0,0 +1,34 @@
/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "esp_bit_defs.h"
/* Analog function control register */
#define I2C_MST_ANA_CONF0_REG 0x6000E040
#define I2C_MST_BBPLL_STOP_FORCE_HIGH (BIT(2))
#define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3))
#define ANA_CONFIG_REG 0x6000E044
#define ANA_CONFIG_S (8)
#define ANA_CONFIG_M (0x3FF)
/* Clear to enable APLL */
#define I2C_APLL_M (BIT(14))
/* Clear to enable BBPLL */
#define I2C_BBPLL_M (BIT(17))
/* Clear to enable SAR */
#define I2C_SAR_M (BIT(18))
#define ANA_CONFIG2_REG 0x6000E048
#define ANA_SAR_CFG2_M (BIT(16))
/**
* Restore regi2c analog calibration related configuration registers.
* This is a workaround, and is fixed on later chips
*/
#define REGI2C_ANA_CALI_PD_WORKAROUND 1
#define REGI2C_ANA_CALI_BYTE_NUM 8

4
tools/ci/check_copyright_ignore.txt
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@ -847,7 +847,6 @@ components/hal/esp32/include/hal/twai_ll.h
components/hal/esp32/include/hal/uart_ll.h
components/hal/esp32/interrupt_descriptor_table.c
components/hal/esp32/touch_sensor_hal.c
components/hal/esp32c3/brownout_hal.c
components/hal/esp32c3/hmac_hal.c
components/hal/esp32c3/include/hal/adc_hal_conf.h
components/hal/esp32c3/include/hal/aes_ll.h
@ -870,7 +869,6 @@ components/hal/esp32c3/include/hal/twai_ll.h
components/hal/esp32c3/include/hal/uhci_ll.h
components/hal/esp32c3/include/hal/usb_serial_jtag_ll.h
components/hal/esp32c3/rtc_cntl_hal.c
components/hal/esp32h2/brownout_hal.c
components/hal/esp32h2/hmac_hal.c
components/hal/esp32h2/include/hal/adc_hal_conf.h
components/hal/esp32h2/include/hal/aes_ll.h
@ -893,7 +891,6 @@ components/hal/esp32h2/include/hal/twai_ll.h
components/hal/esp32h2/include/hal/uhci_ll.h
components/hal/esp32h2/include/hal/uhci_types.h
components/hal/esp32h2/include/hal/usb_serial_jtag_ll.h
components/hal/esp32s2/brownout_hal.c
components/hal/esp32s2/cp_dma_hal.c
components/hal/esp32s2/include/hal/adc_hal_conf.h
components/hal/esp32s2/include/hal/aes_ll.h
@ -925,7 +922,6 @@ components/hal/esp32s2/include/hal/twai_ll.h
components/hal/esp32s2/include/hal/usb_ll.h
components/hal/esp32s2/interrupt_descriptor_table.c
components/hal/esp32s2/touch_sensor_hal.c
components/hal/esp32s3/brownout_hal.c
components/hal/esp32s3/include/hal/adc_hal_conf.h
components/hal/esp32s3/include/hal/aes_ll.h
components/hal/esp32s3/include/hal/gpspi_flash_ll.h

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tools/ci/check_public_headers_exceptions.txt
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@ -104,7 +104,6 @@ components/esp_common/include/esp_compiler.h
components/lwip/lwip/src/include/lwip/prot/nd6.h
components/lwip/port/esp32/include/netif/dhcp_state.h
components/soc/src/esp32/rtc_clk_common.h
components/esp_hw_support/port/esp32/regi2c_ctrl.h
components/esp_rom/include/esp32/rom/sha.h
components/esp_rom/include/esp32/rom/secure_boot.h
components/esp_rom/include/esp32c3/rom/spi_flash.h