From d341540a5e940d09de980bc2aefa545e3bebdb86 Mon Sep 17 00:00:00 2001 From: Armando Date: Mon, 8 Apr 2024 11:01:05 +0800 Subject: [PATCH] change(drivers): other driver changes for cache malloc --- components/esp_driver_cam/csi/src/esp_cam_ctlr_csi.c | 2 +- components/esp_driver_jpeg/jpeg_decode.c | 2 +- components/esp_driver_jpeg/jpeg_emit_marker.c | 2 +- components/esp_driver_jpeg/jpeg_encode.c | 2 +- components/esp_driver_spi/src/gpspi/spi_common.c | 2 +- components/esp_driver_spi/src/gpspi/spi_slave.c | 2 +- components/esp_driver_spi/src/gpspi/spi_slave_hd.c | 2 +- components/mbedtls/port/aes/dma/esp_aes_dma_core.c | 6 +++--- components/usb/hcd_dwc.c | 2 +- 9 files changed, 11 insertions(+), 11 deletions(-) diff --git a/components/esp_driver_cam/csi/src/esp_cam_ctlr_csi.c b/components/esp_driver_cam/csi/src/esp_cam_ctlr_csi.c index e5c686fa65..06ee4f9567 100644 --- a/components/esp_driver_cam/csi/src/esp_cam_ctlr_csi.c +++ b/components/esp_driver_cam/csi/src/esp_cam_ctlr_csi.c @@ -149,7 +149,7 @@ esp_err_t esp_cam_new_csi_ctlr(const esp_cam_ctlr_csi_config_t *config, esp_cam_ size_t dma_alignment = 4; //TODO: IDF-9126, replace with dwgdma alignment API size_t cache_alignment = 1; - ESP_GOTO_ON_ERROR(esp_cache_get_alignment(ESP_CACHE_MALLOC_FLAG_PSRAM | ESP_CACHE_MALLOC_FLAG_DMA, &cache_alignment), err, TAG, "failed to get cache alignment"); + ESP_GOTO_ON_ERROR(esp_cache_get_alignment(MALLOC_CAP_SPIRAM | MALLOC_CAP_DMA, &cache_alignment), err, TAG, "failed to get cache alignment"); size_t alignment = MAX(cache_alignment, dma_alignment); ESP_LOGD(TAG, "alignment: 0x%x\n", alignment); diff --git a/components/esp_driver_jpeg/jpeg_decode.c b/components/esp_driver_jpeg/jpeg_decode.c index 7ccf3e5155..d06fa13e1f 100644 --- a/components/esp_driver_jpeg/jpeg_decode.c +++ b/components/esp_driver_jpeg/jpeg_decode.c @@ -289,7 +289,7 @@ void *jpeg_alloc_decoder_mem(size_t size, const jpeg_decode_memory_alloc_cfg_t * FOr input buffer(for decoder is PSRAM write to 2DDMA), no restriction for any align (both cache writeback and requirement from 2DDMA). */ size_t cache_align = 0; - esp_cache_get_alignment(ESP_CACHE_MALLOC_FLAG_PSRAM, &cache_align); + esp_cache_get_alignment(MALLOC_CAP_SPIRAM, &cache_align); if (mem_cfg->buffer_direction == JPEG_DEC_ALLOC_OUTPUT_BUFFER) { size = JPEG_ALIGN_UP(size, cache_align); *allocated_size = size; diff --git a/components/esp_driver_jpeg/jpeg_emit_marker.c b/components/esp_driver_jpeg/jpeg_emit_marker.c index 34db223917..cc6b2be117 100644 --- a/components/esp_driver_jpeg/jpeg_emit_marker.c +++ b/components/esp_driver_jpeg/jpeg_emit_marker.c @@ -228,7 +228,7 @@ esp_err_t emit_com_marker(jpeg_enc_header_info_t *header_info) { // Calculate how many bytes should be compensate to make it byte aligned. size_t cache_align = 0; - esp_cache_get_alignment(ESP_CACHE_MALLOC_FLAG_PSRAM, &cache_align); + esp_cache_get_alignment(MALLOC_CAP_SPIRAM, &cache_align); // compensate_size = aligned_size - SOS marker size(2 * header_info->num_components + 2 + 1 + 3 + 2) - COM marker size(4). int compensate_size = ((header_info->header_len / cache_align + 1) * cache_align) - header_info->header_len - (2 * header_info->num_components + 2 + 1 + 3 + 2) - 4; if (compensate_size < 0) { diff --git a/components/esp_driver_jpeg/jpeg_encode.c b/components/esp_driver_jpeg/jpeg_encode.c index d03b3fcce1..9b5d260baf 100644 --- a/components/esp_driver_jpeg/jpeg_encode.c +++ b/components/esp_driver_jpeg/jpeg_encode.c @@ -294,7 +294,7 @@ void *jpeg_alloc_encoder_mem(size_t size, const jpeg_encode_memory_alloc_cfg_t * For input buffer(for decoder is PSRAM write to 2DDMA), no restriction for any align (both cache writeback and requirement from 2DDMA). */ size_t cache_align = 0; - esp_cache_get_alignment(ESP_CACHE_MALLOC_FLAG_PSRAM, &cache_align); + esp_cache_get_alignment(MALLOC_CAP_SPIRAM, &cache_align); if (mem_cfg->buffer_direction == JPEG_ENC_ALLOC_OUTPUT_BUFFER) { size = JPEG_ALIGN_UP(size, cache_align); *allocated_size = size; diff --git a/components/esp_driver_spi/src/gpspi/spi_common.c b/components/esp_driver_spi/src/gpspi/spi_common.c index 68353afca5..7d5b139a0c 100644 --- a/components/esp_driver_spi/src/gpspi/spi_common.c +++ b/components/esp_driver_spi/src/gpspi/spi_common.c @@ -835,7 +835,7 @@ esp_err_t spi_bus_initialize(spi_host_device_t host_id, const spi_bus_config_t * goto cleanup; } #if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE - esp_cache_get_alignment(ESP_CACHE_MALLOC_FLAG_DMA, (size_t *)&bus_attr->internal_mem_align_size); + esp_cache_get_alignment(MALLOC_CAP_DMA, (size_t *)&bus_attr->internal_mem_align_size); #else bus_attr->internal_mem_align_size = 4; #endif diff --git a/components/esp_driver_spi/src/gpspi/spi_slave.c b/components/esp_driver_spi/src/gpspi/spi_slave.c index 73c9eab3c9..8aa5e2beae 100644 --- a/components/esp_driver_spi/src/gpspi/spi_slave.c +++ b/components/esp_driver_spi/src/gpspi/spi_slave.c @@ -192,7 +192,7 @@ esp_err_t spi_slave_initialize(spi_host_device_t host, const spi_bus_config_t *b #if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE size_t alignment; - esp_cache_get_alignment(ESP_CACHE_MALLOC_FLAG_DMA, &alignment); + esp_cache_get_alignment(MALLOC_CAP_DMA, &alignment); spihost[host]->internal_mem_align_size = alignment; #else spihost[host]->internal_mem_align_size = 4; diff --git a/components/esp_driver_spi/src/gpspi/spi_slave_hd.c b/components/esp_driver_spi/src/gpspi/spi_slave_hd.c index e85698825a..22a53255cf 100644 --- a/components/esp_driver_spi/src/gpspi/spi_slave_hd.c +++ b/components/esp_driver_spi/src/gpspi/spi_slave_hd.c @@ -122,7 +122,7 @@ esp_err_t spi_slave_hd_init(spi_host_device_t host_id, const spi_bus_config_t *b #if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE size_t alignment; - esp_cache_get_alignment(ESP_CACHE_MALLOC_FLAG_DMA, &alignment); + esp_cache_get_alignment(MALLOC_CAP_DMA, &alignment); host->internal_mem_align_size = alignment; #else host->internal_mem_align_size = 4; diff --git a/components/mbedtls/port/aes/dma/esp_aes_dma_core.c b/components/mbedtls/port/aes/dma/esp_aes_dma_core.c index cc64191490..bcf18069b4 100644 --- a/components/mbedtls/port/aes/dma/esp_aes_dma_core.c +++ b/components/mbedtls/port/aes/dma/esp_aes_dma_core.c @@ -291,11 +291,11 @@ static inline size_t get_cache_line_size(const void *addr) #if (CONFIG_SPIRAM && SOC_PSRAM_DMA_CAPABLE) if (esp_ptr_external_ram(addr)) { - ret = esp_cache_get_alignment(ESP_CACHE_MALLOC_FLAG_PSRAM, &cache_line_size); + ret = esp_cache_get_alignment(MALLOC_CAP_SPIRAM, &cache_line_size); } else #endif { - ret = esp_cache_get_alignment(ESP_CACHE_MALLOC_FLAG_DMA, &cache_line_size); + ret = esp_cache_get_alignment(MALLOC_CAP_DMA, &cache_line_size); } if (ret != ESP_OK) { @@ -949,7 +949,7 @@ int esp_aes_process_dma(esp_aes_context *ctx, const unsigned char *input, unsign } if (esp_ptr_external_ram(output)) { size_t dcache_line_size; - ret = esp_cache_get_alignment(ESP_CACHE_MALLOC_FLAG_PSRAM, &dcache_line_size); + ret = esp_cache_get_alignment(MALLOC_CAP_SPIRAM, &dcache_line_size); if (ret != ESP_OK) { return ret; } diff --git a/components/usb/hcd_dwc.c b/components/usb/hcd_dwc.c index 24108d33f6..f9834b7ad8 100644 --- a/components/usb/hcd_dwc.c +++ b/components/usb/hcd_dwc.c @@ -1065,7 +1065,7 @@ void *transfer_descriptor_list_alloc(size_t list_len, size_t *list_len_bytes_out #if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE // Required Transfer Descriptor List size (in bytes) might not be aligned to cache line size, align the size up size_t data_cache_line_size = 0; - esp_cache_get_alignment(ESP_CACHE_MALLOC_FLAG_DMA, &data_cache_line_size); + esp_cache_get_alignment(MALLOC_CAP_DMA, &data_cache_line_size); const size_t required_list_len_bytes = list_len * sizeof(usb_dwc_ll_dma_qtd_t); *list_len_bytes_out = ALIGN_UP_BY(required_list_len_bytes, data_cache_line_size); #else