From c9d6a11d1d43bd5eb2461ef3f5a36effac6c2071 Mon Sep 17 00:00:00 2001 From: laokaiyao Date: Wed, 13 Mar 2024 19:27:08 +0800 Subject: [PATCH] feat(esp32c5mp): support to run hello world on esp32c5 mp --- .gitlab/ci/docs.yml | 2 +- Kconfig | 3 +- .../src/esp32c5/bootloader_esp32c5.c | 1 - .../esp_mm/port/esp32c5/ext_mem_layout.c | 6 ++-- .../esp_system/ld/esp32c5/mp/memory.ld.in | 30 +++++-------------- .../esp_system/ld/esp32c5/mp/sections.ld.in | 30 +++++++++---------- components/hal/esp32c5/include/hal/rmt_ll.h | 5 ++++ components/hal/esp32c5/modem_clock_hal.c | 4 +-- components/hal/include/hal/modem_clock_hal.h | 2 +- components/heap/port/esp32c5/memory_layout.c | 19 ++++++++++++ components/riscv/include/riscv/rv_utils.h | 25 +++++++++++----- .../esp32c5/mp/include/soc/gdma_channel.h} | 0 .../soc/esp32c5/mp/include/soc/gpio_struct.h | 6 ++-- .../soc/esp32c5/mp/include/soc/soc_caps.h | 1 + docs/doxygen/Doxyfile_esp32c5 | 9 +++--- 15 files changed, 81 insertions(+), 62 deletions(-) rename components/{esp_phy/esp32c5/include/.gitkeep => soc/esp32c5/mp/include/soc/gdma_channel.h} (100%) diff --git a/.gitlab/ci/docs.yml b/.gitlab/ci/docs.yml index d98a7d4046..2368f0f7ee 100644 --- a/.gitlab/ci/docs.yml +++ b/.gitlab/ci/docs.yml @@ -102,7 +102,7 @@ check_docs_lang_sync: parallel: matrix: - DOCLANG: ["en", "zh_CN"] - DOCTGT: ["esp32", "esp32s2", "esp32s3", "esp32c3", "esp32c2", "esp32c5", "esp32c6", "esp32h2", "esp32p4"] + DOCTGT: ["esp32", "esp32s2", "esp32s3", "esp32c3", "esp32c2", "esp32c6", "esp32h2", "esp32p4"] check_docs_gh_links: image: $ESP_IDF_DOC_ENV_IMAGE diff --git a/Kconfig b/Kconfig index fe4e12f863..4ec9edb028 100644 --- a/Kconfig +++ b/Kconfig @@ -123,7 +123,7 @@ mainmenu "Espressif IoT Development Framework Configuration" choice IDF_TARGET_ESP32C5_VERSION prompt "ESP32-C5 version" depends on IDF_TARGET_ESP32C5 - default IDF_TARGET_ESP32C5_BETA3_VERSION + default IDF_TARGET_ESP32C5_MP_VERSION help ESP32-C5 will support two versions for a period. This option is for internal use only. @@ -138,6 +138,7 @@ mainmenu "Espressif IoT Development Framework Configuration" bool prompt "ESP32-C5 MP" select ESPTOOLPY_NO_STUB + select IDF_ENV_FPGA endchoice config IDF_TARGET_ESP32P4 diff --git a/components/bootloader_support/src/esp32c5/bootloader_esp32c5.c b/components/bootloader_support/src/esp32c5/bootloader_esp32c5.c index 1b82b0312f..f73ec1291a 100644 --- a/components/bootloader_support/src/esp32c5/bootloader_esp32c5.c +++ b/components/bootloader_support/src/esp32c5/bootloader_esp32c5.c @@ -96,7 +96,6 @@ static inline void bootloader_hardware_init(void) static inline void bootloader_ana_reset_config(void) { -// TODO: IDF-9197 // TODO: [ESP32C5] IDF-8650 //Enable super WDT reset. // bootloader_ana_super_wdt_reset_config(true); diff --git a/components/esp_mm/port/esp32c5/ext_mem_layout.c b/components/esp_mm/port/esp32c5/ext_mem_layout.c index 5ef0cfc003..5797513f45 100644 --- a/components/esp_mm/port/esp32c5/ext_mem_layout.c +++ b/components/esp_mm/port/esp32c5/ext_mem_layout.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -21,7 +21,7 @@ const mmu_mem_region_t g_mmu_mem_regions[SOC_MMU_LINEAR_ADDRESS_REGION_NUM] = { .end = SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH, .size = SOC_BUS_SIZE(SOC_MMU_IRAM0_LINEAR), .bus_id = CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0, - .targets = MMU_TARGET_FLASH0, - .caps = MMU_MEM_CAP_EXEC | MMU_MEM_CAP_READ | MMU_MEM_CAP_32BIT | MMU_MEM_CAP_8BIT, + .targets = MMU_TARGET_FLASH0 | MMU_TARGET_PSRAM0, + .caps = MMU_MEM_CAP_EXEC | MMU_MEM_CAP_READ | MMU_MEM_CAP_WRITE | MMU_MEM_CAP_32BIT | MMU_MEM_CAP_8BIT, }, }; diff --git a/components/esp_system/ld/esp32c5/mp/memory.ld.in b/components/esp_system/ld/esp32c5/mp/memory.ld.in index 41b06aa691..a2d44f20aa 100644 --- a/components/esp_system/ld/esp32c5/mp/memory.ld.in +++ b/components/esp_system/ld/esp32c5/mp/memory.ld.in @@ -15,20 +15,9 @@ #include "sdkconfig.h" #include "ld.common" -/** - * physical memory is mapped twice to the vritual address (IRAM and DRAM). - * `I_D_SRAM_OFFSET` is the offset between the two locations of the same physical memory - */ -#define SRAM_IRAM_START 0x40800000 -#define SRAM_DRAM_START 0x40800000 - -#define I_D_SRAM_OFFSET (SRAM_IRAM_START - SRAM_DRAM_START) -#define SRAM_DRAM_END 0x4086E610 - I_D_SRAM_OFFSET /* 2nd stage bootloader iram_loader_seg start address */ - -#define SRAM_IRAM_ORG (SRAM_IRAM_START) -#define SRAM_DRAM_ORG (SRAM_DRAM_START) - -#define I_D_SRAM_SIZE SRAM_DRAM_END - SRAM_DRAM_ORG +#define SRAM_SEG_START 0x40800000 +#define SRAM_SEG_END 0x4086E610 /* 2nd stage bootloader iram_loader_seg start address */ +#define SRAM_SEG_SIZE SRAM_SEG_END - SRAM_SEG_START #if CONFIG_APP_BUILD_USE_FLASH_SECTIONS /* @@ -37,8 +26,6 @@ #define IDRAM0_2_SEG_SIZE (CONFIG_MMU_PAGE_SIZE << 8) #endif -#define DRAM0_0_SEG_LEN I_D_SRAM_SIZE - MEMORY { /** @@ -47,9 +34,6 @@ MEMORY * are connected to the data port of the CPU and eg allow byte-wise access. */ - /* IRAM for PRO CPU. */ - iram0_0_seg (RX) : org = SRAM_IRAM_ORG, len = I_D_SRAM_SIZE - #if CONFIG_APP_BUILD_USE_FLASH_SECTIONS /* Flash mapped instruction data */ irom_seg (RX) : org = 0x42000020, len = IDRAM0_2_SEG_SIZE - 0x20 @@ -67,7 +51,7 @@ MEMORY * Shared data RAM, excluding memory reserved for ROM bss/data/stack. * Enabling Bluetooth & Trace Memory features in menuconfig will decrease the amount of RAM available. */ - dram0_0_seg (RW) : org = SRAM_DRAM_ORG, len = DRAM0_0_SEG_LEN + sram_seg (RWX) : org = SRAM_SEG_START, len = SRAM_SEG_SIZE #if CONFIG_APP_BUILD_USE_FLASH_SECTIONS /* Flash mapped constant data */ @@ -96,7 +80,7 @@ MEMORY lp_reserved_seg(RW) : org = 0x50000000 + 0x4000 - RESERVE_RTC_MEM, len = RESERVE_RTC_MEM } -/* Heap ends at top of dram0_0_seg */ +/* Heap ends at top of sram_seg */ _heap_end = 0x40000000; _data_seg_org = ORIGIN(rtc_data_seg); @@ -115,13 +99,13 @@ REGION_ALIAS("rtc_reserved_seg", lp_reserved_seg ); #if CONFIG_APP_BUILD_USE_FLASH_SECTIONS REGION_ALIAS("default_code_seg", irom_seg); #else - REGION_ALIAS("default_code_seg", iram0_0_seg); + REGION_ALIAS("default_code_seg", sram_seg); #endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS #if CONFIG_APP_BUILD_USE_FLASH_SECTIONS REGION_ALIAS("default_rodata_seg", drom_seg); #else - REGION_ALIAS("default_rodata_seg", dram0_0_seg); + REGION_ALIAS("default_rodata_seg", sram_seg); #endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS /** diff --git a/components/esp_system/ld/esp32c5/mp/sections.ld.in b/components/esp_system/ld/esp32c5/mp/sections.ld.in index c18b9510f2..c0b76d0af2 100644 --- a/components/esp_system/ld/esp32c5/mp/sections.ld.in +++ b/components/esp_system/ld/esp32c5/mp/sections.ld.in @@ -161,13 +161,13 @@ SECTIONS mapping[iram0_text] - } > iram0_0_seg + } > sram_seg /* Marks the end of IRAM code segment */ .iram0.text_end (NOLOAD) : { ALIGNED_SYMBOL(4, _iram_text_end) - } > iram0_0_seg + } > sram_seg .iram0.data : { @@ -176,7 +176,7 @@ SECTIONS mapping[iram0_data] _iram_data_end = ABSOLUTE(.); - } > iram0_0_seg + } > sram_seg .iram0.bss (NOLOAD) : { @@ -186,16 +186,16 @@ SECTIONS _iram_bss_end = ABSOLUTE(.); ALIGNED_SYMBOL(16, _iram_end) - } > iram0_0_seg + } > sram_seg /** - * This section is required to skip .iram0.text area because iram0_0_seg and - * dram0_0_seg reflect the same address space on different buses. + * This section is required to skip .iram0.text area because sram_seg and + * sram_seg reflect the same address space on different buses. */ .dram0.dummy (NOLOAD): { - . = ORIGIN(dram0_0_seg) + _iram_end - _iram_start; - } > dram0_0_seg + . = ORIGIN(sram_seg) + _iram_end - _iram_start; + } > sram_seg .dram0.data : { @@ -212,7 +212,7 @@ SECTIONS mapping[dram0_data] _data_end = ABSOLUTE(.); - } > dram0_0_seg + } > sram_seg /** * This section holds data that should not be initialized at power up. @@ -227,7 +227,7 @@ SECTIONS *(.noinit .noinit.*) ALIGNED_SYMBOL(4, _noinit_end) - } > dram0_0_seg + } > sram_seg /* Shared RAM */ .dram0.bss (NOLOAD) : @@ -241,9 +241,9 @@ SECTIONS mapping[dram0_bss] ALIGNED_SYMBOL(8, _bss_end) - } > dram0_0_seg + } > sram_seg - ASSERT(((_bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)), "DRAM segment data does not fit.") + ASSERT(((_bss_end - ORIGIN(sram_seg)) <= LENGTH(sram_seg)), "DRAM segment data does not fit.") .flash.text : { @@ -440,7 +440,7 @@ SECTIONS .dram0.heap_start (NOLOAD) : { ALIGNED_SYMBOL(16, _heap_start) - } > dram0_0_seg + } > sram_seg /** * Discarding .rela.* sections results in the following mapping: @@ -451,8 +451,8 @@ SECTIONS /DISCARD/ : { *(.rela.*) } } -ASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)), +ASSERT(((_iram_end - ORIGIN(sram_seg)) <= LENGTH(sram_seg)), "IRAM0 segment data does not fit.") -ASSERT(((_heap_start - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)), +ASSERT(((_heap_start - ORIGIN(sram_seg)) <= LENGTH(sram_seg)), "DRAM segment data does not fit.") diff --git a/components/hal/esp32c5/include/hal/rmt_ll.h b/components/hal/esp32c5/include/hal/rmt_ll.h index 4989a2585e..f62639604c 100644 --- a/components/hal/esp32c5/include/hal/rmt_ll.h +++ b/components/hal/esp32c5/include/hal/rmt_ll.h @@ -13,6 +13,7 @@ #include #include #include +#include "sdkconfig.h" // TODO: [ESP32C5] IDF-8726 #include "hal/misc.h" #include "hal/assert.h" #include "hal/rmt_types.h" @@ -23,6 +24,8 @@ extern "C" { #endif +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION + #define RMT_LL_EVENT_TX_DONE(channel) (1 << (channel)) #define RMT_LL_EVENT_TX_THRES(channel) (1 << ((channel) + 8)) #define RMT_LL_EVENT_TX_LOOP_END(channel) (1 << ((channel) + 12)) @@ -880,6 +883,8 @@ static inline uint32_t rmt_ll_get_tx_loop_interrupt_status(rmt_dev_t *dev) return (dev->int_st.val >> 12) & 0x03; } +#endif // CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32c5/modem_clock_hal.c b/components/hal/esp32c5/modem_clock_hal.c index 5beb69f955..2d917b62d2 100644 --- a/components/hal/esp32c5/modem_clock_hal.c +++ b/components/hal/esp32c5/modem_clock_hal.c @@ -1,10 +1,10 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -// The HAL layer for MODEM CLOCK (ESP32-C6 specific part) +// The HAL layer for MODEM CLOCK (ESP32-C5 specific part) #include #include "soc/soc.h" #include "esp_attr.h" diff --git a/components/hal/include/hal/modem_clock_hal.h b/components/hal/include/hal/modem_clock_hal.h index 27b95cafdd..a898feb63e 100644 --- a/components/hal/include/hal/modem_clock_hal.h +++ b/components/hal/include/hal/modem_clock_hal.h @@ -9,7 +9,7 @@ #pragma once #include "soc/soc_caps.h" -#if SOC_MODEM_CLOCK_IS_INDEPENDENT +#if SOC_MODEM_CLOCK_IS_INDEPENDENT && SOC_MODEM_CLOCK_SUPPORTED #include "hal/modem_syscon_ll.h" #include "hal/modem_lpcon_ll.h" #include "hal/modem_clock_types.h" diff --git a/components/heap/port/esp32c5/memory_layout.c b/components/heap/port/esp32c5/memory_layout.c index b65d0007d6..6ba81dbd37 100644 --- a/components/heap/port/esp32c5/memory_layout.c +++ b/components/heap/port/esp32c5/memory_layout.c @@ -29,6 +29,9 @@ enum { SOC_MEMORY_TYPE_RAM = 0, SOC_MEMORY_TYPE_RTCRAM = 1, +#if CONFIG_IDF_TARGET_ESP32C5_MP_VERSION + SOC_MEMORY_TYPE_SPIRAM = 2, +#endif SOC_MEMORY_TYPE_NUM, }; @@ -49,6 +52,9 @@ const soc_memory_type_desc_t soc_memory_types[SOC_MEMORY_TYPE_NUM] = { /* Mem Type Name High Priority Matching Medium Priorty Matching Low Priority Matching */ [SOC_MEMORY_TYPE_RAM] = { "RAM", { ESP32C5_MEM_COMMON_CAPS | MALLOC_CAP_DMA, 0, 0 }}, [SOC_MEMORY_TYPE_RTCRAM] = { "RTCRAM", { MALLOC_CAP_RTCRAM, ESP32C5_MEM_COMMON_CAPS, 0 }}, +#if CONFIG_IDF_TARGET_ESP32C5_MP_VERSION + [SOC_MEMORY_TYPE_SPIRAM] = { "SPIRAM", { MALLOC_CAP_SPIRAM | MALLOC_CAP_DEFAULT, 0, MALLOC_CAP_8BIT | MALLOC_CAP_32BIT}}, +#endif }; const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t); @@ -67,10 +73,17 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor #define APP_USABLE_DRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE) const soc_memory_region_t soc_memory_regions[] = { +#if CONFIG_SPIRAM && CONFIG_IDF_TARGET_ESP32C5_MP_VERSION + { SOC_EXTRAM_DATA_LOW, (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW),SOC_MEMORY_TYPE_SPIRAM, 0}, //SPI SRAM, if available +#endif { 0x40800000, 0x20000, SOC_MEMORY_TYPE_RAM, 0x40800000, false}, //D/IRAM level0, can be used as trace memory { 0x40820000, 0x20000, SOC_MEMORY_TYPE_RAM, 0x40820000, false}, //D/IRAM level1, can be used as trace memory +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION { 0x40840000, 0x20000, SOC_MEMORY_TYPE_RAM, 0x40840000, false}, //D/IRAM level2, can be used as trace memory { 0x40860000, (APP_USABLE_DRAM_END-0x40860000), SOC_MEMORY_TYPE_RAM, 0x40860000, false}, //D/IRAM level3, can be used as trace memory +#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION + { 0x40840000, (APP_USABLE_DRAM_END-0x40840000), SOC_MEMORY_TYPE_RAM, 0x40840000, false}, //D/IRAM level3, can be used as trace memory +#endif { APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_RAM, APP_USABLE_DRAM_END, true}, //D/IRAM level3, can be used as trace memory (ROM reserved area) #ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP { 0x50000000, 0x4000, SOC_MEMORY_TYPE_RTCRAM, 0, false}, //LPRAM @@ -101,3 +114,9 @@ SOC_RESERVE_MEMORY_REGION(SOC_RTC_DRAM_LOW, (intptr_t)&_rtc_force_slow_end, rtcr #endif SOC_RESERVE_MEMORY_REGION((intptr_t)&_rtc_reserved_start, (intptr_t)&_rtc_reserved_end, rtc_reserved_data); + +#ifdef CONFIG_SPIRAM +/* Reserve the whole possible SPIRAM region here, spiram.c will add some or all of this + * memory to heap depending on the actual SPIRAM chip size. */ +SOC_RESERVE_MEMORY_REGION(SOC_DROM_LOW, SOC_DROM_HIGH, extram_data_region); +#endif diff --git a/components/riscv/include/riscv/rv_utils.h b/components/riscv/include/riscv/rv_utils.h index 31b46cc4ce..9928e57134 100644 --- a/components/riscv/include/riscv/rv_utils.h +++ b/components/riscv/include/riscv/rv_utils.h @@ -140,7 +140,8 @@ FORCE_INLINE_ATTR void rv_utils_set_mtvec(uint32_t mtvec_val) RV_WRITE_CSR(mtvec, mtvec_val); } -#if SOC_INT_CLIC_SUPPORTED +// TODO: [ESP32C5] IDF-8655 need refactor for C5 MP +#if SOC_INT_CLIC_SUPPORTED && !CONFIG_IDF_TARGET_ESP32C5_MP_VERSION FORCE_INLINE_ATTR __attribute__((pure)) uint32_t rv_utils_get_interrupt_level(void) { #if CONFIG_IDF_TARGET_ESP32P4 @@ -184,20 +185,28 @@ FORCE_INLINE_ATTR void rv_utils_intr_disable(uint32_t intr_mask) FORCE_INLINE_ATTR void __attribute__((always_inline)) rv_utils_restore_intlevel(uint32_t restoreval) { + // TODO: [ESP32C5] IDF-8655 need refactor for C5 MP +#if CONFIG_IDF_TARGET_ESP32C5_MP_VERSION + #define MINTTHRESH 0x347 + RV_WRITE_CSR(MINTTHRESH, restoreval); +#elif CONFIG_IDF_TARGET_ESP32C61 // TODO: [ESP32C61] IDF-9261, changed in verify code, pls check // RV_WRITE_CSR(MINTTHRESH, restoreval); +#else REG_SET_FIELD(CLIC_INT_THRESH_REG, CLIC_CPU_INT_THRESH, ((restoreval << (8 - NLBITS))) | 0x1f); +#endif // !CONFIG_IDF_TARGET_ESP32C5_MP_VERSION } FORCE_INLINE_ATTR uint32_t __attribute__((always_inline)) rv_utils_set_intlevel(uint32_t intlevel) { -// TODO: [ESP32C61] IDF-9261, added in verify code, pls check -// #if CONFIG_IDF_TARGET_ESP32C61 -// uint32_t old_thresh = RV_READ_CSR(MINTTHRESH); -// RV_WRITE_CSR(MINTTHRESH, ((intlevel << (8 - NLBITS)) | 0x1f)); -// #else - uint32_t old_mstatus = RV_CLEAR_CSR(mstatus, MSTATUS_MIE); uint32_t old_thresh; + // TODO: [ESP32C5] IDF-8655 need refactor for C5 MP +#if CONFIG_IDF_TARGET_ESP32C5_MP_VERSION + old_thresh = RV_READ_CSR(MINTTHRESH); + RV_WRITE_CSR(MINTTHRESH, ((intlevel << (8 - NLBITS)) | 0x1f)); +#else + // TODO: [ESP32C61] IDF-9261 pls check + uint32_t old_mstatus = RV_CLEAR_CSR(mstatus, MSTATUS_MIE); old_thresh = REG_GET_FIELD(CLIC_INT_THRESH_REG, CLIC_CPU_INT_THRESH); old_thresh = (old_thresh >> (8 - NLBITS)); @@ -212,7 +221,7 @@ FORCE_INLINE_ATTR uint32_t __attribute__((always_inline)) rv_utils_set_intlevel( */ REG_READ(CLIC_INT_THRESH_REG); RV_SET_CSR(mstatus, old_mstatus & MSTATUS_MIE); -// #endif +#endif return old_thresh; } diff --git a/components/esp_phy/esp32c5/include/.gitkeep b/components/soc/esp32c5/mp/include/soc/gdma_channel.h similarity index 100% rename from components/esp_phy/esp32c5/include/.gitkeep rename to components/soc/esp32c5/mp/include/soc/gdma_channel.h diff --git a/components/soc/esp32c5/mp/include/soc/gpio_struct.h b/components/soc/esp32c5/mp/include/soc/gpio_struct.h index f09e9f9879..30980ddd09 100644 --- a/components/soc/esp32c5/mp/include/soc/gpio_struct.h +++ b/components/soc/esp32c5/mp/include/soc/gpio_struct.h @@ -1115,8 +1115,10 @@ typedef struct { volatile gpio_pin31_reg_t pin31; volatile gpio_pin32_reg_t pin32; uint32_t reserved_148[95]; - volatile gpio_func_in_sel_cfg_reg_t func_in_sel_cfg[128]; // 1-5, 18-26, 36-40, 44-45, 67-69, 71-73, 93-96, 117-127 are reserved - uint32_t reserved_48d[384]; + volatile gpio_func_in_sel_cfg_reg_t func_in_sel_cfg[256]; /* 1-5, 18-26, 36-40, 44-45, 67-69, 71-73, 93-96, 117-255 are reserved + * The length ought to match the SIG_GPIO_OUT_IDX that defined in `gpio_sig_map.h` + */ + uint32_t reserved_48d[256]; volatile gpio_func_out_sel_cfg_reg_t func_out_sel_cfg[29]; volatile gpio_func29_out_sel_cfg_reg_t func29_out_sel_cfg; volatile gpio_func30_out_sel_cfg_reg_t func30_out_sel_cfg; diff --git a/components/soc/esp32c5/mp/include/soc/soc_caps.h b/components/soc/esp32c5/mp/include/soc/soc_caps.h index 991108a73b..aa04303056 100644 --- a/components/soc/esp32c5/mp/include/soc/soc_caps.h +++ b/components/soc/esp32c5/mp/include/soc/soc_caps.h @@ -71,6 +71,7 @@ // #define SOC_ECDSA_SUPPORTED 1 // TODO: [ESP32C5] IDF-8618 // #define SOC_KEY_MANAGER_SUPPORTED 1 // TODO: [ESP32C5] IDF-8621 // #define SOC_HUK_SUPPORTED 1 // TODO: [ESP32C5] IDF-8617 +// #define SOC_MODEM_CLOCK_SUPPORTED 1 // TODO: [ESP32C5] IDF-8845 /*-------------------------- XTAL CAPS ---------------------------------------*/ #define SOC_XTAL_SUPPORT_40M 1 diff --git a/docs/doxygen/Doxyfile_esp32c5 b/docs/doxygen/Doxyfile_esp32c5 index a09b545efb..82c15ca68e 100644 --- a/docs/doxygen/Doxyfile_esp32c5 +++ b/docs/doxygen/Doxyfile_esp32c5 @@ -1,10 +1,9 @@ # TODO: IDF-9197 Use beta3 in doc temprory INPUT += \ - $(PROJECT_PATH)/components/soc/$(IDF_TARGET)/beta3/include/soc/soc_caps.h \ - $(PROJECT_PATH)/components/soc/$(IDF_TARGET)/beta3/include/soc/adc_channel.h \ - $(PROJECT_PATH)/components/soc/$(IDF_TARGET)/beta3/include/soc/clk_tree_defs.h \ - $(PROJECT_PATH)/components/soc/$(IDF_TARGET)/beta3/include/soc/gpio_num.h \ - $(PROJECT_PATH)/components/soc/$(IDF_TARGET)/beta3/include/soc/uart_channel.h \ + $(PROJECT_PATH)/components/soc/$(IDF_TARGET)/mp/include/soc/soc_caps.h \ + $(PROJECT_PATH)/components/soc/$(IDF_TARGET)/mp/include/soc/clk_tree_defs.h \ + $(PROJECT_PATH)/components/soc/$(IDF_TARGET)/mp/include/soc/gpio_num.h \ + $(PROJECT_PATH)/components/soc/$(IDF_TARGET)/mp/include/soc/uart_channel.h \ $(PROJECT_PATH)/components/ulp/lp_core/include/lp_core_i2c.h \ $(PROJECT_PATH)/components/ulp/lp_core/include/lp_core_uart.h \ $(PROJECT_PATH)/components/ulp/lp_core/include/ulp_lp_core.h \