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feat(uart): uart(hp,lp) support on esp32p4

pull/12384/head
gaoxu 2023-09-07 15:40:14 +08:00
rodzic 366bb1f99a
commit c7afa0dcef
14 zmienionych plików z 833 dodań i 164 usunięć
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2
components/driver/test_apps/uart/main/test_uart.c
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@ -389,7 +389,7 @@ TEST_CASE("uart int state restored after flush", "[uart]")
};
const uart_port_t uart_echo = UART_NUM_1;
const int uart_tx_signal = U1TXD_OUT_IDX;
const int uart_tx_signal = uart_periph_signal[uart_echo].pins[SOC_UART_TX_PIN_IDX].signal;
const int uart_tx = UART1_TX_PIN;
const int uart_rx = UART1_RX_PIN;
const int buf_size = 256;

79
components/driver/uart/uart.c
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@ -159,6 +159,12 @@ static uart_context_t uart_context[UART_NUM_MAX] = {
#if SOC_UART_HP_NUM > 2
UART_CONTEX_INIT_DEF(UART_NUM_2),
#endif
#if SOC_UART_HP_NUM > 3
UART_CONTEX_INIT_DEF(UART_NUM_3),
#endif
#if SOC_UART_HP_NUM > 4
UART_CONTEX_INIT_DEF(UART_NUM_4),
#endif
#if (SOC_UART_LP_NUM >= 1)
UART_CONTEX_INIT_DEF(LP_UART_NUM_0),
#endif
@ -643,7 +649,7 @@ esp_err_t uart_set_pin(uart_port_t uart_num, int tx_io_num, int rx_io_num, int r
ESP_RETURN_ON_FALSE((rts_io_num < 0 || (GPIO_IS_VALID_OUTPUT_GPIO(rts_io_num))), ESP_FAIL, UART_TAG, "rts_io_num error");
ESP_RETURN_ON_FALSE((cts_io_num < 0 || (GPIO_IS_VALID_GPIO(cts_io_num))), ESP_FAIL, UART_TAG, "cts_io_num error");
}
#if (SOC_UART_LP_NUM >= 1)
#if (SOC_UART_LP_NUM >= 1 && !SOC_LP_GPIO_MATRIX_SUPPORTED)
else { // LP_UART has its fixed IOs
const uart_periph_sig_t *pins = uart_periph_signal[uart_num].pins;
ESP_RETURN_ON_FALSE((tx_io_num < 0 || (tx_io_num == pins[SOC_UART_TX_PIN_IDX].default_gpio)), ESP_FAIL, UART_TAG, "tx_io_num error");
@ -655,31 +661,76 @@ esp_err_t uart_set_pin(uart_port_t uart_num, int tx_io_num, int rx_io_num, int r
/* In the following statements, if the io_num is negative, no need to configure anything. */
if (tx_io_num >= 0 && !uart_try_set_iomux_pin(uart_num, tx_io_num, SOC_UART_TX_PIN_IDX)) {
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[tx_io_num], PIN_FUNC_GPIO);
if (uart_num < SOC_UART_HP_NUM) {
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[tx_io_num], PIN_FUNC_GPIO);
gpio_set_level(tx_io_num, 1);
esp_rom_gpio_connect_out_signal(tx_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_TX_PIN_IDX), 0, 0);
}
#if SOC_LP_GPIO_MATRIX_SUPPORTED
else {
//TODO:IDF-7815
rtc_gpio_set_direction(tx_io_num, RTC_GPIO_MODE_OUTPUT_ONLY);
rtc_gpio_init(tx_io_num);
rtc_gpio_iomux_func_sel(tx_io_num, 1);
LP_GPIO.func10_out_sel_cfg.reg_gpio_func10_out_sel = uart_periph_signal[uart_num].pins[SOC_UART_TX_PIN_IDX].signal;
}
#endif
}
if (rx_io_num >= 0 && !uart_try_set_iomux_pin(uart_num, rx_io_num, SOC_UART_RX_PIN_IDX)) {
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[rx_io_num], PIN_FUNC_GPIO);
gpio_set_pull_mode(rx_io_num, GPIO_PULLUP_ONLY);
gpio_set_direction(rx_io_num, GPIO_MODE_INPUT);
esp_rom_gpio_connect_in_signal(rx_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_RX_PIN_IDX), 0);
if (uart_num < SOC_UART_HP_NUM) {
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[rx_io_num], PIN_FUNC_GPIO);
gpio_set_pull_mode(rx_io_num, GPIO_PULLUP_ONLY);
gpio_set_direction(rx_io_num, GPIO_MODE_INPUT);
esp_rom_gpio_connect_in_signal(rx_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_RX_PIN_IDX), 0);
}
#if SOC_LP_GPIO_MATRIX_SUPPORTED
else {
//TODO:IDF-7815
rtc_gpio_set_direction(rx_io_num, RTC_GPIO_MODE_INPUT_ONLY);
rtc_gpio_init(rx_io_num);
rtc_gpio_iomux_func_sel(rx_io_num, 1);
LP_GPIO.func2_in_sel_cfg.reg_gpio_sig2_in_sel = 1;
LP_GPIO.func2_in_sel_cfg.reg_gpio_func2_in_sel = 11;
}
#endif
}
if (rts_io_num >= 0 && !uart_try_set_iomux_pin(uart_num, rts_io_num, SOC_UART_RTS_PIN_IDX)) {
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[rts_io_num], PIN_FUNC_GPIO);
gpio_set_direction(rts_io_num, GPIO_MODE_OUTPUT);
esp_rom_gpio_connect_out_signal(rts_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_RTS_PIN_IDX), 0, 0);
if (uart_num < SOC_UART_HP_NUM) {
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[rts_io_num], PIN_FUNC_GPIO);
gpio_set_direction(rts_io_num, GPIO_MODE_OUTPUT);
esp_rom_gpio_connect_out_signal(rts_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_RTS_PIN_IDX), 0, 0);
}
#if SOC_LP_GPIO_MATRIX_SUPPORTED
else {
//TODO:IDF-7815
rtc_gpio_set_direction(rts_io_num, RTC_GPIO_MODE_OUTPUT_ONLY);
rtc_gpio_init(rts_io_num);
rtc_gpio_iomux_func_sel(rts_io_num, 1);
LP_GPIO.func10_out_sel_cfg.reg_gpio_func12_out_sel = uart_periph_signal[uart_num].pins[SOC_UART_RTS_PIN_IDX].signal;
}
#endif
}
if (cts_io_num >= 0 && !uart_try_set_iomux_pin(uart_num, cts_io_num, SOC_UART_CTS_PIN_IDX)) {
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[cts_io_num], PIN_FUNC_GPIO);
gpio_set_pull_mode(cts_io_num, GPIO_PULLUP_ONLY);
gpio_set_direction(cts_io_num, GPIO_MODE_INPUT);
esp_rom_gpio_connect_in_signal(cts_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_CTS_PIN_IDX), 0);
if (uart_num < SOC_UART_HP_NUM) {
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[cts_io_num], PIN_FUNC_GPIO);
gpio_set_pull_mode(cts_io_num, GPIO_PULLUP_ONLY);
gpio_set_direction(cts_io_num, GPIO_MODE_INPUT);
esp_rom_gpio_connect_in_signal(cts_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_CTS_PIN_IDX), 0);
}
#if SOC_LP_GPIO_MATRIX_SUPPORTED
else {
//TODO:IDF-7815
rtc_gpio_set_direction(cts_io_num, RTC_GPIO_MODE_INPUT_ONLY);
rtc_gpio_init(cts_io_num);
rtc_gpio_iomux_func_sel(cts_io_num, 1);
LP_GPIO.func2_in_sel_cfg.reg_gpio_sig3_in_sel = 1;
LP_GPIO.func2_in_sel_cfg.reg_gpio_func3_in_sel = 13;
}
#endif
}
return ESP_OK;
}

6
components/esp_hw_support/port/esp32p4/esp_clk_tree.c
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@ -25,6 +25,12 @@ uint32_t *freq_value)
case SOC_MOD_CLK_XTAL:
clk_src_freq = 40 * MHZ;
break;
case SOC_MOD_CLK_XTAL_D2:
clk_src_freq = (40* MHZ) >> 1;
break;
case SOC_MOD_CLK_LP_PLL:
clk_src_freq = 8 * MHZ;
break;
default:
break;
}

542
components/hal/esp32p4/include/hal/uart_ll.h
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Plik diff jest za duży Load Diff

8
components/hal/include/hal/uart_types.h
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -25,6 +25,12 @@ typedef enum {
#if SOC_UART_HP_NUM > 2
UART_NUM_2, /*!< UART port 2 */
#endif
#if SOC_UART_HP_NUM > 3
UART_NUM_3, /*!< UART port 3 */
#endif
#if SOC_UART_HP_NUM > 4
UART_NUM_4, /*!< UART port 4 */
#endif
#if (SOC_UART_LP_NUM >= 1)
LP_UART_NUM_0, /*!< LP UART port 0 */
#endif

8
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
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@ -1037,16 +1037,20 @@ config SOC_FLASH_ENCRYPTION_XTS_AES_128
config SOC_UART_NUM
int
default 2
default 5
config SOC_UART_HP_NUM
int
default 2
default 5
config SOC_UART_FIFO_LEN
int
default 128
config SOC_LP_UART_FIFO_LEN
int
default 16
config SOC_UART_BITRATE_MAX
int
default 5000000

18
components/soc/esp32p4/include/soc/clk_tree_defs.h
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@ -151,7 +151,10 @@ typedef enum {
SOC_MOD_CLK_RC_FAST, /*!< RC_FAST_CLK comes from the internal 20MHz rc oscillator, passing a clock gating to the peripherals */
SOC_MOD_CLK_XTAL, /*!< XTAL_CLK comes from the external 40MHz crystal */
SOC_MOD_CLK_APLL, /*!< Audio PLL is sourced from PLL, and its frequency is configurable through APLL configuration registers */
// For LP peripherals
SOC_MOD_CLK_XTAL_D2, /*!< XTAL_D2_CLK comes from the external 40MHz crystal, passing a div of 2 to the LP peripherals */
SOC_MOD_CLK_INVALID, /*!< Indication of the end of the available module clock sources */
SOC_MOD_CLK_LP_PLL,
} soc_module_clk_t;
//////////////////////////////////////////////////SYSTIMER//////////////////////////////////////////////////////////////
@ -254,7 +257,6 @@ typedef enum {
///////////////////////////////////////////////////UART/////////////////////////////////////////////////////////////////
//TODO: IDF-6511
/**
* @brief Type of UART clock source, reserved for the legacy UART driver
*/
@ -262,9 +264,23 @@ typedef enum {
UART_SCLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< UART source clock is PLL_F80M */
UART_SCLK_RTC = SOC_MOD_CLK_RC_FAST, /*!< UART source clock is RC_FAST */
UART_SCLK_XTAL = SOC_MOD_CLK_XTAL, /*!< UART source clock is XTAL */
#if SOC_CLK_TREE_SUPPORTED
UART_SCLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< UART source clock default choice is PLL_F80M */
#else
UART_SCLK_DEFAULT = SOC_MOD_CLK_XTAL, /*!< UART source clock default choice is XTAL for FPGA environment */
#endif
} soc_periph_uart_clk_src_legacy_t;
/**
* @brief Type of LP_UART clock source
*/
typedef enum {
LP_UART_SCLK_LP_FAST = SOC_MOD_CLK_RTC_FAST, /*!< LP_UART source clock is LP(RTC)_FAST */
LP_UART_SCLK_XTAL_D2 = SOC_MOD_CLK_XTAL_D2, /*!< LP_UART source clock is XTAL_D2 */
LP_UART_SCLK_LP_PLL = SOC_MOD_CLK_LP_PLL, /*!< LP_UART source clock is LP_PLL (8M PLL) */
LP_UART_SCLK_DEFAULT = SOC_MOD_CLK_XTAL_D2, /*!< LP_UART source clock default choice is XTAL_D2 */
} soc_periph_lp_uart_clk_src_t;
//////////////////////////////////////////////////MCPWM/////////////////////////////////////////////////////////////////
/**

3
components/soc/esp32p4/include/soc/lpperi_struct.h
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@ -348,7 +348,7 @@ typedef union {
} lpperi_date_reg_t;
typedef struct {
typedef struct lpperi_dev_t {
volatile lpperi_clk_en_reg_t clk_en;
volatile lpperi_core_clk_sel_reg_t core_clk_sel;
volatile lpperi_reset_en_reg_t reset_en;
@ -364,6 +364,7 @@ typedef struct {
volatile lpperi_date_reg_t date;
} lpperi_dev_t;
extern lpperi_dev_t LPPERI;
#ifndef __cplusplus
_Static_assert(sizeof(lpperi_dev_t) == 0x400, "Invalid size of lpperi_dev_t structure");

9
components/soc/esp32p4/include/soc/soc_caps.h
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@ -208,6 +208,7 @@
// Support to hold a single digital I/O when the digital domain is powered off
#define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1)
// #define SOC_LP_GPIO_MATRIX_SUPPORTED (1)
/*-------------------------- RTCIO CAPS --------------------------------------*/
#define SOC_RTCIO_PIN_COUNT 16
#define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1 /* This macro indicates that the target has separate RTC IOMUX hardware feature,
@ -470,11 +471,13 @@
/*-------------------------- MEMPROT CAPS ------------------------------------*/
/*-------------------------- UART CAPS ---------------------------------------*/
// ESP32-P4 has 2 UARTs
#define SOC_UART_NUM (2)
#define SOC_UART_HP_NUM (2)
// ESP32-P4 has 6 UARTs (5 HP UART, and 1 LP UART)
// The RTC GPIO and sigmap is not supported yet, so make SOC_UART_NUM->5 to avoid lp-uart build errors
#define SOC_UART_NUM (5)
#define SOC_UART_HP_NUM (5)
// #define SOC_UART_LP_NUM (1U)
#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */
#define SOC_LP_UART_FIFO_LEN (16) /*!< The LP UART hardware FIFO length */
#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */
#define SOC_UART_SUPPORT_PLL_F80M_CLK (1) /*!< Support PLL_F80M as the clock source */
#define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */

32
components/soc/esp32p4/include/soc/uart_channel.h
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@ -4,6 +4,36 @@
* SPDX-License-Identifier: Apache-2.0
*/
// This file defines GPIO lookup macros for available UART IO_MUX pins on ESP32C6.
// This file defines GPIO lookup macros for available UART IO_MUX pins on ESP32P4.
#pragma once
//UART0 channels
#define UART_GPIO37_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_TXD_DIRECT_GPIO_NUM 37
#define UART_GPIO38_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_RXD_DIRECT_GPIO_NUM 38
#define UART_GPIO8_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_RTS_DIRECT_GPIO_NUM 8
#define UART_GPIO9_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_CTS_DIRECT_GPIO_NUM 9
#define UART_TXD_GPIO37_DIRECT_CHANNEL UART_GPIO38_DIRECT_CHANNEL
#define UART_RXD_GPIO38_DIRECT_CHANNEL UART_GPIO38_DIRECT_CHANNEL
#define UART_RTS_GPIO8_DIRECT_CHANNEL UART_GPIO8_DIRECT_CHANNEL
#define UART_CTS_GPIO9_DIRECT_CHANNEL UART_GPIO9_DIRECT_CHANNEL
//UART1 channels
#define UART_GPIO10_DIRECT_CHANNEL UART_NUM_1
#define UART_NUM_1_TXD_DIRECT_GPIO_NUM 10
#define UART_GPIO11_DIRECT_CHANNEL UART_NUM_1
#define UART_NUM_1_RXD_DIRECT_GPIO_NUM 11
#define UART_GPIO12_DIRECT_CHANNEL UART_NUM_1
#define UART_NUM_1_RTS_DIRECT_GPIO_NUM 12
#define UART_GPIO13_DIRECT_CHANNEL UART_NUM_1
#define UART_NUM_1_CTS_DIRECT_GPIO_NUM 13
#define UART_TXD_GPIO10_DIRECT_CHANNEL UART_GPIO10_DIRECT_CHANNEL
#define UART_RXD_GPIO11_DIRECT_CHANNEL UART_GPIO11_DIRECT_CHANNEL
#define UART_RTS_GPIO12_DIRECT_CHANNEL UART_GPIO12_DIRECT_CHANNEL
#define UART_CTS_GPIO13_DIRECT_CHANNEL UART_GPIO13_DIRECT_CHANNEL

65
components/soc/esp32p4/include/soc/uart_pins.h
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@ -10,3 +10,68 @@
/* Specify the number of pins for UART */
#define SOC_UART_PINS_COUNT (4)
/* Specify the GPIO pin number for each UART signal in the IOMUX */
#define U0RXD_GPIO_NUM 38
#define U0TXD_GPIO_NUM 37
#define U0RTS_GPIO_NUM 8
#define U0CTS_GPIO_NUM 9
#define U1RXD_GPIO_NUM 11
#define U1TXD_GPIO_NUM 10
#define U1RTS_GPIO_NUM 12
#define U1CTS_GPIO_NUM 13
#define U2RXD_GPIO_NUM (-1)
#define U2TXD_GPIO_NUM (-1)
#define U2RTS_GPIO_NUM (-1)
#define U2CTS_GPIO_NUM (-1)
#define U3RXD_GPIO_NUM (-1)
#define U3TXD_GPIO_NUM (-1)
#define U3RTS_GPIO_NUM (-1)
#define U3CTS_GPIO_NUM (-1)
#define U4RXD_GPIO_NUM (-1)
#define U4TXD_GPIO_NUM (-1)
#define U4RTS_GPIO_NUM (-1)
#define U4CTS_GPIO_NUM (-1)
#define LP_U0RXD_GPIO_NUM 15
#define LP_U0TXD_GPIO_NUM 14
#define LP_U0RTS_GPIO_NUM (-1)
#define LP_U0CTS_GPIO_NUM (-1)
/* The following defines are necessary for reconfiguring the UART
* to use IOMUX, at runtime. */
#define U0TXD_MUX_FUNC (FUNC_GPIO37_UART0_TXD_PAD)
#define U0RXD_MUX_FUNC (FUNC_GPIO38_UART0_RXD_PAD)
#define U0RTS_MUX_FUNC (FUNC_GPIO8_UART0_RTS_PAD)
#define U0CTS_MUX_FUNC (FUNC_GPIO9_UART0_CTS_PAD)
/* Same goes for UART1 */
#define U1TXD_MUX_FUNC (FUNC_GPIO10_UART1_TXD_PAD)
#define U1RXD_MUX_FUNC (FUNC_GPIO11_UART1_RXD_PAD)
#define U1RTS_MUX_FUNC (FUNC_GPIO12_UART1_RTS_PAD)
#define U1CTS_MUX_FUNC (FUNC_GPIO13_UART1_CTS_PAD)
/* No func for the following pins, they shall not be used */
#define U2TXD_MUX_FUNC (-1)
#define U2RXD_MUX_FUNC (-1)
#define U2RTS_MUX_FUNC (-1)
#define U2CTS_MUX_FUNC (-1)
#define U3TXD_MUX_FUNC (-1)
#define U3RXD_MUX_FUNC (-1)
#define U3RTS_MUX_FUNC (-1)
#define U3CTS_MUX_FUNC (-1)
#define U4TXD_MUX_FUNC (-1)
#define U4RXD_MUX_FUNC (-1)
#define U4RTS_MUX_FUNC (-1)
#define U4CTS_MUX_FUNC (-1)
#define LP_U0TXD_MUX_FUNC (0)
#define LP_U0RXD_MUX_FUNC (0)
#define LP_U0RTS_MUX_FUNC (-1)
#define LP_U0CTS_MUX_FUNC (-1)

21
components/soc/esp32p4/include/soc/uart_struct.h
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@ -19,8 +19,7 @@ typedef union {
/** rxfifo_rd_byte : RO; bitpos: [7:0]; default: 0;
* UART $n accesses FIFO via this register.
*/
uint32_t rxfifo_rd_byte:8;
uint32_t reserved_8:24;
uint32_t rxfifo_rd_byte:32;
};
uint32_t val;
} uart_fifo_reg_t;
@ -1216,7 +1215,7 @@ typedef union {
} uart_id_reg_t;
typedef struct {
typedef struct uart_dev_t{
volatile uart_fifo_reg_t fifo;
volatile uart_int_raw_reg_t int_raw;
volatile uart_int_st_reg_t int_st;
@ -1246,12 +1245,12 @@ typedef struct {
volatile uart_mem_tx_status_reg_t mem_tx_status;
volatile uart_mem_rx_status_reg_t mem_rx_status;
volatile uart_fsm_status_reg_t fsm_status;
volatile uart_pospulse_reg_t pospulse;
volatile uart_negpulse_reg_t negpulse;
volatile uart_lowpulse_reg_t lowpulse;
volatile uart_highpulse_reg_t highpulse;
volatile uart_rxd_cnt_reg_t rxd_cnt;
volatile uart_clk_conf_reg_t clk_conf;
volatile uart_pospulse_reg_t pospulse; /* LP_UART instance has this register reserved */
volatile uart_negpulse_reg_t negpulse; /* LP_UART instance has this register reserved */
volatile uart_lowpulse_reg_t lowpulse; /* LP_UART instance has this register reserved */
volatile uart_highpulse_reg_t highpulse; /* LP_UART instance has this register reserved */
volatile uart_rxd_cnt_reg_t rxd_cnt; /* LP_UART instance has this register reserved */
volatile uart_clk_conf_reg_t clk_conf; /* UART0/1/2/3/4 instance have this register reserved, configure in corresponding PCR registers */
volatile uart_date_reg_t date;
volatile uart_afifo_status_reg_t afifo_status;
uint32_t reserved_094;
@ -1261,6 +1260,10 @@ typedef struct {
extern uart_dev_t UART0;
extern uart_dev_t UART1;
extern uart_dev_t UART2;
extern uart_dev_t UART3;
extern uart_dev_t UART4;
extern uart_dev_t LP_UART;
#ifndef __cplusplus
_Static_assert(sizeof(uart_dev_t) == 0xa0, "Invalid size of uart_dev_t structure");

1
components/soc/esp32p4/ld/esp32p4.peripherals.ld
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@ -68,6 +68,7 @@ PROVIDE ( PMU = 0x50115000 );
PROVIDE ( LP_SYS = 0x50110000 );
PROVIDE ( LP_AON_CLKRST = 0x50111000 );
PROVIDE ( EFUSE = 0x5012D000 );
PROVIDE ( LPPERI = 0x50120000 );
PROVIDE ( LP_TIMER = 0x50112000 );
PROVIDE ( LP_UART = 0x50121000 );
PROVIDE ( LP_I2C = 0x50122000 );

203
components/soc/esp32p4/uart_periph.c
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@ -5,10 +5,213 @@
*/
#include "soc/uart_periph.h"
#include "soc/lp_gpio_sig_map.h"
/*
Bunch of constants for every UART peripheral: GPIO signals, irqs, hw addr of registers etc
*/
const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
{ // HP UART0
.pins = {
[SOC_UART_TX_PIN_IDX] = {
.default_gpio = U0TXD_GPIO_NUM,
.iomux_func = U0TXD_MUX_FUNC,
.input = 0,
.signal = UART0_TXD_PAD_OUT_IDX,
},
[SOC_UART_RX_PIN_IDX] = {
.default_gpio = U0RXD_GPIO_NUM,
.iomux_func = U0RXD_MUX_FUNC,
.input = 1,
.signal = UART0_RXD_PAD_IN_IDX,
},
[SOC_UART_RTS_PIN_IDX] = {
.default_gpio = U0RTS_GPIO_NUM,
.iomux_func = U0RTS_MUX_FUNC,
.input = 0,
.signal = UART0_RTS_PAD_OUT_IDX,
},
[SOC_UART_CTS_PIN_IDX] = {
.default_gpio = U0CTS_GPIO_NUM,
.iomux_func = U0CTS_MUX_FUNC,
.input = 1,
.signal = UART0_CTS_PAD_IN_IDX,
}
},
.irq = ETS_UART0_INTR_SOURCE,
.module = PERIPH_UART0_MODULE,
},
{ // HP UART1
.pins = {
[SOC_UART_TX_PIN_IDX] = {
.default_gpio = U1TXD_GPIO_NUM,
.iomux_func = U1TXD_MUX_FUNC,
.input = 0,
.signal = UART1_TXD_PAD_OUT_IDX,
},
[SOC_UART_RX_PIN_IDX] = {
.default_gpio = U1RXD_GPIO_NUM,
.iomux_func = U1RXD_MUX_FUNC,
.input = 1,
.signal = UART1_RXD_PAD_IN_IDX,
},
[SOC_UART_RTS_PIN_IDX] = {
.default_gpio = U1RTS_GPIO_NUM,
.iomux_func = U1RTS_MUX_FUNC,
.input = 0,
.signal = UART1_RTS_PAD_OUT_IDX,
},
[SOC_UART_CTS_PIN_IDX] = {
.default_gpio = U1CTS_GPIO_NUM,
.iomux_func = U1CTS_MUX_FUNC,
.input = 1,
.signal = UART1_CTS_PAD_IN_IDX,
},
},
.irq = ETS_UART1_INTR_SOURCE,
.module = PERIPH_UART1_MODULE,
},
{ // HP UART2
.pins = {
[SOC_UART_TX_PIN_IDX] = {
.default_gpio = U2TXD_GPIO_NUM,
.iomux_func = U2TXD_MUX_FUNC,
.input = 0,
.signal = UART2_TXD_PAD_OUT_IDX,
},
[SOC_UART_RX_PIN_IDX] = {
.default_gpio = U2RXD_GPIO_NUM,
.iomux_func = U2RXD_MUX_FUNC,
.input = 1,
.signal = UART2_RXD_PAD_IN_IDX,
},
[SOC_UART_RTS_PIN_IDX] = {
.default_gpio = U2RTS_GPIO_NUM,
.iomux_func = U2RTS_MUX_FUNC,
.input = 0,
.signal = UART2_RTS_PAD_OUT_IDX,
},
[SOC_UART_CTS_PIN_IDX] = {
.default_gpio = U2CTS_GPIO_NUM,
.iomux_func = U2CTS_MUX_FUNC,
.input = 1,
.signal = UART2_CTS_PAD_IN_IDX,
},
},
.irq = ETS_UART2_INTR_SOURCE,
.module = PERIPH_UART2_MODULE,
},
{ // HP UART3
.pins = {
[SOC_UART_TX_PIN_IDX] = {
.default_gpio = U3TXD_GPIO_NUM,
.iomux_func = U3TXD_MUX_FUNC,
.input = 0,
.signal = UART3_TXD_PAD_OUT_IDX,
},
[SOC_UART_RX_PIN_IDX] = {
.default_gpio = U3RXD_GPIO_NUM,
.iomux_func = U3RXD_MUX_FUNC,
.input = 1,
.signal = UART3_RXD_PAD_IN_IDX,
},
[SOC_UART_RTS_PIN_IDX] = {
.default_gpio = U3RTS_GPIO_NUM,
.iomux_func = U3RTS_MUX_FUNC,
.input = 0,
.signal = UART3_RTS_PAD_OUT_IDX,
},
[SOC_UART_CTS_PIN_IDX] = {
.default_gpio = U3CTS_GPIO_NUM,
.iomux_func = U3CTS_MUX_FUNC,
.input = 1,
.signal = UART3_CTS_PAD_IN_IDX,
},
},
.irq = ETS_UART3_INTR_SOURCE,
.module = PERIPH_UART3_MODULE,
},
{ // HP UART4
.pins = {
[SOC_UART_TX_PIN_IDX] = {
.default_gpio = U4TXD_GPIO_NUM,
.iomux_func = U4TXD_MUX_FUNC,
.input = 0,
.signal = UART4_TXD_PAD_OUT_IDX,
},
[SOC_UART_RX_PIN_IDX] = {
.default_gpio = U4RXD_GPIO_NUM,
.iomux_func = U4RXD_MUX_FUNC,
.input = 1,
.signal = UART4_RXD_PAD_IN_IDX,
},
[SOC_UART_RTS_PIN_IDX] = {
.default_gpio = U4RTS_GPIO_NUM,
.iomux_func = U4RTS_MUX_FUNC,
.input = 0,
.signal = UART4_RTS_PAD_OUT_IDX,
},
[SOC_UART_CTS_PIN_IDX] = {
.default_gpio = U4CTS_GPIO_NUM,
.iomux_func = U4CTS_MUX_FUNC,
.input = 1,
.signal = UART4_CTS_PAD_IN_IDX,
},
},
.irq = ETS_UART4_INTR_SOURCE,
.module = PERIPH_UART4_MODULE,
},
//TODO:IDF-7815
// { // LP UART0
// .pins = {
// [SOC_UART_TX_PIN_IDX] = {
// .default_gpio = LP_U0TXD_GPIO_NUM,
// .iomux_func = LP_U0TXD_MUX_FUNC,
// .input = 0,
// .signal = LP_UART_TXD_PAD_OUT_IDX,
// },
// [SOC_UART_RX_PIN_IDX] = {
// .default_gpio = LP_U0RXD_GPIO_NUM,
// .iomux_func = LP_U0RXD_MUX_FUNC,
// .input = 1,
// .signal = LP_UART_RXD_PAD_IN_IDX,
// },
// [SOC_UART_RTS_PIN_IDX] = {
// .default_gpio = LP_U0RTS_GPIO_NUM,
// .iomux_func = LP_U0RTS_MUX_FUNC,
// .input = 0,
// .signal = LP_UART_RTSN_PAD_OUT_IDX,
// },
// [SOC_UART_CTS_PIN_IDX] = {
// .default_gpio = LP_U0CTS_GPIO_NUM,
// .iomux_func = LP_U0CTS_MUX_FUNC,
// .input = 1,
// .signal = LP_UART_CTSN_PAD_IN_IDX,
// },
// },
// .irq = ETS_LP_UART_INTR_SOURCE,
// .module = PERIPH_LP_UART0_MODULE,
// },
};