build-system: include soc_caps defines into kconfig

Adds gen_soc_caps_kconfig.py which parses the soc caps (soc_caps.h) into
a format that can be included in kconfig.
pull/8057/head
Marius Vikhammer 2021-11-05 17:23:24 +08:00
rodzic ae9f42383c
commit c6d60615c6
42 zmienionych plików z 4305 dodań i 240 usunięć

Wyświetl plik

@ -416,3 +416,9 @@ test_linux_example:
- idf.py build
- timeout 5 ./build/linux_host_app.elf >test.log || true
- grep "Restarting" test.log
test_gen_soc_caps_kconfig:
extends: .host_test_template
script:
- cd ${IDF_PATH}/tools/gen_soc_caps_kconfig/
- ./test/test_gen_soc_caps_kconfig.py

Wyświetl plik

@ -134,6 +134,8 @@
- "tools/ci/test_reproducible_build.sh"
- "tools/gen_soc_caps_kconfig/*"
.patterns-windows: &patterns-windows
- "tools/windows/**/*"

Wyświetl plik

@ -119,6 +119,14 @@ repos:
additional_dependencies:
- PyYAML == 5.3.1
pass_filenames: false
- id: check-generated-soc-caps-kconfig
name: Check soc caps kconfig files are generated (based on components/soc/IDF_TARGET/include/soc/soc_caps.h)
entry: tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py -d 'components/soc/*/include/soc/' 'components/esp_rom/*/'
language: python
files: 'components/soc/.+/include/soc/.+_caps\.h|components/esp_rom/.+/.+_caps\.h|kconfig\.soc_caps.in'
pass_filenames: false
additional_dependencies:
- pyparsing
- repo: https://github.com/pre-commit/pre-commit-hooks
rev: v4.0.1
hooks:

Wyświetl plik

@ -4,6 +4,8 @@
#
mainmenu "Espressif IoT Development Framework Configuration"
orsource "./components/soc/$IDF_TARGET/include/soc/Kconfig.soc_caps.in"
config IDF_CMAKE
bool
default "y"
@ -130,6 +132,7 @@ mainmenu "Espressif IoT Development Framework Configuration"
endmenu # SDK tool configuration
menu "Build type"
choice APP_BUILD_TYPE

Wyświetl plik

@ -20,11 +20,15 @@ set(srcs
set(includes "include" "${target}/include" "deprecated")
if(CONFIG_SOC_MCPWM_SUPPORTED)
list(APPEND srcs
"mcpwm.c")
endif()
if(${target} STREQUAL "esp32")
# SDMMC and MCPWM are in ESP32 only.
list(APPEND srcs "adc_common.c"
"dac_common.c"
"mcpwm.c"
"sdio_slave.c"
"sdmmc_host.c"
"i2s.c"
@ -61,7 +65,6 @@ if(${target} STREQUAL "esp32s3")
"gdma.c"
"sdmmc_host.c"
"sdmmc_transaction.c"
"mcpwm.c"
"rmt.c"
"sigmadelta.c"
"usb_serial_jtag.c"

Wyświetl plik

@ -500,7 +500,7 @@ esp_err_t gpio_sleep_set_pull_mode(gpio_num_t gpio_num, gpio_pull_mode_t pull);
#if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
#define GPIO_IS_DEEP_SLEEP_WAKEUP_VALID_GPIO(gpio_num) ((gpio_num & ~SOC_GPIO_DEEP_SLEEP_WAKEUP_VALID_GPIO_MASK) == 0)
#define GPIO_IS_DEEP_SLEEP_WAKEUP_VALID_GPIO(gpio_num) ((gpio_num & ~SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK) == 0)
/**
* @brief Enable GPIO deep-sleep wake-up function.

Wyświetl plik

@ -192,7 +192,7 @@ static void touch_wakeup_prepare(void);
static void esp_deep_sleep_wakeup_prepare(void);
#endif
#if SOC_PM_SUPPORT_DEEPSLEEP_VERIFY_STUB_ONLY
#if SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY
static RTC_FAST_ATTR esp_deep_sleep_wake_stub_fn_t wake_stub_fn_handler = NULL;
static void RTC_IRAM_ATTR __attribute__((used, noinline)) esp_wake_stub_start(void)
@ -215,14 +215,14 @@ static void __attribute__((section(".rtc.entry.text"))) esp_wake_stub_entry(void
// which is sufficient for instruction addressing in RTC fast memory.
__asm__ __volatile__ ("call4 " SYM2STR(esp_wake_stub_start) "\n");
}
#endif // SOC_PM_SUPPORT_DEEPSLEEP_VERIFY_STUB_ONLY
#endif // SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY
/* Wake from deep sleep stub
See esp_deepsleep.h esp_wake_deep_sleep() comments for details.
*/
esp_deep_sleep_wake_stub_fn_t esp_get_deep_sleep_wake_stub(void)
{
#if SOC_PM_SUPPORT_DEEPSLEEP_VERIFY_STUB_ONLY
#if SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY
esp_deep_sleep_wake_stub_fn_t stub_ptr = wake_stub_fn_handler;
#else
esp_deep_sleep_wake_stub_fn_t stub_ptr = (esp_deep_sleep_wake_stub_fn_t) REG_READ(RTC_ENTRY_ADDR_REG);
@ -235,7 +235,7 @@ esp_deep_sleep_wake_stub_fn_t esp_get_deep_sleep_wake_stub(void)
void esp_set_deep_sleep_wake_stub(esp_deep_sleep_wake_stub_fn_t new_stub)
{
#if SOC_PM_SUPPORT_DEEPSLEEP_VERIFY_STUB_ONLY
#if SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY
wake_stub_fn_handler = new_stub;
#else
REG_WRITE(RTC_ENTRY_ADDR_REG, (uint32_t)new_stub);
@ -446,7 +446,7 @@ static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags)
*/
portENTER_CRITICAL(&spinlock_rtc_deep_sleep);
#if SOC_PM_SUPPORT_DEEPSLEEP_VERIFY_STUB_ONLY
#if SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY
extern char _rtc_text_start[];
#if CONFIG_ESP32S3_RTCDATA_IN_FAST_MEM
extern char _rtc_noinit_end[];
@ -469,7 +469,7 @@ static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags)
/* Otherwise, need to call the dedicated soc function for this */
result = rtc_deep_sleep_start(s_config.wakeup_triggers, reject_triggers);
#endif
#endif // SOC_PM_SUPPORT_DEEPSLEEP_VERIFY_STUB_ONLY
#endif // SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY
portEXIT_CRITICAL(&spinlock_rtc_deep_sleep);
} else {

Wyświetl plik

@ -1,3 +1,5 @@
orsource "./$IDF_TARGET//Kconfig.soc_caps.in"
menu "Boot ROM Behavior"
visible if !IDF_TARGET_ESP32 # no options ere currently supported on ESP32

Wyświetl plik

@ -0,0 +1,20 @@
#####################################################
# This file is auto-generated from SoC caps
# using gen_soc_caps_kconfig.py, do not edit manually
#####################################################
config ESP_ROM_HAS_CRC_LE
bool
default y
config ESP_ROM_HAS_CRC_BE
bool
default y
config ESP_ROM_HAS_JPEG_DECODE
bool
default y
config ESP_ROM_SUPPORT_MULTIPLE_UART
bool
default y

Wyświetl plik

@ -0,0 +1,36 @@
#####################################################
# This file is auto-generated from SoC caps
# using gen_soc_caps_kconfig.py, do not edit manually
#####################################################
config ESP_ROM_HAS_CRC_LE
bool
default y
config ESP_ROM_HAS_CRC_BE
bool
default y
config ESP_ROM_HAS_JPEG_DECODE
bool
default y
config ESP_ROM_UART_CLK_IS_XTAL
bool
default y
config ESP_ROM_USB_SERIAL_DEVICE_NUM
int
default 3
config ESP_ROM_HAS_RETARGETABLE_LOCKING
bool
default y
config ESP_ROM_HAS_ERASE_0_REGION_BUG
bool
default y
config ESP_ROM_GET_CLK_FREQ
bool
default y

Wyświetl plik

@ -0,0 +1,36 @@
#####################################################
# This file is auto-generated from SoC caps
# using gen_soc_caps_kconfig.py, do not edit manually
#####################################################
config ESP_ROM_HAS_CRC_LE
bool
default y
config ESP_ROM_HAS_CRC_BE
bool
default y
config ESP_ROM_HAS_JPEG_DECODE
bool
default y
config ESP_ROM_UART_CLK_IS_XTAL
bool
default y
config ESP_ROM_USB_SERIAL_DEVICE_NUM
int
default 3
config ESP_ROM_HAS_RETARGETABLE_LOCKING
bool
default y
config ESP_ROM_HAS_ERASE_0_REGION_BUG
bool
default y
config ESP_ROM_GET_CLK_FREQ
bool
default y

Wyświetl plik

@ -0,0 +1,12 @@
#####################################################
# This file is auto-generated from SoC caps
# using gen_soc_caps_kconfig.py, do not edit manually
#####################################################
config ESP_ROM_HAS_CRC_LE
bool
default y
config ESP_ROM_SUPPORT_MULTIPLE_UART
bool
default y

Wyświetl plik

@ -0,0 +1,40 @@
#####################################################
# This file is auto-generated from SoC caps
# using gen_soc_caps_kconfig.py, do not edit manually
#####################################################
config ESP_ROM_HAS_CRC_LE
bool
default y
config ESP_ROM_HAS_CRC_BE
bool
default y
config ESP_ROM_HAS_JPEG_DECODE
bool
default y
config ESP_ROM_SUPPORT_MULTIPLE_UART
bool
default y
config ESP_ROM_UART_CLK_IS_XTAL
bool
default y
config ESP_ROM_HAS_RETARGETABLE_LOCKING
bool
default y
config ESP_ROM_USB_SERIAL_DEVICE_NUM
int
default 4
config ESP_ROM_HAS_ERASE_0_REGION_BUG
bool
default y
config ESP_ROM_GET_CLK_FREQ
bool
default y

Wyświetl plik

@ -0,0 +1,24 @@
#####################################################
# This file is auto-generated from SoC caps
# using gen_soc_caps_kconfig.py, do not edit manually
#####################################################
config ESP_ROM_HAS_CRC_LE
bool
default y
config ESP_ROM_HAS_CRC_BE
bool
default y
config ESP_ROM_UART_CLK_IS_XTAL
bool
default y
config ESP_ROM_HAS_RETARGETABLE_LOCKING
bool
default y
config ESP_ROM_GET_CLK_FREQ
bool
default y

Wyświetl plik

@ -22,6 +22,8 @@
extern "C" {
#endif
#define RTCIO_LL_PIN_FUNC 0
typedef enum {
RTCIO_FUNC_RTC = 0x0, /*!< The pin controled by RTC module. */
RTCIO_FUNC_DIGITAL = 0x1, /*!< The pin controlled by DIGITAL module. */

Wyświetl plik

@ -101,7 +101,7 @@ esp_err_t spi_flash_hal_configure_host_io_mode(
return ESP_ERR_NOT_SUPPORTED;
}
#if SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT
#if SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT
// The CONTROL_DUMMY_OUTPUT feature is used to control M7-M0 bits.
spi_flash_ll_set_dummy_out(dev, (conf_required? 1: 0), 1);
#else

Wyświetl plik

@ -0,0 +1,516 @@
#####################################################
# This file is auto-generated from SoC caps
# using gen_soc_caps_kconfig.py, do not edit manually
#####################################################
config SOC_BROWNOUT_RESET_SUPPORTED
string
default "Not determined"
config SOC_TWAI_BRP_DIV_SUPPORTED
string
default "Not determined"
config SOC_CAPS_ECO_VER_MAX
int
default 3
config SOC_DAC_SUPPORTED
bool
default y
config SOC_MCPWM_SUPPORTED
bool
default y
config SOC_SDMMC_HOST_SUPPORTED
bool
default y
config SOC_BT_SUPPORTED
bool
default y
config SOC_CLASSIC_BT_SUPPORTED
bool
default y
config SOC_PCNT_SUPPORTED
bool
default y
config SOC_SDIO_SLAVE_SUPPORTED
bool
default y
config SOC_TWAI_SUPPORTED
bool
default y
config SOC_EMAC_SUPPORTED
bool
default y
config SOC_CPU_CORES_NUM
int
default 2
config SOC_ULP_SUPPORTED
bool
default y
config SOC_CCOMP_TIMER_SUPPORTED
bool
default y
config SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS
bool
default y
config SOC_RTC_FAST_MEM_SUPPORTED
bool
default y
config SOC_RTC_SLOW_MEM_SUPPORTED
bool
default y
config SOC_ADC_RTC_CTRL_SUPPORTED
bool
default y
config SOC_ADC_PERIPH_NUM
int
default 2
config SOC_ADC_MAX_CHANNEL_NUM
int
default 10
config SOC_ADC_DIGI_CONTROLLER_NUM
int
default 2
config SOC_ADC_PATT_LEN_MAX
int
default 16
config SOC_ADC_DIGI_MIN_BITWIDTH
int
default 9
config SOC_ADC_DIGI_MAX_BITWIDTH
int
default 12
config SOC_ADC_SAMPLE_FREQ_THRES_HIGH
int
default 83333
config SOC_ADC_SAMPLE_FREQ_THRES_LOW
int
default 611
config SOC_ADC_MAX_BITWIDTH
int
default 12
config SOC_CPU_BREAKPOINTS_NUM
int
default 2
config SOC_CPU_WATCHPOINTS_NUM
int
default 2
config SOC_CPU_WATCHPOINT_SIZE
int
default 64
config SOC_CPU_HAS_FPU
bool
default y
config SOC_DAC_PERIPH_NUM
int
default 2
config SOC_DAC_RESOLUTION
int
default 8
config SOC_GPIO_PORT
int
default 1
config SOC_GPIO_PIN_COUNT
int
default 40
config SOC_GPIO_VALID_GPIO_MASK
hex
default 0xFFFFFFFFFF
config SOC_GPIO_SUPPORT_SLP_SWITCH
bool
default y
config SOC_I2C_NUM
int
default 2
config SOC_I2C_FIFO_LEN
int
default 32
config SOC_I2C_SUPPORT_APB
bool
default y
config SOC_I2S_NUM
int
default 2
config SOC_I2S_SUPPORTS_PDM_TX
bool
default y
config SOC_I2S_SUPPORTS_PDM_RX
bool
default y
config SOC_I2S_SUPPORTS_ADC
bool
default y
config SOC_I2S_SUPPORTS_DAC
bool
default y
config SOC_I2S_SUPPORTS_APLL
bool
default y
config SOC_I2S_APLL_MIN_FREQ
int
default 250000000
config SOC_I2S_APLL_MAX_FREQ
int
default 500000000
config SOC_I2S_APLL_MIN_RATE
int
default 10675
config SOC_I2S_TRANS_SIZE_ALIGN_WORD
bool
default y
config SOC_I2S_LCD_I80_VARIANT
bool
default y
config SOC_LCD_I80_SUPPORTED
bool
default y
config SOC_LCD_I80_BUSES
bool
default y
config SOC_LCD_I80_BUS_WIDTH
int
default 24
config SOC_LEDC_HAS_TIMER_SPECIFIC_MUX
bool
default y
config SOC_LEDC_SUPPORT_REF_TICK
bool
default y
config SOC_LEDC_SUPPORT_HS_MODE
bool
default y
config SOC_LEDC_CHANNEL_NUM
int
default 8
config SOC_LEDC_TIMER_BIT_WIDE_NUM
int
default 20
config SOC_MCPWM_GROUPS
int
default 2
config SOC_MCPWM_TIMERS_PER_GROUP
int
default 3
config SOC_MCPWM_OPERATORS_PER_GROUP
int
default 3
config SOC_MCPWM_COMPARATORS_PER_OPERATOR
int
default 2
config SOC_MCPWM_GENERATORS_PER_OPERATOR
int
default 2
config SOC_MCPWM_TRIGGERS_PER_OPERATOR
int
default 2
config SOC_MCPWM_GPIO_FAULTS_PER_GROUP
int
default 3
config SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP
bool
default y
config SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER
int
default 3
config SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP
int
default 3
config SOC_MCPWM_BASE_CLK_HZ
int
default 160000000
config SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED
bool
default n
config SOC_MPU_MIN_REGION_SIZE
hex
default 0x20000000
config SOC_MPU_REGIONS_MAX_NUM
int
default 8
config SOC_MPU_REGION_RO_SUPPORTED
bool
default n
config SOC_MPU_REGION_WO_SUPPORTED
bool
default n
config SOC_PCNT_GROUPS
int
default 1
config SOC_PCNT_UNITS_PER_GROUP
int
default 8
config SOC_PCNT_CHANNELS_PER_UNIT
int
default 2
config SOC_PCNT_THRES_POINT_PER_UNIT
int
default 2
config SOC_RMT_GROUPS
int
default 1
config SOC_RMT_TX_CANDIDATES_PER_GROUP
int
default 8
config SOC_RMT_RX_CANDIDATES_PER_GROUP
int
default 8
config SOC_RMT_CHANNELS_PER_GROUP
int
default 8
config SOC_RMT_MEM_WORDS_PER_CHANNEL
int
default 64
config SOC_RMT_SUPPORT_REF_TICK
bool
default y
config SOC_RMT_CHANNEL_CLK_INDEPENDENT
bool
default y
config SOC_RTCIO_PIN_COUNT
int
default 18
config SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
bool
default y
config SOC_RTCIO_HOLD_SUPPORTED
bool
default y
config SOC_RTCIO_WAKE_SUPPORTED
bool
default y
config SOC_SIGMADELTA_NUM
int
default 1
config SOC_SIGMADELTA_CHANNEL_NUM
int
default 8
config SOC_SPI_PERIPH_NUM
int
default 3
config SOC_SPI_DMA_CHAN_NUM
int
default 2
config SOC_SPI_MAXIMUM_BUFFER_SIZE
int
default 64
config SOC_SPI_MAX_PRE_DIVIDER
int
default 8192
config SOC_SPI_SUPPORT_AS_CS
bool
default y
config SOC_TIMER_GROUPS
int
default 2
config SOC_TIMER_GROUP_TIMERS_PER_GROUP
int
default 2
config SOC_TIMER_GROUP_COUNTER_BIT_WIDTH
int
default 64
config SOC_TOUCH_VERSION_1
bool
default y
config SOC_TOUCH_SENSOR_NUM
int
default 10
config SOC_TOUCH_PAD_MEASURE_WAIT_MAX
hex
default 0xFF
config SOC_TOUCH_PAD_THRESHOLD_MAX
bool
default n
config SOC_TWAI_BRP_MIN
int
default 2
config SOC_TWAI_SUPPORT_MULTI_ADDRESS_LAYOUT
bool
default y
config SOC_UART_NUM
int
default 3
config SOC_UART_SUPPORT_REF_TICK
bool
default y
config SOC_UART_FIFO_LEN
int
default 128
config SOC_UART_BITRATE_MAX
int
default 5000000
config SOC_SPIRAM_SUPPORTED
bool
default y
config SOC_SHA_SUPPORT_PARALLEL_ENG
bool
default y
config SOC_SHA_SUPPORT_SHA1
bool
default y
config SOC_SHA_SUPPORT_SHA256
bool
default y
config SOC_SHA_SUPPORT_SHA384
bool
default y
config SOC_SHA_SUPPORT_SHA512
bool
default y
config SOC_RSA_MAX_BIT_LEN
int
default 4096
config SOC_AES_SUPPORT_AES_128
bool
default y
config SOC_AES_SUPPORT_AES_192
bool
default y
config SOC_AES_SUPPORT_AES_256
bool
default y
config SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX
int
default 32
config SOC_PHY_DIG_REGS_MEM_SIZE
int
default 21
config SOC_PM_SUPPORT_EXT_WAKEUP
bool
default y
config SOC_PM_SUPPORT_TOUCH_SENSOR_WAKEUP
bool
default y
config SOC_SDMMC_USE_IOMUX
bool
default y
config SOC_SDMMC_NUM_SLOTS
int
default 2
config SOC_BLE_DONT_UPDATE_OWN_RPA
bool
default y

Wyświetl plik

@ -1,3 +1,4 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
@ -24,6 +25,16 @@
* ECO & exceptions:
* For ECO-ed booleans, `#define x "Not determined"` for them. This will cause error when used by
* `#if x` and `#if !x`, making these missing definitions more obvious.
*
* These defines are parsed and imported as kconfig variables via the script
* `tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py`
*
* If this file is changed the script will automatically run the script
* and generate the kconfig variables as part of the pre-commit hooks.
*
* It can also be ran manually with `./tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py 'components/soc/esp32/include/soc/'`
*
* For more information see `tools/gen_soc_caps_kconfig/README.md`
*/
#pragma once
@ -117,7 +128,7 @@
/*-------------------------- GPIO CAPS ---------------------------------------*/
// ESP32 has 1 GPIO peripheral
#define SOC_GPIO_PORT (1)
#define SOC_GPIO_PORT (1U)
#define SOC_GPIO_PIN_COUNT 40
// SOC_GPIO_SUPPORT_RTC_INDEPENDENT not defined. On ESP32 those PADs which have RTC functions must
@ -190,13 +201,13 @@
#define SOC_MPU_REGION_WO_SUPPORTED 0
/*-------------------------- PCNT CAPS ---------------------------------------*/
#define SOC_PCNT_GROUPS (1)
#define SOC_PCNT_GROUPS (1U)
#define SOC_PCNT_UNITS_PER_GROUP (8)
#define SOC_PCNT_CHANNELS_PER_UNIT (2)
#define SOC_PCNT_THRES_POINT_PER_UNIT (2)
/*-------------------------- RMT CAPS ----------------------------------------*/
#define SOC_RMT_GROUPS (1) /*!< One RMT group */
#define SOC_RMT_GROUPS (1U) /*!< One RMT group */
#define SOC_RMT_TX_CANDIDATES_PER_GROUP (8) /*!< Number of channels that capable of Transmit in each group */
#define SOC_RMT_RX_CANDIDATES_PER_GROUP (8) /*!< Number of channels that capable of Receive in each group */
#define SOC_RMT_CHANNELS_PER_GROUP (8) /*!< Total 8 channels */
@ -211,7 +222,7 @@
#define SOC_RTCIO_WAKE_SUPPORTED 1
/*-------------------------- SIGMA DELTA CAPS --------------------------------*/
#define SOC_SIGMADELTA_NUM 1
#define SOC_SIGMADELTA_NUM 1U
#define SOC_SIGMADELTA_CHANNEL_NUM (8) // 8 channels
/*-------------------------- SPI CAPS ----------------------------------------*/

Wyświetl plik

@ -0,0 +1,604 @@
#####################################################
# This file is auto-generated from SoC caps
# using gen_soc_caps_kconfig.py, do not edit manually
#####################################################
config SOC_CPU_CORES_NUM
bool
default y
config SOC_DEDICATED_GPIO_SUPPORTED
bool
default y
config SOC_GDMA_SUPPORTED
bool
default y
config SOC_TWAI_SUPPORTED
bool
default y
config SOC_BT_SUPPORTED
bool
default y
config SOC_DIG_SIGN_SUPPORTED
bool
default y
config SOC_HMAC_SUPPORTED
bool
default y
config SOC_ASYNC_MEMCPY_SUPPORTED
bool
default y
config SOC_USB_SERIAL_JTAG_SUPPORTED
bool
default y
config SOC_TEMP_SENSOR_SUPPORTED
bool
default y
config SOC_FLASH_ENCRYPTION_XTS_AES
bool
default y
config SOC_XT_WDT_SUPPORTED
bool
default y
config SOC_SUPPORTS_SECURE_DL_MODE
bool
default y
config SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS
int
default 3
config SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS
bool
default y
config SOC_ICACHE_ACCESS_RODATA_SUPPORTED
bool
default y
config SOC_RTC_FAST_MEM_SUPPORTED
bool
default y
config SOC_RTC_SLOW_MEM_SUPPORTED
bool
default n
config SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY
bool
default y
config SOC_AES_SUPPORT_DMA
bool
default y
config SOC_AES_GDMA
bool
default y
config SOC_AES_SUPPORT_AES_128
bool
default y
config SOC_AES_SUPPORT_AES_256
bool
default y
config SOC_ADC_ARBITER_SUPPORTED
bool
default y
config SOC_ADC_FILTER_SUPPORTED
bool
default y
config SOC_ADC_MONITOR_SUPPORTED
bool
default y
config SOC_ADC_PERIPH_NUM
int
default 2
config SOC_ADC_MAX_CHANNEL_NUM
int
default 5
config SOC_ADC_DIGI_CONTROLLER_NUM
bool
default y
config SOC_ADC_PATT_LEN_MAX
int
default 8
config SOC_ADC_DIGI_MAX_BITWIDTH
int
default 12
config SOC_ADC_DIGI_FILTER_NUM
int
default 2
config SOC_ADC_DIGI_MONITOR_NUM
int
default 2
config SOC_ADC_SAMPLE_FREQ_THRES_HIGH
int
default 83333
config SOC_ADC_SAMPLE_FREQ_THRES_LOW
int
default 611
config SOC_ADC_MAX_BITWIDTH
int
default 12
config SOC_ADC_CALIBRATION_V1_SUPPORTED
bool
default y
config SOC_APB_BACKUP_DMA
bool
default y
config SOC_BROWNOUT_RESET_SUPPORTED
bool
default y
config SOC_CPU_BREAKPOINTS_NUM
int
default 8
config SOC_CPU_WATCHPOINTS_NUM
int
default 8
config SOC_CPU_HAS_FLEXIBLE_INTC
bool
default y
config SOC_CPU_WATCHPOINT_SIZE
hex
default 0x80000000
config SOC_DS_SIGNATURE_MAX_BIT_LEN
int
default 3072
config SOC_DS_KEY_PARAM_MD_IV_LENGTH
int
default 16
config SOC_DS_KEY_CHECK_MAX_WAIT_US
int
default 1100
config SOC_GDMA_GROUPS
int
default 1
config SOC_GDMA_PAIRS_PER_GROUP
int
default 3
config SOC_GDMA_TX_RX_SHARE_INTERRUPT
bool
default y
config SOC_GPIO_PORT
int
default 1
config SOC_GPIO_PIN_COUNT
int
default 22
config SOC_GPIO_SUPPORTS_RTC_INDEPENDENT
bool
default y
config SOC_GPIO_SUPPORT_FORCE_HOLD
bool
default y
config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
bool
default y
config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
int
default 0
config SOC_GPIO_SUPPORT_SLP_SWITCH
bool
default y
config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
int
default 8
config SOC_DEDIC_GPIO_IN_CHANNELS_NUM
int
default 8
config SOC_DEDIC_PERIPH_AUTO_ENABLE
bool
default y
config SOC_I2C_NUM
int
default 1
config SOC_I2C_FIFO_LEN
int
default 32
config SOC_I2C_SUPPORT_HW_FSM_RST
bool
default y
config SOC_I2C_SUPPORT_HW_CLR_BUS
bool
default y
config SOC_I2C_SUPPORT_XTAL
bool
default y
config SOC_I2C_SUPPORT_RTC
bool
default y
config SOC_I2S_NUM
int
default 1
config SOC_I2S_SUPPORTS_PCM
bool
default y
config SOC_I2S_SUPPORTS_PDM_TX
bool
default y
config SOC_I2S_SUPPORTS_PDM_CODEC
bool
default y
config SOC_I2S_SUPPORTS_TDM
bool
default y
config SOC_LEDC_SUPPORT_XTAL_CLOCK
bool
default y
config SOC_LEDC_CHANNEL_NUM
int
default 6
config SOC_LEDC_TIMER_BIT_WIDE_NUM
int
default 14
config SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED
bool
default n
config SOC_MPU_MIN_REGION_SIZE
hex
default 0x20000000
config SOC_MPU_REGIONS_MAX_NUM
int
default 8
config SOC_MPU_REGION_RO_SUPPORTED
bool
default n
config SOC_MPU_REGION_WO_SUPPORTED
bool
default n
config SOC_RMT_GROUPS
int
default 1
config SOC_RMT_TX_CANDIDATES_PER_GROUP
int
default 2
config SOC_RMT_RX_CANDIDATES_PER_GROUP
int
default 2
config SOC_RMT_CHANNELS_PER_GROUP
int
default 4
config SOC_RMT_MEM_WORDS_PER_CHANNEL
int
default 48
config SOC_RMT_SUPPORT_RX_PINGPONG
bool
default y
config SOC_RMT_SUPPORT_RX_DEMODULATION
bool
default y
config SOC_RMT_SUPPORT_TX_LOOP_COUNT
bool
default y
config SOC_RMT_SUPPORT_TX_SYNCHRO
bool
default y
config SOC_RMT_SUPPORT_XTAL
bool
default y
config SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH
int
default 128
config SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM
int
default 108
config SOC_RTCIO_PIN_COUNT
bool
default n
config SOC_RSA_MAX_BIT_LEN
int
default 3072
config SOC_SHA_DMA_MAX_BUFFER_SIZE
int
default 3968
config SOC_SHA_SUPPORT_DMA
bool
default y
config SOC_SHA_SUPPORT_RESUME
bool
default y
config SOC_SHA_GDMA
bool
default y
config SOC_SHA_SUPPORT_SHA1
bool
default y
config SOC_SHA_SUPPORT_SHA224
bool
default y
config SOC_SHA_SUPPORT_SHA256
bool
default y
config SOC_SIGMADELTA_NUM
int
default 1
config SOC_SIGMADELTA_CHANNEL_NUM
int
default 4
config SOC_SPI_PERIPH_NUM
int
default 2
config SOC_SPI_MAXIMUM_BUFFER_SIZE
int
default 64
config SOC_SPI_SUPPORT_DDRCLK
bool
default y
config SOC_SPI_SLAVE_SUPPORT_SEG_TRANS
bool
default y
config SOC_SPI_SUPPORT_CD_SIG
bool
default y
config SOC_SPI_SUPPORT_CONTINUOUS_TRANS
bool
default y
config SOC_SPI_SUPPORT_SLAVE_HD_VER2
bool
default y
config SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT
bool
default y
config SOC_MEMSPI_IS_INDEPENDENT
bool
default y
config SOC_SPI_MAX_PRE_DIVIDER
int
default 16
config SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE
bool
default y
config SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND
bool
default y
config SOC_SPI_MEM_SUPPORT_AUTO_RESUME
bool
default y
config SOC_SPI_MEM_SUPPORT_IDLE_INTR
bool
default y
config SOC_SPI_MEM_SUPPORT_SW_SUSPEND
bool
default y
config SOC_SPI_MEM_SUPPORT_CHECK_SUS
bool
default y
config SOC_SYSTIMER_COUNTER_NUM
int
default 2
config SOC_SYSTIMER_ALARM_NUM
int
default 3
config SOC_SYSTIMER_BIT_WIDTH_LO
int
default 32
config SOC_SYSTIMER_BIT_WIDTH_HI
int
default 20
config SOC_SYSTIMER_FIXED_TICKS_US
int
default 16
config SOC_SYSTIMER_INT_LEVEL
bool
default y
config SOC_SYSTIMER_ALARM_MISS_COMPENSATE
bool
default y
config SOC_TIMER_GROUPS
int
default 2
config SOC_TIMER_GROUP_TIMERS_PER_GROUP
bool
default y
config SOC_TIMER_GROUP_COUNTER_BIT_WIDTH
int
default 54
config SOC_TIMER_GROUP_SUPPORT_XTAL
bool
default y
config SOC_TOUCH_SENSOR_NUM
bool
default n
config SOC_TWAI_BRP_MIN
int
default 2
config SOC_TWAI_BRP_MAX
int
default 16384
config SOC_TWAI_SUPPORTS_RX_STATUS
bool
default y
config SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX
int
default 32
config SOC_UART_NUM
int
default 2
config SOC_UART_FIFO_LEN
int
default 128
config SOC_UART_BITRATE_MAX
int
default 5000000
config SOC_UART_SUPPORT_RTC_CLK
bool
default y
config SOC_UART_SUPPORT_XTAL_CLK
bool
default y
config SOC_UART_REQUIRE_CORE_RESET
bool
default y
config SOC_UART_SUPPORT_FSM_TX_WAIT_SEND
bool
default y
config SOC_WIFI_HW_TSF
bool
default y
config SOC_COEX_HW_PTI
bool
default y
config SOC_PHY_DIG_REGS_MEM_SIZE
int
default 21
config SOC_MAC_BB_PD_MEM_SIZE
int
default 192
config SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH
int
default 12
config SOC_PM_SUPPORT_WIFI_WAKEUP
bool
default y
config SOC_PM_SUPPORT_BT_WAKEUP
bool
default y
config SOC_PM_SUPPORT_CPU_PD
bool
default y
config SOC_PM_SUPPORT_WIFI_PD
bool
default y
config SOC_PM_SUPPORT_BT_PD
bool
default y

Wyświetl plik

@ -3,6 +3,19 @@
// seperate these information into periph_caps.h for each peripheral and
// include them here.
/*
* These defines are parsed and imported as kconfig variables via the script
* `tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py`
*
* If this file is changed the script will automatically run the script
* and generate the kconfig variables as part of the pre-commit hooks.
*
* It can also be ran manually with `./tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py 'components/soc/esp32c3/include/soc/'`
*
* For more information see `tools/gen_soc_caps_kconfig/README.md`
*
*/
#pragma once
/*-------------------------- COMMON CAPS ---------------------------------------*/
@ -86,18 +99,18 @@
#define SOC_DS_KEY_CHECK_MAX_WAIT_US (1100)
/*-------------------------- GDMA CAPS -------------------------------------*/
#define SOC_GDMA_GROUPS (1) // Number of GDMA groups
#define SOC_GDMA_PAIRS_PER_GROUP (3) // Number of GDMA pairs in each group
#define SOC_GDMA_TX_RX_SHARE_INTERRUPT (1) // TX and RX channel in the same pair will share the same interrupt source number
#define SOC_GDMA_GROUPS (1U) // Number of GDMA groups
#define SOC_GDMA_PAIRS_PER_GROUP (3) // Number of GDMA pairs in each group
#define SOC_GDMA_TX_RX_SHARE_INTERRUPT (1) // TX and RX channel in the same pair will share the same interrupt source number
/*-------------------------- GPIO CAPS ---------------------------------------*/
// ESP32-C3 has 1 GPIO peripheral
#define SOC_GPIO_PORT (1)
#define SOC_GPIO_PORT (1U)
#define SOC_GPIO_PIN_COUNT (22)
// Target has no full RTC IO subsystem, so GPIO is 100% "independent" of RTC
// On ESP32-C3, Digital IOs have their own registers to control pullup/down capability, independent of RTC registers.
#define GPIO_SUPPORTS_RTC_INDEPENDENT (1)
#define SOC_GPIO_SUPPORTS_RTC_INDEPENDENT (1)
// Force hold is a new function of ESP32-C3
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
// GPIO0~5 on ESP32C3 can support chip deep sleep wakeup
@ -105,7 +118,7 @@
#define SOC_GPIO_VALID_GPIO_MASK ((1U<<SOC_GPIO_PIN_COUNT) - 1)
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
#define SOC_GPIO_DEEP_SLEEP_WAKEUP_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5)
#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5)
// Support to configure sleep status
#define SOC_GPIO_SUPPORT_SLP_SWITCH (1)
@ -117,7 +130,7 @@
/*-------------------------- I2C CAPS ----------------------------------------*/
// ESP32-C3 have 2 I2C.
#define SOC_I2C_NUM (1)
#define SOC_I2C_NUM (1U)
#define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */
@ -128,7 +141,7 @@
#define SOC_I2C_SUPPORT_RTC (1)
/*-------------------------- I2S CAPS ----------------------------------------*/
#define SOC_I2S_NUM (1)
#define SOC_I2S_NUM (1U)
#define SOC_I2S_SUPPORTS_PCM (1)
#define SOC_I2S_SUPPORTS_PDM_TX (1)
#define SOC_I2S_SUPPORTS_PDM_CODEC (1)
@ -147,7 +160,7 @@
#define SOC_MPU_REGION_WO_SUPPORTED 0
/*--------------------------- RMT CAPS ---------------------------------------*/
#define SOC_RMT_GROUPS (1) /*!< One RMT group */
#define SOC_RMT_GROUPS (1U) /*!< One RMT group */
#define SOC_RMT_TX_CANDIDATES_PER_GROUP (2) /*!< Number of channels that capable of Transmit */
#define SOC_RMT_RX_CANDIDATES_PER_GROUP (2) /*!< Number of channels that capable of Receive */
#define SOC_RMT_CHANNELS_PER_GROUP (4) /*!< Total 4 channels */
@ -195,8 +208,8 @@
#define SOC_SHA_SUPPORT_SHA256 (1)
/*-------------------------- SIGMA DELTA CAPS --------------------------------*/
#define SOC_SIGMADELTA_NUM (1) // 1 sigma-delta peripheral
#define SOC_SIGMADELTA_CHANNEL_NUM (4) // 4 channels
#define SOC_SIGMADELTA_NUM (1U) // 1 sigma-delta peripheral
#define SOC_SIGMADELTA_CHANNEL_NUM (4) // 4 channels
/*-------------------------- SPI CAPS ----------------------------------------*/
#define SOC_SPI_PERIPH_NUM 2
@ -215,7 +228,7 @@
#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;})
// Peripheral supports output given level during its "dummy phase"
#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT 1
#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT 1
#define SOC_MEMSPI_IS_INDEPENDENT 1
#define SOC_SPI_MAX_PRE_DIVIDER 16

Wyświetl plik

@ -8,6 +8,19 @@
// seperate these information into periph_caps.h for each peripheral and
// include them here.
/*
* These defines are parsed and imported as kconfig variables via the script
* `tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py`
*
* If this file is changed the script will automatically run the script
* and generate the kconfig variables as part of the pre-commit hooks.
*
* It can also be ran manually with `./tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py 'components/soc/esp32h2/include/soc/'`
*
* For more information see `tools/gen_soc_caps_kconfig/README.md`
*
*/
#pragma once
/*-------------------------- COMMON CAPS ---------------------------------------*/
@ -77,18 +90,18 @@
#define SOC_DS_KEY_CHECK_MAX_WAIT_US (1100)
/*-------------------------- GDMA CAPS -------------------------------------*/
#define SOC_GDMA_GROUPS (1) // Number of GDMA groups
#define SOC_GDMA_PAIRS_PER_GROUP (3) // Number of GDMA pairs in each group
#define SOC_GDMA_TX_RX_SHARE_INTERRUPT (1) // TX and RX channel in the same pair will share the same interrupt source number
#define SOC_GDMA_GROUPS (1U) // Number of GDMA groups
#define SOC_GDMA_PAIRS_PER_GROUP (3) // Number of GDMA pairs in each group
#define SOC_GDMA_TX_RX_SHARE_INTERRUPT (1) // TX and RX channel in the same pair will share the same interrupt source number
/*-------------------------- GPIO CAPS ---------------------------------------*/
// ESP32-C3 has 1 GPIO peripheral
#define SOC_GPIO_PORT (1)
#define SOC_GPIO_PORT (1U)
#define SOC_GPIO_PIN_COUNT (22)
// Target has no full RTC IO subsystem, so GPIO is 100% "independent" of RTC
// On ESP32-C3, Digital IOs have their own registers to control pullup/down capability, independent of RTC registers.
#define GPIO_SUPPORTS_RTC_INDEPENDENT (1)
#define SOC_GPIO_SUPPORTS_RTC_INDEPENDENT (1)
// Force hold is a new function of ESP32-C3
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
// GPIO0~5 on ESP32C3 can support chip deep sleep wakeup
@ -96,7 +109,7 @@
#define SOC_GPIO_VALID_GPIO_MASK ((1U<<SOC_GPIO_PIN_COUNT) - 1)
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
#define SOC_GPIO_DEEP_SLEEP_WAKEUP_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5)
#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5)
// Support to configure sleep status
#define SOC_GPIO_SUPPORT_SLP_SWITCH (1)
@ -108,7 +121,7 @@
/*-------------------------- I2C CAPS ----------------------------------------*/
// ESP32-C3 have 2 I2C.
#define SOC_I2C_NUM (1)
#define SOC_I2C_NUM (1U)
#define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */
@ -138,7 +151,7 @@
#define SOC_MPU_REGION_WO_SUPPORTED 0
/*--------------------------- RMT CAPS ---------------------------------------*/
#define SOC_RMT_GROUPS (1) /*!< One RMT group */
#define SOC_RMT_GROUPS (1U) /*!< One RMT group */
#define SOC_RMT_TX_CANDIDATES_PER_GROUP (2) /*!< Number of channels that capable of Transmit */
#define SOC_RMT_RX_CANDIDATES_PER_GROUP (2) /*!< Number of channels that capable of Receive */
#define SOC_RMT_CHANNELS_PER_GROUP (4) /*!< Total 4 channels */
@ -186,8 +199,8 @@
#define SOC_SHA_SUPPORT_SHA256 (1)
/*-------------------------- SIGMA DELTA CAPS --------------------------------*/
#define SOC_SIGMADELTA_NUM (1) // 1 sigma-delta peripheral
#define SOC_SIGMADELTA_CHANNEL_NUM (4) // 4 channels
#define SOC_SIGMADELTA_NUM (1U) // 1 sigma-delta peripheral
#define SOC_SIGMADELTA_CHANNEL_NUM (4) // 4 channels
/*-------------------------- SPI CAPS ----------------------------------------*/
#define SOC_SPI_PERIPH_NUM 2
@ -206,7 +219,7 @@
#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;})
// Peripheral supports output given level during its "dummy phase"
#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT 1
#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT 1
#define SOC_MEMSPI_IS_INDEPENDENT 1
#define SOC_SPI_MAX_PRE_DIVIDER 16

Wyświetl plik

@ -0,0 +1,552 @@
#####################################################
# This file is auto-generated from SoC caps
# using gen_soc_caps_kconfig.py, do not edit manually
#####################################################
config SOC_CPU_CORES_NUM
bool
default y
config SOC_DEDICATED_GPIO_SUPPORTED
bool
default y
config SOC_GDMA_SUPPORTED
bool
default y
config SOC_TWAI_SUPPORTED
bool
default y
config SOC_BT_SUPPORTED
bool
default y
config SOC_DIG_SIGN_SUPPORTED
bool
default y
config SOC_HMAC_SUPPORTED
bool
default y
config SOC_ASYNC_MEMCPY_SUPPORTED
bool
default y
config SOC_USB_SERIAL_JTAG_SUPPORTED
bool
default y
config SOC_SUPPORTS_SECURE_DL_MODE
bool
default y
config SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS
int
default 3
config SOC_ICACHE_ACCESS_RODATA_SUPPORTED
bool
default y
config SOC_TEMP_SENSOR_SUPPORTED
bool
default y
config SOC_RTC_FAST_MEM_SUPPORTED
bool
default y
config SOC_RTC_SLOW_MEM_SUPPORTED
bool
default n
config SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY
bool
default y
config SOC_AES_SUPPORT_DMA
bool
default y
config SOC_AES_GDMA
bool
default y
config SOC_AES_SUPPORT_AES_128
bool
default y
config SOC_AES_SUPPORT_AES_256
bool
default y
config SOC_ADC_PERIPH_NUM
int
default 2
config SOC_ADC_PATT_LEN_MAX
int
default 16
config SOC_ADC_MAX_CHANNEL_NUM
int
default 5
config SOC_ADC_MAX_BITWIDTH
int
default 12
config SOC_ADC_DIGI_FILTER_NUM
int
default 2
config SOC_ADC_DIGI_MONITOR_NUM
int
default 2
config SOC_ADC_CALIBRATION_V1_SUPPORTED
bool
default y
config SOC_ADC_SAMPLE_FREQ_THRES_HIGH
int
default 83333
config SOC_ADC_SAMPLE_FREQ_THRES_LOW
int
default 611
config SOC_APB_BACKUP_DMA
bool
default y
config SOC_BROWNOUT_RESET_SUPPORTED
bool
default y
config SOC_CPU_BREAKPOINTS_NUM
int
default 8
config SOC_CPU_WATCHPOINTS_NUM
int
default 8
config SOC_CPU_HAS_FLEXIBLE_INTC
bool
default y
config SOC_CPU_WATCHPOINT_SIZE
hex
default 0x80000000
config SOC_DS_SIGNATURE_MAX_BIT_LEN
int
default 3072
config SOC_DS_KEY_PARAM_MD_IV_LENGTH
int
default 16
config SOC_DS_KEY_CHECK_MAX_WAIT_US
int
default 1100
config SOC_GDMA_GROUPS
int
default 1
config SOC_GDMA_PAIRS_PER_GROUP
int
default 3
config SOC_GDMA_TX_RX_SHARE_INTERRUPT
bool
default y
config SOC_GPIO_PORT
int
default 1
config SOC_GPIO_PIN_COUNT
int
default 22
config SOC_GPIO_SUPPORTS_RTC_INDEPENDENT
bool
default y
config SOC_GPIO_SUPPORT_FORCE_HOLD
bool
default y
config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
bool
default y
config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
int
default 0
config SOC_GPIO_SUPPORT_SLP_SWITCH
bool
default y
config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
int
default 8
config SOC_DEDIC_GPIO_IN_CHANNELS_NUM
int
default 8
config SOC_DEDIC_PERIPH_AUTO_ENABLE
bool
default y
config SOC_I2C_NUM
int
default 1
config SOC_I2C_FIFO_LEN
int
default 32
config SOC_I2C_SUPPORT_HW_FSM_RST
bool
default y
config SOC_I2C_SUPPORT_HW_CLR_BUS
bool
default y
config SOC_I2C_SUPPORT_XTAL
bool
default y
config SOC_I2C_SUPPORT_RTC
bool
default y
config SOC_I2S_NUM
bool
default y
config SOC_I2S_SUPPORTS_PCM
bool
default y
config SOC_I2S_SUPPORTS_PDM_TX
bool
default y
config SOC_I2S_SUPPORTS_PDM_CODEC
bool
default y
config SOC_I2S_SUPPORTS_TDM
bool
default y
config SOC_LEDC_SUPPORT_XTAL_CLOCK
bool
default y
config SOC_LEDC_CHANNEL_NUM
int
default 6
config SOC_LEDC_TIMER_BIT_WIDE_NUM
int
default 14
config SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED
bool
default n
config SOC_MPU_MIN_REGION_SIZE
hex
default 0x20000000
config SOC_MPU_REGIONS_MAX_NUM
int
default 8
config SOC_MPU_REGION_RO_SUPPORTED
bool
default n
config SOC_MPU_REGION_WO_SUPPORTED
bool
default n
config SOC_RMT_GROUPS
int
default 1
config SOC_RMT_TX_CANDIDATES_PER_GROUP
int
default 2
config SOC_RMT_RX_CANDIDATES_PER_GROUP
int
default 2
config SOC_RMT_CHANNELS_PER_GROUP
int
default 4
config SOC_RMT_MEM_WORDS_PER_CHANNEL
int
default 48
config SOC_RMT_SUPPORT_RX_PINGPONG
bool
default y
config SOC_RMT_SUPPORT_RX_DEMODULATION
bool
default y
config SOC_RMT_SUPPORT_TX_LOOP_COUNT
bool
default y
config SOC_RMT_SUPPORT_TX_SYNCHRO
bool
default y
config SOC_RMT_SUPPORT_XTAL
bool
default y
config SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH
int
default 128
config SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM
int
default 108
config SOC_RTCIO_PIN_COUNT
bool
default n
config SOC_RSA_MAX_BIT_LEN
int
default 3072
config SOC_SHA_DMA_MAX_BUFFER_SIZE
int
default 3968
config SOC_SHA_SUPPORT_DMA
bool
default y
config SOC_SHA_SUPPORT_RESUME
bool
default y
config SOC_SHA_GDMA
bool
default y
config SOC_SHA_SUPPORT_SHA1
bool
default y
config SOC_SHA_SUPPORT_SHA224
bool
default y
config SOC_SHA_SUPPORT_SHA256
bool
default y
config SOC_SIGMADELTA_NUM
int
default 1
config SOC_SIGMADELTA_CHANNEL_NUM
int
default 4
config SOC_SPI_PERIPH_NUM
int
default 2
config SOC_SPI_MAXIMUM_BUFFER_SIZE
int
default 64
config SOC_SPI_SUPPORT_DDRCLK
bool
default y
config SOC_SPI_SLAVE_SUPPORT_SEG_TRANS
bool
default y
config SOC_SPI_SUPPORT_CD_SIG
bool
default y
config SOC_SPI_SUPPORT_CONTINUOUS_TRANS
bool
default y
config SOC_SPI_SUPPORT_SLAVE_HD_VER2
bool
default y
config SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT
bool
default y
config SOC_MEMSPI_IS_INDEPENDENT
bool
default y
config SOC_SPI_MAX_PRE_DIVIDER
int
default 16
config SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE
bool
default y
config SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND
bool
default y
config SOC_SPI_MEM_SUPPORT_AUTO_RESUME
bool
default y
config SOC_SPI_MEM_SUPPORT_IDLE_INTR
bool
default y
config SOC_SPI_MEM_SUPPORT_SW_SUSPEND
bool
default y
config SOC_SPI_MEM_SUPPORT_CHECK_SUS
bool
default y
config SOC_SYSTIMER_COUNTER_NUM
int
default 2
config SOC_SYSTIMER_ALARM_NUM
int
default 3
config SOC_SYSTIMER_BIT_WIDTH_LO
int
default 32
config SOC_SYSTIMER_BIT_WIDTH_HI
int
default 20
config SOC_SYSTIMER_FIXED_TICKS_US
int
default 16
config SOC_SYSTIMER_INT_LEVEL
bool
default y
config SOC_SYSTIMER_ALARM_MISS_COMPENSATE
bool
default y
config SOC_TIMER_GROUPS
int
default 2
config SOC_TIMER_GROUP_TIMERS_PER_GROUP
bool
default y
config SOC_TIMER_GROUP_COUNTER_BIT_WIDTH
int
default 54
config SOC_TIMER_GROUP_SUPPORT_XTAL
bool
default y
config SOC_TOUCH_SENSOR_NUM
bool
default n
config SOC_TWAI_BRP_MIN
int
default 2
config SOC_TWAI_BRP_MAX
int
default 16384
config SOC_TWAI_SUPPORTS_RX_STATUS
bool
default y
config SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX
int
default 32
config SOC_UART_NUM
int
default 2
config SOC_UART_FIFO_LEN
int
default 128
config SOC_UART_BITRATE_MAX
int
default 5000000
config SOC_UART_SUPPORT_RTC_CLK
bool
default y
config SOC_UART_SUPPORT_XTAL_CLK
bool
default y
config SOC_UART_SUPPORT_FSM_TX_WAIT_SEND
bool
default y
config SOC_COEX_HW_PTI
bool
default y
config SOC_PHY_DIG_REGS_MEM_SIZE
int
default 21
config SOC_MAC_BB_PD_MEM_SIZE
int
default 192
config SOC_PM_SUPPORT_BT_WAKEUP
bool
default y
config SOC_PM_SUPPORT_CPU_PD
bool
default y
config SOC_PM_SUPPORT_BT_PD
bool
default y

Wyświetl plik

@ -1,22 +0,0 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#define RTC_CNTL_CPU_PD_DMA_BUS_WIDTH (128)
#define RTC_CNTL_CPU_PD_REG_FILE_NUM (108)
#define RTC_CNTL_CPU_PD_DMA_ADDR_ALIGN (RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3)
#define RTC_CNTL_CPU_PD_DMA_BLOCK_SIZE (RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3)
#define RTC_CNTL_CPU_PD_RETENTION_MEM_SIZE (RTC_CNTL_CPU_PD_REG_FILE_NUM * (RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3))

Wyświetl plik

@ -1,21 +0,0 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
/* No dedicated RTCIO subsystem on ESP32-H2. RTC functions are still supported
* for hold, wake & 32kHz crystal functions - via rtc_cntl_reg */
#define SOC_RTCIO_PIN_COUNT 0
#define RTCIO_LL_PIN_FUNC 0

Wyświetl plik

@ -1,38 +0,0 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#define SOC_SPI_PERIPH_NUM 2
#define SOC_SPI_DMA_CHAN_NUM 3
#define SOC_SPI_PERIPH_CS_NUM(i) 3
#define SOC_SPI_MAXIMUM_BUFFER_SIZE 72
//#define SOC_SPI_SUPPORT_AS_CS //don't support to toggle the CS while the clock toggles
#define SOC_SPI_SUPPORT_DDRCLK 1
#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1
#define SOC_SPI_SUPPORT_CD_SIG 1
#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1
#define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1
// Peripheral supports DIO, DOUT, QIO, or QOUT
#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ((host_id) != 2)
// Peripheral supports output given level during its "dummy phase"
#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT 1
#define SOC_MEMSPI_IS_INDEPENDENT 1
#define SOC_SPI_MAX_PRE_DIVIDER 16

Wyświetl plik

@ -0,0 +1,680 @@
#####################################################
# This file is auto-generated from SoC caps
# using gen_soc_caps_kconfig.py, do not edit manually
#####################################################
config SOC_DAC_SUPPORTED
bool
default y
config SOC_TWAI_SUPPORTED
bool
default y
config SOC_CP_DMA_SUPPORTED
bool
default y
config SOC_CPU_CORES_NUM
bool
default y
config SOC_DEDICATED_GPIO_SUPPORTED
bool
default y
config SOC_SUPPORTS_SECURE_DL_MODE
bool
default y
config SOC_RISCV_COPROC_SUPPORTED
bool
default y
config SOC_USB_OTG_SUPPORTED
bool
default y
config SOC_PCNT_SUPPORTED
bool
default y
config SOC_ULP_SUPPORTED
bool
default y
config SOC_CCOMP_TIMER_SUPPORTED
bool
default y
config SOC_DIG_SIGN_SUPPORTED
bool
default y
config SOC_HMAC_SUPPORTED
bool
default y
config SOC_ASYNC_MEMCPY_SUPPORTED
bool
default y
config SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS
int
default 3
config SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS
bool
default y
config SOC_ICACHE_ACCESS_RODATA_SUPPORTED
bool
default y
config SOC_TEMP_SENSOR_SUPPORTED
bool
default y
config SOC_CACHE_SUPPORT_WRAP
bool
default y
config SOC_FLASH_ENCRYPTION_XTS_AES
bool
default y
config SOC_FLASH_ENCRYPTION_XTS_AES_256
bool
default y
config SOC_RTC_FAST_MEM_SUPPORTED
bool
default y
config SOC_RTC_SLOW_MEM_SUPPORTED
bool
default y
config SOC_PSRAM_DMA_CAPABLE
bool
default y
config SOC_XT_WDT_SUPPORTED
bool
default y
config SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY
bool
default y
config SOC_ADC_RTC_CTRL_SUPPORTED
bool
default y
config SOC_ADC_ARBITER_SUPPORTED
bool
default y
config SOC_ADC_FILTER_SUPPORTED
bool
default y
config SOC_ADC_MONITOR_SUPPORTED
bool
default y
config SOC_ADC_PERIPH_NUM
int
default 2
config SOC_ADC_MAX_CHANNEL_NUM
int
default 10
config SOC_ADC_DIGI_CONTROLLER_NUM
int
default 2
config SOC_ADC_PATT_LEN_MAX
int
default 32
config SOC_ADC_DIGI_MAX_BITWIDTH
int
default 12
config SOC_ADC_SAMPLE_FREQ_THRES_HIGH
int
default 83333
config SOC_ADC_SAMPLE_FREQ_THRES_LOW
int
default 611
config SOC_ADC_MAX_BITWIDTH
int
default 13
config SOC_ADC_CALIBRATION_V1_SUPPORTED
bool
default y
config SOC_BROWNOUT_RESET_SUPPORTED
bool
default y
config SOC_CP_DMA_MAX_BUFFER_SIZE
int
default 4095
config SOC_CPU_BREAKPOINTS_NUM
int
default 2
config SOC_CPU_WATCHPOINTS_NUM
int
default 2
config SOC_CPU_WATCHPOINT_SIZE
int
default 64
config SOC_DAC_PERIPH_NUM
int
default 2
config SOC_DAC_RESOLUTION
int
default 8
config SOC_GPIO_PORT
int
default 1
config SOC_GPIO_PIN_COUNT
int
default 48
config SOC_GPIO_SUPPORT_RTC_INDEPENDENT
bool
default y
config SOC_GPIO_SUPPORT_FORCE_HOLD
bool
default y
config SOC_GPIO_VALID_GPIO_MASK
hex
default 0xFFFFFFFFFFFF
config SOC_GPIO_SUPPORT_SLP_SWITCH
bool
default y
config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
int
default 8
config SOC_DEDIC_GPIO_IN_CHANNELS_NUM
int
default 8
config SOC_DEDIC_GPIO_ALLOW_REG_ACCESS
bool
default y
config SOC_DEDIC_GPIO_HAS_INTERRUPT
bool
default y
config SOC_DEDIC_GPIO_OUT_AUTO_ENABLE
bool
default y
config SOC_I2C_NUM
int
default 2
config SOC_I2C_FIFO_LEN
int
default 32
config SOC_I2C_SUPPORT_HW_FSM_RST
bool
default y
config SOC_I2C_SUPPORT_HW_CLR_BUS
bool
default y
config SOC_I2C_SUPPORT_REF_TICK
bool
default y
config SOC_I2C_SUPPORT_APB
bool
default y
config SOC_I2S_NUM
int
default 1
config SOC_I2S_SUPPORTS_APLL
bool
default y
config SOC_I2S_SUPPORTS_DMA_EQUAL
bool
default y
config SOC_I2S_APLL_MIN_FREQ
int
default 250000000
config SOC_I2S_APLL_MAX_FREQ
int
default 500000000
config SOC_I2S_APLL_MIN_RATE
int
default 10675
config SOC_I2S_LCD_I80_VARIANT
bool
default y
config SOC_LCD_I80_SUPPORTED
bool
default y
config SOC_LCD_I80_BUSES
bool
default y
config SOC_LCD_I80_BUS_WIDTH
int
default 24
config SOC_LEDC_HAS_TIMER_SPECIFIC_MUX
bool
default y
config SOC_LEDC_SUPPORT_REF_TICK
bool
default y
config SOC_LEDC_SUPPORT_XTAL_CLOCK
bool
default y
config SOC_LEDC_CHANNEL_NUM
int
default 8
config SOC_LEDC_TIMER_BIT_WIDE_NUM
int
default 14
config SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED
bool
default n
config SOC_MPU_MIN_REGION_SIZE
hex
default 0x20000000
config SOC_MPU_REGIONS_MAX_NUM
int
default 8
config SOC_MPU_REGION_RO_SUPPORTED
bool
default n
config SOC_MPU_REGION_WO_SUPPORTED
bool
default n
config SOC_PCNT_GROUPS
int
default 1
config SOC_PCNT_UNITS_PER_GROUP
int
default 4
config SOC_PCNT_CHANNELS_PER_UNIT
int
default 2
config SOC_PCNT_THRES_POINT_PER_UNIT
int
default 2
config SOC_RMT_GROUPS
int
default 1
config SOC_RMT_TX_CANDIDATES_PER_GROUP
int
default 4
config SOC_RMT_RX_CANDIDATES_PER_GROUP
int
default 4
config SOC_RMT_CHANNELS_PER_GROUP
int
default 4
config SOC_RMT_MEM_WORDS_PER_CHANNEL
int
default 64
config SOC_RMT_SUPPORT_RX_PINGPONG
bool
default y
config SOC_RMT_SUPPORT_RX_DEMODULATION
bool
default y
config SOC_RMT_SUPPORT_TX_LOOP_COUNT
bool
default y
config SOC_RMT_SUPPORT_TX_SYNCHRO
bool
default y
config SOC_RMT_SUPPORT_REF_TICK
bool
default y
config SOC_RMT_CHANNEL_CLK_INDEPENDENT
bool
default y
config SOC_RTCIO_PIN_COUNT
int
default 22
config SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
bool
default y
config SOC_RTCIO_HOLD_SUPPORTED
bool
default y
config SOC_RTCIO_WAKE_SUPPORTED
bool
default y
config SOC_SIGMADELTA_NUM
int
default 1
config SOC_SIGMADELTA_CHANNEL_NUM
int
default 8
config SOC_SPI_PERIPH_NUM
int
default 3
config SOC_SPI_DMA_CHAN_NUM
int
default 3
config SOC_SPI_MAXIMUM_BUFFER_SIZE
int
default 72
config SOC_SPI_MAX_PRE_DIVIDER
int
default 8192
config SOC_SPI_SUPPORT_DDRCLK
bool
default y
config SOC_SPI_SLAVE_SUPPORT_SEG_TRANS
bool
default y
config SOC_SPI_SUPPORT_CD_SIG
bool
default y
config SOC_SPI_SUPPORT_CONTINUOUS_TRANS
bool
default y
config SOC_SPI_SUPPORT_SLAVE_HD_VER2
bool
default y
config SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT
bool
default y
config SOC_MEMSPI_IS_INDEPENDENT
bool
default y
config SOC_SPI_SUPPORT_OCT
bool
default y
config SOC_SYSTIMER_COUNTER_NUM
bool
default y
config SOC_SYSTIMER_ALARM_NUM
int
default 3
config SOC_SYSTIMER_BIT_WIDTH_LO
int
default 32
config SOC_SYSTIMER_BIT_WIDTH_HI
int
default 32
config SOC_TIMER_GROUP_COUNTER_BIT_WIDTH
int
default 64
config SOC_TIMER_GROUPS
int
default 2
config SOC_TIMER_GROUP_TIMERS_PER_GROUP
int
default 2
config SOC_TIMER_GROUP_SUPPORT_XTAL
bool
default y
config SOC_TOUCH_VERSION_2
bool
default y
config SOC_TOUCH_SENSOR_NUM
int
default 15
config SOC_TOUCH_PROXIMITY_CHANNEL_NUM
int
default 3
config SOC_TOUCH_PAD_THRESHOLD_MAX
hex
default 0x1FFFFF
config SOC_TOUCH_PAD_MEASURE_WAIT_MAX
hex
default 0xFF
config SOC_TWAI_BRP_MIN
int
default 2
config SOC_TWAI_BRP_MAX
int
default 32768
config SOC_TWAI_SUPPORTS_RX_STATUS
bool
default y
config SOC_UART_NUM
int
default 2
config SOC_UART_SUPPORT_REF_TICK
bool
default y
config SOC_UART_FIFO_LEN
int
default 128
config SOC_UART_BITRATE_MAX
int
default 5000000
config SOC_SPIRAM_SUPPORTED
bool
default y
config SOC_USB_PERIPH_NUM
bool
default y
config SOC_SHA_DMA_MAX_BUFFER_SIZE
int
default 3968
config SOC_SHA_SUPPORT_DMA
bool
default y
config SOC_SHA_SUPPORT_RESUME
bool
default y
config SOC_SHA_CRYPTO_DMA
bool
default y
config SOC_SHA_SUPPORT_SHA1
bool
default y
config SOC_SHA_SUPPORT_SHA224
bool
default y
config SOC_SHA_SUPPORT_SHA256
bool
default y
config SOC_SHA_SUPPORT_SHA384
bool
default y
config SOC_SHA_SUPPORT_SHA512
bool
default y
config SOC_SHA_SUPPORT_SHA512_224
bool
default y
config SOC_SHA_SUPPORT_SHA512_256
bool
default y
config SOC_SHA_SUPPORT_SHA512_T
bool
default y
config SOC_RSA_MAX_BIT_LEN
int
default 4096
config SOC_AES_SUPPORT_DMA
bool
default y
config SOC_AES_SUPPORT_GCM
bool
default y
config SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX
int
default 64
config SOC_AES_CRYPTO_DMA
bool
default y
config SOC_AES_SUPPORT_AES_128
bool
default y
config SOC_AES_SUPPORT_AES_192
bool
default y
config SOC_AES_SUPPORT_AES_256
bool
default y
config SOC_WIFI_HW_TSF
bool
default y
config SOC_PHY_DIG_REGS_MEM_SIZE
int
default 21
config SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH
int
default 12
config SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE
bool
default y
config SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND
bool
default y
config SOC_SPI_MEM_SUPPORT_SW_SUSPEND
bool
default y
config SOC_PM_SUPPORT_EXT_WAKEUP
bool
default y
config SOC_PM_SUPPORT_WIFI_WAKEUP
bool
default y
config SOC_PM_SUPPORT_WIFI_PD
bool
default y
config SOC_PM_SUPPORT_TOUCH_SENSOR_WAKEUP
bool
default y
config SOC_COEX_HW_PTI
bool
default y

Wyświetl plik

@ -24,6 +24,16 @@
* ECO & exceptions:
* For ECO-ed booleans, `#define x "Not determined"` for them. This will cause error when used by
* `#if x` and `#if !x`, making these missing definitions more obvious.
*
* These defines are parsed and imported as kconfig variables via the script
* `tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py`
*
* If this file is changed the script will automatically run the script
* and generate the kconfig variables as part of the pre-commit hooks.
*
* It can also be ran manually with `./tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py 'components/soc/esp32s2/include/soc/'`
*
* For more information see `tools/gen_soc_caps_kconfig/README.md`
*/
#pragma once
@ -100,7 +110,7 @@
/*-------------------------- GPIO CAPS ---------------------------------------*/
// ESP32-S2 has 1 GPIO peripheral
#define SOC_GPIO_PORT (1)
#define SOC_GPIO_PORT (1U)
#define SOC_GPIO_PIN_COUNT (48)
// On ESP32 those PADs which have RTC functions must set pullup/down/capability via RTC register.
@ -140,7 +150,7 @@
/*-------------------------- I2S CAPS ----------------------------------------*/
// ESP32-S2 have 1 I2S
#define SOC_I2S_NUM (1)
#define SOC_I2S_NUM (1U)
#define SOC_I2S_SUPPORTS_APLL (1)// ESP32-S2 support APLL
#define SOC_I2S_SUPPORTS_DMA_EQUAL (1)
#define SOC_I2S_APLL_MIN_FREQ (250000000)
@ -170,13 +180,13 @@
#define SOC_MPU_REGION_WO_SUPPORTED 0
/*-------------------------- PCNT CAPS ---------------------------------------*/
#define SOC_PCNT_GROUPS (1)
#define SOC_PCNT_GROUPS (1U)
#define SOC_PCNT_UNITS_PER_GROUP (4)
#define SOC_PCNT_CHANNELS_PER_UNIT (2)
#define SOC_PCNT_THRES_POINT_PER_UNIT (2)
/*-------------------------- RMT CAPS ----------------------------------------*/
#define SOC_RMT_GROUPS (1) /*!< One RMT group */
#define SOC_RMT_GROUPS (1U) /*!< One RMT group */
#define SOC_RMT_TX_CANDIDATES_PER_GROUP (4) /*!< Number of channels that capable of Transmit in each group */
#define SOC_RMT_RX_CANDIDATES_PER_GROUP (4) /*!< Number of channels that capable of Receive in each group */
#define SOC_RMT_CHANNELS_PER_GROUP (4) /*!< Total 4 channels */
@ -196,7 +206,7 @@
/*-------------------------- SIGMA DELTA CAPS --------------------------------*/
#define SOC_SIGMADELTA_NUM 1
#define SOC_SIGMADELTA_NUM 1U
#define SOC_SIGMADELTA_CHANNEL_NUM (8) // 8 channels
/*-------------------------- SPI CAPS ----------------------------------------*/
@ -221,7 +231,7 @@
// Peripheral supports output given level during its "dummy phase"
// Only SPI1 supports this feature
#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT 1
#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT 1
#define SOC_MEMSPI_IS_INDEPENDENT 1
#define SOC_SPI_SUPPORT_OCT 1
@ -291,12 +301,6 @@
#define SOC_SHA_SUPPORT_SHA512_256 (1)
#define SOC_SHA_SUPPORT_SHA512_T (1)
/* Supported HW algorithms */
#define SOC_SHA_SUPPORT_SHA1 (1)
#define SOC_SHA_SUPPORT_SHA256 (1)
#define SOC_SHA_SUPPORT_SHA384 (1)
#define SOC_SHA_SUPPORT_SHA512 (1)
/*--------------------------- RSA CAPS ---------------------------------------*/
#define SOC_RSA_MAX_BIT_LEN (4096)

Wyświetl plik

@ -0,0 +1,836 @@
#####################################################
# This file is auto-generated from SoC caps
# using gen_soc_caps_kconfig.py, do not edit manually
#####################################################
config SOC_BROWNOUT_RESET_SUPPORTED
bool
default y
config SOC_CPU_BREAKPOINTS_NUM
int
default 2
config SOC_CPU_WATCHPOINTS_NUM
int
default 2
config SOC_CPU_WATCHPOINT_SIZE
int
default 64
config SOC_CPU_HAS_FPU
bool
default y
config SOC_GPIO_PORT
int
default 1
config SOC_GPIO_PIN_COUNT
int
default 49
config SOC_GPIO_SUPPORT_RTC_INDEPENDENT
bool
default y
config SOC_GPIO_SUPPORT_FORCE_HOLD
bool
default y
config SOC_GPIO_VALID_GPIO_MASK
hex
default 0x1FFFFFFFFFFFF
config SOC_GPIO_SUPPORT_SLP_SWITCH
bool
default y
config SOC_I2C_NUM
int
default 2
config SOC_I2C_FIFO_LEN
int
default 32
config SOC_I2C_SUPPORT_HW_FSM_RST
bool
default y
config SOC_I2C_SUPPORT_HW_CLR_BUS
bool
default y
config SOC_I2C_SUPPORT_XTAL
bool
default y
config SOC_I2C_SUPPORT_RTC
bool
default y
config SOC_LEDC_HAS_TIMER_SPECIFIC_MUX
bool
default y
config SOC_LEDC_SUPPORT_REF_TICK
bool
default y
config SOC_LEDC_SUPPORT_XTAL_CLOCK
bool
default y
config SOC_LEDC_CHANNEL_NUM
int
default 8
config SOC_LEDC_TIMER_BIT_WIDE_NUM
int
default 14
config SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED
bool
default n
config SOC_MPU_MIN_REGION_SIZE
hex
default 0x20000000
config SOC_MPU_REGIONS_MAX_NUM
int
default 8
config SOC_MPU_REGION_RO_SUPPORTED
bool
default n
config SOC_MPU_REGION_WO_SUPPORTED
bool
default n
config SOC_PCNT_PORT_NUM
bool
default y
config SOC_PCNT_UNIT_NUM
int
default 4
config SOC_RTCIO_PIN_COUNT
int
default 22
config SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
bool
default y
config SOC_RTCIO_HOLD_SUPPORTED
bool
default y
config SOC_RTCIO_WAKE_SUPPORTED
bool
default y
config SOC_PCNT_SUPPORTED
bool
default y
config SOC_TWAI_SUPPORTED
bool
default y
config SOC_GDMA_SUPPORTED
bool
default y
config SOC_LCDCAM_SUPPORTED
bool
default y
config SOC_MCPWM_SUPPORTED
bool
default y
config SOC_DEDICATED_GPIO_SUPPORTED
bool
default y
config SOC_CPU_CORES_NUM
int
default 2
config SOC_CACHE_SUPPORT_WRAP
bool
default y
config SOC_ULP_SUPPORTED
bool
default y
config SOC_BT_SUPPORTED
bool
default y
config SOC_USB_OTG_SUPPORTED
bool
default y
config SOC_USB_SERIAL_JTAG_SUPPORTED
bool
default y
config SOC_CCOMP_TIMER_SUPPORTED
bool
default y
config SOC_DIG_SIGN_SUPPORTED
bool
default y
config SOC_HMAC_SUPPORTED
bool
default y
config SOC_ASYNC_MEMCPY_SUPPORTED
bool
default y
config SOC_SUPPORTS_SECURE_DL_MODE
bool
default y
config SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS
int
default 3
config SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS
bool
default y
config SOC_SDMMC_HOST_SUPPORTED
bool
default y
config SOC_FLASH_ENCRYPTION_XTS_AES
bool
default y
config SOC_RTC_FAST_MEM_SUPPORTED
bool
default y
config SOC_RTC_SLOW_MEM_SUPPORTED
bool
default y
config SOC_FLASH_ENCRYPTION_XTS_AES_256
bool
default y
config SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY
bool
default y
config SOC_PSRAM_DMA_CAPABLE
bool
default y
config SOC_XT_WDT_SUPPORTED
bool
default y
config SOC_APPCPU_HAS_CLOCK_GATING_BUG
bool
default y
config SOC_ADC_RTC_CTRL_SUPPORTED
bool
default y
config SOC_ADC_ARBITER_SUPPORTED
bool
default y
config SOC_ADC_FILTER_SUPPORTED
bool
default y
config SOC_ADC_MONITOR_SUPPORTED
bool
default y
config SOC_ADC_PERIPH_NUM
int
default 2
config SOC_ADC_MAX_CHANNEL_NUM
int
default 10
config SOC_ADC_DIGI_CONTROLLER_NUM
int
default 2
config SOC_ADC_PATT_LEN_MAX
int
default 24
config SOC_ADC_DIGI_MAX_BITWIDTH
int
default 13
config SOC_ADC_SAMPLE_FREQ_THRES_HIGH
int
default 83333
config SOC_ADC_SAMPLE_FREQ_THRES_LOW
int
default 611
config SOC_ADC_MAX_BITWIDTH
int
default 12
config SOC_ADC_CALIBRATION_V1_SUPPORTED
bool
default y
config SOC_APB_BACKUP_DMA
bool
default y
config SOC_DS_SIGNATURE_MAX_BIT_LEN
int
default 4096
config SOC_DS_KEY_PARAM_MD_IV_LENGTH
int
default 16
config SOC_DS_KEY_CHECK_MAX_WAIT_US
int
default 1100
config SOC_GDMA_GROUPS
bool
default y
config SOC_GDMA_PAIRS_PER_GROUP
int
default 5
config SOC_GDMA_SUPPORT_PSRAM
bool
default y
config SOC_GDMA_PSRAM_MIN_ALIGN
int
default 16
config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
int
default 8
config SOC_DEDIC_GPIO_IN_CHANNELS_NUM
int
default 8
config SOC_DEDIC_GPIO_OUT_AUTO_ENABLE
bool
default y
config SOC_I2S_NUM
int
default 2
config SOC_I2S_SUPPORTS_PCM
bool
default y
config SOC_I2S_SUPPORTS_PDM_TX
bool
default y
config SOC_I2S_SUPPORTS_PDM_RX
bool
default y
config SOC_I2S_SUPPORTS_PDM_CODEC
bool
default y
config SOC_I2S_SUPPORTS_TDM
bool
default y
config SOC_MCPWM_GROUPS
int
default 2
config SOC_MCPWM_TIMERS_PER_GROUP
int
default 3
config SOC_MCPWM_OPERATORS_PER_GROUP
int
default 3
config SOC_MCPWM_COMPARATORS_PER_OPERATOR
int
default 2
config SOC_MCPWM_GENERATORS_PER_OPERATOR
int
default 2
config SOC_MCPWM_TRIGGERS_PER_OPERATOR
int
default 2
config SOC_MCPWM_GPIO_FAULTS_PER_GROUP
int
default 3
config SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP
bool
default y
config SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER
int
default 3
config SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP
int
default 3
config SOC_MCPWM_SWSYNC_CAN_PROPAGATE
bool
default y
config SOC_MCPWM_BASE_CLK_HZ
int
default 160000000
config SOC_PCNT_GROUPS
bool
default y
config SOC_PCNT_UNITS_PER_GROUP
int
default 4
config SOC_PCNT_CHANNELS_PER_UNIT
int
default 2
config SOC_PCNT_THRES_POINT_PER_UNIT
int
default 2
config SOC_RMT_GROUPS
bool
default y
config SOC_RMT_TX_CANDIDATES_PER_GROUP
int
default 4
config SOC_RMT_RX_CANDIDATES_PER_GROUP
int
default 4
config SOC_RMT_CHANNELS_PER_GROUP
int
default 8
config SOC_RMT_MEM_WORDS_PER_CHANNEL
int
default 48
config SOC_RMT_SUPPORT_RX_PINGPONG
bool
default y
config SOC_RMT_SUPPORT_RX_DEMODULATION
bool
default y
config SOC_RMT_SUPPORT_TX_LOOP_COUNT
bool
default y
config SOC_RMT_SUPPORT_TX_LOOP_AUTOSTOP
bool
default y
config SOC_RMT_SUPPORT_TX_SYNCHRO
bool
default y
config SOC_RMT_SUPPORT_XTAL
bool
default y
config SOC_LCD_I80_SUPPORTED
bool
default y
config SOC_LCD_RGB_SUPPORTED
bool
default y
config SOC_LCD_I80_BUSES
bool
default y
config SOC_LCD_RGB_PANELS
bool
default y
config SOC_LCD_I80_BUS_WIDTH
int
default 16
config SOC_LCD_RGB_DATA_WIDTH
int
default 16
config SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH
int
default 128
config SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM
int
default 549
config SOC_RTC_CNTL_TAGMEM_PD_DMA_BUS_WIDTH
int
default 128
config SOC_SIGMADELTA_NUM
bool
default y
config SOC_SIGMADELTA_CHANNEL_NUM
int
default 8
config SOC_SPI_PERIPH_NUM
int
default 3
config SOC_SPI_DMA_CHAN_NUM
int
default 3
config SOC_SPI_MAXIMUM_BUFFER_SIZE
int
default 64
config SOC_SPI_SUPPORT_DDRCLK
bool
default y
config SOC_SPI_SLAVE_SUPPORT_SEG_TRANS
bool
default y
config SOC_SPI_SUPPORT_CD_SIG
bool
default y
config SOC_SPI_SUPPORT_CONTINUOUS_TRANS
bool
default y
config SOC_SPI_SUPPORT_SLAVE_HD_VER2
bool
default y
config SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT
bool
default y
config SOC_MEMSPI_IS_INDEPENDENT
bool
default y
config SOC_SPI_MAX_PRE_DIVIDER
int
default 16
config SOC_SPI_SUPPORT_OCT
bool
default y
config SOC_SPIRAM_SUPPORTED
bool
default y
config SOC_TOUCH_VERSION_2
bool
default y
config SOC_SYSTIMER_COUNTER_NUM
int
default 2
config SOC_SYSTIMER_ALARM_NUM
int
default 3
config SOC_SYSTIMER_BIT_WIDTH_LO
int
default 32
config SOC_SYSTIMER_BIT_WIDTH_HI
int
default 20
config SOC_SYSTIMER_FIXED_TICKS_US
int
default 16
config SOC_SYSTIMER_INT_LEVEL
bool
default y
config SOC_SYSTIMER_ALARM_MISS_COMPENSATE
bool
default y
config SOC_TIMER_GROUPS
int
default 2
config SOC_TIMER_GROUP_TIMERS_PER_GROUP
int
default 2
config SOC_TIMER_GROUP_COUNTER_BIT_WIDTH
int
default 54
config SOC_TIMER_GROUP_SUPPORT_XTAL
bool
default y
config SOC_TOUCH_SENSOR_NUM
int
default 15
config SOC_TOUCH_PROXIMITY_CHANNEL_NUM
int
default 3
config SOC_TOUCH_PROXIMITY_MEAS_DONE_SUPPORTED
bool
default y
config SOC_TOUCH_PAD_THRESHOLD_MAX
hex
default 0x1FFFFF
config SOC_TOUCH_PAD_MEASURE_WAIT_MAX
hex
default 0xFF
config SOC_UART_SUPPORT_RTC_CLK
bool
default y
config SOC_UART_SUPPORT_XTAL_CLK
bool
default y
config SOC_USB_PERIPH_NUM
bool
default y
config SOC_SHA_DMA_MAX_BUFFER_SIZE
int
default 3968
config SOC_SHA_SUPPORT_DMA
bool
default y
config SOC_SHA_SUPPORT_RESUME
bool
default y
config SOC_SHA_GDMA
bool
default y
config SOC_SHA_SUPPORT_SHA1
bool
default y
config SOC_SHA_SUPPORT_SHA224
bool
default y
config SOC_SHA_SUPPORT_SHA256
bool
default y
config SOC_SHA_SUPPORT_SHA384
bool
default y
config SOC_SHA_SUPPORT_SHA512
bool
default y
config SOC_SHA_SUPPORT_SHA512_224
bool
default y
config SOC_SHA_SUPPORT_SHA512_256
bool
default y
config SOC_SHA_SUPPORT_SHA512_T
bool
default y
config SOC_RSA_MAX_BIT_LEN
int
default 4096
config SOC_AES_SUPPORT_DMA
bool
default y
config SOC_AES_GDMA
bool
default y
config SOC_AES_SUPPORT_AES_128
bool
default y
config SOC_AES_SUPPORT_AES_256
bool
default y
config SOC_PM_SUPPORT_EXT_WAKEUP
bool
default y
config SOC_PM_SUPPORT_WIFI_WAKEUP
bool
default y
config SOC_PM_SUPPORT_BT_WAKEUP
bool
default y
config SOC_PM_SUPPORT_CPU_PD
bool
default y
config SOC_PM_SUPPORT_TAGMEM_PD
bool
default y
config SOC_PM_SUPPORT_TOUCH_SENSOR_WAKEUP
bool
default y
config SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY
bool
default y
config SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX
int
default 64
config SOC_WIFI_HW_TSF
bool
default y
config SOC_PHY_DIG_REGS_MEM_SIZE
int
default 21
config SOC_MAC_BB_PD_MEM_SIZE
int
default 192
config SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH
int
default 12
config SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE
bool
default y
config SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND
bool
default y
config SOC_SPI_MEM_SUPPORT_AUTO_RESUME
bool
default y
config SOC_SPI_MEM_SUPPORT_SW_SUSPEND
bool
default y
config SOC_SPI_MEM_SUPPORT_OPI_MODE
bool
default y
config SOC_SPI_MEM_SUPPORT_TIME_TUNING
bool
default y
config SOC_COEX_HW_PTI
bool
default y
config SOC_SDMMC_USE_GPIO_MATRIX
bool
default y
config SOC_SDMMC_NUM_SLOTS
int
default 2
config SOC_SDMMC_SUPPORT_XTAL_CLOCK
bool
default y
config SOC_TWAI_BRP_MIN
int
default 2
config SOC_TWAI_BRP_MAX
int
default 16384
config SOC_TWAI_SUPPORTS_RX_STATUS
bool
default y
config SOC_UART_FIFO_LEN
int
default 128
config SOC_UART_BITRATE_MAX
int
default 5000000
config SOC_UART_NUM
int
default 3
config SOC_UART_SUPPORT_FSM_TX_WAIT_SEND
bool
default y

Wyświetl plik

@ -1,16 +1,8 @@
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
@ -19,7 +11,7 @@ extern "C" {
#endif
// ESP32-S3 has 1 GPIO peripheral
#define SOC_GPIO_PORT (1)
#define SOC_GPIO_PORT (1U)
#define SOC_GPIO_PIN_COUNT (49)
// On ESP32-S3, Digital IOs have their own registers to control pullup/down/capability, independent with RTC registers.

Wyświetl plik

@ -1,21 +1,12 @@
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#define SOC_RTCIO_PIN_COUNT 22
#define RTCIO_LL_PIN_FUNC 0
#define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1
#define SOC_RTCIO_HOLD_SUPPORTED 1
#define SOC_RTCIO_WAKE_SUPPORTED 1

Wyświetl plik

@ -1,37 +0,0 @@
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
// ESP32-S3 have 1 SIGMADELTA peripheral.
#define SIGMADELTA_PORT_0 (0) /*!< SIGMADELTA port 0 */
#define SIGMADELTA_PORT_MAX (1) /*!< SIGMADELTA port max */
#define SOC_SIGMADELTA_NUM (SIGMADELTA_PORT_MAX)
#define SIGMADELTA_CHANNEL_0 (0) /*!< Sigma-delta channel 0 */
#define SIGMADELTA_CHANNEL_1 (1) /*!< Sigma-delta channel 1 */
#define SIGMADELTA_CHANNEL_2 (2) /*!< Sigma-delta channel 2 */
#define SIGMADELTA_CHANNEL_3 (3) /*!< Sigma-delta channel 3 */
#define SIGMADELTA_CHANNEL_4 (4) /*!< Sigma-delta channel 4 */
#define SIGMADELTA_CHANNEL_5 (5) /*!< Sigma-delta channel 5 */
#define SIGMADELTA_CHANNEL_6 (6) /*!< Sigma-delta channel 6 */
#define SIGMADELTA_CHANNEL_7 (7) /*!< Sigma-delta channel 7 */
#define SIGMADELTA_CHANNEL_MAX (8)
#ifdef __cplusplus
}
#endif

Wyświetl plik

@ -9,6 +9,19 @@
// separate these information into periph_caps.h for each peripheral and
// include them here to avoid developing conflicts.
/*
* These defines are parsed and imported as kconfig variables via the script
* `tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py`
*
* If this file is changed the script will automatically run the script
* and generate the kconfig variables as part of the pre-commit hooks.
*
* It can also be ran manually with `./tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py 'components/soc/esp32s3/include/soc/'`
*
* For more information see `tools/gen_soc_caps_kconfig/README.md`
*
*/
#pragma once
/*-------------------------- COMMON CAPS ---------------------------------------*/
@ -196,7 +209,7 @@
#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;})
// Peripheral supports output given level during its "dummy phase"
#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT 1
#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT 1
#define SOC_MEMSPI_IS_INDEPENDENT 1
#define SOC_SPI_MAX_PRE_DIVIDER 16
#define SOC_SPI_SUPPORT_OCT 1
@ -261,7 +274,6 @@
#define SOC_SHA_SUPPORT_SHA224 (1)
#define SOC_SHA_SUPPORT_SHA256 (1)
#define SOC_SHA_SUPPORT_SHA384 (1)
#define SOC_SHA_SUPPORT_SHA256 (1)
#define SOC_SHA_SUPPORT_SHA512 (1)
#define SOC_SHA_SUPPORT_SHA512_224 (1)
#define SOC_SHA_SUPPORT_SHA512_256 (1)
@ -295,7 +307,7 @@
#define SOC_PM_SUPPORT_TOUCH_SENSOR_WAKEUP (1) /*!<Supports waking up from touch pad trigger */
#define SOC_PM_SUPPORT_DEEPSLEEP_VERIFY_STUB_ONLY (1)
#define SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY (1)
/*-------------------------- Flash Encryption CAPS----------------------------*/

Wyświetl plik

@ -1,17 +0,0 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#define SOC_USB_PERIPH_NUM 1

Wyświetl plik

@ -0,0 +1,504 @@
#####################################################
# This file is auto-generated from SoC caps
# using gen_soc_caps_kconfig.py, do not edit manually
#####################################################
config SOC_CPU_CORES_NUM
bool
default y
config SOC_GDMA_SUPPORTED
bool
default y
config SOC_BT_SUPPORTED
bool
default y
config SOC_DIG_SIGN_SUPPORTED
bool
default y
config SOC_HMAC_SUPPORTED
bool
default y
config SOC_ASYNC_MEMCPY_SUPPORTED
bool
default y
config SOC_SUPPORTS_SECURE_DL_MODE
bool
default y
config SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS
int
default 3
config SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS
bool
default y
config SOC_RTC_FAST_MEM_SUPPORTED
bool
default n
config SOC_RTC_SLOW_MEM_SUPPORTED
bool
default n
config SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY
bool
default n
config SOC_ICACHE_ACCESS_RODATA_SUPPORTED
bool
default y
config SOC_AES_SUPPORT_DMA
bool
default y
config SOC_AES_GDMA
bool
default y
config SOC_ADC_PERIPH_NUM
int
default 2
config SOC_ADC_PATT_LEN_MAX
int
default 16
config SOC_ADC_MAX_CHANNEL_NUM
int
default 5
config SOC_ADC_MAX_BITWIDTH
int
default 12
config SOC_ADC_CALIBRATION_V1_SUPPORTED
bool
default y
config SOC_ADC_DIGI_FILTER_NUM
int
default 2
config SOC_ADC_DIGI_MONITOR_NUM
int
default 2
config SOC_ADC_HW_CALIBRATION_V1
bool
default y
config SOC_ADC_SAMPLE_FREQ_THRES_HIGH
int
default 83333
config SOC_ADC_SAMPLE_FREQ_THRES_LOW
int
default 611
config SOC_APB_BACKUP_DMA
bool
default y
config SOC_BROWNOUT_RESET_SUPPORTED
bool
default y
config SOC_CPU_BREAKPOINTS_NUM
int
default 2
config SOC_CPU_WATCHPOINTS_NUM
int
default 2
config SOC_CPU_HAS_FLEXIBLE_INTC
bool
default y
config SOC_CPU_WATCHPOINT_SIZE
hex
default 0x80000000
config SOC_DS_SIGNATURE_MAX_BIT_LEN
int
default 3072
config SOC_DS_KEY_PARAM_MD_IV_LENGTH
int
default 16
config SOC_DS_KEY_CHECK_MAX_WAIT_US
int
default 1100
config SOC_GDMA_GROUPS
int
default 1
config SOC_GDMA_PAIRS_PER_GROUP
int
default 3
config SOC_GDMA_TX_RX_SHARE_INTERRUPT
bool
default y
config SOC_GPIO_PORT
int
default 1
config SOC_GPIO_PIN_COUNT
int
default 21
config SOC_GPIO_SUPPORTS_RTC_INDEPENDENT
bool
default y
config SOC_GPIO_SUPPORT_FORCE_HOLD
bool
default y
config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
bool
default y
config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
int
default 0
config SOC_GPIO_SUPPORT_SLP_SWITCH
bool
default y
config SOC_I2C_NUM
int
default 1
config SOC_I2C_FIFO_LEN
int
default 32
config SOC_I2C_SUPPORT_HW_FSM_RST
bool
default y
config SOC_I2C_SUPPORT_HW_CLR_BUS
bool
default y
config SOC_I2C_SUPPORT_XTAL
bool
default y
config SOC_I2C_SUPPORT_RTC
bool
default y
config SOC_LEDC_SUPPORT_XTAL_CLOCK
bool
default y
config SOC_LEDC_CHANNEL_NUM
int
default 6
config SOC_LEDC_TIMER_BIT_WIDE_NUM
int
default 14
config SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED
bool
default n
config SOC_MPU_MIN_REGION_SIZE
hex
default 0x20000000
config SOC_MPU_REGIONS_MAX_NUM
int
default 8
config SOC_MPU_REGION_RO_SUPPORTED
bool
default n
config SOC_MPU_REGION_WO_SUPPORTED
bool
default n
config SOC_RMT_GROUPS
int
default 1
config SOC_RMT_TX_CANDIDATES_PER_GROUP
int
default 2
config SOC_RMT_RX_CANDIDATES_PER_GROUP
int
default 2
config SOC_RMT_CHANNELS_PER_GROUP
int
default 4
config SOC_RMT_MEM_WORDS_PER_CHANNEL
int
default 48
config SOC_RMT_SUPPORT_RX_PINGPONG
bool
default y
config SOC_RMT_SUPPORT_RX_DEMODULATION
bool
default y
config SOC_RMT_SUPPORT_TX_LOOP_COUNT
bool
default y
config SOC_RMT_SUPPORT_TX_SYNCHRO
bool
default y
config SOC_RMT_SUPPORT_XTAL
bool
default y
config SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH
int
default 128
config SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM
int
default 108
config SOC_RSA_MAX_BIT_LEN
int
default 3072
config SOC_SHA_DMA_MAX_BUFFER_SIZE
int
default 3968
config SOC_SHA_SUPPORT_DMA
bool
default y
config SOC_SHA_SUPPORT_RESUME
bool
default y
config SOC_SHA_GDMA
bool
default y
config SOC_SHA_SUPPORT_SHA1
bool
default y
config SOC_SHA_SUPPORT_SHA224
bool
default y
config SOC_SHA_SUPPORT_SHA256
bool
default y
config SOC_SIGMADELTA_NUM
int
default 1
config SOC_SIGMADELTA_CHANNEL_NUM
int
default 4
config SOC_SPI_PERIPH_NUM
int
default 2
config SOC_SPI_MAXIMUM_BUFFER_SIZE
int
default 64
config SOC_SPI_SUPPORT_DDRCLK
bool
default y
config SOC_SPI_SLAVE_SUPPORT_SEG_TRANS
bool
default y
config SOC_SPI_SUPPORT_CD_SIG
bool
default y
config SOC_SPI_SUPPORT_CONTINUOUS_TRANS
bool
default y
config SOC_SPI_SUPPORT_SLAVE_HD_VER2
bool
default y
config SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT
bool
default y
config SOC_MEMSPI_IS_INDEPENDENT
bool
default y
config SOC_SPI_MAX_PRE_DIVIDER
int
default 16
config SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE
bool
default y
config SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND
bool
default y
config SOC_SPI_MEM_SUPPORT_AUTO_RESUME
bool
default y
config SOC_SPI_MEM_SUPPORT_IDLE_INTR
bool
default y
config SOC_SPI_MEM_SUPPORT_SW_SUSPEND
bool
default y
config SOC_SPI_MEM_SUPPORT_CHECK_SUS
bool
default y
config SOC_SYSTIMER_COUNTER_NUM
int
default 2
config SOC_SYSTIMER_ALARM_NUM
int
default 3
config SOC_SYSTIMER_BIT_WIDTH_LO
int
default 32
config SOC_SYSTIMER_BIT_WIDTH_HI
int
default 20
config SOC_SYSTIMER_FIXED_TICKS_US
int
default 16
config SOC_SYSTIMER_INT_LEVEL
bool
default y
config SOC_SYSTIMER_ALARM_MISS_COMPENSATE
bool
default y
config SOC_TIMER_GROUPS
int
default 1
config SOC_TIMER_GROUP_TIMERS_PER_GROUP
int
default 1
config SOC_TIMER_GROUP_COUNTER_BIT_WIDTH
int
default 54
config SOC_TIMER_GROUP_SUPPORT_XTAL
bool
default y
config SOC_TOUCH_SENSOR_NUM
int
default 0
config SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX
int
default 32
config SOC_UART_NUM
int
default 2
config SOC_UART_FIFO_LEN
int
default 128
config SOC_UART_BITRATE_MAX
int
default 5000000
config SOC_UART_SUPPORT_RTC_CLK
bool
default y
config SOC_UART_SUPPORT_XTAL_CLK
bool
default y
config SOC_UART_SUPPORT_FSM_TX_WAIT_SEND
bool
default y
config SOC_WIFI_HW_TSF
bool
default y
config SOC_COEX_HW_PTI
bool
default y
config SOC_PHY_DIG_REGS_MEM_SIZE
int
default 21
config SOC_MAC_BB_PD_MEM_SIZE
int
default 192
config SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH
int
default 12
config SOC_PM_SUPPORT_WIFI_WAKEUP
bool
default y
config SOC_PM_SUPPORT_BT_WAKEUP
bool
default y
config SOC_PM_SUPPORT_CPU_PD
bool
default y
config SOC_PM_SUPPORT_WIFI_PD
bool
default y
config SOC_PM_SUPPORT_BT_PD
bool
default y

Wyświetl plik

@ -67,23 +67,24 @@
/** Initialization vector (IV) length for the RSA key parameter message digest (MD) in bytes. */
#define SOC_DS_KEY_PARAM_MD_IV_LENGTH (16)
/** Maximum wait time for DS parameter decryption key. If overdue, then key error.
See TRM DS chapter for more details */
#define SOC_DS_KEY_CHECK_MAX_WAIT_US (1100)
/*-------------------------- GDMA CAPS -------------------------------------*/
#define SOC_GDMA_GROUPS (1) // Number of GDMA groups
#define SOC_GDMA_PAIRS_PER_GROUP (3) // Number of GDMA pairs in each group
#define SOC_GDMA_TX_RX_SHARE_INTERRUPT (1) // TX and RX channel in the same pair will share the same interrupt source number
#define SOC_GDMA_GROUPS (1U) // Number of GDMA groups
#define SOC_GDMA_PAIRS_PER_GROUP (3) // Number of GDMA pairs in each group
#define SOC_GDMA_TX_RX_SHARE_INTERRUPT (1) // TX and RX channel in the same pair will share the same interrupt source number
/*-------------------------- GPIO CAPS ---------------------------------------*/
// ESP8684 has 1 GPIO peripheral
#define SOC_GPIO_PORT (1)
#define SOC_GPIO_PORT (1U)
#define SOC_GPIO_PIN_COUNT (21)
// Target has no full RTC IO subsystem, so GPIO is 100% "independent" of RTC
// On ESP8684, Digital IOs have their own registers to control pullup/down capability, independent of RTC registers.
#define GPIO_SUPPORTS_RTC_INDEPENDENT (1)
#define SOC_GPIO_SUPPORTS_RTC_INDEPENDENT (1)
// Force hold is a new function of ESP8684
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
// GPIO0~5 on ESP8684 can support chip deep sleep wakeup
@ -92,14 +93,14 @@
// GPIO19 on ESP8684 is invalid.
#define SOC_GPIO_VALID_GPIO_MASK (((1U<<SOC_GPIO_PIN_COUNT) - 1) & (~(BIT19)))
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
#define SOC_GPIO_DEEP_SLEEP_WAKEUP_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5)
#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5)
// Support to configure sleep status
#define SOC_GPIO_SUPPORT_SLP_SWITCH (1)
/*-------------------------- I2C CAPS ----------------------------------------*/
// TODO IDF-3918
#define SOC_I2C_NUM (1)
#define SOC_I2C_NUM (1U)
#define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */
@ -125,7 +126,7 @@
#define SOC_MPU_REGION_WO_SUPPORTED 0
/*--------------------------- RMT CAPS ---------------------------------------*/
#define SOC_RMT_GROUPS (1) /*!< One RMT group */
#define SOC_RMT_GROUPS (1U) /*!< One RMT group */
#define SOC_RMT_TX_CANDIDATES_PER_GROUP (2) /*!< Number of channels that capable of Transmit */
#define SOC_RMT_RX_CANDIDATES_PER_GROUP (2) /*!< Number of channels that capable of Receive */
#define SOC_RMT_CHANNELS_PER_GROUP (4) /*!< Total 4 channels */
@ -144,11 +145,6 @@
#define SOC_RTC_CNTL_CPU_PD_RETENTION_MEM_SIZE (SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM * (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3))
/*-------------------------- RTCIO CAPS --------------------------------------*/
/* No dedicated RTCIO subsystem on ESP8684. RTC functions are still supported
* for hold, wake & 32kHz crystal functions - via rtc_cntl_reg */
#define SOC_RTCIO_PIN_COUNT 0
/*--------------------------- RSA CAPS ---------------------------------------*/
#define SOC_RSA_MAX_BIT_LEN (3072)
@ -173,8 +169,8 @@
#define SOC_SHA_SUPPORT_SHA256 (1)
/*-------------------------- SIGMA DELTA CAPS --------------------------------*/
#define SOC_SIGMADELTA_NUM (1) // 1 sigma-delta peripheral
#define SOC_SIGMADELTA_CHANNEL_NUM (4) // 4 channels
#define SOC_SIGMADELTA_NUM (1U) // 1 sigma-delta peripheral
#define SOC_SIGMADELTA_CHANNEL_NUM (4) // 4 channels
/*-------------------------- SPI CAPS ----------------------------------------*/
#define SOC_SPI_PERIPH_NUM 2
@ -193,7 +189,7 @@
#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;})
// Peripheral supports output given level during its "dummy phase"
#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT 1
#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT 1
#define SOC_MEMSPI_IS_INDEPENDENT 1
#define SOC_SPI_MAX_PRE_DIVIDER 16
@ -217,14 +213,14 @@
#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE (1) // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
#define SOC_TIMER_GROUPS (1)
#define SOC_TIMER_GROUP_TIMERS_PER_GROUP (1)
#define SOC_TIMER_GROUPS (1U)
#define SOC_TIMER_GROUP_TIMERS_PER_GROUP (1U)
#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54)
#define SOC_TIMER_GROUP_SUPPORT_XTAL (1)
#define SOC_TIMER_GROUP_TOTAL_TIMERS (SOC_TIMER_GROUPS * SOC_TIMER_GROUP_TIMERS_PER_GROUP)
/*-------------------------- TOUCH SENSOR CAPS -------------------------------*/
#define SOC_TOUCH_SENSOR_NUM (0) /*! No touch sensors on ESP8684 */
#define SOC_TOUCH_SENSOR_NUM (0U) /*! No touch sensors on ESP8684 */
/*-------------------------- TWAI CAPS ---------------------------------------*/
// TODO IDF-3897

Wyświetl plik

@ -0,0 +1,4 @@
#####################################################
# This file is auto-generated from SoC caps
# using gen_soc_caps_kconfig.py, do not edit manually
#####################################################

Wyświetl plik

@ -1937,11 +1937,9 @@ components/soc/esp32h2/include/soc/reset_reasons.h
components/soc/esp32h2/include/soc/rtc_caps.h
components/soc/esp32h2/include/soc/rtc_i2c_reg.h
components/soc/esp32h2/include/soc/rtc_i2c_struct.h
components/soc/esp32h2/include/soc/rtc_io_caps.h
components/soc/esp32h2/include/soc/sensitive_struct.h
components/soc/esp32h2/include/soc/soc_caps.h
components/soc/esp32h2/include/soc/soc_pins.h
components/soc/esp32h2/include/soc/spi_caps.h
components/soc/esp32h2/include/soc/spi_mem_reg.h
components/soc/esp32h2/include/soc/spi_mem_struct.h
components/soc/esp32h2/include/soc/spi_pins.h
@ -2091,7 +2089,6 @@ components/soc/esp32s3/include/soc/efuse_struct.h
components/soc/esp32s3/include/soc/extmem_reg.h
components/soc/esp32s3/include/soc/extmem_struct.h
components/soc/esp32s3/include/soc/fe_reg.h
components/soc/esp32s3/include/soc/gpio_caps.h
components/soc/esp32s3/include/soc/gpio_pins.h
components/soc/esp32s3/include/soc/gpio_reg.h
components/soc/esp32s3/include/soc/gpio_sd_reg.h
@ -2131,7 +2128,6 @@ components/soc/esp32s3/include/soc/rmt_struct.h
components/soc/esp32s3/include/soc/rtc_gpio_channel.h
components/soc/esp32s3/include/soc/rtc_i2c_reg.h
components/soc/esp32s3/include/soc/rtc_i2c_struct.h
components/soc/esp32s3/include/soc/rtc_io_caps.h
components/soc/esp32s3/include/soc/rtc_io_channel.h
components/soc/esp32s3/include/soc/rtc_io_reg.h
components/soc/esp32s3/include/soc/rtc_io_struct.h
@ -2142,7 +2138,6 @@ components/soc/esp32s3/include/soc/sdmmc_struct.h
components/soc/esp32s3/include/soc/sens_reg.h
components/soc/esp32s3/include/soc/sensitive_reg.h
components/soc/esp32s3/include/soc/sensitive_struct.h
components/soc/esp32s3/include/soc/sigmadelta_caps.h
components/soc/esp32s3/include/soc/soc.h
components/soc/esp32s3/include/soc/soc_ulp.h
components/soc/esp32s3/include/soc/spi_mem_reg.h
@ -2167,7 +2162,6 @@ components/soc/esp32s3/include/soc/uart_reg.h
components/soc/esp32s3/include/soc/uart_struct.h
components/soc/esp32s3/include/soc/uhci_reg.h
components/soc/esp32s3/include/soc/uhci_struct.h
components/soc/esp32s3/include/soc/usb_caps.h
components/soc/esp32s3/include/soc/usb_device_reg.h
components/soc/esp32s3/include/soc/usb_pins.h
components/soc/esp32s3/include/soc/usb_reg.h

Wyświetl plik

@ -78,6 +78,8 @@ tools/esp_app_trace/test/sysview/test.sh
tools/find_apps.py
tools/format.sh
tools/gen_esp_err_to_name.py
tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py
tools/gen_soc_caps_kconfig/test/test_gen_soc_caps_kconfig.py
tools/idf.py
tools/idf_monitor.py
tools/idf_size.py

Wyświetl plik

@ -214,6 +214,7 @@ tools/esp_prov/utils/convenience.py
tools/find_apps.py
tools/find_build_apps/common.py
tools/gen_esp_err_to_name.py
tools/gen_soc_caps_kconfig/test/test_gen_soc_caps_kconfig.py
tools/idf.py
tools/idf_py_actions/core_ext.py
tools/idf_py_actions/create_ext.py

Wyświetl plik

@ -0,0 +1,21 @@
# Generate kconfig variables from SoC caps headers
`gen_soc_caps_config.py` is used to turn defines from `soc_caps.h` into kconfig variables that can be included and used both in menuconfig and during the build process
The script will automatically run as part of the pre-commit hook if any of the `soc_caps` related files have been modified.
To run it manually from IDF_PATH run:
`python tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py 'components/soc/*/include/soc/'`
The results are `kconfig.soc_caps.in`-files containing the bool/int/hex/string values defined in the `soc_caps.h` file.
This target specific kconfig file is then imported in `$IDF_PATH/Kconfig`.
# Tips
Defines that are 0 or 1 will automatically be interpreted as Booleans. If it's necessary to have this variable available as an integer instead then this can be achieved by adding an `U` suffix when defining it. E.g:
`#define SOC_I2C_NUM (1U)`
The script is not able to evaluate expressions, e.g X*Y. If you need a variable to be available in kconfig it needs to be a simple assignment expression.

Wyświetl plik

@ -0,0 +1,206 @@
#!/usr/bin/env python
#
# SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
# SPDX-License-Identifier: Apache-2.0
"""
Generate Kconfig.soc_caps.in with defines from soc_caps.h
"""
import argparse
import inspect
import io
import logging
import sys
from difflib import unified_diff
from os import path
from pathlib import Path
from string import Template
import pyparsing
from pyparsing import (CaselessLiteral, Char, Combine, Group, Literal, OneOrMore, # pylint: disable=unused-import
Optional, ParserElement, QuotedString, Word, alphas, hexnums, nums)
pyparsing.usePackrat = True
try:
import typing # noqa: F401 # pylint: disable=unused-import
except ImportError:
pass
class KconfigWriter():
PREAMBLE = inspect.cleandoc('''
#####################################################
# This file is auto-generated from SoC caps
# using gen_soc_caps_kconfig.py, do not edit manually
#####################################################
''')
KCONFIG_ENTRY_TEMPLATE = Template(
inspect.cleandoc('''
config $name
$entry_type
default $value
'''))
def __init__(self): # type: () -> None
self.entries = set('')
self.kconfig_text = io.StringIO('')
self.kconfig_text.write(self.PREAMBLE)
def add_entry(self, name, entry_type, value): # type: (str, str, typing.Any) -> None
if name in self.entries:
logging.info('Duplicate entry: {}'.format(name))
return
self.entries.add(name)
self.kconfig_text.write('\n\n')
# Format values for kconfig
if entry_type == 'bool':
value = 'y' if value else 'n'
elif entry_type == 'string':
value = '"' + value + '"'
entry = self.KCONFIG_ENTRY_TEMPLATE.substitute(name=name, entry_type=entry_type, value=value)
self.kconfig_text.write(entry)
def update_file(self, kconfig_path, always_write): # type: (Path, bool) -> bool
try:
with open(kconfig_path, 'r') as f:
old_content = f.readlines()
except FileNotFoundError:
old_content = ['']
self.kconfig_text.seek(0)
new_content = self.kconfig_text.readlines()
new_content[-1] += '\n' # Add final newline to end of file
file_needs_update = always_write
# Check if file was updated and print diff for users
diff = unified_diff(old_content, new_content, fromfile=str(kconfig_path), n=2)
for line in diff:
print(line, end='')
file_needs_update = True
if file_needs_update:
print('\n' + 'Updating file: {}'.format(kconfig_path))
with open(kconfig_path, 'w') as f:
f.writelines(new_content)
return file_needs_update
def parse_define(define_line): # type: (str) -> typing.Any[typing.Type[ParserElement]]
# Group for parsing literal suffix of a numbers, e.g. 100UL
literal_symbol = Group(CaselessLiteral('L') | CaselessLiteral('U'))
literal_suffix = OneOrMore(literal_symbol)
# Define name
name = Word(alphas, alphas + nums + '_')
# Define value, either a hex, int or a string
hex_value = Combine(Literal('0x') + Word(hexnums) + Optional(literal_suffix).suppress())('hex_value')
int_value = Word(nums)('int_value') + ~Char('.') + Optional(literal_suffix)('literal_suffix')
str_value = QuotedString('"')('str_value')
# Remove optional parenthesis around values
value = Optional('(').suppress() + (hex_value ^ int_value ^ str_value)('value') + Optional(')').suppress()
expr = '#define' + Optional(name)('name') + Optional(value)
res = expr.parseString(define_line)
return res
def generate_defines(soc_caps_dir, filename, always_write): # type: (Path, str, bool) -> bool
soc_headers = list(soc_caps_dir.glob(filename))
if soc_headers == []:
return False
# Sort header files to make the generated files deterministic
soc_headers.sort(key=lambda file: file.name)
defines = []
for soc_header in soc_headers:
defines.extend(get_defines(soc_header))
writer = KconfigWriter()
for line in defines:
try:
res = parse_define(line)
except pyparsing.ParseException:
logging.debug('Failed to parse: {}'.format(line))
continue
# Add the kconfig entry corresponding to the type we parsed
if 'str_value' in res:
writer.add_entry(res.name, 'string', res.str_value)
elif 'int_value' in res:
# defines with an integer value of 0 or 1 are
# added as bool entries as long they have no literal suffix
if 'literal_suffix' not in res and res.int_value == '0':
writer.add_entry(res.name, 'bool', False)
elif 'literal_suffix' not in res and res.int_value == '1':
writer.add_entry(res.name, 'bool', True)
else:
writer.add_entry(res.name, 'int', res.int_value)
elif 'hex_value' in res:
writer.add_entry(res.name, 'hex', res.hex_value)
# Updates output if necessary
updated = writer.update_file(Path(soc_caps_dir) / 'Kconfig.soc_caps.in', always_write)
return updated
def get_defines(header_path): # type: (Path) -> list[str]
defines = []
logging.info('Reading macros from {}...'.format(header_path))
with open(header_path, 'r') as f:
output = f.read()
for line in output.split('\n'):
line = line.strip()
if len(line):
defines.append(line)
return defines
if __name__ == '__main__':
parser = argparse.ArgumentParser(description=__doc__)
parser.add_argument('-d', '--dir', help='SoC caps folder paths, support wildcards', nargs='+', default=[])
parser.add_argument('-n', '--filename', nargs='?', default='*caps.h',
help='SoC caps filename, support wildcards')
parser.add_argument('-v', '--verbose', action='count', help='Increase the logging level of the script. Can be specified multiple times.')
parser.add_argument('--always-write', help='Always generate new output files', action='store_true')
args = parser.parse_args()
if not args.verbose:
log_level = logging.WARNING
elif args.verbose == 1:
log_level = logging.INFO
else:
log_level = logging.DEBUG
logging.basicConfig(level=log_level)
files_updated = []
for caps_dir in args.dir:
soc_caps_dirs = Path().glob(caps_dir)
files_updated += [generate_defines(d, args.filename, args.always_write) for d in soc_caps_dirs if path.isdir(d)]
print('Updated {} files'.format(sum(files_updated)))
sys.exit(all(files_updated))

Wyświetl plik

@ -0,0 +1,54 @@
#!/usr/bin/env python
# SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
# SPDX-License-Identifier: Apache-2.0
import sys
import unittest
try:
import gen_soc_caps_kconfig
except ImportError:
sys.path.append('..')
import gen_soc_caps_kconfig
class ParserTests(unittest.TestCase):
def test_parse_name(self):
res = gen_soc_caps_kconfig.parse_define('#define TEST_NAME (2)')
self.assertEqual(res.name, 'TEST_NAME')
def test_parse_int(self):
res = gen_soc_caps_kconfig.parse_define('#define TEST_INT (2)')
self.assertEqual(res.int_value, '2')
def test_parse_string(self):
res = gen_soc_caps_kconfig.parse_define('#define TEST_STRING "this is a test string"')
self.assertEqual(res.str_value, 'this is a test string')
def test_parse_hex(self):
res = gen_soc_caps_kconfig.parse_define('#define TEST_HEX 0xDEADBEEF')
self.assertEqual(res.hex_value, '0xDEADBEEF')
res = gen_soc_caps_kconfig.parse_define('#define TEST_HEX 0x0000000')
self.assertEqual(res.hex_value, '0x0000000')
def test_parse_literal_suffix(self):
res = gen_soc_caps_kconfig.parse_define('#define TEST (0x200UL)')
self.assertEqual(res.hex_value, '0x200')
res = gen_soc_caps_kconfig.parse_define('#define TEST_U 20000u')
self.assertEqual(res.int_value, '20000')
res = gen_soc_caps_kconfig.parse_define('#define TEST_U 329000LL')
self.assertEqual(res.int_value, '329000')
def test_parse_float(self):
# Kconfig doesnt support floats, should not be parsed as anything
res = gen_soc_caps_kconfig.parse_define('#define TEST_FLOAT (3.14)')
self.assertEqual(res.value, '')
if __name__ == '__main__':
print('Running gen_soc_caps_config tests...')
unittest.main()