From c50cbfe2ed7f8b4acf7c95816c32a84a08638281 Mon Sep 17 00:00:00 2001 From: wanlei Date: Fri, 8 Mar 2024 14:31:19 +0800 Subject: [PATCH] feat(esp32c61): new chip add rom and efuse support --- components/efuse/esp32c61/esp_efuse_fields.c | 53 + .../efuse/esp32c61/esp_efuse_rtc_calib.c | 138 ++ components/efuse/esp32c61/esp_efuse_table.c | 1528 +++++++++++++++++ components/efuse/esp32c61/esp_efuse_table.csv | 201 +++ components/efuse/esp32c61/esp_efuse_utility.c | 203 +++ .../efuse/esp32c61/include/esp_efuse_chip.h | 79 + .../esp32c61/include/esp_efuse_rtc_calib.h | 76 + .../efuse/esp32c61/include/esp_efuse_table.h | 237 +++ .../private_include/esp_efuse_utility.h | 21 + components/efuse/esp32c61/sources.cmake | 4 + components/esp_rom/esp32c61/.gitkeep | 0 .../esp_rom/esp32c61/Kconfig.soc_caps.in | 92 + components/esp_rom/esp32c61/esp_rom_caps.h | 32 + .../esp_rom/esp32c61/ld/esp32c61.rom.api.ld | 65 + .../esp32c61/ld/esp32c61.rom.coexist.ld | 47 + .../esp_rom/esp32c61/ld/esp32c61.rom.heap.ld | 80 + .../esp_rom/esp32c61/ld/esp32c61.rom.ld | 376 ++++ .../esp32c61/ld/esp32c61.rom.libgcc.ld | 119 ++ .../esp32c61/ld/esp32c61.rom.net80211.ld | 65 + .../esp32c61/ld/esp32c61.rom.newlib-nano.ld | 32 + .../esp32c61/ld/esp32c61.rom.newlib.ld | 99 ++ .../esp_rom/esp32c61/ld/esp32c61.rom.phy.ld | 196 +++ .../esp_rom/esp32c61/ld/esp32c61.rom.pp.ld | 263 +++ .../esp_rom/esp32c61/ld/esp32c61.rom.rvfp.ld | 62 + .../esp32c61/ld/esp32c61.rom.spiflash.ld | 165 ++ .../esp32c61/ld/esp32c61.rom.systimer.ld | 26 + .../esp32c61/ld/esp32c61.rom.version.ld | 13 + .../esp_rom/esp32c61/ld/esp32c61.rom.wdt.ld | 22 + components/esp_rom/include/esp32c61/.gitkeep | 0 .../esp_rom/include/esp32c61/rom/bigint.h | 35 + .../esp_rom/include/esp32c61/rom/cache.h | 626 +++++++ components/esp_rom/include/esp32c61/rom/crc.h | 119 ++ .../esp_rom/include/esp32c61/rom/ecdsa.h | 26 + .../esp_rom/include/esp32c61/rom/efuse.h | 283 +++ .../esp_rom/include/esp32c61/rom/esp_flash.h | 46 + .../esp_rom/include/esp32c61/rom/ets_sys.h | 432 +++++ .../esp_rom/include/esp32c61/rom/gpio.h | 208 +++ .../esp_rom/include/esp32c61/rom/libc_stubs.h | 83 + .../esp_rom/include/esp32c61/rom/lldesc.h | 139 ++ .../esp_rom/include/esp32c61/rom/md5_hash.h | 41 + .../esp_rom/include/esp32c61/rom/miniz.h | 8 + .../esp_rom/include/esp32c61/rom/opi_flash.h | 321 ++++ .../esp_rom/include/esp32c61/rom/rom_layout.h | 102 ++ components/esp_rom/include/esp32c61/rom/rtc.h | 255 +++ .../include/esp32c61/rom/secure_boot.h | 132 ++ components/esp_rom/include/esp32c61/rom/sha.h | 53 + .../esp_rom/include/esp32c61/rom/spi_flash.h | 458 +++++ .../esp_rom/include/esp32c61/rom/tjpgd.h | 104 ++ .../esp_rom/include/esp32c61/rom/uart.h | 353 ++++ tools/ci/check_public_headers_exceptions.txt | 1 + 50 files changed, 8119 insertions(+) create mode 100644 components/efuse/esp32c61/esp_efuse_fields.c create mode 100644 components/efuse/esp32c61/esp_efuse_rtc_calib.c create mode 100644 components/efuse/esp32c61/esp_efuse_table.c create mode 100644 components/efuse/esp32c61/esp_efuse_table.csv create mode 100644 components/efuse/esp32c61/esp_efuse_utility.c create mode 100644 components/efuse/esp32c61/include/esp_efuse_chip.h create mode 100644 components/efuse/esp32c61/include/esp_efuse_rtc_calib.h create mode 100644 components/efuse/esp32c61/include/esp_efuse_table.h create mode 100644 components/efuse/esp32c61/private_include/esp_efuse_utility.h create mode 100644 components/efuse/esp32c61/sources.cmake delete mode 100644 components/esp_rom/esp32c61/.gitkeep create mode 100644 components/esp_rom/esp32c61/Kconfig.soc_caps.in create mode 100644 components/esp_rom/esp32c61/esp_rom_caps.h create mode 100644 components/esp_rom/esp32c61/ld/esp32c61.rom.api.ld create mode 100644 components/esp_rom/esp32c61/ld/esp32c61.rom.coexist.ld create mode 100644 components/esp_rom/esp32c61/ld/esp32c61.rom.heap.ld create mode 100644 components/esp_rom/esp32c61/ld/esp32c61.rom.ld create mode 100644 components/esp_rom/esp32c61/ld/esp32c61.rom.libgcc.ld create mode 100644 components/esp_rom/esp32c61/ld/esp32c61.rom.net80211.ld create mode 100644 components/esp_rom/esp32c61/ld/esp32c61.rom.newlib-nano.ld create mode 100644 components/esp_rom/esp32c61/ld/esp32c61.rom.newlib.ld create mode 100644 components/esp_rom/esp32c61/ld/esp32c61.rom.phy.ld create mode 100644 components/esp_rom/esp32c61/ld/esp32c61.rom.pp.ld create mode 100644 components/esp_rom/esp32c61/ld/esp32c61.rom.rvfp.ld create mode 100644 components/esp_rom/esp32c61/ld/esp32c61.rom.spiflash.ld create mode 100644 components/esp_rom/esp32c61/ld/esp32c61.rom.systimer.ld create mode 100644 components/esp_rom/esp32c61/ld/esp32c61.rom.version.ld create mode 100644 components/esp_rom/esp32c61/ld/esp32c61.rom.wdt.ld delete mode 100644 components/esp_rom/include/esp32c61/.gitkeep create mode 100644 components/esp_rom/include/esp32c61/rom/bigint.h create mode 100644 components/esp_rom/include/esp32c61/rom/cache.h create mode 100644 components/esp_rom/include/esp32c61/rom/crc.h create mode 100644 components/esp_rom/include/esp32c61/rom/ecdsa.h create mode 100644 components/esp_rom/include/esp32c61/rom/efuse.h create mode 100644 components/esp_rom/include/esp32c61/rom/esp_flash.h create mode 100644 components/esp_rom/include/esp32c61/rom/ets_sys.h create mode 100644 components/esp_rom/include/esp32c61/rom/gpio.h create mode 100644 components/esp_rom/include/esp32c61/rom/libc_stubs.h create mode 100644 components/esp_rom/include/esp32c61/rom/lldesc.h create mode 100644 components/esp_rom/include/esp32c61/rom/md5_hash.h create mode 100644 components/esp_rom/include/esp32c61/rom/miniz.h create mode 100644 components/esp_rom/include/esp32c61/rom/opi_flash.h create mode 100644 components/esp_rom/include/esp32c61/rom/rom_layout.h create mode 100644 components/esp_rom/include/esp32c61/rom/rtc.h create mode 100644 components/esp_rom/include/esp32c61/rom/secure_boot.h create mode 100644 components/esp_rom/include/esp32c61/rom/sha.h create mode 100644 components/esp_rom/include/esp32c61/rom/spi_flash.h create mode 100644 components/esp_rom/include/esp32c61/rom/tjpgd.h create mode 100644 components/esp_rom/include/esp32c61/rom/uart.h diff --git a/components/efuse/esp32c61/esp_efuse_fields.c b/components/efuse/esp32c61/esp_efuse_fields.c new file mode 100644 index 0000000000..223fab34e3 --- /dev/null +++ b/components/efuse/esp32c61/esp_efuse_fields.c @@ -0,0 +1,53 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "esp_efuse.h" +#include "esp_efuse_utility.h" +#include "esp_efuse_table.h" +#include "stdlib.h" +#include "esp_types.h" +#include "assert.h" +#include "esp_err.h" +#include "esp_log.h" +#include "soc/efuse_periph.h" +#include "sys/param.h" + +static __attribute__((unused)) const char *TAG = "efuse"; + +// Contains functions that provide access to efuse fields which are often used in IDF. + +// Returns chip package from efuse +uint32_t esp_efuse_get_pkg_ver(void) +{ + uint32_t pkg_ver = 0; + esp_efuse_read_field_blob(ESP_EFUSE_PKG_VERSION, &pkg_ver, ESP_EFUSE_PKG_VERSION[0]->bit_count); + return pkg_ver; +} + + +esp_err_t esp_efuse_set_rom_log_scheme(esp_efuse_rom_log_scheme_t log_scheme) +{ + int cur_log_scheme = 0; + esp_efuse_read_field_blob(ESP_EFUSE_UART_PRINT_CONTROL, &cur_log_scheme, 2); + if (!cur_log_scheme) { // not burned yet + return esp_efuse_write_field_blob(ESP_EFUSE_UART_PRINT_CONTROL, &log_scheme, 2); + } else { + return ESP_ERR_INVALID_STATE; + } +} + +esp_err_t esp_efuse_disable_rom_download_mode(void) +{ + return esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MODE); +} + +esp_err_t esp_efuse_enable_rom_secure_download_mode(void) +{ + if (esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MODE)) { + return ESP_ERR_INVALID_STATE; + } + return esp_efuse_write_field_bit(ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD); +} diff --git a/components/efuse/esp32c61/esp_efuse_rtc_calib.c b/components/efuse/esp32c61/esp_efuse_rtc_calib.c new file mode 100644 index 0000000000..3980b3c9b3 --- /dev/null +++ b/components/efuse/esp32c61/esp_efuse_rtc_calib.c @@ -0,0 +1,138 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "esp_efuse.h" +#include "esp_efuse_table.h" +#include "esp_efuse_rtc_calib.h" +#include "hal/efuse_hal.h" + +/** + * @brief Get the signed value by the raw data that read from eFuse + * @param data The raw data that read from eFuse + * @param sign_bit The index of the sign bit, start from 0 + */ +#define RTC_CALIB_GET_SIGNED_VAL(data, sign_bit) ((data & BIT##sign_bit) ? -(int)(data & ~BIT##sign_bit) : (int)data) + +int esp_efuse_rtc_calib_get_ver(void) +{ + uint32_t cali_version = 0; + uint32_t blk_ver = efuse_hal_blk_version(); + if (blk_ver == 1) { + cali_version = ESP_EFUSE_ADC_CALIB_VER1; + } else if (blk_ver >= 2) { + cali_version = ESP_EFUSE_ADC_CALIB_VER2; + } else { + ESP_LOGW("eFuse", "calibration efuse version does not match, set default version to 0"); + } + + return cali_version; +} + +uint32_t esp_efuse_rtc_calib_get_init_code(int version, uint32_t adc_unit, int atten) +{ + /* Version validation should be guaranteed in the caller */ + assert(atten >=0 && atten < 4); + (void) adc_unit; + + const esp_efuse_desc_t** init_code_efuse; + if (atten == 0) { + init_code_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN0; + } else if (atten == 1) { + init_code_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN1; + } else if (atten == 2) { + init_code_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN2; + } else { + init_code_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN3; + } + + int init_code_size = esp_efuse_get_field_size(init_code_efuse); + assert(init_code_size == 10); + + uint32_t init_code = 0; + ESP_ERROR_CHECK(esp_efuse_read_field_blob(init_code_efuse, &init_code, init_code_size)); + return init_code + 1600; // version 1 logic +} + +int esp_efuse_rtc_calib_get_chan_compens(int version, uint32_t adc_unit, uint32_t adc_channel, int atten) +{ + /* Version validation should be guaranteed in the caller */ + assert(atten < 4); + assert(adc_channel < SOC_ADC_CHANNEL_NUM(adc_unit)); + + const esp_efuse_desc_t** chan_diff_efuse = NULL; + switch (adc_channel) { + case 0: + chan_diff_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH0; + break; + case 1: + chan_diff_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH1; + break; + case 2: + chan_diff_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH2; + break; + case 3: + chan_diff_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH3; + break; + case 4: + chan_diff_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH4; + break; + case 5: + chan_diff_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH5; + break; + default: + chan_diff_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH6; + break; + } + + int chan_diff_size = esp_efuse_get_field_size(chan_diff_efuse); + assert(chan_diff_size == 4); + uint32_t chan_diff = 0; + ESP_ERROR_CHECK(esp_efuse_read_field_blob(chan_diff_efuse, &chan_diff, chan_diff_size)); + return RTC_CALIB_GET_SIGNED_VAL(chan_diff, 3) * (4 - atten); +} + +esp_err_t esp_efuse_rtc_calib_get_cal_voltage(int version, uint32_t adc_unit, int atten, uint32_t* out_digi, uint32_t* out_vol_mv) +{ + (void) adc_unit; + const esp_efuse_desc_t** cal_vol_efuse[4] = { + ESP_EFUSE_ADC1_CAL_VOL_ATTEN0, + ESP_EFUSE_ADC1_CAL_VOL_ATTEN1, + ESP_EFUSE_ADC1_CAL_VOL_ATTEN2, + ESP_EFUSE_ADC1_CAL_VOL_ATTEN3, + }; + const uint32_t input_vout_mv[2][4] = { + {400, 550, 750, 1370}, // Calibration V1 coefficients + {750, 1000, 1500, 2800}, // Calibration V2 coefficients + }; + + if ((version < ESP_EFUSE_ADC_CALIB_VER_MIN) || + (version > ESP_EFUSE_ADC_CALIB_VER_MAX)) { + return ESP_ERR_INVALID_ARG; + } + if (atten >= 4 || atten < 0) { + return ESP_ERR_INVALID_ARG; + } + + assert(cal_vol_efuse[atten][0]->bit_count == 10); + + uint32_t cal_vol = 0; + esp_err_t ret = esp_efuse_read_field_blob(cal_vol_efuse[atten], &cal_vol, cal_vol_efuse[atten][0]->bit_count); + if (ret != ESP_OK) { + return ret; + } + uint32_t chk_offset = (version == ESP_EFUSE_ADC_CALIB_VER1) ? 1500 : (atten == 2) ? 2900 : 2850; + *out_digi = chk_offset + RTC_CALIB_GET_SIGNED_VAL(cal_vol, 9); + *out_vol_mv = input_vout_mv[VER2IDX(version)][atten]; + return ESP_OK; +} + +esp_err_t esp_efuse_rtc_calib_get_tsens_val(float* tsens_cal) +{ + // Currently calibration is not supported on ESP32-C6, IDF-5236 + *tsens_cal = 0; + return ESP_OK; +} diff --git a/components/efuse/esp32c61/esp_efuse_table.c b/components/efuse/esp32c61/esp_efuse_table.c new file mode 100644 index 0000000000..a0f5eb430d --- /dev/null +++ b/components/efuse/esp32c61/esp_efuse_table.c @@ -0,0 +1,1528 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "sdkconfig.h" +#include "esp_efuse.h" +#include +#include "esp_efuse_table.h" + +// TODO: [ESP32C61] IDF-9282, file inherit from verify code, pls check + +// md5_digest_table 873c3e466a4c31bca2e00afae2073f94 +// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. +// If you want to change some fields, you need to change esp_efuse_table.csv file +// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. +// To show efuse_table run the command 'show_efuse_table'. + +static const esp_efuse_desc_t WR_DIS[] = { + {EFUSE_BLK0, 0, 32}, // [] Disable programming of individual eFuses, +}; + +static const esp_efuse_desc_t WR_DIS_RD_DIS[] = { + {EFUSE_BLK0, 0, 1}, // [] wr_dis of RD_DIS, +}; + +static const esp_efuse_desc_t WR_DIS_CRYPT_DPA_ENABLE[] = { + {EFUSE_BLK0, 1, 1}, // [] wr_dis of CRYPT_DPA_ENABLE, +}; + +static const esp_efuse_desc_t WR_DIS_SWAP_UART_SDIO_EN[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of SWAP_UART_SDIO_EN, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_ICACHE[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_ICACHE, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_USB_JTAG[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_USB_JTAG, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_DOWNLOAD_ICACHE[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_DOWNLOAD_ICACHE, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_USB_SERIAL_JTAG[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_USB_SERIAL_JTAG, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_FORCE_DOWNLOAD[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_FORCE_DOWNLOAD, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_TWAI[] = { + {EFUSE_BLK0, 2, 1}, // [WR_DIS.DIS_CAN] wr_dis of DIS_TWAI, +}; + +static const esp_efuse_desc_t WR_DIS_JTAG_SEL_ENABLE[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of JTAG_SEL_ENABLE, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_PAD_JTAG[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_PAD_JTAG, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT, +}; + +static const esp_efuse_desc_t WR_DIS_WDT_DELAY_SEL[] = { + {EFUSE_BLK0, 3, 1}, // [] wr_dis of WDT_DELAY_SEL, +}; + +static const esp_efuse_desc_t WR_DIS_SPI_BOOT_CRYPT_CNT[] = { + {EFUSE_BLK0, 4, 1}, // [] wr_dis of SPI_BOOT_CRYPT_CNT, +}; + +static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE0[] = { + {EFUSE_BLK0, 5, 1}, // [] wr_dis of SECURE_BOOT_KEY_REVOKE0, +}; + +static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE1[] = { + {EFUSE_BLK0, 6, 1}, // [] wr_dis of SECURE_BOOT_KEY_REVOKE1, +}; + +static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE2[] = { + {EFUSE_BLK0, 7, 1}, // [] wr_dis of SECURE_BOOT_KEY_REVOKE2, +}; + +static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_0[] = { + {EFUSE_BLK0, 8, 1}, // [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0, +}; + +static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_1[] = { + {EFUSE_BLK0, 9, 1}, // [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1, +}; + +static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_2[] = { + {EFUSE_BLK0, 10, 1}, // [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2, +}; + +static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_3[] = { + {EFUSE_BLK0, 11, 1}, // [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3, +}; + +static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_4[] = { + {EFUSE_BLK0, 12, 1}, // [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4, +}; + +static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_5[] = { + {EFUSE_BLK0, 13, 1}, // [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5, +}; + +static const esp_efuse_desc_t WR_DIS_SEC_DPA_LEVEL[] = { + {EFUSE_BLK0, 14, 1}, // [WR_DIS.DPA_SEC_LEVEL] wr_dis of SEC_DPA_LEVEL, +}; + +static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_EN[] = { + {EFUSE_BLK0, 15, 1}, // [] wr_dis of SECURE_BOOT_EN, +}; + +static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = { + {EFUSE_BLK0, 16, 1}, // [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE, +}; + +static const esp_efuse_desc_t WR_DIS_SPI_DOWNLOAD_MSPI_DIS[] = { + {EFUSE_BLK0, 17, 1}, // [] wr_dis of SPI_DOWNLOAD_MSPI_DIS, +}; + +static const esp_efuse_desc_t WR_DIS_FLASH_TPUW[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of FLASH_TPUW, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_DOWNLOAD_MODE[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of DIS_DOWNLOAD_MODE, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_DIRECT_BOOT[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of DIS_DIRECT_BOOT, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[] = { + {EFUSE_BLK0, 18, 1}, // [WR_DIS.DIS_USB_PRINT] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, +}; + +static const esp_efuse_desc_t WR_DIS_ENABLE_SECURITY_DOWNLOAD[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of ENABLE_SECURITY_DOWNLOAD, +}; + +static const esp_efuse_desc_t WR_DIS_UART_PRINT_CONTROL[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of UART_PRINT_CONTROL, +}; + +static const esp_efuse_desc_t WR_DIS_FORCE_SEND_RESUME[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of FORCE_SEND_RESUME, +}; + +static const esp_efuse_desc_t WR_DIS_SECURE_VERSION[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of SECURE_VERSION, +}; + +static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[] = { + {EFUSE_BLK0, 19, 1}, // [] wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE, +}; + +static const esp_efuse_desc_t WR_DIS_DISABLE_WAFER_VERSION_MAJOR[] = { + {EFUSE_BLK0, 19, 1}, // [] wr_dis of DISABLE_WAFER_VERSION_MAJOR, +}; + +static const esp_efuse_desc_t WR_DIS_DISABLE_BLK_VERSION_MAJOR[] = { + {EFUSE_BLK0, 19, 1}, // [] wr_dis of DISABLE_BLK_VERSION_MAJOR, +}; + +static const esp_efuse_desc_t WR_DIS_BLK1[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of BLOCK1, +}; + +static const esp_efuse_desc_t WR_DIS_MAC[] = { + {EFUSE_BLK0, 20, 1}, // [WR_DIS.MAC_FACTORY] wr_dis of MAC, +}; + +static const esp_efuse_desc_t WR_DIS_MAC_EXT[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of MAC_EXT, +}; + +static const esp_efuse_desc_t WR_DIS_WAFER_VERSION_MINOR[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of WAFER_VERSION_MINOR, +}; + +static const esp_efuse_desc_t WR_DIS_WAFER_VERSION_MAJOR[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of WAFER_VERSION_MAJOR, +}; + +static const esp_efuse_desc_t WR_DIS_PKG_VERSION[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of PKG_VERSION, +}; + +static const esp_efuse_desc_t WR_DIS_BLK_VERSION_MINOR[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of BLK_VERSION_MINOR, +}; + +static const esp_efuse_desc_t WR_DIS_BLK_VERSION_MAJOR[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of BLK_VERSION_MAJOR, +}; + +static const esp_efuse_desc_t WR_DIS_FLASH_CAP[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of FLASH_CAP, +}; + +static const esp_efuse_desc_t WR_DIS_FLASH_TEMP[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of FLASH_TEMP, +}; + +static const esp_efuse_desc_t WR_DIS_FLASH_VENDOR[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of FLASH_VENDOR, +}; + +static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART1[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of BLOCK2, +}; + +static const esp_efuse_desc_t WR_DIS_OPTIONAL_UNIQUE_ID[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of OPTIONAL_UNIQUE_ID, +}; + +static const esp_efuse_desc_t WR_DIS_TEMP_CALIB[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of TEMP_CALIB, +}; + +static const esp_efuse_desc_t WR_DIS_OCODE[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of OCODE, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN0[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN0, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN1[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN1, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN2[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN2, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN3[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN3, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_CAL_VOL_ATTEN0[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CAL_VOL_ATTEN0, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_CAL_VOL_ATTEN1[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CAL_VOL_ATTEN1, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_CAL_VOL_ATTEN2[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CAL_VOL_ATTEN2, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_CAL_VOL_ATTEN3[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CAL_VOL_ATTEN3, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN0_CH0[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH0, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN0_CH1[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH1, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN0_CH2[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH2, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN0_CH3[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH3, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN0_CH4[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH4, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN0_CH5[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH5, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_INIT_CODE_ATTEN0_CH6[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH6, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK_USR_DATA[] = { + {EFUSE_BLK0, 22, 1}, // [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA, +}; + +static const esp_efuse_desc_t WR_DIS_CUSTOM_MAC[] = { + {EFUSE_BLK0, 22, 1}, // [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK_KEY0[] = { + {EFUSE_BLK0, 23, 1}, // [WR_DIS.KEY0] wr_dis of BLOCK_KEY0, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK_KEY1[] = { + {EFUSE_BLK0, 24, 1}, // [WR_DIS.KEY1] wr_dis of BLOCK_KEY1, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK_KEY2[] = { + {EFUSE_BLK0, 25, 1}, // [WR_DIS.KEY2] wr_dis of BLOCK_KEY2, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK_KEY3[] = { + {EFUSE_BLK0, 26, 1}, // [WR_DIS.KEY3] wr_dis of BLOCK_KEY3, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK_KEY4[] = { + {EFUSE_BLK0, 27, 1}, // [WR_DIS.KEY4] wr_dis of BLOCK_KEY4, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK_KEY5[] = { + {EFUSE_BLK0, 28, 1}, // [WR_DIS.KEY5] wr_dis of BLOCK_KEY5, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK_SYS_DATA2[] = { + {EFUSE_BLK0, 29, 1}, // [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2, +}; + +static const esp_efuse_desc_t WR_DIS_USB_EXCHG_PINS[] = { + {EFUSE_BLK0, 30, 1}, // [] wr_dis of USB_EXCHG_PINS, +}; + +static const esp_efuse_desc_t WR_DIS_VDD_SPI_AS_GPIO[] = { + {EFUSE_BLK0, 30, 1}, // [] wr_dis of VDD_SPI_AS_GPIO, +}; + +static const esp_efuse_desc_t WR_DIS_SOFT_DIS_JTAG[] = { + {EFUSE_BLK0, 31, 1}, // [] wr_dis of SOFT_DIS_JTAG, +}; + +static const esp_efuse_desc_t RD_DIS[] = { + {EFUSE_BLK0, 32, 7}, // [] Disable reading from BlOCK4-10, +}; + +static const esp_efuse_desc_t RD_DIS_BLOCK_KEY0[] = { + {EFUSE_BLK0, 32, 1}, // [RD_DIS.KEY0] rd_dis of BLOCK_KEY0, +}; + +static const esp_efuse_desc_t RD_DIS_BLOCK_KEY1[] = { + {EFUSE_BLK0, 33, 1}, // [RD_DIS.KEY1] rd_dis of BLOCK_KEY1, +}; + +static const esp_efuse_desc_t RD_DIS_BLOCK_KEY2[] = { + {EFUSE_BLK0, 34, 1}, // [RD_DIS.KEY2] rd_dis of BLOCK_KEY2, +}; + +static const esp_efuse_desc_t RD_DIS_BLOCK_KEY3[] = { + {EFUSE_BLK0, 35, 1}, // [RD_DIS.KEY3] rd_dis of BLOCK_KEY3, +}; + +static const esp_efuse_desc_t RD_DIS_BLOCK_KEY4[] = { + {EFUSE_BLK0, 36, 1}, // [RD_DIS.KEY4] rd_dis of BLOCK_KEY4, +}; + +static const esp_efuse_desc_t RD_DIS_BLOCK_KEY5[] = { + {EFUSE_BLK0, 37, 1}, // [RD_DIS.KEY5] rd_dis of BLOCK_KEY5, +}; + +static const esp_efuse_desc_t RD_DIS_BLOCK_SYS_DATA2[] = { + {EFUSE_BLK0, 38, 1}, // [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2, +}; + +static const esp_efuse_desc_t DIS_ICACHE[] = { + {EFUSE_BLK0, 39, 1}, // [] Represents whether icache is disabled or enabled. 1: disabled. 0: enabled, +}; + +static const esp_efuse_desc_t DIS_USB_JTAG[] = { + {EFUSE_BLK0, 40, 1}, // [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled, +}; + +static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG[] = { + {EFUSE_BLK0, 41, 1}, // [] Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled, +}; + +static const esp_efuse_desc_t DIS_FORCE_DOWNLOAD[] = { + {EFUSE_BLK0, 42, 1}, // [] Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled, +}; + +static const esp_efuse_desc_t SPI_DOWNLOAD_MSPI_DIS[] = { + {EFUSE_BLK0, 43, 1}, // [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled. 0: enabled, +}; + +static const esp_efuse_desc_t JTAG_SEL_ENABLE[] = { + {EFUSE_BLK0, 44, 1}, // [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled. 0: disabled, +}; + +static const esp_efuse_desc_t DIS_PAD_JTAG[] = { + {EFUSE_BLK0, 45, 1}, // [] Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled, +}; + +static const esp_efuse_desc_t DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { + {EFUSE_BLK0, 46, 1}, // [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled, +}; + +static const esp_efuse_desc_t USB_DREFH[] = { + {EFUSE_BLK0, 47, 2}, // [] Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged, +}; + +static const esp_efuse_desc_t USB_DREFL[] = { + {EFUSE_BLK0, 49, 2}, // [] Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not functioned, +}; + +static const esp_efuse_desc_t USB_EXCHG_PINS[] = { + {EFUSE_BLK0, 51, 1}, // [] Represents whether the D+ and D- pins is exchanged., +}; + +static const esp_efuse_desc_t VDD_SPI_AS_GPIO[] = { + {EFUSE_BLK0, 52, 1}, // [] vdd spi as gpio, +}; + +static const esp_efuse_desc_t WDT_DELAY_SEL[] = { + {EFUSE_BLK0, 53, 2}, // [] Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected, +}; + +static const esp_efuse_desc_t SPI_BOOT_CRYPT_CNT[] = { + {EFUSE_BLK0, 55, 3}, // [] Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"}, +}; + +static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE0[] = { + {EFUSE_BLK0, 58, 1}, // [] Revoke 1st secure boot key, +}; + +static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE1[] = { + {EFUSE_BLK0, 59, 1}, // [] Revoke 2nd secure boot key, +}; + +static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE2[] = { + {EFUSE_BLK0, 60, 1}, // [] Revoke 3rd secure boot key, +}; + +static const esp_efuse_desc_t KEY_PURPOSE_0[] = { + {EFUSE_BLK0, 64, 4}, // [KEY0_PURPOSE] Represents the purpose of Key0, +}; + +static const esp_efuse_desc_t KEY_PURPOSE_1[] = { + {EFUSE_BLK0, 68, 4}, // [KEY1_PURPOSE] Represents the purpose of Key1, +}; + +static const esp_efuse_desc_t KEY_PURPOSE_2[] = { + {EFUSE_BLK0, 72, 4}, // [KEY2_PURPOSE] Represents the purpose of Key2, +}; + +static const esp_efuse_desc_t KEY_PURPOSE_3[] = { + {EFUSE_BLK0, 76, 4}, // [KEY3_PURPOSE] Represents the purpose of Key3, +}; + +static const esp_efuse_desc_t KEY_PURPOSE_4[] = { + {EFUSE_BLK0, 80, 4}, // [KEY4_PURPOSE] Represents the purpose of Key4, +}; + +static const esp_efuse_desc_t KEY_PURPOSE_5[] = { + {EFUSE_BLK0, 84, 4}, // [KEY5_PURPOSE] Represents the purpose of Key5, +}; + +static const esp_efuse_desc_t SEC_DPA_LEVEL[] = { + {EFUSE_BLK0, 88, 2}, // [DPA_SEC_LEVEL] Represents the spa secure level by configuring the clock random divide mode, +}; + +static const esp_efuse_desc_t SECURE_BOOT_EN[] = { + {EFUSE_BLK0, 90, 1}, // [] Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled, +}; + +static const esp_efuse_desc_t SECURE_BOOT_AGGRESSIVE_REVOKE[] = { + {EFUSE_BLK0, 91, 1}, // [] Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled, +}; + +static const esp_efuse_desc_t FLASH_TPUW[] = { + {EFUSE_BLK0, 92, 4}, // [] Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the programmed value. Otherwise; the waiting time is 2 times the programmed value, +}; + +static const esp_efuse_desc_t DIS_DOWNLOAD_MODE[] = { + {EFUSE_BLK0, 96, 1}, // [] Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled, +}; + +static const esp_efuse_desc_t DIS_DIRECT_BOOT[] = { + {EFUSE_BLK0, 97, 1}, // [] Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled, +}; + +static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG_ROM_PRINT[] = { + {EFUSE_BLK0, 98, 1}, // [DIS_USB_PRINT] Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled, +}; + +static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = { + {EFUSE_BLK0, 99, 1}, // [] Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled, +}; + +static const esp_efuse_desc_t ENABLE_SECURITY_DOWNLOAD[] = { + {EFUSE_BLK0, 100, 1}, // [] Represents whether security download is enabled or disabled. 1: enabled. 0: disabled, +}; + +static const esp_efuse_desc_t UART_PRINT_CONTROL[] = { + {EFUSE_BLK0, 101, 2}, // [] Set the default UARTboot message output mode {0: "Enable"; 1: "Enable when GPIO8 is low at reset"; 2: "Enable when GPIO8 is high at reset"; 3: "Disable"}, +}; + +static const esp_efuse_desc_t FORCE_SEND_RESUME[] = { + {EFUSE_BLK0, 103, 1}, // [] Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced, +}; + +static const esp_efuse_desc_t SECURE_VERSION[] = { + {EFUSE_BLK0, 104, 16}, // [] Represents the version used by ESP-IDF anti-rollback feature, +}; + +static const esp_efuse_desc_t SECURE_BOOT_DISABLE_FAST_WAKE[] = { + {EFUSE_BLK0, 120, 1}, // [] Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled, +}; + +static const esp_efuse_desc_t HYS_EN_PAD[] = { + {EFUSE_BLK0, 121, 1}, // [] Disables check of wafer version major, +}; + +static const esp_efuse_desc_t XTS_DPA_CLK_ENABLE[] = { + {EFUSE_BLK0, 122, 1}, // [] Disables check of blk version major, +}; + +static const esp_efuse_desc_t XTS_DPA_PSEUDO_LEVEL[] = { + {EFUSE_BLK0, 123, 1}, // [] Represents the anti-dpa attack pseudo function level., +}; + +static const esp_efuse_desc_t MAC[] = { + {EFUSE_BLK1, 40, 8}, // [MAC_FACTORY] MAC address, + {EFUSE_BLK1, 32, 8}, // [MAC_FACTORY] MAC address, + {EFUSE_BLK1, 24, 8}, // [MAC_FACTORY] MAC address, + {EFUSE_BLK1, 16, 8}, // [MAC_FACTORY] MAC address, + {EFUSE_BLK1, 8, 8}, // [MAC_FACTORY] MAC address, + {EFUSE_BLK1, 0, 8}, // [MAC_FACTORY] MAC address, +}; + +static const esp_efuse_desc_t MAC_EXT[] = { + {EFUSE_BLK1, 56, 8}, // [] Stores the extended bits of MAC address, + {EFUSE_BLK1, 48, 8}, // [] Stores the extended bits of MAC address, +}; + +static const esp_efuse_desc_t WAFER_VERSION_MINOR[] = { + {EFUSE_BLK1, 114, 4}, // [], +}; + +static const esp_efuse_desc_t WAFER_VERSION_MAJOR[] = { + {EFUSE_BLK1, 118, 2}, // [], +}; + +static const esp_efuse_desc_t PKG_VERSION[] = { + {EFUSE_BLK1, 120, 3}, // [] Package version, +}; + +static const esp_efuse_desc_t BLK_VERSION_MINOR[] = { + {EFUSE_BLK1, 123, 3}, // [] BLK_VERSION_MINOR of BLOCK2, +}; + +static const esp_efuse_desc_t BLK_VERSION_MAJOR[] = { + {EFUSE_BLK1, 126, 2}, // [] BLK_VERSION_MAJOR of BLOCK2, +}; + +static const esp_efuse_desc_t FLASH_CAP[] = { + {EFUSE_BLK1, 128, 3}, // [], +}; + +static const esp_efuse_desc_t FLASH_TEMP[] = { + {EFUSE_BLK1, 131, 2}, // [], +}; + +static const esp_efuse_desc_t FLASH_VENDOR[] = { + {EFUSE_BLK1, 133, 3}, // [], +}; + +static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = { + {EFUSE_BLK2, 0, 128}, // [] Optional unique 128-bit ID, +}; + +static const esp_efuse_desc_t TEMP_CALIB[] = { + {EFUSE_BLK2, 128, 9}, // [] Temperature calibration data, +}; + +static const esp_efuse_desc_t OCODE[] = { + {EFUSE_BLK2, 137, 8}, // [] ADC OCode, +}; + +static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN0[] = { + {EFUSE_BLK2, 145, 10}, // [] ADC1 init code at atten0, +}; + +static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN1[] = { + {EFUSE_BLK2, 155, 10}, // [] ADC1 init code at atten1, +}; + +static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN2[] = { + {EFUSE_BLK2, 165, 10}, // [] ADC1 init code at atten2, +}; + +static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN3[] = { + {EFUSE_BLK2, 175, 10}, // [] ADC1 init code at atten3, +}; + +static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN0[] = { + {EFUSE_BLK2, 185, 10}, // [] ADC1 calibration voltage at atten0, +}; + +static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN1[] = { + {EFUSE_BLK2, 195, 10}, // [] ADC1 calibration voltage at atten1, +}; + +static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN2[] = { + {EFUSE_BLK2, 205, 10}, // [] ADC1 calibration voltage at atten2, +}; + +static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN3[] = { + {EFUSE_BLK2, 215, 10}, // [] ADC1 calibration voltage at atten3, +}; + +static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN0_CH0[] = { + {EFUSE_BLK2, 225, 4}, // [] ADC1 init code at atten0 ch0, +}; + +static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN0_CH1[] = { + {EFUSE_BLK2, 229, 4}, // [] ADC1 init code at atten0 ch1, +}; + +static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN0_CH2[] = { + {EFUSE_BLK2, 233, 4}, // [] ADC1 init code at atten0 ch2, +}; + +static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN0_CH3[] = { + {EFUSE_BLK2, 237, 4}, // [] ADC1 init code at atten0 ch3, +}; + +static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN0_CH4[] = { + {EFUSE_BLK2, 241, 4}, // [] ADC1 init code at atten0 ch4, +}; + +static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN0_CH5[] = { + {EFUSE_BLK2, 245, 4}, // [] ADC1 init code at atten0 ch5, +}; + +static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN0_CH6[] = { + {EFUSE_BLK2, 249, 4}, // [] ADC1 init code at atten0 ch6, +}; + +static const esp_efuse_desc_t USER_DATA[] = { + {EFUSE_BLK3, 0, 256}, // [BLOCK_USR_DATA] User data, +}; + +static const esp_efuse_desc_t USER_DATA_MAC_CUSTOM[] = { + {EFUSE_BLK3, 200, 48}, // [MAC_CUSTOM CUSTOM_MAC] Custom MAC, +}; + +static const esp_efuse_desc_t KEY0[] = { + {EFUSE_BLK4, 0, 256}, // [BLOCK_KEY0] Key0 or user data, +}; + +static const esp_efuse_desc_t KEY1[] = { + {EFUSE_BLK5, 0, 256}, // [BLOCK_KEY1] Key1 or user data, +}; + +static const esp_efuse_desc_t KEY2[] = { + {EFUSE_BLK6, 0, 256}, // [BLOCK_KEY2] Key2 or user data, +}; + +static const esp_efuse_desc_t KEY3[] = { + {EFUSE_BLK7, 0, 256}, // [BLOCK_KEY3] Key3 or user data, +}; + +static const esp_efuse_desc_t KEY4[] = { + {EFUSE_BLK8, 0, 256}, // [BLOCK_KEY4] Key4 or user data, +}; + +static const esp_efuse_desc_t KEY5[] = { + {EFUSE_BLK9, 0, 256}, // [BLOCK_KEY5] Key5 or user data, +}; + +static const esp_efuse_desc_t SYS_DATA_PART2[] = { + {EFUSE_BLK10, 0, 256}, // [BLOCK_SYS_DATA2] System data part 2 (reserved), +}; + + + + + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[] = { + &WR_DIS[0], // [] Disable programming of individual eFuses + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[] = { + &WR_DIS_RD_DIS[0], // [] wr_dis of RD_DIS + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CRYPT_DPA_ENABLE[] = { + &WR_DIS_CRYPT_DPA_ENABLE[0], // [] wr_dis of CRYPT_DPA_ENABLE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SWAP_UART_SDIO_EN[] = { + &WR_DIS_SWAP_UART_SDIO_EN[0], // [] wr_dis of SWAP_UART_SDIO_EN + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_ICACHE[] = { + &WR_DIS_DIS_ICACHE[0], // [] wr_dis of DIS_ICACHE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_JTAG[] = { + &WR_DIS_DIS_USB_JTAG[0], // [] wr_dis of DIS_USB_JTAG + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_ICACHE[] = { + &WR_DIS_DIS_DOWNLOAD_ICACHE[0], // [] wr_dis of DIS_DOWNLOAD_ICACHE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG[] = { + &WR_DIS_DIS_USB_SERIAL_JTAG[0], // [] wr_dis of DIS_USB_SERIAL_JTAG + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_FORCE_DOWNLOAD[] = { + &WR_DIS_DIS_FORCE_DOWNLOAD[0], // [] wr_dis of DIS_FORCE_DOWNLOAD + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_TWAI[] = { + &WR_DIS_DIS_TWAI[0], // [WR_DIS.DIS_CAN] wr_dis of DIS_TWAI + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_JTAG_SEL_ENABLE[] = { + &WR_DIS_JTAG_SEL_ENABLE[0], // [] wr_dis of JTAG_SEL_ENABLE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_PAD_JTAG[] = { + &WR_DIS_DIS_PAD_JTAG[0], // [] wr_dis of DIS_PAD_JTAG + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { + &WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[0], // [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[] = { + &WR_DIS_WDT_DELAY_SEL[0], // [] wr_dis of WDT_DELAY_SEL + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[] = { + &WR_DIS_SPI_BOOT_CRYPT_CNT[0], // [] wr_dis of SPI_BOOT_CRYPT_CNT + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[] = { + &WR_DIS_SECURE_BOOT_KEY_REVOKE0[0], // [] wr_dis of SECURE_BOOT_KEY_REVOKE0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[] = { + &WR_DIS_SECURE_BOOT_KEY_REVOKE1[0], // [] wr_dis of SECURE_BOOT_KEY_REVOKE1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[] = { + &WR_DIS_SECURE_BOOT_KEY_REVOKE2[0], // [] wr_dis of SECURE_BOOT_KEY_REVOKE2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_0[] = { + &WR_DIS_KEY_PURPOSE_0[0], // [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_1[] = { + &WR_DIS_KEY_PURPOSE_1[0], // [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_2[] = { + &WR_DIS_KEY_PURPOSE_2[0], // [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_3[] = { + &WR_DIS_KEY_PURPOSE_3[0], // [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_4[] = { + &WR_DIS_KEY_PURPOSE_4[0], // [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[] = { + &WR_DIS_KEY_PURPOSE_5[0], // [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SEC_DPA_LEVEL[] = { + &WR_DIS_SEC_DPA_LEVEL[0], // [WR_DIS.DPA_SEC_LEVEL] wr_dis of SEC_DPA_LEVEL + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[] = { + &WR_DIS_SECURE_BOOT_EN[0], // [] wr_dis of SECURE_BOOT_EN + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = { + &WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[0], // [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_DOWNLOAD_MSPI_DIS[] = { + &WR_DIS_SPI_DOWNLOAD_MSPI_DIS[0], // [] wr_dis of SPI_DOWNLOAD_MSPI_DIS + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TPUW[] = { + &WR_DIS_FLASH_TPUW[0], // [] wr_dis of FLASH_TPUW + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MODE[] = { + &WR_DIS_DIS_DOWNLOAD_MODE[0], // [] wr_dis of DIS_DOWNLOAD_MODE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT[] = { + &WR_DIS_DIS_DIRECT_BOOT[0], // [] wr_dis of DIS_DIRECT_BOOT + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[] = { + &WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[0], // [WR_DIS.DIS_USB_PRINT] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = { + &WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[0], // [] wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ENABLE_SECURITY_DOWNLOAD[] = { + &WR_DIS_ENABLE_SECURITY_DOWNLOAD[0], // [] wr_dis of ENABLE_SECURITY_DOWNLOAD + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_PRINT_CONTROL[] = { + &WR_DIS_UART_PRINT_CONTROL[0], // [] wr_dis of UART_PRINT_CONTROL + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_SEND_RESUME[] = { + &WR_DIS_FORCE_SEND_RESUME[0], // [] wr_dis of FORCE_SEND_RESUME + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_VERSION[] = { + &WR_DIS_SECURE_VERSION[0], // [] wr_dis of SECURE_VERSION + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[] = { + &WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[0], // [] wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[] = { + &WR_DIS_DISABLE_WAFER_VERSION_MAJOR[0], // [] wr_dis of DISABLE_WAFER_VERSION_MAJOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[] = { + &WR_DIS_DISABLE_BLK_VERSION_MAJOR[0], // [] wr_dis of DISABLE_BLK_VERSION_MAJOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[] = { + &WR_DIS_BLK1[0], // [] wr_dis of BLOCK1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[] = { + &WR_DIS_MAC[0], // [WR_DIS.MAC_FACTORY] wr_dis of MAC + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC_EXT[] = { + &WR_DIS_MAC_EXT[0], // [] wr_dis of MAC_EXT + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR[] = { + &WR_DIS_WAFER_VERSION_MINOR[0], // [] wr_dis of WAFER_VERSION_MINOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR[] = { + &WR_DIS_WAFER_VERSION_MAJOR[0], // [] wr_dis of WAFER_VERSION_MAJOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[] = { + &WR_DIS_PKG_VERSION[0], // [] wr_dis of PKG_VERSION + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[] = { + &WR_DIS_BLK_VERSION_MINOR[0], // [] wr_dis of BLK_VERSION_MINOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[] = { + &WR_DIS_BLK_VERSION_MAJOR[0], // [] wr_dis of BLK_VERSION_MAJOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_CAP[] = { + &WR_DIS_FLASH_CAP[0], // [] wr_dis of FLASH_CAP + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TEMP[] = { + &WR_DIS_FLASH_TEMP[0], // [] wr_dis of FLASH_TEMP + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_VENDOR[] = { + &WR_DIS_FLASH_VENDOR[0], // [] wr_dis of FLASH_VENDOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[] = { + &WR_DIS_SYS_DATA_PART1[0], // [] wr_dis of BLOCK2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[] = { + &WR_DIS_OPTIONAL_UNIQUE_ID[0], // [] wr_dis of OPTIONAL_UNIQUE_ID + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP_CALIB[] = { + &WR_DIS_TEMP_CALIB[0], // [] wr_dis of TEMP_CALIB + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OCODE[] = { + &WR_DIS_OCODE[0], // [] wr_dis of OCODE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0[] = { + &WR_DIS_ADC1_INIT_CODE_ATTEN0[0], // [] wr_dis of ADC1_INIT_CODE_ATTEN0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN1[] = { + &WR_DIS_ADC1_INIT_CODE_ATTEN1[0], // [] wr_dis of ADC1_INIT_CODE_ATTEN1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN2[] = { + &WR_DIS_ADC1_INIT_CODE_ATTEN2[0], // [] wr_dis of ADC1_INIT_CODE_ATTEN2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN3[] = { + &WR_DIS_ADC1_INIT_CODE_ATTEN3[0], // [] wr_dis of ADC1_INIT_CODE_ATTEN3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN0[] = { + &WR_DIS_ADC1_CAL_VOL_ATTEN0[0], // [] wr_dis of ADC1_CAL_VOL_ATTEN0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN1[] = { + &WR_DIS_ADC1_CAL_VOL_ATTEN1[0], // [] wr_dis of ADC1_CAL_VOL_ATTEN1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN2[] = { + &WR_DIS_ADC1_CAL_VOL_ATTEN2[0], // [] wr_dis of ADC1_CAL_VOL_ATTEN2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN3[] = { + &WR_DIS_ADC1_CAL_VOL_ATTEN3[0], // [] wr_dis of ADC1_CAL_VOL_ATTEN3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH0[] = { + &WR_DIS_ADC1_INIT_CODE_ATTEN0_CH0[0], // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH1[] = { + &WR_DIS_ADC1_INIT_CODE_ATTEN0_CH1[0], // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH2[] = { + &WR_DIS_ADC1_INIT_CODE_ATTEN0_CH2[0], // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH3[] = { + &WR_DIS_ADC1_INIT_CODE_ATTEN0_CH3[0], // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH4[] = { + &WR_DIS_ADC1_INIT_CODE_ATTEN0_CH4[0], // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH4 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH5[] = { + &WR_DIS_ADC1_INIT_CODE_ATTEN0_CH5[0], // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH5 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH6[] = { + &WR_DIS_ADC1_INIT_CODE_ATTEN0_CH6[0], // [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH6 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[] = { + &WR_DIS_BLOCK_USR_DATA[0], // [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[] = { + &WR_DIS_CUSTOM_MAC[0], // [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY0[] = { + &WR_DIS_BLOCK_KEY0[0], // [WR_DIS.KEY0] wr_dis of BLOCK_KEY0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY1[] = { + &WR_DIS_BLOCK_KEY1[0], // [WR_DIS.KEY1] wr_dis of BLOCK_KEY1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY2[] = { + &WR_DIS_BLOCK_KEY2[0], // [WR_DIS.KEY2] wr_dis of BLOCK_KEY2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY3[] = { + &WR_DIS_BLOCK_KEY3[0], // [WR_DIS.KEY3] wr_dis of BLOCK_KEY3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY4[] = { + &WR_DIS_BLOCK_KEY4[0], // [WR_DIS.KEY4] wr_dis of BLOCK_KEY4 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY5[] = { + &WR_DIS_BLOCK_KEY5[0], // [WR_DIS.KEY5] wr_dis of BLOCK_KEY5 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[] = { + &WR_DIS_BLOCK_SYS_DATA2[0], // [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_EXCHG_PINS[] = { + &WR_DIS_USB_EXCHG_PINS[0], // [] wr_dis of USB_EXCHG_PINS + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_AS_GPIO[] = { + &WR_DIS_VDD_SPI_AS_GPIO[0], // [] wr_dis of VDD_SPI_AS_GPIO + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[] = { + &WR_DIS_SOFT_DIS_JTAG[0], // [] wr_dis of SOFT_DIS_JTAG + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[] = { + &RD_DIS[0], // [] Disable reading from BlOCK4-10 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY0[] = { + &RD_DIS_BLOCK_KEY0[0], // [RD_DIS.KEY0] rd_dis of BLOCK_KEY0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY1[] = { + &RD_DIS_BLOCK_KEY1[0], // [RD_DIS.KEY1] rd_dis of BLOCK_KEY1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY2[] = { + &RD_DIS_BLOCK_KEY2[0], // [RD_DIS.KEY2] rd_dis of BLOCK_KEY2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY3[] = { + &RD_DIS_BLOCK_KEY3[0], // [RD_DIS.KEY3] rd_dis of BLOCK_KEY3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY4[] = { + &RD_DIS_BLOCK_KEY4[0], // [RD_DIS.KEY4] rd_dis of BLOCK_KEY4 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY5[] = { + &RD_DIS_BLOCK_KEY5[0], // [RD_DIS.KEY5] rd_dis of BLOCK_KEY5 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[] = { + &RD_DIS_BLOCK_SYS_DATA2[0], // [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[] = { + &DIS_ICACHE[0], // [] Represents whether icache is disabled or enabled. 1: disabled. 0: enabled + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[] = { + &DIS_USB_JTAG[0], // [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG[] = { + &DIS_USB_SERIAL_JTAG[0], // [] Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[] = { + &DIS_FORCE_DOWNLOAD[0], // [] Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SPI_DOWNLOAD_MSPI_DIS[] = { + &SPI_DOWNLOAD_MSPI_DIS[0], // [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled. 0: enabled + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[] = { + &JTAG_SEL_ENABLE[0], // [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled. 0: disabled + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[] = { + &DIS_PAD_JTAG[0], // [] Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { + &DIS_DOWNLOAD_MANUAL_ENCRYPT[0], // [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_USB_DREFH[] = { + &USB_DREFH[0], // [] Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_USB_DREFL[] = { + &USB_DREFL[0], // [] Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not functioned + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[] = { + &USB_EXCHG_PINS[0], // [] Represents whether the D+ and D- pins is exchanged. + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_AS_GPIO[] = { + &VDD_SPI_AS_GPIO[0], // [] vdd spi as gpio + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[] = { + &WDT_DELAY_SEL[0], // [] Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[] = { + &SPI_BOOT_CRYPT_CNT[0], // [] Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"} + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[] = { + &SECURE_BOOT_KEY_REVOKE0[0], // [] Revoke 1st secure boot key + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[] = { + &SECURE_BOOT_KEY_REVOKE1[0], // [] Revoke 2nd secure boot key + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[] = { + &SECURE_BOOT_KEY_REVOKE2[0], // [] Revoke 3rd secure boot key + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[] = { + &KEY_PURPOSE_0[0], // [KEY0_PURPOSE] Represents the purpose of Key0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[] = { + &KEY_PURPOSE_1[0], // [KEY1_PURPOSE] Represents the purpose of Key1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[] = { + &KEY_PURPOSE_2[0], // [KEY2_PURPOSE] Represents the purpose of Key2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[] = { + &KEY_PURPOSE_3[0], // [KEY3_PURPOSE] Represents the purpose of Key3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[] = { + &KEY_PURPOSE_4[0], // [KEY4_PURPOSE] Represents the purpose of Key4 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[] = { + &KEY_PURPOSE_5[0], // [KEY5_PURPOSE] Represents the purpose of Key5 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SEC_DPA_LEVEL[] = { + &SEC_DPA_LEVEL[0], // [DPA_SEC_LEVEL] Represents the spa secure level by configuring the clock random divide mode + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[] = { + &SECURE_BOOT_EN[0], // [] Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[] = { + &SECURE_BOOT_AGGRESSIVE_REVOKE[0], // [] Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[] = { + &FLASH_TPUW[0], // [] Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the programmed value. Otherwise; the waiting time is 2 times the programmed value + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[] = { + &DIS_DOWNLOAD_MODE[0], // [] Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[] = { + &DIS_DIRECT_BOOT[0], // [] Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[] = { + &DIS_USB_SERIAL_JTAG_ROM_PRINT[0], // [DIS_USB_PRINT] Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = { + &DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[0], // [] Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[] = { + &ENABLE_SECURITY_DOWNLOAD[0], // [] Represents whether security download is enabled or disabled. 1: enabled. 0: disabled + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[] = { + &UART_PRINT_CONTROL[0], // [] Set the default UARTboot message output mode {0: "Enable"; 1: "Enable when GPIO8 is low at reset"; 2: "Enable when GPIO8 is high at reset"; 3: "Disable"} + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[] = { + &FORCE_SEND_RESUME[0], // [] Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[] = { + &SECURE_VERSION[0], // [] Represents the version used by ESP-IDF anti-rollback feature + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE[] = { + &SECURE_BOOT_DISABLE_FAST_WAKE[0], // [] Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_HYS_EN_PAD[] = { + &HYS_EN_PAD[0], // [] Disables check of wafer version major + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_XTS_DPA_CLK_ENABLE[] = { + &XTS_DPA_CLK_ENABLE[0], // [] Disables check of blk version major + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_XTS_DPA_PSEUDO_LEVEL[] = { + &XTS_DPA_PSEUDO_LEVEL[0], // [] Represents the anti-dpa attack pseudo function level. + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_MAC[] = { + &MAC[0], // [MAC_FACTORY] MAC address + &MAC[1], // [MAC_FACTORY] MAC address + &MAC[2], // [MAC_FACTORY] MAC address + &MAC[3], // [MAC_FACTORY] MAC address + &MAC[4], // [MAC_FACTORY] MAC address + &MAC[5], // [MAC_FACTORY] MAC address + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_MAC_EXT[] = { + &MAC_EXT[0], // [] Stores the extended bits of MAC address + &MAC_EXT[1], // [] Stores the extended bits of MAC address + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[] = { + &WAFER_VERSION_MINOR[0], // [] + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[] = { + &WAFER_VERSION_MAJOR[0], // [] + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[] = { + &PKG_VERSION[0], // [] Package version + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[] = { + &BLK_VERSION_MINOR[0], // [] BLK_VERSION_MINOR of BLOCK2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[] = { + &BLK_VERSION_MAJOR[0], // [] BLK_VERSION_MAJOR of BLOCK2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_FLASH_CAP[] = { + &FLASH_CAP[0], // [] + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_FLASH_TEMP[] = { + &FLASH_TEMP[0], // [] + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_FLASH_VENDOR[] = { + &FLASH_VENDOR[0], // [] + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = { + &OPTIONAL_UNIQUE_ID[0], // [] Optional unique 128-bit ID + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[] = { + &TEMP_CALIB[0], // [] Temperature calibration data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_OCODE[] = { + &OCODE[0], // [] ADC OCode + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0[] = { + &ADC1_INIT_CODE_ATTEN0[0], // [] ADC1 init code at atten0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN1[] = { + &ADC1_INIT_CODE_ATTEN1[0], // [] ADC1 init code at atten1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN2[] = { + &ADC1_INIT_CODE_ATTEN2[0], // [] ADC1 init code at atten2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN3[] = { + &ADC1_INIT_CODE_ATTEN3[0], // [] ADC1 init code at atten3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN0[] = { + &ADC1_CAL_VOL_ATTEN0[0], // [] ADC1 calibration voltage at atten0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN1[] = { + &ADC1_CAL_VOL_ATTEN1[0], // [] ADC1 calibration voltage at atten1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN2[] = { + &ADC1_CAL_VOL_ATTEN2[0], // [] ADC1 calibration voltage at atten2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN3[] = { + &ADC1_CAL_VOL_ATTEN3[0], // [] ADC1 calibration voltage at atten3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH0[] = { + &ADC1_INIT_CODE_ATTEN0_CH0[0], // [] ADC1 init code at atten0 ch0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH1[] = { + &ADC1_INIT_CODE_ATTEN0_CH1[0], // [] ADC1 init code at atten0 ch1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH2[] = { + &ADC1_INIT_CODE_ATTEN0_CH2[0], // [] ADC1 init code at atten0 ch2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH3[] = { + &ADC1_INIT_CODE_ATTEN0_CH3[0], // [] ADC1 init code at atten0 ch3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH4[] = { + &ADC1_INIT_CODE_ATTEN0_CH4[0], // [] ADC1 init code at atten0 ch4 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH5[] = { + &ADC1_INIT_CODE_ATTEN0_CH5[0], // [] ADC1 init code at atten0 ch5 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH6[] = { + &ADC1_INIT_CODE_ATTEN0_CH6[0], // [] ADC1 init code at atten0 ch6 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[] = { + &USER_DATA[0], // [BLOCK_USR_DATA] User data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[] = { + &USER_DATA_MAC_CUSTOM[0], // [MAC_CUSTOM CUSTOM_MAC] Custom MAC + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY0[] = { + &KEY0[0], // [BLOCK_KEY0] Key0 or user data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY1[] = { + &KEY1[0], // [BLOCK_KEY1] Key1 or user data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY2[] = { + &KEY2[0], // [BLOCK_KEY2] Key2 or user data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY3[] = { + &KEY3[0], // [BLOCK_KEY3] Key3 or user data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY4[] = { + &KEY4[0], // [BLOCK_KEY4] Key4 or user data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY5[] = { + &KEY5[0], // [BLOCK_KEY5] Key5 or user data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[] = { + &SYS_DATA_PART2[0], // [BLOCK_SYS_DATA2] System data part 2 (reserved) + NULL +}; diff --git a/components/efuse/esp32c61/esp_efuse_table.csv b/components/efuse/esp32c61/esp_efuse_table.csv new file mode 100644 index 0000000000..c1dd66939d --- /dev/null +++ b/components/efuse/esp32c61/esp_efuse_table.csv @@ -0,0 +1,201 @@ + +# field_name, | efuse_block, | bit_start, | bit_count, |comment # +# | (EFUSE_BLK0 | (0..255) | (1-256) | # +# | EFUSE_BLK1 | | | # +# | ...) | | | # +########################################################################## +# !!!!!!!!!!! # +# After editing this file, run the command manually "idf.py efuse-common-table" +# this will generate new source files, next rebuild all the sources. +# !!!!!!!!!!! # + +# This file was generated by regtools.py based on the efuses.yaml file with the version: df46b69f0ed3913114ba53d3a0b2b843 + +# TODO: [ESP32C61] IDF-9282, file inherit from verify code, pls check + +WR_DIS, EFUSE_BLK0, 0, 32, [] Disable programming of individual eFuses +WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [] wr_dis of RD_DIS +WR_DIS.CRYPT_DPA_ENABLE, EFUSE_BLK0, 1, 1, [] wr_dis of CRYPT_DPA_ENABLE +WR_DIS.SWAP_UART_SDIO_EN, EFUSE_BLK0, 2, 1, [] wr_dis of SWAP_UART_SDIO_EN +WR_DIS.DIS_ICACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_ICACHE +WR_DIS.DIS_USB_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_USB_JTAG +WR_DIS.DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_ICACHE +WR_DIS.DIS_USB_SERIAL_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_USB_SERIAL_JTAG +WR_DIS.DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_FORCE_DOWNLOAD +WR_DIS.DIS_TWAI, EFUSE_BLK0, 2, 1, [WR_DIS.DIS_CAN] wr_dis of DIS_TWAI +WR_DIS.JTAG_SEL_ENABLE, EFUSE_BLK0, 2, 1, [] wr_dis of JTAG_SEL_ENABLE +WR_DIS.DIS_PAD_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_PAD_JTAG +WR_DIS.DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT +WR_DIS.WDT_DELAY_SEL, EFUSE_BLK0, 3, 1, [] wr_dis of WDT_DELAY_SEL +WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 4, 1, [] wr_dis of SPI_BOOT_CRYPT_CNT +WR_DIS.SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 5, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE0 +WR_DIS.SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 6, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE1 +WR_DIS.SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 7, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE2 +WR_DIS.KEY_PURPOSE_0, EFUSE_BLK0, 8, 1, [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0 +WR_DIS.KEY_PURPOSE_1, EFUSE_BLK0, 9, 1, [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1 +WR_DIS.KEY_PURPOSE_2, EFUSE_BLK0, 10, 1, [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2 +WR_DIS.KEY_PURPOSE_3, EFUSE_BLK0, 11, 1, [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3 +WR_DIS.KEY_PURPOSE_4, EFUSE_BLK0, 12, 1, [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4 +WR_DIS.KEY_PURPOSE_5, EFUSE_BLK0, 13, 1, [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5 +WR_DIS.SEC_DPA_LEVEL, EFUSE_BLK0, 14, 1, [WR_DIS.DPA_SEC_LEVEL] wr_dis of SEC_DPA_LEVEL +WR_DIS.SECURE_BOOT_EN, EFUSE_BLK0, 15, 1, [] wr_dis of SECURE_BOOT_EN +WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 16, 1, [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE +WR_DIS.SPI_DOWNLOAD_MSPI_DIS, EFUSE_BLK0, 17, 1, [] wr_dis of SPI_DOWNLOAD_MSPI_DIS +WR_DIS.FLASH_TPUW, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_TPUW +WR_DIS.DIS_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_DOWNLOAD_MODE +WR_DIS.DIS_DIRECT_BOOT, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_DIRECT_BOOT +WR_DIS.DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 18, 1, [WR_DIS.DIS_USB_PRINT] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT +WR_DIS.DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE +WR_DIS.ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 18, 1, [] wr_dis of ENABLE_SECURITY_DOWNLOAD +WR_DIS.UART_PRINT_CONTROL, EFUSE_BLK0, 18, 1, [] wr_dis of UART_PRINT_CONTROL +WR_DIS.FORCE_SEND_RESUME, EFUSE_BLK0, 18, 1, [] wr_dis of FORCE_SEND_RESUME +WR_DIS.SECURE_VERSION, EFUSE_BLK0, 18, 1, [] wr_dis of SECURE_VERSION +WR_DIS.SECURE_BOOT_DISABLE_FAST_WAKE, EFUSE_BLK0, 19, 1, [] wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE +WR_DIS.DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 19, 1, [] wr_dis of DISABLE_WAFER_VERSION_MAJOR +WR_DIS.DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 19, 1, [] wr_dis of DISABLE_BLK_VERSION_MAJOR +WR_DIS.BLK1, EFUSE_BLK0, 20, 1, [] wr_dis of BLOCK1 +WR_DIS.MAC, EFUSE_BLK0, 20, 1, [WR_DIS.MAC_FACTORY] wr_dis of MAC +WR_DIS.MAC_EXT, EFUSE_BLK0, 20, 1, [] wr_dis of MAC_EXT +WR_DIS.ACTIVE_HP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of ACTIVE_HP_DBIAS +WR_DIS.ACTIVE_LP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of ACTIVE_LP_DBIAS +WR_DIS.LSLP_HP_DBG, EFUSE_BLK0, 20, 1, [] wr_dis of LSLP_HP_DBG +WR_DIS.LSLP_HP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of LSLP_HP_DBIAS +WR_DIS.DSLP_LP_DBG, EFUSE_BLK0, 20, 1, [] wr_dis of DSLP_LP_DBG +WR_DIS.DSLP_LP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of DSLP_LP_DBIAS +WR_DIS.DBIAS_VOL_GAP, EFUSE_BLK0, 20, 1, [] wr_dis of DBIAS_VOL_GAP +WR_DIS.WAFER_VERSION_MINOR, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MINOR +WR_DIS.WAFER_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MAJOR +WR_DIS.PKG_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of PKG_VERSION +WR_DIS.BLK_VERSION_MINOR, EFUSE_BLK0, 20, 1, [] wr_dis of BLK_VERSION_MINOR +WR_DIS.BLK_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of BLK_VERSION_MAJOR +WR_DIS.FLASH_CAP, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_CAP +WR_DIS.FLASH_TEMP, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_TEMP +WR_DIS.FLASH_VENDOR, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_VENDOR +WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, [] wr_dis of BLOCK2 +WR_DIS.OPTIONAL_UNIQUE_ID, EFUSE_BLK0, 21, 1, [] wr_dis of OPTIONAL_UNIQUE_ID +WR_DIS.TEMP_CALIB, EFUSE_BLK0, 21, 1, [] wr_dis of TEMP_CALIB +WR_DIS.OCODE, EFUSE_BLK0, 21, 1, [] wr_dis of OCODE +WR_DIS.ADC1_INIT_CODE_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN0 +WR_DIS.ADC1_INIT_CODE_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN1 +WR_DIS.ADC1_INIT_CODE_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN2 +WR_DIS.ADC1_INIT_CODE_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN3 +WR_DIS.ADC1_CAL_VOL_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN0 +WR_DIS.ADC1_CAL_VOL_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN1 +WR_DIS.ADC1_CAL_VOL_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN2 +WR_DIS.ADC1_CAL_VOL_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN3 +WR_DIS.ADC1_INIT_CODE_ATTEN0_CH0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH0 +WR_DIS.ADC1_INIT_CODE_ATTEN0_CH1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH1 +WR_DIS.ADC1_INIT_CODE_ATTEN0_CH2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH2 +WR_DIS.ADC1_INIT_CODE_ATTEN0_CH3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH3 +WR_DIS.ADC1_INIT_CODE_ATTEN0_CH4, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH4 +WR_DIS.ADC1_INIT_CODE_ATTEN0_CH5, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH5 +WR_DIS.ADC1_INIT_CODE_ATTEN0_CH6, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN0_CH6 +WR_DIS.BLOCK_USR_DATA, EFUSE_BLK0, 22, 1, [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA +WR_DIS.CUSTOM_MAC, EFUSE_BLK0, 22, 1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC +WR_DIS.BLOCK_KEY0, EFUSE_BLK0, 23, 1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0 +WR_DIS.BLOCK_KEY1, EFUSE_BLK0, 24, 1, [WR_DIS.KEY1] wr_dis of BLOCK_KEY1 +WR_DIS.BLOCK_KEY2, EFUSE_BLK0, 25, 1, [WR_DIS.KEY2] wr_dis of BLOCK_KEY2 +WR_DIS.BLOCK_KEY3, EFUSE_BLK0, 26, 1, [WR_DIS.KEY3] wr_dis of BLOCK_KEY3 +WR_DIS.BLOCK_KEY4, EFUSE_BLK0, 27, 1, [WR_DIS.KEY4] wr_dis of BLOCK_KEY4 +WR_DIS.BLOCK_KEY5, EFUSE_BLK0, 28, 1, [WR_DIS.KEY5] wr_dis of BLOCK_KEY5 +WR_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 29, 1, [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2 +WR_DIS.USB_EXCHG_PINS, EFUSE_BLK0, 30, 1, [] wr_dis of USB_EXCHG_PINS +WR_DIS.VDD_SPI_AS_GPIO, EFUSE_BLK0, 30, 1, [] wr_dis of VDD_SPI_AS_GPIO +WR_DIS.SOFT_DIS_JTAG, EFUSE_BLK0, 31, 1, [] wr_dis of SOFT_DIS_JTAG +RD_DIS, EFUSE_BLK0, 32, 7, [] Disable reading from BlOCK4-10 +RD_DIS.BLOCK_KEY0, EFUSE_BLK0, 32, 1, [RD_DIS.KEY0] rd_dis of BLOCK_KEY0 +RD_DIS.BLOCK_KEY1, EFUSE_BLK0, 33, 1, [RD_DIS.KEY1] rd_dis of BLOCK_KEY1 +RD_DIS.BLOCK_KEY2, EFUSE_BLK0, 34, 1, [RD_DIS.KEY2] rd_dis of BLOCK_KEY2 +RD_DIS.BLOCK_KEY3, EFUSE_BLK0, 35, 1, [RD_DIS.KEY3] rd_dis of BLOCK_KEY3 +RD_DIS.BLOCK_KEY4, EFUSE_BLK0, 36, 1, [RD_DIS.KEY4] rd_dis of BLOCK_KEY4 +RD_DIS.BLOCK_KEY5, EFUSE_BLK0, 37, 1, [RD_DIS.KEY5] rd_dis of BLOCK_KEY5 +RD_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 38, 1, [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2 +DIS_ICACHE, EFUSE_BLK0, 39, 1, [] Represents whether icache is disabled or enabled. 1: disabled. 0: enabled +DIS_USB_JTAG, EFUSE_BLK0, 40, 1, [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled +DIS_USB_SERIAL_JTAG, EFUSE_BLK0, 41, 1, [] Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled +DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 42, 1, [] Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled +SPI_DOWNLOAD_MSPI_DIS, EFUSE_BLK0, 43, 1, [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled. 0: enabled +JTAG_SEL_ENABLE, EFUSE_BLK0, 44, 1, [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled. 0: disabled +DIS_PAD_JTAG, EFUSE_BLK0, 45, 1, [] Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled +DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 46, 1, [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled +USB_DREFH, EFUSE_BLK0, 47, 2, [] Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged +USB_DREFL, EFUSE_BLK0, 49, 2, [] Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not functioned +USB_EXCHG_PINS, EFUSE_BLK0, 51, 1, [] Represents whether the D+ and D- pins is exchanged. +VDD_SPI_AS_GPIO, EFUSE_BLK0, 52, 1, [] vdd spi as gpio +WDT_DELAY_SEL, EFUSE_BLK0, 53, 2, [] Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected +SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 55, 3, [] Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"} +SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 58, 1, [] Revoke 1st secure boot key +SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 59, 1, [] Revoke 2nd secure boot key +SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 60, 1, [] Revoke 3rd secure boot key +KEY_PURPOSE_0, EFUSE_BLK0, 64, 4, [KEY0_PURPOSE] Represents the purpose of Key0 +KEY_PURPOSE_1, EFUSE_BLK0, 68, 4, [KEY1_PURPOSE] Represents the purpose of Key1 +KEY_PURPOSE_2, EFUSE_BLK0, 72, 4, [KEY2_PURPOSE] Represents the purpose of Key2 +KEY_PURPOSE_3, EFUSE_BLK0, 76, 4, [KEY3_PURPOSE] Represents the purpose of Key3 +KEY_PURPOSE_4, EFUSE_BLK0, 80, 4, [KEY4_PURPOSE] Represents the purpose of Key4 +KEY_PURPOSE_5, EFUSE_BLK0, 84, 4, [KEY5_PURPOSE] Represents the purpose of Key5 +SEC_DPA_LEVEL, EFUSE_BLK0, 88, 2, [DPA_SEC_LEVEL] Represents the spa secure level by configuring the clock random divide mode +SECURE_BOOT_EN, EFUSE_BLK0, 90, 1, [] Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled +SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 91, 1, [] Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled +FLASH_TPUW, EFUSE_BLK0, 92, 4, [] Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the programmed value. Otherwise; the waiting time is 2 times the programmed value +DIS_DOWNLOAD_MODE, EFUSE_BLK0, 96, 1, [] Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled +DIS_DIRECT_BOOT, EFUSE_BLK0, 97, 1, [] Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled +DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 98, 1, [DIS_USB_PRINT] Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled +DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 99, 1, [] Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled +ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 100, 1, [] Represents whether security download is enabled or disabled. 1: enabled. 0: disabled +UART_PRINT_CONTROL, EFUSE_BLK0, 101, 2, [] Set the default UARTboot message output mode {0: "Enable"; 1: "Enable when GPIO8 is low at reset"; 2: "Enable when GPIO8 is high at reset"; 3: "Disable"} +FORCE_SEND_RESUME, EFUSE_BLK0, 103, 1, [] Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced +SECURE_VERSION, EFUSE_BLK0, 104, 16, [] Represents the version used by ESP-IDF anti-rollback feature +SECURE_BOOT_DISABLE_FAST_WAKE, EFUSE_BLK0, 120, 1, [] Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled +HYS_EN_PAD, EFUSE_BLK0, 121, 1, [] Disables check of wafer version major +XTS_DPA_CLK_ENABLE, EFUSE_BLK0, 122, 1, [] Disables check of blk version major +XTS_DPA_PSEUDO_LEVEL, EFUSE_BLK0, 123, 1, [] Represents the anti-dpa attack pseudo function level. +MAC, EFUSE_BLK1, 40, 8, [MAC_FACTORY] MAC address +, EFUSE_BLK1, 32, 8, [MAC_FACTORY] MAC address +, EFUSE_BLK1, 24, 8, [MAC_FACTORY] MAC address +, EFUSE_BLK1, 16, 8, [MAC_FACTORY] MAC address +, EFUSE_BLK1, 8, 8, [MAC_FACTORY] MAC address +, EFUSE_BLK1, 0, 8, [MAC_FACTORY] MAC address +MAC_EXT, EFUSE_BLK1, 56, 8, [] Stores the extended bits of MAC address +, EFUSE_BLK1, 48, 8, [] Stores the extended bits of MAC address +ACTIVE_HP_DBIAS, EFUSE_BLK1, 64, 5, [] Stores the active hp dbias +ACTIVE_LP_DBIAS, EFUSE_BLK1, 69, 5, [] Stores the active lp dbias +LSLP_HP_DBG, EFUSE_BLK1, 74, 2, [] Stores the lslp hp dbg +LSLP_HP_DBIAS, EFUSE_BLK1, 76, 4, [] Stores the lslp hp dbias +DSLP_LP_DBG, EFUSE_BLK1, 80, 3, [] Stores the dslp lp dbg +DSLP_LP_DBIAS, EFUSE_BLK1, 83, 4, [] Stores the dslp lp dbias +DBIAS_VOL_GAP, EFUSE_BLK1, 87, 5, [] Stores the hp and lp dbias vol gap +WAFER_VERSION_MINOR, EFUSE_BLK1, 114, 4, [] +WAFER_VERSION_MAJOR, EFUSE_BLK1, 118, 2, [] +PKG_VERSION, EFUSE_BLK1, 120, 3, [] Package version +BLK_VERSION_MINOR, EFUSE_BLK1, 123, 3, [] BLK_VERSION_MINOR of BLOCK2 +BLK_VERSION_MAJOR, EFUSE_BLK1, 126, 2, [] BLK_VERSION_MAJOR of BLOCK2 +FLASH_CAP, EFUSE_BLK1, 128, 3, [] +FLASH_TEMP, EFUSE_BLK1, 131, 2, [] +FLASH_VENDOR, EFUSE_BLK1, 133, 3, [] +OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, [] Optional unique 128-bit ID +TEMP_CALIB, EFUSE_BLK2, 128, 9, [] Temperature calibration data +OCODE, EFUSE_BLK2, 137, 8, [] ADC OCode +ADC1_INIT_CODE_ATTEN0, EFUSE_BLK2, 145, 10, [] ADC1 init code at atten0 +ADC1_INIT_CODE_ATTEN1, EFUSE_BLK2, 155, 10, [] ADC1 init code at atten1 +ADC1_INIT_CODE_ATTEN2, EFUSE_BLK2, 165, 10, [] ADC1 init code at atten2 +ADC1_INIT_CODE_ATTEN3, EFUSE_BLK2, 175, 10, [] ADC1 init code at atten3 +ADC1_CAL_VOL_ATTEN0, EFUSE_BLK2, 185, 10, [] ADC1 calibration voltage at atten0 +ADC1_CAL_VOL_ATTEN1, EFUSE_BLK2, 195, 10, [] ADC1 calibration voltage at atten1 +ADC1_CAL_VOL_ATTEN2, EFUSE_BLK2, 205, 10, [] ADC1 calibration voltage at atten2 +ADC1_CAL_VOL_ATTEN3, EFUSE_BLK2, 215, 10, [] ADC1 calibration voltage at atten3 +ADC1_INIT_CODE_ATTEN0_CH0, EFUSE_BLK2, 225, 4, [] ADC1 init code at atten0 ch0 +ADC1_INIT_CODE_ATTEN0_CH1, EFUSE_BLK2, 229, 4, [] ADC1 init code at atten0 ch1 +ADC1_INIT_CODE_ATTEN0_CH2, EFUSE_BLK2, 233, 4, [] ADC1 init code at atten0 ch2 +ADC1_INIT_CODE_ATTEN0_CH3, EFUSE_BLK2, 237, 4, [] ADC1 init code at atten0 ch3 +ADC1_INIT_CODE_ATTEN0_CH4, EFUSE_BLK2, 241, 4, [] ADC1 init code at atten0 ch4 +ADC1_INIT_CODE_ATTEN0_CH5, EFUSE_BLK2, 245, 4, [] ADC1 init code at atten0 ch5 +ADC1_INIT_CODE_ATTEN0_CH6, EFUSE_BLK2, 249, 4, [] ADC1 init code at atten0 ch6 +USER_DATA, EFUSE_BLK3, 0, 256, [BLOCK_USR_DATA] User data +USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC +KEY0, EFUSE_BLK4, 0, 256, [BLOCK_KEY0] Key0 or user data +KEY1, EFUSE_BLK5, 0, 256, [BLOCK_KEY1] Key1 or user data +KEY2, EFUSE_BLK6, 0, 256, [BLOCK_KEY2] Key2 or user data +KEY3, EFUSE_BLK7, 0, 256, [BLOCK_KEY3] Key3 or user data +KEY4, EFUSE_BLK8, 0, 256, [BLOCK_KEY4] Key4 or user data +KEY5, EFUSE_BLK9, 0, 256, [BLOCK_KEY5] Key5 or user data +SYS_DATA_PART2, EFUSE_BLK10, 0, 256, [BLOCK_SYS_DATA2] System data part 2 (reserved) diff --git a/components/efuse/esp32c61/esp_efuse_utility.c b/components/efuse/esp32c61/esp_efuse_utility.c new file mode 100644 index 0000000000..8778cddf9c --- /dev/null +++ b/components/efuse/esp32c61/esp_efuse_utility.c @@ -0,0 +1,203 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "sdkconfig.h" +#include "esp_log.h" +#include "assert.h" +#include "esp_efuse_utility.h" +#include "soc/efuse_periph.h" +#include "hal/efuse_hal.h" + +// TODO: [ESP32C61] IDF-9282, file inherit from verify code, pls check + +static const char *TAG = "efuse"; + +#ifdef CONFIG_EFUSE_VIRTUAL +extern uint32_t virt_blocks[EFUSE_BLK_MAX][COUNT_EFUSE_REG_PER_BLOCK]; +#endif // CONFIG_EFUSE_VIRTUAL + +/*Range addresses to read blocks*/ +const esp_efuse_range_addr_t range_read_addr_blocks[] = { + {EFUSE_RD_WR_DIS0_REG, EFUSE_RD_REPEAT_DATA4_REG}, // range address of EFUSE_BLK0 REPEAT + {EFUSE_RD_MAC_SYS0_REG, EFUSE_RD_MAC_SYS5_REG}, // range address of EFUSE_BLK1 MAC_SPI_8M + {EFUSE_RD_SYS_PART1_DATA0_REG, EFUSE_RD_SYS_PART1_DATA7_REG}, // range address of EFUSE_BLK2 SYS_DATA + {EFUSE_RD_USR_DATA0_REG, EFUSE_RD_USR_DATA7_REG}, // range address of EFUSE_BLK3 USR_DATA + {EFUSE_RD_KEY0_DATA0_REG, EFUSE_RD_KEY0_DATA7_REG}, // range address of EFUSE_BLK4 KEY0 + {EFUSE_RD_KEY1_DATA0_REG, EFUSE_RD_KEY1_DATA7_REG}, // range address of EFUSE_BLK5 KEY1 + {EFUSE_RD_KEY2_DATA0_REG, EFUSE_RD_KEY2_DATA7_REG}, // range address of EFUSE_BLK6 KEY2 + {EFUSE_RD_KEY3_DATA0_REG, EFUSE_RD_KEY3_DATA7_REG}, // range address of EFUSE_BLK7 KEY3 + {EFUSE_RD_KEY4_DATA0_REG, EFUSE_RD_KEY4_DATA7_REG}, // range address of EFUSE_BLK8 KEY4 + {EFUSE_RD_KEY5_DATA0_REG, EFUSE_RD_KEY5_DATA7_REG}, // range address of EFUSE_BLK9 KEY5 + {EFUSE_RD_SYS_PART2_DATA0_REG, EFUSE_RD_SYS_PART2_DATA7_REG} // range address of EFUSE_BLK10 KEY6 +}; + +static uint32_t write_mass_blocks[EFUSE_BLK_MAX][COUNT_EFUSE_REG_PER_BLOCK] = { 0 }; + +/*Range addresses to write blocks (it is not real regs, it is buffer) */ +const esp_efuse_range_addr_t range_write_addr_blocks[] = { + {(uint32_t) &write_mass_blocks[EFUSE_BLK0][0], (uint32_t) &write_mass_blocks[EFUSE_BLK0][5]}, + {(uint32_t) &write_mass_blocks[EFUSE_BLK1][0], (uint32_t) &write_mass_blocks[EFUSE_BLK1][5]}, + {(uint32_t) &write_mass_blocks[EFUSE_BLK2][0], (uint32_t) &write_mass_blocks[EFUSE_BLK2][7]}, + {(uint32_t) &write_mass_blocks[EFUSE_BLK3][0], (uint32_t) &write_mass_blocks[EFUSE_BLK3][7]}, + {(uint32_t) &write_mass_blocks[EFUSE_BLK4][0], (uint32_t) &write_mass_blocks[EFUSE_BLK4][7]}, + {(uint32_t) &write_mass_blocks[EFUSE_BLK5][0], (uint32_t) &write_mass_blocks[EFUSE_BLK5][7]}, + {(uint32_t) &write_mass_blocks[EFUSE_BLK6][0], (uint32_t) &write_mass_blocks[EFUSE_BLK6][7]}, + {(uint32_t) &write_mass_blocks[EFUSE_BLK7][0], (uint32_t) &write_mass_blocks[EFUSE_BLK7][7]}, + {(uint32_t) &write_mass_blocks[EFUSE_BLK8][0], (uint32_t) &write_mass_blocks[EFUSE_BLK8][7]}, + {(uint32_t) &write_mass_blocks[EFUSE_BLK9][0], (uint32_t) &write_mass_blocks[EFUSE_BLK9][7]}, + {(uint32_t) &write_mass_blocks[EFUSE_BLK10][0], (uint32_t) &write_mass_blocks[EFUSE_BLK10][7]}, +}; + +#ifndef CONFIG_EFUSE_VIRTUAL +// Update Efuse timing configuration +static esp_err_t esp_efuse_set_timing(void) +{ + // efuse clock is fixed. + // An argument (0) is for compatibility and will be ignored. + efuse_hal_set_timing(0); + return ESP_OK; +} +#endif // ifndef CONFIG_EFUSE_VIRTUAL + +// Efuse read operation: copies data from physical efuses to efuse read registers. +void esp_efuse_utility_clear_program_registers(void) +{ + efuse_hal_read(); + efuse_hal_clear_program_registers(); +} + +esp_err_t esp_efuse_utility_check_errors(void) +{ + return ESP_OK; +} + +// Burn values written to the efuse write registers +esp_err_t esp_efuse_utility_burn_chip(void) +{ + esp_err_t error = ESP_OK; +#ifdef CONFIG_EFUSE_VIRTUAL + ESP_LOGW(TAG, "Virtual efuses enabled: Not really burning eFuses"); + for (int num_block = EFUSE_BLK_MAX - 1; num_block >= EFUSE_BLK0; num_block--) { + int subblock = 0; + for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) { + virt_blocks[num_block][subblock++] |= REG_READ(addr_wr_block); + } + } +#ifdef CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH + esp_efuse_utility_write_efuses_to_flash(); +#endif +#else // CONFIG_EFUSE_VIRTUAL + if (esp_efuse_set_timing() != ESP_OK) { + ESP_LOGE(TAG, "Efuse fields are not burnt"); + } else { + // Permanently update values written to the efuse write registers + // It is necessary to process blocks in the order from MAX-> EFUSE_BLK0, because EFUSE_BLK0 has protection bits for other blocks. + for (int num_block = EFUSE_BLK_MAX - 1; num_block >= EFUSE_BLK0; num_block--) { + bool need_burn_block = false; + for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) { + if (REG_READ(addr_wr_block) != 0) { + need_burn_block = true; + break; + } + } + if (!need_burn_block) { + continue; + } + if (error) { + // It is done for a use case: BLOCK2 (Flash encryption key) could have an error (incorrect written data) + // in this case we can not burn any data into BLOCK0 because it might set read/write protections of BLOCK2. + ESP_LOGE(TAG, "BLOCK%d can not be burned because a previous block got an error, skipped.", num_block); + continue; + } + efuse_hal_clear_program_registers(); + if (esp_efuse_get_coding_scheme(num_block) == EFUSE_CODING_SCHEME_RS) { + uint8_t block_rs[12]; + efuse_hal_rs_calculate((void *)range_write_addr_blocks[num_block].start, block_rs); + hal_memcpy((void *)EFUSE_PGM_CHECK_VALUE0_REG, block_rs, sizeof(block_rs)); + } + unsigned r_data_len = (range_read_addr_blocks[num_block].end - range_read_addr_blocks[num_block].start) + sizeof(uint32_t); + unsigned data_len = (range_write_addr_blocks[num_block].end - range_write_addr_blocks[num_block].start) + sizeof(uint32_t); + memcpy((void *)EFUSE_PGM_DATA0_REG, (void *)range_write_addr_blocks[num_block].start, data_len); + + uint32_t backup_write_data[8 + 3]; // 8 words are data and 3 words are RS coding data + hal_memcpy(backup_write_data, (void *)EFUSE_PGM_DATA0_REG, sizeof(backup_write_data)); + int repeat_burn_op = 1; + bool correct_written_data; + bool coding_error_before = efuse_hal_is_coding_error_in_block(num_block); + if (coding_error_before) { + ESP_LOGW(TAG, "BLOCK%d already has a coding error", num_block); + } + bool coding_error_occurred; + + do { + ESP_LOGI(TAG, "BURN BLOCK%d", num_block); + efuse_hal_program(num_block); // BURN a block + + bool coding_error_after; + for (unsigned i = 0; i < 5; i++) { + efuse_hal_read(); + coding_error_after = efuse_hal_is_coding_error_in_block(num_block); + if (coding_error_after == true) { + break; + } + } + coding_error_occurred = (coding_error_before != coding_error_after) && coding_error_before == false; + if (coding_error_occurred) { + ESP_LOGW(TAG, "BLOCK%d got a coding error", num_block); + } + + correct_written_data = esp_efuse_utility_is_correct_written_data(num_block, r_data_len); + if (!correct_written_data || coding_error_occurred) { + ESP_LOGW(TAG, "BLOCK%d: next retry to fix an error [%d/3]...", num_block, repeat_burn_op); + hal_memcpy((void *)EFUSE_PGM_DATA0_REG, (void *)backup_write_data, sizeof(backup_write_data)); + } + + } while ((!correct_written_data || coding_error_occurred) && repeat_burn_op++ < 3); + + if (coding_error_occurred) { + ESP_LOGW(TAG, "Coding error was not fixed"); + if (num_block == 0) { + ESP_LOGE(TAG, "BLOCK0 got a coding error, which might be critical for security"); + error = ESP_FAIL; + } + } + if (!correct_written_data) { + ESP_LOGE(TAG, "Written data are incorrect"); + error = ESP_FAIL; + } + } + } +#endif // CONFIG_EFUSE_VIRTUAL + esp_efuse_utility_reset(); + return error; +} + +// After esp_efuse_write.. functions EFUSE_BLKx_WDATAx_REG were filled is not coded values. +// This function reads EFUSE_BLKx_WDATAx_REG registers, and checks possible to write these data with RS coding scheme. +// The RS coding scheme does not require data changes for the encoded data. esp32s2 has special registers for this. +// They will be filled during the burn operation. +esp_err_t esp_efuse_utility_apply_new_coding_scheme() +{ + // start with EFUSE_BLK1. EFUSE_BLK0 - always uses EFUSE_CODING_SCHEME_NONE. + for (int num_block = EFUSE_BLK1; num_block < EFUSE_BLK_MAX; num_block++) { + if (esp_efuse_get_coding_scheme(num_block) == EFUSE_CODING_SCHEME_RS) { + for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) { + if (REG_READ(addr_wr_block)) { + int num_reg = 0; + for (uint32_t addr_rd_block = range_read_addr_blocks[num_block].start; addr_rd_block <= range_read_addr_blocks[num_block].end; addr_rd_block += 4, ++num_reg) { + if (esp_efuse_utility_read_reg(num_block, num_reg)) { + ESP_LOGE(TAG, "Bits are not empty. Write operation is forbidden."); + return ESP_ERR_CODING; + } + } + break; + } + } + } + } + return ESP_OK; +} diff --git a/components/efuse/esp32c61/include/esp_efuse_chip.h b/components/efuse/esp32c61/include/esp_efuse_chip.h new file mode 100644 index 0000000000..2bc74db0b5 --- /dev/null +++ b/components/efuse/esp32c61/include/esp_efuse_chip.h @@ -0,0 +1,79 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Type of eFuse blocks ESP32C61 + */ +typedef enum { + EFUSE_BLK0 = 0, /**< Number of eFuse BLOCK0. REPEAT_DATA */ + + EFUSE_BLK1 = 1, /**< Number of eFuse BLOCK1. MAC_SPI_8M_SYS */ + + EFUSE_BLK2 = 2, /**< Number of eFuse BLOCK2. SYS_DATA_PART1 */ + EFUSE_BLK_SYS_DATA_PART1 = 2, /**< Number of eFuse BLOCK2. SYS_DATA_PART1 */ + + EFUSE_BLK3 = 3, /**< Number of eFuse BLOCK3. USER_DATA*/ + EFUSE_BLK_USER_DATA = 3, /**< Number of eFuse BLOCK3. USER_DATA*/ + + EFUSE_BLK4 = 4, /**< Number of eFuse BLOCK4. KEY0 */ + EFUSE_BLK_KEY0 = 4, /**< Number of eFuse BLOCK4. KEY0 */ + + EFUSE_BLK5 = 5, /**< Number of eFuse BLOCK5. KEY1 */ + EFUSE_BLK_KEY1 = 5, /**< Number of eFuse BLOCK5. KEY1 */ + + EFUSE_BLK6 = 6, /**< Number of eFuse BLOCK6. KEY2 */ + EFUSE_BLK_KEY2 = 6, /**< Number of eFuse BLOCK6. KEY2 */ + + EFUSE_BLK7 = 7, /**< Number of eFuse BLOCK7. KEY3 */ + EFUSE_BLK_KEY3 = 7, /**< Number of eFuse BLOCK7. KEY3 */ + + EFUSE_BLK8 = 8, /**< Number of eFuse BLOCK8. KEY4 */ + EFUSE_BLK_KEY4 = 8, /**< Number of eFuse BLOCK8. KEY4 */ + + EFUSE_BLK9 = 9, /**< Number of eFuse BLOCK9. KEY5 */ + EFUSE_BLK_KEY5 = 9, /**< Number of eFuse BLOCK9. KEY5 */ + EFUSE_BLK_KEY_MAX = 10, + + EFUSE_BLK10 = 10, /**< Number of eFuse BLOCK10. SYS_DATA_PART2 */ + EFUSE_BLK_SYS_DATA_PART2 = 10, /**< Number of eFuse BLOCK10. SYS_DATA_PART2 */ + + EFUSE_BLK_MAX +} esp_efuse_block_t; + +/** + * @brief Type of coding scheme + */ +typedef enum { + EFUSE_CODING_SCHEME_NONE = 0, /**< None */ + EFUSE_CODING_SCHEME_RS = 3, /**< Reed-Solomon coding */ +} esp_efuse_coding_scheme_t; + +/** + * @brief Type of key purpose + */ +typedef enum { + ESP_EFUSE_KEY_PURPOSE_USER = 0, /**< User purposes (software-only use) */ + ESP_EFUSE_KEY_PURPOSE_RESERVED = 1, /**< Reserved */ + ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY = 4, /**< XTS_AES_128_KEY (flash/PSRAM encryption) */ + ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL = 5, /**< HMAC Downstream mode */ + ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG = 6, /**< JTAG soft enable key (uses HMAC Downstream mode) */ + ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE = 7, /**< Digital Signature peripheral key (uses HMAC Downstream mode) */ + ESP_EFUSE_KEY_PURPOSE_HMAC_UP = 8, /**< HMAC Upstream mode */ + ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST0 = 9, /**< SECURE_BOOT_DIGEST0 (Secure Boot key digest) */ + ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST1 = 10, /**< SECURE_BOOT_DIGEST1 (Secure Boot key digest) */ + ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST2 = 11, /**< SECURE_BOOT_DIGEST2 (Secure Boot key digest) */ + ESP_EFUSE_KEY_PURPOSE_MAX, /**< MAX PURPOSE */ +} esp_efuse_purpose_t; + +#ifdef __cplusplus +} +#endif diff --git a/components/efuse/esp32c61/include/esp_efuse_rtc_calib.h b/components/efuse/esp32c61/include/esp_efuse_rtc_calib.h new file mode 100644 index 0000000000..925fe4f889 --- /dev/null +++ b/components/efuse/esp32c61/include/esp_efuse_rtc_calib.h @@ -0,0 +1,76 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +// TODO: [ESP32C61] IDF-9282, file inherit from verify code, pls check + +//This is the ADC calibration value version burnt in efuse +#define ESP_EFUSE_ADC_CALIB_VER1 1 +#define ESP_EFUSE_ADC_CALIB_VER2 2 +#define ESP_EFUSE_ADC_CALIB_VER_MIN ESP_EFUSE_ADC_CALIB_VER1 +#define ESP_EFUSE_ADC_CALIB_VER_MAX ESP_EFUSE_ADC_CALIB_VER2 +#define VER2IDX(ver) ((ver) - 1) // Version number to index number of the array +/** + * @brief Get the RTC calibration efuse version + * + * @return Version of the stored efuse + */ +int esp_efuse_rtc_calib_get_ver(void); + +/** + * @brief Get the init code in the efuse, for the corresponding attenuation. + * + * @param version Version of the stored efuse + * @param adc_unit ADC unit. Not used, for compatibility. On esp32c61, for calibration v1, both ADC units use the same init code (calibrated by ADC1) + * @param atten Attenuation of the init code + * @return The init code stored in efuse + */ +uint32_t esp_efuse_rtc_calib_get_init_code(int version, uint32_t adc_unit, int atten); + +/** + * @brief Get the channel specific calibration compensation + * + * @param version Version of the stored efuse + * @param adc_unit ADC unit. Not used, for compatibility. On esp32c61, for calibration v1, both ADC units use the same init code (calibrated by ADC1) + * @param adc_channel ADC channel number + * @param atten Attenuation of the init code + * @return The channel calibration compensation value + */ +int esp_efuse_rtc_calib_get_chan_compens(int version, uint32_t adc_unit, uint32_t adc_channel, int atten); + +/** + * @brief Get the calibration digits stored in the efuse, and the corresponding voltage. + * + * @param version Version of the stored efuse + * @param adc_unit ADC unit (not used on ESP32C6, for compatibility) + * @param atten Attenuation to use + * @param out_digi Output buffer of the digits + * @param out_vol_mv Output of the voltage, in mV + * @return + * - ESP_ERR_INVALID_ARG: If efuse version or attenuation is invalid + * - ESP_OK: if success + */ +esp_err_t esp_efuse_rtc_calib_get_cal_voltage(int version, uint32_t adc_unit, int atten, uint32_t* out_digi, uint32_t* out_vol_mv); + +/** + * @brief Get the temperature sensor calibration number delta_T stored in the efuse. + * + * @param tsens_cal Pointer of the specification of temperature sensor calibration number in efuse. + * + * @return ESP_OK if get the calibration value successfully. + * ESP_ERR_INVALID_ARG if can't get the calibration value. + */ +esp_err_t esp_efuse_rtc_calib_get_tsens_val(float* tsens_cal); + +#ifdef __cplusplus +} +#endif diff --git a/components/efuse/esp32c61/include/esp_efuse_table.h b/components/efuse/esp32c61/include/esp_efuse_table.h new file mode 100644 index 0000000000..694faec0bd --- /dev/null +++ b/components/efuse/esp32c61/include/esp_efuse_table.h @@ -0,0 +1,237 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "esp_efuse.h" + +// TODO: [ESP32C61] IDF-9282, file inherit from verify code, pls check + +// md5_digest_table 873c3e466a4c31bca2e00afae2073f94 +// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. +// If you want to change some fields, you need to change esp_efuse_table.csv file +// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. +// To show efuse_table run the command 'show_efuse_table'. + + +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CRYPT_DPA_ENABLE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SWAP_UART_SDIO_EN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_ICACHE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_JTAG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_ICACHE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_FORCE_DOWNLOAD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_TWAI[]; +#define ESP_EFUSE_WR_DIS_DIS_CAN ESP_EFUSE_WR_DIS_DIS_TWAI +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_JTAG_SEL_ENABLE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_PAD_JTAG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_0[]; +#define ESP_EFUSE_WR_DIS_KEY0_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_0 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_1[]; +#define ESP_EFUSE_WR_DIS_KEY1_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_1 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_2[]; +#define ESP_EFUSE_WR_DIS_KEY2_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_2 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_3[]; +#define ESP_EFUSE_WR_DIS_KEY3_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_3 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_4[]; +#define ESP_EFUSE_WR_DIS_KEY4_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_4 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[]; +#define ESP_EFUSE_WR_DIS_KEY5_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_5 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SEC_DPA_LEVEL[]; +#define ESP_EFUSE_WR_DIS_DPA_SEC_LEVEL ESP_EFUSE_WR_DIS_SEC_DPA_LEVEL +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_DOWNLOAD_MSPI_DIS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TPUW[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[]; +#define ESP_EFUSE_WR_DIS_DIS_USB_PRINT ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ENABLE_SECURITY_DOWNLOAD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_PRINT_CONTROL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_SEND_RESUME[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[]; +#define ESP_EFUSE_WR_DIS_MAC_FACTORY ESP_EFUSE_WR_DIS_MAC +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC_EXT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_CAP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TEMP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_VENDOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP_CALIB[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OCODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH4[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH5[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0_CH6[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[]; +#define ESP_EFUSE_WR_DIS_USER_DATA ESP_EFUSE_WR_DIS_BLOCK_USR_DATA +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[]; +#define ESP_EFUSE_WR_DIS_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC +#define ESP_EFUSE_WR_DIS_USER_DATA_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY0[]; +#define ESP_EFUSE_WR_DIS_KEY0 ESP_EFUSE_WR_DIS_BLOCK_KEY0 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY1[]; +#define ESP_EFUSE_WR_DIS_KEY1 ESP_EFUSE_WR_DIS_BLOCK_KEY1 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY2[]; +#define ESP_EFUSE_WR_DIS_KEY2 ESP_EFUSE_WR_DIS_BLOCK_KEY2 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY3[]; +#define ESP_EFUSE_WR_DIS_KEY3 ESP_EFUSE_WR_DIS_BLOCK_KEY3 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY4[]; +#define ESP_EFUSE_WR_DIS_KEY4 ESP_EFUSE_WR_DIS_BLOCK_KEY4 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY5[]; +#define ESP_EFUSE_WR_DIS_KEY5 ESP_EFUSE_WR_DIS_BLOCK_KEY5 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[]; +#define ESP_EFUSE_WR_DIS_SYS_DATA_PART2 ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_EXCHG_PINS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_AS_GPIO[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY0[]; +#define ESP_EFUSE_RD_DIS_KEY0 ESP_EFUSE_RD_DIS_BLOCK_KEY0 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY1[]; +#define ESP_EFUSE_RD_DIS_KEY1 ESP_EFUSE_RD_DIS_BLOCK_KEY1 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY2[]; +#define ESP_EFUSE_RD_DIS_KEY2 ESP_EFUSE_RD_DIS_BLOCK_KEY2 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY3[]; +#define ESP_EFUSE_RD_DIS_KEY3 ESP_EFUSE_RD_DIS_BLOCK_KEY3 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY4[]; +#define ESP_EFUSE_RD_DIS_KEY4 ESP_EFUSE_RD_DIS_BLOCK_KEY4 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY5[]; +#define ESP_EFUSE_RD_DIS_KEY5 ESP_EFUSE_RD_DIS_BLOCK_KEY5 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[]; +#define ESP_EFUSE_RD_DIS_SYS_DATA_PART2 ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2 +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_DOWNLOAD_MSPI_DIS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_USB_DREFH[]; +extern const esp_efuse_desc_t* ESP_EFUSE_USB_DREFL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_AS_GPIO[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[]; +#define ESP_EFUSE_KEY0_PURPOSE ESP_EFUSE_KEY_PURPOSE_0 +extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[]; +#define ESP_EFUSE_KEY1_PURPOSE ESP_EFUSE_KEY_PURPOSE_1 +extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[]; +#define ESP_EFUSE_KEY2_PURPOSE ESP_EFUSE_KEY_PURPOSE_2 +extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[]; +#define ESP_EFUSE_KEY3_PURPOSE ESP_EFUSE_KEY_PURPOSE_3 +extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[]; +#define ESP_EFUSE_KEY4_PURPOSE ESP_EFUSE_KEY_PURPOSE_4 +extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[]; +#define ESP_EFUSE_KEY5_PURPOSE ESP_EFUSE_KEY_PURPOSE_5 +extern const esp_efuse_desc_t* ESP_EFUSE_SEC_DPA_LEVEL[]; +#define ESP_EFUSE_DPA_SEC_LEVEL ESP_EFUSE_SEC_DPA_LEVEL +extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[]; +#define ESP_EFUSE_DIS_USB_PRINT ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_HYS_EN_PAD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_XTS_DPA_CLK_ENABLE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_XTS_DPA_PSEUDO_LEVEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_MAC[]; +#define ESP_EFUSE_MAC_FACTORY ESP_EFUSE_MAC +extern const esp_efuse_desc_t* ESP_EFUSE_MAC_EXT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_CAP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TEMP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_VENDOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[]; +extern const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[]; +extern const esp_efuse_desc_t* ESP_EFUSE_OCODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH4[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH5[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0_CH6[]; +extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[]; +#define ESP_EFUSE_BLOCK_USR_DATA ESP_EFUSE_USER_DATA +extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[]; +#define ESP_EFUSE_MAC_CUSTOM ESP_EFUSE_USER_DATA_MAC_CUSTOM +#define ESP_EFUSE_CUSTOM_MAC ESP_EFUSE_USER_DATA_MAC_CUSTOM +extern const esp_efuse_desc_t* ESP_EFUSE_KEY0[]; +#define ESP_EFUSE_BLOCK_KEY0 ESP_EFUSE_KEY0 +extern const esp_efuse_desc_t* ESP_EFUSE_KEY1[]; +#define ESP_EFUSE_BLOCK_KEY1 ESP_EFUSE_KEY1 +extern const esp_efuse_desc_t* ESP_EFUSE_KEY2[]; +#define ESP_EFUSE_BLOCK_KEY2 ESP_EFUSE_KEY2 +extern const esp_efuse_desc_t* ESP_EFUSE_KEY3[]; +#define ESP_EFUSE_BLOCK_KEY3 ESP_EFUSE_KEY3 +extern const esp_efuse_desc_t* ESP_EFUSE_KEY4[]; +#define ESP_EFUSE_BLOCK_KEY4 ESP_EFUSE_KEY4 +extern const esp_efuse_desc_t* ESP_EFUSE_KEY5[]; +#define ESP_EFUSE_BLOCK_KEY5 ESP_EFUSE_KEY5 +extern const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[]; +#define ESP_EFUSE_BLOCK_SYS_DATA2 ESP_EFUSE_SYS_DATA_PART2 + +#ifdef __cplusplus +} +#endif diff --git a/components/efuse/esp32c61/private_include/esp_efuse_utility.h b/components/efuse/esp32c61/private_include/esp_efuse_utility.h new file mode 100644 index 0000000000..9752e679df --- /dev/null +++ b/components/efuse/esp32c61/private_include/esp_efuse_utility.h @@ -0,0 +1,21 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#define COUNT_EFUSE_REG_PER_BLOCK 8 /* The number of registers per block. */ + +#define ESP_EFUSE_SECURE_VERSION_NUM_BLOCK EFUSE_BLK0 + +#define ESP_EFUSE_FIELD_CORRESPONDS_CODING_SCHEME(scheme, max_num_bit) + +#ifdef __cplusplus +} +#endif diff --git a/components/efuse/esp32c61/sources.cmake b/components/efuse/esp32c61/sources.cmake new file mode 100644 index 0000000000..9dffd72008 --- /dev/null +++ b/components/efuse/esp32c61/sources.cmake @@ -0,0 +1,4 @@ +set(EFUSE_SOC_SRCS "esp_efuse_table.c" + "esp_efuse_fields.c" + "esp_efuse_rtc_calib.c" + "esp_efuse_utility.c") diff --git a/components/esp_rom/esp32c61/.gitkeep b/components/esp_rom/esp32c61/.gitkeep deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/components/esp_rom/esp32c61/Kconfig.soc_caps.in b/components/esp_rom/esp32c61/Kconfig.soc_caps.in new file mode 100644 index 0000000000..9ea64682e7 --- /dev/null +++ b/components/esp_rom/esp32c61/Kconfig.soc_caps.in @@ -0,0 +1,92 @@ +##################################################### +# This file is auto-generated from SoC caps +# using gen_soc_caps_kconfig.py, do not edit manually +##################################################### + +config ESP_ROM_HAS_CRC_LE + bool + default y + +config ESP_ROM_HAS_CRC_BE + bool + default y + +config ESP_ROM_HAS_JPEG_DECODE + bool + default y + +config ESP_ROM_UART_CLK_IS_XTAL + bool + default y + +config ESP_ROM_USB_SERIAL_DEVICE_NUM + int + default 3 + +config ESP_ROM_HAS_RETARGETABLE_LOCKING + bool + default y + +config ESP_ROM_GET_CLK_FREQ + bool + default y + +config ESP_ROM_HAS_RVFPLIB + bool + default y + +config ESP_ROM_HAS_HAL_WDT + bool + default y + +config ESP_ROM_HAS_HAL_SYSTIMER + bool + default y + +config ESP_ROM_HAS_HEAP_TLSF + bool + default y + +config ESP_ROM_TLSF_CHECK_PATCH + bool + default y + +config ESP_ROM_HAS_LAYOUT_TABLE + bool + default y + +config ESP_ROM_HAS_SPI_FLASH + bool + default y + +config ESP_ROM_HAS_NEWLIB + bool + default y + +config ESP_ROM_HAS_NEWLIB_NANO_FORMAT + bool + default y + +config ESP_ROM_HAS_VERSION + bool + default y + +config ESP_ROM_REV0_HAS_NO_ECDSA_INTERFACE + bool + default y + +config ESP_ROM_WDT_INIT_PATCH + bool + default y + +config ESP_ROM_RAM_APP_NEEDS_MMU_INIT + bool + default y + +config ESP_ROM_HAS_SW_FLOAT + bool + default y + +config ESP_ROM_USB_OTG_NUM + int + default -1 diff --git a/components/esp_rom/esp32c61/esp_rom_caps.h b/components/esp_rom/esp32c61/esp_rom_caps.h new file mode 100644 index 0000000000..f7b73b796e --- /dev/null +++ b/components/esp_rom/esp32c61/esp_rom_caps.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#define ESP_ROM_HAS_CRC_LE (1) // ROM CRC library supports Little Endian +#define ESP_ROM_HAS_CRC_BE (1) // ROM CRC library supports Big Endian +#define ESP_ROM_HAS_JPEG_DECODE (1) // ROM has JPEG decode library +#define ESP_ROM_UART_CLK_IS_XTAL (1) // UART clock source is selected to XTAL in ROM +#define ESP_ROM_USB_SERIAL_DEVICE_NUM (3) // UART uses USB_SERIAL_JTAG port in ROM. +#define ESP_ROM_HAS_RETARGETABLE_LOCKING (1) // ROM was built with retargetable locking +#define ESP_ROM_GET_CLK_FREQ (1) // Get clk frequency with rom function `ets_get_cpu_frequency` +#define ESP_ROM_HAS_RVFPLIB (1) // ROM has the rvfplib +#define ESP_ROM_HAS_HAL_WDT (1) // ROM has the implementation of Watchdog HAL driver +#define ESP_ROM_HAS_HAL_SYSTIMER (1) // ROM has the implementation of Systimer HAL driver +#define ESP_ROM_HAS_HEAP_TLSF (1) // ROM has the implementation of the tlsf and multi-heap library +#define ESP_ROM_TLSF_CHECK_PATCH (1) // ROM does not contain the patch of tlsf_check_pool() +#define ESP_ROM_HAS_LAYOUT_TABLE (1) // ROM has the layout table +#define ESP_ROM_HAS_SPI_FLASH (1) // ROM has the implementation of SPI Flash driver +// TODO: [ESP32C61] IDF-9276, still should be true, temp commented +// #define ESP_ROM_HAS_REGI2C_BUG (1) // ROM has the regi2c bug +#define ESP_ROM_HAS_NEWLIB (1) // ROM has newlib (at least parts of it) functions included +#define ESP_ROM_HAS_NEWLIB_NANO_FORMAT (1) // ROM has the newlib nano version of formatting functions +#define ESP_ROM_HAS_VERSION (1) // ROM has version/eco information +#define ESP_ROM_REV0_HAS_NO_ECDSA_INTERFACE (1) // ECO 0 does not have ets_ecdsa_verify symbol, future revision will have it +#define ESP_ROM_WDT_INIT_PATCH (1) // ROM version does not configure the clock +#define ESP_ROM_RAM_APP_NEEDS_MMU_INIT (1) // ROM doesn't init cache MMU when it's a RAM APP, needs MMU hal to init +#define ESP_ROM_HAS_SW_FLOAT (1) // ROM has libgcc software floating point emulation functions +#define ESP_ROM_USB_OTG_NUM (-1) // No USB_OTG CDC in the ROM, set -1 for Kconfig usage. diff --git a/components/esp_rom/esp32c61/ld/esp32c61.rom.api.ld b/components/esp_rom/esp32c61/ld/esp32c61.rom.api.ld new file mode 100644 index 0000000000..421134e7c2 --- /dev/null +++ b/components/esp_rom/esp32c61/ld/esp32c61.rom.api.ld @@ -0,0 +1,65 @@ +/* + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +/** ROM APIs + */ + +PROVIDE ( esp_rom_crc32_le = crc32_le ); +PROVIDE ( esp_rom_crc16_le = crc16_le ); +PROVIDE ( esp_rom_crc8_le = crc8_le ); +PROVIDE ( esp_rom_crc32_be = crc32_be ); +PROVIDE ( esp_rom_crc16_be = crc16_be ); +PROVIDE ( esp_rom_crc8_be = crc8_be ); + +PROVIDE ( esp_rom_gpio_pad_select_gpio = gpio_pad_select_gpio ); +PROVIDE ( esp_rom_gpio_pad_pullup_only = gpio_pad_pullup ); +PROVIDE ( esp_rom_gpio_pad_set_drv = gpio_pad_set_drv ); +PROVIDE ( esp_rom_gpio_pad_unhold = gpio_pad_unhold ); +PROVIDE ( esp_rom_gpio_connect_in_signal = gpio_matrix_in ); +PROVIDE ( esp_rom_gpio_connect_out_signal = gpio_matrix_out ); + +PROVIDE ( esp_rom_efuse_mac_address_crc8 = esp_crc8 ); +PROVIDE ( esp_rom_efuse_is_secure_boot_enabled = ets_efuse_secure_boot_enabled ); + +PROVIDE ( esp_rom_uart_flush_tx = uart_tx_flush ); +PROVIDE ( esp_rom_uart_tx_one_char = uart_tx_one_char2 ); +PROVIDE ( esp_rom_uart_tx_wait_idle = uart_tx_wait_idle ); +PROVIDE ( esp_rom_uart_rx_one_char = uart_rx_one_char ); +PROVIDE ( esp_rom_uart_rx_string = UartRxString ); +PROVIDE ( esp_rom_uart_set_as_console = uart_tx_switch ); +PROVIDE ( esp_rom_uart_putc = ets_write_char_uart ); + +PROVIDE ( esp_rom_output_flush_tx = uart_tx_flush ); +PROVIDE ( esp_rom_output_tx_one_char = uart_tx_one_char ); +PROVIDE ( esp_rom_output_tx_wait_idle = uart_tx_wait_idle ); +PROVIDE ( esp_rom_output_rx_one_char = uart_rx_one_char ); +PROVIDE ( esp_rom_output_rx_string = UartRxString ); +PROVIDE ( esp_rom_output_set_as_console = uart_tx_switch ); +PROVIDE ( esp_rom_output_putc = ets_write_char_uart ); + +PROVIDE ( esp_rom_md5_init = MD5Init ); +PROVIDE ( esp_rom_md5_update = MD5Update ); +PROVIDE ( esp_rom_md5_final = MD5Final ); + +PROVIDE ( esp_rom_software_reset_system = software_reset ); +PROVIDE ( esp_rom_software_reset_cpu = software_reset_cpu ); + +PROVIDE ( esp_rom_printf = ets_printf ); +PROVIDE ( esp_rom_install_uart_printf = ets_install_uart_printf ); +PROVIDE ( esp_rom_delay_us = ets_delay_us ); +PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason ); +PROVIDE ( esp_rom_route_intr_matrix = intr_matrix_set ); +PROVIDE ( esp_rom_get_cpu_ticks_per_us = ets_get_cpu_frequency ); +PROVIDE ( esp_rom_set_cpu_ticks_per_us = ets_update_cpu_frequency ); + +PROVIDE ( esp_rom_spiflash_attach = spi_flash_attach ); +PROVIDE ( esp_rom_spiflash_clear_bp = esp_rom_spiflash_unlock ); +PROVIDE ( esp_rom_spiflash_write_enable = SPI_write_enable ); +PROVIDE ( esp_rom_spiflash_erase_area = SPIEraseArea ); + +PROVIDE ( esp_rom_spiflash_fix_dummylen = spi_dummy_len_fix ); +PROVIDE ( esp_rom_spiflash_set_drvs = SetSpiDrvs); +PROVIDE ( esp_rom_spiflash_select_padsfunc = SelectSpiFunction ); +PROVIDE ( esp_rom_spiflash_common_cmd = SPI_Common_Command ); diff --git a/components/esp_rom/esp32c61/ld/esp32c61.rom.coexist.ld b/components/esp_rom/esp32c61/ld/esp32c61.rom.coexist.ld new file mode 100644 index 0000000000..9d5a84ce4b --- /dev/null +++ b/components/esp_rom/esp32c61/ld/esp32c61.rom.coexist.ld @@ -0,0 +1,47 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +/* ROM function interface esp32c6lite.rom.coexist.ld for esp32c6lite + * + * + * Generated from ./target/esp32c6lite/interface-esp32c6lite.yml md5sum d875746dfc29a51e6d327cc923b7a095 + * + * Compatible with ROM where ECO version equal or greater to 0. + * + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + */ + +/*************************************** + Group rom_coexist + ***************************************/ + +/* Functions */ +esp_coex_rom_version_get = 0x40000a1c; +coex_bt_release = 0x40000a20; +coex_bt_request = 0x40000a24; +coex_core_ble_conn_dyn_prio_get = 0x40000a28; +coex_core_event_duration_get = 0x40000a2c; +coex_core_pti_get = 0x40000a30; +coex_core_release = 0x40000a34; +coex_core_request = 0x40000a38; +coex_core_status_get = 0x40000a3c; +coex_core_timer_idx_get = 0x40000a40; +coex_event_duration_get = 0x40000a44; +coex_hw_timer_disable = 0x40000a48; +coex_hw_timer_enable = 0x40000a4c; +coex_hw_timer_set = 0x40000a50; +coex_schm_interval_set = 0x40000a54; +coex_schm_lock = 0x40000a58; +coex_schm_unlock = 0x40000a5c; +coex_status_get = 0x40000a60; +coex_wifi_release = 0x40000a64; +esp_coex_ble_conn_dynamic_prio_get = 0x40000a68; +/* Data (.data, .bss, .rodata) */ +coex_env_ptr = 0x4084ffc4; +coex_pti_tab_ptr = 0x4084ffc0; +coex_schm_env_ptr = 0x4084ffbc; +coexist_funcs = 0x4084ffb8; +g_coa_funcs_p = 0x4084ffb4; +g_coex_param_ptr = 0x4084ffb0; diff --git a/components/esp_rom/esp32c61/ld/esp32c61.rom.heap.ld b/components/esp_rom/esp32c61/ld/esp32c61.rom.heap.ld new file mode 100644 index 0000000000..c639285d0b --- /dev/null +++ b/components/esp_rom/esp32c61/ld/esp32c61.rom.heap.ld @@ -0,0 +1,80 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +/* ROM function interface esp32c6lite.rom.heap.ld for esp32c6lite + * + * + * Generated from ./target/esp32c6lite/interface-esp32c6lite.yml md5sum d875746dfc29a51e6d327cc923b7a095 + * + * Compatible with ROM where ECO version equal or greater to 0. + * + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + */ + +/*************************************** + Group heap + ***************************************/ + +/* Functions */ +tlsf_create = 0x4000040c; +tlsf_create_with_pool = 0x40000410; +tlsf_get_pool = 0x40000414; +tlsf_add_pool = 0x40000418; +tlsf_remove_pool = 0x4000041c; +tlsf_malloc = 0x40000420; +tlsf_memalign = 0x40000424; +tlsf_memalign_offs = 0x40000428; +tlsf_realloc = 0x4000042c; +tlsf_free = 0x40000430; +tlsf_block_size = 0x40000434; +tlsf_size = 0x40000438; +tlsf_align_size = 0x4000043c; +tlsf_block_size_min = 0x40000440; +tlsf_block_size_max = 0x40000444; +tlsf_pool_overhead = 0x40000448; +tlsf_alloc_overhead = 0x4000044c; +tlsf_walk_pool = 0x40000450; +tlsf_check = 0x40000454; +tlsf_check_pool = 0x40000458; +tlsf_poison_fill_pfunc_set = 0x4000045c; +tlsf_poison_check_pfunc_set = 0x40000460; +multi_heap_get_block_address_impl = 0x40000464; +multi_heap_get_allocated_size_impl = 0x40000468; +multi_heap_register_impl = 0x4000046c; +multi_heap_set_lock = 0x40000470; +multi_heap_os_funcs_init = 0x40000474; +multi_heap_internal_lock = 0x40000478; +multi_heap_internal_unlock = 0x4000047c; +multi_heap_get_first_block = 0x40000480; +multi_heap_get_next_block = 0x40000484; +multi_heap_is_free = 0x40000488; +multi_heap_malloc_impl = 0x4000048c; +multi_heap_free_impl = 0x40000490; +multi_heap_realloc_impl = 0x40000494; +multi_heap_aligned_alloc_impl_offs = 0x40000498; +multi_heap_aligned_alloc_impl = 0x4000049c; +multi_heap_check = 0x400004a0; +multi_heap_dump = 0x400004a4; +multi_heap_free_size_impl = 0x400004a8; +multi_heap_minimum_free_size_impl = 0x400004ac; +multi_heap_get_info_impl = 0x400004b0; +/* Data (.data, .bss, .rodata) */ +heap_tlsf_table_ptr = 0x4084ffd8; + +PROVIDE (multi_heap_malloc = multi_heap_malloc_impl); +PROVIDE (multi_heap_free = multi_heap_free_impl); +PROVIDE (multi_heap_realloc = multi_heap_realloc_impl); +PROVIDE (multi_heap_get_allocated_size = multi_heap_get_allocated_size_impl); +PROVIDE (multi_heap_register = multi_heap_register_impl); +PROVIDE (multi_heap_get_info = multi_heap_get_info_impl); +PROVIDE (multi_heap_free_size = multi_heap_free_size_impl); +PROVIDE (multi_heap_minimum_free_size = multi_heap_minimum_free_size_impl); +PROVIDE (multi_heap_get_block_address = multi_heap_get_block_address_impl); +PROVIDE (multi_heap_aligned_alloc = multi_heap_aligned_alloc_impl); +PROVIDE (multi_heap_aligned_free = multi_heap_aligned_free_impl); +PROVIDE (multi_heap_check = multi_heap_check); +PROVIDE (multi_heap_set_lock = multi_heap_set_lock); +PROVIDE (multi_heap_internal_lock = multi_heap_internal_lock); +PROVIDE (multi_heap_internal_unlock = multi_heap_internal_unlock); diff --git a/components/esp_rom/esp32c61/ld/esp32c61.rom.ld b/components/esp_rom/esp32c61/ld/esp32c61.rom.ld new file mode 100644 index 0000000000..e5489aa013 --- /dev/null +++ b/components/esp_rom/esp32c61/ld/esp32c61.rom.ld @@ -0,0 +1,376 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +/* ROM function interface esp32c6lite.rom.ld for esp32c6lite + * + * + * Generated from ./target/esp32c6lite/interface-esp32c6lite.yml md5sum d875746dfc29a51e6d327cc923b7a095 + * + * Compatible with ROM where ECO version equal or greater to 0. + * + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + */ + +/*************************************** + Group common + ***************************************/ + +/* Functions */ +rtc_get_reset_reason = 0x40000018; +rtc_get_wakeup_cause = 0x4000001c; +pmu_enable_unhold_pads = 0x40000020; +ets_printf = 0x40000024; +ets_install_putc1 = 0x40000028; +ets_install_putc2 = 0x4000002c; +ets_install_uart_printf = 0x40000030; +ets_install_usb_printf = 0x40000034; +ets_get_printf_channel = 0x40000038; +ets_delay_us = 0x4000003c; +ets_get_cpu_frequency = 0x40000040; +ets_update_cpu_frequency = 0x40000044; +ets_install_lock = 0x40000048; +UartRxString = 0x4000004c; +UartGetCmdLn = 0x40000050; +uart_tx_one_char = 0x40000054; +uart_tx_one_char2 = 0x40000058; +uart_tx_one_char3 = 0x4000005c; +uart_rx_one_char = 0x40000060; +uart_rx_one_char_block = 0x40000064; +uart_rx_intr_handler = 0x40000068; +uart_rx_readbuff = 0x4000006c; +uartAttach = 0x40000070; +uart_tx_flush = 0x40000074; +uart_tx_wait_idle = 0x40000078; +uart_div_modify = 0x4000007c; +ets_write_char_uart = 0x40000080; +uart_tx_switch = 0x40000084; +uart_buff_switch = 0x40000088; +roundup2 = 0x4000008c; +multofup = 0x40000090; +software_reset = 0x40000094; +software_reset_cpu = 0x40000098; +ets_clk_assist_debug_clock_enable = 0x4000009c; +clear_super_wdt_reset_flag = 0x400000a0; +disable_default_watchdog = 0x400000a4; +esp_rom_set_rtc_wake_addr = 0x400000a8; +esp_rom_get_rtc_wake_addr = 0x400000ac; +send_packet = 0x400000b0; +recv_packet = 0x400000b4; +GetUartDevice = 0x400000b8; +UartDwnLdProc = 0x400000bc; +GetSecurityInfoProc = 0x400000c0; +Uart_Init = 0x400000c4; +ets_set_user_start = 0x400000c8; +/* Data (.data, .bss, .rodata) */ +ets_rom_layout_p = 0x4003fffc; +ets_ops_table_ptr = 0x4084fff8; +g_saved_pc = 0x4084fffc; + + +/*************************************** + Group miniz + ***************************************/ + +/* Functions */ +mz_adler32 = 0x400000cc; +mz_free = 0x400000d0; +tdefl_compress = 0x400000d4; +tdefl_compress_buffer = 0x400000d8; +tdefl_compress_mem_to_heap = 0x400000dc; +tdefl_compress_mem_to_mem = 0x400000e0; +tdefl_compress_mem_to_output = 0x400000e4; +tdefl_get_adler32 = 0x400000e8; +tdefl_get_prev_return_status = 0x400000ec; +tdefl_init = 0x400000f0; +tdefl_write_image_to_png_file_in_memory = 0x400000f4; +tdefl_write_image_to_png_file_in_memory_ex = 0x400000f8; +tinfl_decompress = 0x400000fc; +tinfl_decompress_mem_to_callback = 0x40000100; +tinfl_decompress_mem_to_heap = 0x40000104; +tinfl_decompress_mem_to_mem = 0x40000108; + + +/*************************************** + Group tjpgd + ***************************************/ + +/* Functions */ +jd_prepare = 0x4000010c; +jd_decomp = 0x40000110; + + +/*************************************** + Group spi_extmem_common + ***************************************/ + +/* Functions */ +esp_rom_spi_cmd_config = 0x40000114; +esp_rom_spi_cmd_start = 0x40000118; +esp_rom_spi_set_op_mode = 0x4000011c; + + +/*************************************** + Group spiflash_legacy + ***************************************/ + +/* Functions */ +esp_rom_spiflash_wait_idle = 0x40000120; +esp_rom_spiflash_write_encrypted = 0x40000124; +esp_rom_spiflash_write_encrypted_dest = 0x40000128; +esp_rom_spiflash_write_encrypted_enable = 0x4000012c; +esp_rom_spiflash_write_encrypted_disable = 0x40000130; +esp_rom_spiflash_erase_chip = 0x40000134; +_esp_rom_spiflash_erase_sector = 0x40000138; +_esp_rom_spiflash_erase_block = 0x4000013c; +_esp_rom_spiflash_write = 0x40000140; +_esp_rom_spiflash_read = 0x40000144; +_esp_rom_spiflash_unlock = 0x40000148; +_SPIEraseArea = 0x4000014c; +_SPI_write_enable = 0x40000150; +esp_rom_spiflash_erase_sector = 0x40000154; +esp_rom_spiflash_erase_block = 0x40000158; +esp_rom_spiflash_write = 0x4000015c; +esp_rom_spiflash_read = 0x40000160; +esp_rom_spiflash_unlock = 0x40000164; +SPIEraseArea = 0x40000168; +SPI_write_enable = 0x4000016c; +esp_rom_spiflash_config_param = 0x40000170; +esp_rom_spiflash_read_user_cmd = 0x40000174; +esp_rom_spiflash_select_qio_pins = 0x40000178; +esp_rom_spi_flash_auto_sus_res = 0x4000017c; +esp_rom_spi_flash_send_resume = 0x40000180; +esp_rom_spi_flash_update_id = 0x40000184; +esp_rom_spiflash_config_clk = 0x40000188; +esp_rom_spiflash_config_readmode = 0x4000018c; +esp_rom_spiflash_read_status = 0x40000190; +esp_rom_spiflash_read_statushigh = 0x40000194; +esp_rom_spiflash_write_status = 0x40000198; +esp_rom_spiflash_write_disable = 0x4000019c; +spi_cache_mode_switch = 0x400001a0; +spi_common_set_dummy_output = 0x400001a4; +spi_common_set_flash_cs_timing = 0x400001a8; +esp_rom_spi_set_address_bit_len = 0x400001ac; +SPILock = 0x400001b0; +SPIMasterReadModeCnfig = 0x400001b4; +SPI_Common_Command = 0x400001b8; +SPI_WakeUp = 0x400001bc; +SPI_block_erase = 0x400001c0; +SPI_chip_erase = 0x400001c4; +SPI_init = 0x400001c8; +SPI_page_program = 0x400001cc; +SPI_read_data = 0x400001d0; +SPI_sector_erase = 0x400001d4; +SelectSpiFunction = 0x400001d8; +SetSpiDrvs = 0x400001dc; +Wait_SPI_Idle = 0x400001e0; +spi_dummy_len_fix = 0x400001e4; +Disable_QMode = 0x400001e8; +Enable_QMode = 0x400001ec; +spi_flash_attach = 0x400001f0; +spi_flash_get_chip_size = 0x400001f4; +spi_flash_guard_set = 0x400001f8; +spi_flash_guard_get = 0x400001fc; +spi_flash_read_encrypted = 0x40000200; +/* Data (.data, .bss, .rodata) */ +rom_spiflash_legacy_funcs = 0x4084fff0; +rom_spiflash_legacy_data = 0x4084ffec; +g_flash_guard_ops = 0x4084fff4; + + +/*************************************** + Group cache + ***************************************/ + +/* Functions */ +Cache_Get_Line_Size = 0x40000614; +Cache_Get_Mode = 0x40000618; +Cache_Address_Through_Cache = 0x4000061c; +ROM_Boot_Cache_Init = 0x40000620; +MMU_Set_Page_Mode = 0x40000624; +MMU_Get_Page_Mode = 0x40000628; +Cache_Sync_Items = 0x4000062c; +Cache_Op_Addr = 0x40000630; +Cache_Invalidate_Addr = 0x40000634; +Cache_Clean_Addr = 0x40000638; +Cache_WriteBack_Addr = 0x4000063c; +Cache_WriteBack_Invalidate_Addr = 0x40000640; +Cache_Invalidate_All = 0x40000644; +Cache_Clean_All = 0x40000648; +Cache_WriteBack_All = 0x4000064c; +Cache_WriteBack_Invalidate_All = 0x40000650; +Cache_Mask_All = 0x40000654; +Cache_UnMask_Dram0 = 0x40000658; +Cache_Suspend_Autoload = 0x4000065c; +Cache_Resume_Autoload = 0x40000660; +Cache_Start_Preload = 0x40000664; +Cache_Preload_Done = 0x40000668; +Cache_End_Preload = 0x4000066c; +Cache_Config_Autoload = 0x40000670; +Cache_Enable_Autoload = 0x40000674; +Cache_Disable_Autoload = 0x40000678; +Cache_Enable_PreLock = 0x4000067c; +Cache_Disable_PreLock = 0x40000680; +Cache_Lock_Items = 0x40000684; +Cache_Lock_Addr = 0x40000688; +Cache_Unlock_Addr = 0x4000068c; +Cache_Disable_Cache = 0x40000690; +Cache_Enable_Cache = 0x40000694; +Cache_Suspend_Cache = 0x40000698; +Cache_Resume_Cache = 0x4000069c; +Cache_Freeze_Enable = 0x400006a0; +Cache_Freeze_Disable = 0x400006a4; +Cache_Set_IDROM_MMU_Size = 0x400006a8; +Cache_Get_IROM_MMU_End = 0x400006ac; +Cache_Get_DROM_MMU_End = 0x400006b0; +Cache_MMU_Init = 0x400006b4; +Cache_MSPI_MMU_Set = 0x400006b8; +Cache_MSPI_MMU_Set_Secure = 0x400006bc; +Cache_Count_Flash_Pages = 0x400006c0; +Cache_Travel_Tag_Memory = 0x400006c4; +Cache_Get_Virtual_Addr = 0x400006c8; +Cache_Flash_To_SPIRAM_Copy = 0x400006cc; +/* Data (.data, .bss, .rodata) */ +rom_cache_op_cb = 0x4084ffcc; +rom_cache_internal_table_ptr = 0x4084ffc8; + + +/*************************************** + Group clock + ***************************************/ + +/* Functions */ +ets_clk_get_xtal_freq = 0x400006d0; +ets_clk_get_cpu_freq = 0x400006d4; + + +/*************************************** + Group gpio + ***************************************/ + +/* Functions */ +gpio_set_output_level = 0x400006d8; +gpio_get_input_level = 0x400006dc; +gpio_matrix_in = 0x400006e0; +gpio_matrix_out = 0x400006e4; +gpio_bypass_matrix_in = 0x400006e8; +gpio_output_disable = 0x400006ec; +gpio_output_enable = 0x400006f0; +gpio_pad_input_disable = 0x400006f4; +gpio_pad_input_enable = 0x400006f8; +gpio_pad_pulldown = 0x400006fc; +gpio_pad_pullup = 0x40000700; +gpio_pad_select_gpio = 0x40000704; +gpio_pad_set_drv = 0x40000708; +gpio_pad_unhold = 0x4000070c; +gpio_pad_hold = 0x40000710; + + +/*************************************** + Group interrupts + ***************************************/ + +/* Functions */ +esprv_intc_int_set_priority = 0x40000714; +esprv_intc_int_set_threshold = 0x40000718; +esprv_intc_int_enable = 0x4000071c; +esprv_intc_int_disable = 0x40000720; +esprv_intc_int_set_type = 0x40000724; +PROVIDE( intr_handler_set = 0x40000728 ); +intr_matrix_set = 0x4000072c; +ets_intr_register_ctx = 0x40000730; +ets_intr_lock = 0x40000734; +ets_intr_unlock = 0x40000738; +ets_isr_attach = 0x4000073c; +ets_isr_mask = 0x40000740; +ets_isr_unmask = 0x40000744; + + +/*************************************** + Group crypto + ***************************************/ + +/* Functions */ +md5_vector = 0x40000748; +MD5Init = 0x4000074c; +MD5Update = 0x40000750; +MD5Final = 0x40000754; +crc32_le = 0x40000758; +crc16_le = 0x4000075c; +crc8_le = 0x40000760; +crc32_be = 0x40000764; +crc16_be = 0x40000768; +crc8_be = 0x4000076c; +esp_crc8 = 0x40000770; +ets_sha_enable = 0x40000774; +ets_sha_disable = 0x40000778; +ets_sha_get_state = 0x4000077c; +ets_sha_init = 0x40000780; +ets_sha_process = 0x40000784; +ets_sha_starts = 0x40000788; +ets_sha_update = 0x4000078c; +ets_sha_finish = 0x40000790; +ets_sha_clone = 0x40000794; +/* Data (.data, .bss, .rodata) */ +crc32_le_table_ptr = 0x4003fff8; +crc16_le_table_ptr = 0x4003fff4; +crc8_le_table_ptr = 0x4003fff0; +crc32_be_table_ptr = 0x4003ffec; +crc16_be_table_ptr = 0x4003ffe8; +crc8_be_table_ptr = 0x4003ffe4; + + +/*************************************** + Group efuse + ***************************************/ + +/* Functions */ +ets_efuse_read = 0x40000798; +ets_efuse_program = 0x4000079c; +ets_efuse_clear_program_registers = 0x400007a0; +ets_efuse_write_key = 0x400007a4; +ets_efuse_get_read_register_address = 0x400007a8; +ets_efuse_get_key_purpose = 0x400007ac; +ets_efuse_key_block_unused = 0x400007b0; +ets_efuse_find_unused_key_block = 0x400007b4; +ets_efuse_rs_calculate = 0x400007b8; +ets_efuse_count_unused_key_blocks = 0x400007bc; +ets_efuse_secure_boot_enabled = 0x400007c0; +ets_efuse_secure_boot_aggressive_revoke_enabled = 0x400007c4; +ets_efuse_cache_encryption_enabled = 0x400007c8; +ets_efuse_download_modes_disabled = 0x400007cc; +ets_efuse_find_purpose = 0x400007d0; +ets_efuse_force_send_resume = 0x400007d4; +ets_efuse_get_flash_delay_us = 0x400007d8; +ets_efuse_get_uart_print_control = 0x400007dc; +ets_efuse_direct_boot_mode_disabled = 0x400007e0; +ets_efuse_security_download_modes_enabled = 0x400007e4; +ets_efuse_jtag_disabled = 0x400007e8; +ets_efuse_usb_print_is_disabled = 0x400007ec; +ets_efuse_usb_download_mode_disabled = 0x400007f0; +ets_efuse_usb_device_disabled = 0x400007f4; +ets_efuse_secure_boot_fast_wake_enabled = 0x400007f8; + + +/*************************************** + Group secureboot + ***************************************/ + +/* Functions */ +ets_ecdsa_verify = 0x400007fc; +ets_secure_boot_verify_bootloader_with_keys = 0x40000800; +ets_secure_boot_verify_signature = 0x40000804; +ets_secure_boot_read_key_digests = 0x40000808; +ets_secure_boot_revoke_public_key_digest = 0x4000080c; + + +/*************************************** + Group usb_device_uart + ***************************************/ + +/* Functions */ +usb_serial_device_rx_one_char = 0x40000a0c; +usb_serial_device_rx_one_char_block = 0x40000a10; +usb_serial_device_tx_flush = 0x40000a14; +usb_serial_device_tx_one_char = 0x40000a18; diff --git a/components/esp_rom/esp32c61/ld/esp32c61.rom.libgcc.ld b/components/esp_rom/esp32c61/ld/esp32c61.rom.libgcc.ld new file mode 100644 index 0000000000..144dbc6776 --- /dev/null +++ b/components/esp_rom/esp32c61/ld/esp32c61.rom.libgcc.ld @@ -0,0 +1,119 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +/* ROM function interface esp32c6lite.rom.libgcc.ld for esp32c6lite + * + * + * Generated from ./target/esp32c6lite/interface-esp32c6lite.yml md5sum d875746dfc29a51e6d327cc923b7a095 + * + * Compatible with ROM where ECO version equal or greater to 0. + * + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + */ + +/*************************************** + Group libgccsf + ***************************************/ + +/* Functions */ +__addsf3 = 0x40000810; +__divsf3 = 0x40000814; +__eqsf2 = 0x40000818; +__fixsfsi = 0x4000081c; +__floatsisf = 0x40000820; +__floatunsisf = 0x40000824; +__gesf2 = 0x40000828; +__gtsf2 = 0x4000082c; +__lesf2 = 0x40000830; +__ltsf2 = 0x40000834; +__mulsf3 = 0x40000838; +__negsf2 = 0x4000083c; +__nesf2 = 0x40000840; +__powisf2 = 0x40000844; +__subsf3 = 0x40000848; +__truncdfsf2 = 0x4000084c; +__unordsf2 = 0x40000850; + + +/*************************************** + Group libgccdf + ***************************************/ + +/* Functions */ +__absvdi2 = 0x40000854; +__absvsi2 = 0x40000858; +__adddf3 = 0x4000085c; +__addvdi3 = 0x40000860; +__addvsi3 = 0x40000864; +__ashldi3 = 0x40000868; +__ashrdi3 = 0x4000086c; +__bswapdi2 = 0x40000870; +__bswapsi2 = 0x40000874; +__clear_cache = 0x40000878; +__clrsbdi2 = 0x4000087c; +__clrsbsi2 = 0x40000880; +__clzdi2 = 0x40000884; +__clzsi2 = 0x40000888; +__cmpdi2 = 0x4000088c; +__ctzdi2 = 0x40000890; +__ctzsi2 = 0x40000894; +__divdc3 = 0x40000898; +__divdf3 = 0x4000089c; +__divdi3 = 0x400008a0; +__divsc3 = 0x400008a4; +__divsi3 = 0x400008a8; +__eqdf2 = 0x400008ac; +__extendsfdf2 = 0x400008b0; +__ffsdi2 = 0x400008b4; +__ffssi2 = 0x400008b8; +__fixdfdi = 0x400008bc; +__fixdfsi = 0x400008c0; +__fixsfdi = 0x400008c4; +__fixunsdfsi = 0x400008c8; +__fixunssfdi = 0x400008cc; +__fixunssfsi = 0x400008d0; +__floatdidf = 0x400008d4; +__floatdisf = 0x400008d8; +__floatsidf = 0x400008dc; +__floatundidf = 0x400008e0; +__floatundisf = 0x400008e4; +__floatunsidf = 0x400008e8; +__gcc_bcmp = 0x400008ec; +__gedf2 = 0x400008f0; +__gtdf2 = 0x400008f4; +__ledf2 = 0x400008f8; +__lshrdi3 = 0x400008fc; +__ltdf2 = 0x40000900; +__moddi3 = 0x40000904; +__modsi3 = 0x40000908; +__muldc3 = 0x4000090c; +__muldf3 = 0x40000910; +__muldi3 = 0x40000914; +__mulsc3 = 0x40000918; +__mulsi3 = 0x4000091c; +__mulvdi3 = 0x40000920; +__mulvsi3 = 0x40000924; +__nedf2 = 0x40000928; +__negdf2 = 0x4000092c; +__negdi2 = 0x40000930; +__negvdi2 = 0x40000934; +__negvsi2 = 0x40000938; +__paritysi2 = 0x4000093c; +__popcountdi2 = 0x40000940; +__popcountsi2 = 0x40000944; +__powidf2 = 0x40000948; +__subdf3 = 0x4000094c; +__subvdi3 = 0x40000950; +__subvsi3 = 0x40000954; +__ucmpdi2 = 0x40000958; +__udivdi3 = 0x4000095c; +__udivmoddi4 = 0x40000960; +__udivsi3 = 0x40000964; +__udiv_w_sdiv = 0x40000968; +__umoddi3 = 0x4000096c; +__umodsi3 = 0x40000970; +__unorddf2 = 0x40000974; +__extenddftf2 = 0x40000978; +__trunctfdf2 = 0x4000097c; diff --git a/components/esp_rom/esp32c61/ld/esp32c61.rom.net80211.ld b/components/esp_rom/esp32c61/ld/esp32c61.rom.net80211.ld new file mode 100644 index 0000000000..800f1f3c04 --- /dev/null +++ b/components/esp_rom/esp32c61/ld/esp32c61.rom.net80211.ld @@ -0,0 +1,65 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +/* ROM function interface esp32c6lite.rom.net80211.ld for esp32c6lite + * + * + * Generated from ./target/esp32c6lite/interface-esp32c6lite.yml md5sum d875746dfc29a51e6d327cc923b7a095 + * + * Compatible with ROM where ECO version equal or greater to 0. + * + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + */ + +/*************************************** + Group rom_net80211 + ***************************************/ + +/* Functions */ +esp_net80211_rom_version_get = 0x40000a6c; +ampdu_dispatch = 0x40000a70; +ampdu_dispatch_all = 0x40000a74; +ampdu_dispatch_as_many_as_possible = 0x40000a78; +ampdu_dispatch_movement = 0x40000a7c; +ampdu_dispatch_upto = 0x40000a80; +chm_is_at_home_channel = 0x40000a84; +cnx_node_is_existing = 0x40000a88; +cnx_node_search = 0x40000a8c; +ic_ebuf_recycle_rx = 0x40000a90; +ic_ebuf_recycle_tx = 0x40000a94; +ic_reset_rx_ba = 0x40000a98; +ieee80211_align_eb = 0x40000a9c; +ieee80211_ampdu_reorder = 0x40000aa0; +ieee80211_ampdu_start_age_timer = 0x40000aa4; +ieee80211_encap_esfbuf = 0x40000aa8; +ieee80211_is_tx_allowed = 0x40000aac; +ieee80211_output_pending_eb = 0x40000ab0; +ieee80211_output_process = 0x40000ab4; +ieee80211_set_tx_desc = 0x40000ab8; +sta_input = 0x40000abc; +wifi_get_macaddr = 0x40000ac0; +wifi_rf_phy_disable = 0x40000ac4; +wifi_rf_phy_enable = 0x40000ac8; +ic_ebuf_alloc = 0x40000acc; +ieee80211_classify = 0x40000ad0; +ieee80211_copy_eb_header = 0x40000ad4; +ieee80211_recycle_cache_eb = 0x40000ad8; +ieee80211_search_node = 0x40000adc; +ieee80211_crypto_encap = 0x40000ae0; +ieee80211_crypto_decap = 0x40000ae4; +ieee80211_decap = 0x40000ae8; +ieee80211_set_tx_pti = 0x40000aec; +wifi_is_started = 0x40000af0; +ieee80211_gettid = 0x40000af4; +/* Data (.data, .bss, .rodata) */ +net80211_funcs = 0x4084ffac; +g_scan = 0x4084ffa8; +g_chm = 0x4084ffa4; +g_ic_ptr = 0x4084ffa0; +g_hmac_cnt_ptr = 0x4084ff9c; +g_tx_cacheq_ptr = 0x4084ff98; +s_netstack_free = 0x4084ff94; +mesh_rxcb = 0x4084ff90; +sta_rxcb = 0x4084ff8c; diff --git a/components/esp_rom/esp32c61/ld/esp32c61.rom.newlib-nano.ld b/components/esp_rom/esp32c61/ld/esp32c61.rom.newlib-nano.ld new file mode 100644 index 0000000000..2f024e3ef0 --- /dev/null +++ b/components/esp_rom/esp32c61/ld/esp32c61.rom.newlib-nano.ld @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +/* ROM function interface esp32c6lite.rom.newlib-nano.ld for esp32c6lite + * + * + * Generated from ./target/esp32c6lite/interface-esp32c6lite.yml md5sum d875746dfc29a51e6d327cc923b7a095 + * + * Compatible with ROM where ECO version equal or greater to 0. + * + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + */ + +/*************************************** + Group newlib_nano_format + ***************************************/ + +/* Functions */ +__sprint_r = 0x400005e4; +_fiprintf_r = 0x400005e8; +_fprintf_r = 0x400005ec; +_printf_common = 0x400005f0; +_printf_i = 0x400005f4; +_vfiprintf_r = 0x400005f8; +_vfprintf_r = 0x400005fc; +fiprintf = 0x40000600; +fprintf = 0x40000604; +printf = 0x40000608; +vfiprintf = 0x4000060c; +vfprintf = 0x40000610; diff --git a/components/esp_rom/esp32c61/ld/esp32c61.rom.newlib.ld b/components/esp_rom/esp32c61/ld/esp32c61.rom.newlib.ld new file mode 100644 index 0000000000..5bf4d78eca --- /dev/null +++ b/components/esp_rom/esp32c61/ld/esp32c61.rom.newlib.ld @@ -0,0 +1,99 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +/* ROM function interface esp32c6lite.rom.newlib.ld for esp32c6lite + * + * + * Generated from ./target/esp32c6lite/interface-esp32c6lite.yml md5sum d875746dfc29a51e6d327cc923b7a095 + * + * Compatible with ROM where ECO version equal or greater to 0. + * + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + */ + +/*************************************** + Group newlib + ***************************************/ + +/* Functions */ +esp_rom_newlib_init_common_mutexes = 0x400004b4; +memset = 0x400004b8; +memcpy = 0x400004bc; +memmove = 0x400004c0; +memcmp = 0x400004c4; +strcpy = 0x400004c8; +strncpy = 0x400004cc; +strcmp = 0x400004d0; +strncmp = 0x400004d4; +strlen = 0x400004d8; +strstr = 0x400004dc; +bzero = 0x400004e0; +_isatty_r = 0x400004e4; +sbrk = 0x400004e8; +isalnum = 0x400004ec; +isalpha = 0x400004f0; +isascii = 0x400004f4; +isblank = 0x400004f8; +iscntrl = 0x400004fc; +isdigit = 0x40000500; +islower = 0x40000504; +isgraph = 0x40000508; +isprint = 0x4000050c; +ispunct = 0x40000510; +isspace = 0x40000514; +isupper = 0x40000518; +toupper = 0x4000051c; +tolower = 0x40000520; +toascii = 0x40000524; +memccpy = 0x40000528; +memchr = 0x4000052c; +memrchr = 0x40000530; +strcasecmp = 0x40000534; +strcasestr = 0x40000538; +strcat = 0x4000053c; +strdup = 0x40000540; +strchr = 0x40000544; +strcspn = 0x40000548; +strcoll = 0x4000054c; +strlcat = 0x40000550; +strlcpy = 0x40000554; +strlwr = 0x40000558; +strncasecmp = 0x4000055c; +strncat = 0x40000560; +strndup = 0x40000564; +strnlen = 0x40000568; +strrchr = 0x4000056c; +strsep = 0x40000570; +strspn = 0x40000574; +strtok_r = 0x40000578; +strupr = 0x4000057c; +longjmp = 0x40000580; +setjmp = 0x40000584; +abs = 0x40000588; +div = 0x4000058c; +labs = 0x40000590; +ldiv = 0x40000594; +qsort = 0x40000598; +rand_r = 0x4000059c; +rand = 0x400005a0; +srand = 0x400005a4; +utoa = 0x400005a8; +itoa = 0x400005ac; +atoi = 0x400005b0; +atol = 0x400005b4; +strtol = 0x400005b8; +strtoul = 0x400005bc; +fflush = 0x400005c0; +_fflush_r = 0x400005c4; +_fwalk = 0x400005c8; +_fwalk_reent = 0x400005cc; +__smakebuf_r = 0x400005d0; +__swhatbuf_r = 0x400005d4; +__swbuf_r = 0x400005d8; +__swbuf = 0x400005dc; +__swsetup_r = 0x400005e0; +/* Data (.data, .bss, .rodata) */ +syscall_table_ptr = 0x4084ffd4; +_global_impure_ptr = 0x4084ffd0; diff --git a/components/esp_rom/esp32c61/ld/esp32c61.rom.phy.ld b/components/esp_rom/esp32c61/ld/esp32c61.rom.phy.ld new file mode 100644 index 0000000000..24f801103d --- /dev/null +++ b/components/esp_rom/esp32c61/ld/esp32c61.rom.phy.ld @@ -0,0 +1,196 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +/* ROM function interface esp32c6lite.rom.phy.ld for esp32c6lite + * + * + * Generated from ./target/esp32c6lite/interface-esp32c6lite.yml md5sum d875746dfc29a51e6d327cc923b7a095 + * + * Compatible with ROM where ECO version equal or greater to 0. + * + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + */ + +/*************************************** + Group rom_phy + ***************************************/ + +/* Functions */ +phy_get_romfuncs = 0x40000d68; +rom_abs_temp = 0x40000d6c; +rom_bb_bss_cbw40_dig = 0x40000d70; +rom_bb_wdg_test_en = 0x40000d74; +rom_bb_wdt_get_status = 0x40000d78; +rom_bb_wdt_int_enable = 0x40000d7c; +rom_bb_wdt_rst_enable = 0x40000d80; +rom_bb_wdt_timeout_clear = 0x40000d84; +rom_cbw2040_cfg = 0x40000d88; +rom_check_noise_floor = 0x40000d8c; +rom_chip_i2c_readReg = 0x40000d90; +rom_chip_i2c_writeReg = 0x40000d94; +rom_correct_rf_ana_gain = 0x40000d98; +rom_dc_iq_est = 0x40000d9c; +rom_disable_agc = 0x40000da0; +rom_en_pwdet = 0x40000da4; +rom_enable_agc = 0x40000da8; +rom_get_bbgain_db = 0x40000dac; +rom_get_data_sat = 0x40000db0; +rom_get_i2c_read_mask = 0x40000db4; +rom_get_pwctrl_correct = 0x40000db8; +rom_get_rf_gain_qdb = 0x40000dbc; +rom_i2c_readReg = 0x40000dc0; +rom_i2c_readReg_Mask = 0x40000dc4; +rom_i2c_writeReg = 0x40000dc8; +rom_i2c_writeReg_Mask = 0x40000dcc; +rom_index_to_txbbgain = 0x40000dd0; +rom_iq_est_disable = 0x40000dd4; +rom_iq_est_enable = 0x40000dd8; +rom_linear_to_db = 0x40000ddc; +rom_loopback_mode_en = 0x40000de0; +rom_mhz2ieee = 0x40000de4; +rom_noise_floor_auto_set = 0x40000de8; +rom_pbus_debugmode = 0x40000dec; +rom_pbus_force_mode = 0x40000df0; +rom_pbus_force_test = 0x40000df4; +rom_pbus_rd = 0x40000df8; +rom_pbus_rd_addr = 0x40000dfc; +rom_pbus_rd_shift = 0x40000e00; +rom_pbus_set_dco = 0x40000e04; +rom_pbus_set_rxgain = 0x40000e08; +rom_pbus_workmode = 0x40000e0c; +rom_pbus_xpd_rx_off = 0x40000e10; +rom_pbus_xpd_rx_on = 0x40000e14; +rom_pbus_xpd_tx_off = 0x40000e18; +rom_pbus_xpd_tx_on = 0x40000e1c; +rom_phy_byte_to_word = 0x40000e20; +rom_phy_disable_cca = 0x40000e24; +rom_phy_enable_cca = 0x40000e28; +rom_phy_get_noisefloor = 0x40000e2c; +rom_phy_get_rx_freq = 0x40000e30; +rom_phy_set_bbfreq_init = 0x40000e34; +rom_pow_usr = 0x40000e38; +rom_pwdet_sar2_init = 0x40000e3c; +rom_read_hw_noisefloor = 0x40000e40; +rom_read_sar_dout = 0x40000e44; +rom_set_cal_rxdc = 0x40000e48; +rom_set_chan_cal_interp = 0x40000e4c; +rom_set_loopback_gain = 0x40000e50; +rom_set_noise_floor = 0x40000e54; +rom_set_rxclk_en = 0x40000e58; +rom_set_tx_dig_gain = 0x40000e5c; +rom_set_txcap_reg = 0x40000e60; +rom_set_txclk_en = 0x40000e64; +rom_spur_cal = 0x40000e68; +rom_spur_reg_write_one_tone = 0x40000e6c; +rom_target_power_add_backoff = 0x40000e70; +rom_tx_pwctrl_bg_init = 0x40000e74; +rom_txbbgain_to_index = 0x40000e78; +rom_wifi_11g_rate_chg = 0x40000e7c; +rom_write_gain_mem = 0x40000e80; +chip726_phyrom_version = 0x40000e84; +rom_disable_wifi_agc = 0x40000e88; +rom_enable_wifi_agc = 0x40000e8c; +rom_set_tx_gain_table = 0x40000e90; +rom_bt_index_to_bb = 0x40000e94; +rom_bt_bb_to_index = 0x40000e98; +rom_wr_bt_tx_atten = 0x40000e9c; +rom_wr_bt_tx_gain_mem = 0x40000ea0; +rom_spur_coef_cfg = 0x40000ea4; +rom_bb_bss_cbw40 = 0x40000ea8; +rom_set_cca = 0x40000eac; +rom_tx_paon_set = 0x40000eb0; +rom_i2cmst_reg_init = 0x40000eb4; +rom_iq_corr_enable = 0x40000eb8; +rom_fe_reg_init = 0x40000ebc; +rom_agc_reg_init = 0x40000ec0; +rom_bb_reg_init = 0x40000ec4; +rom_mac_enable_bb = 0x40000ec8; +rom_bb_wdg_cfg = 0x40000ecc; +rom_force_txon = 0x40000ed0; +rom_fe_txrx_reset = 0x40000ed4; +rom_set_rx_comp = 0x40000ed8; +rom_set_pbus_reg = 0x40000edc; +rom_write_chan_freq = 0x40000ee0; +rom_phy_xpd_rf = 0x40000ee4; +rom_set_xpd_sar = 0x40000ee8; +rom_write_dac_gain2 = 0x40000eec; +rom_get_target_power_offset = 0x40000ef0; +rom_write_txrate_power_offset = 0x40000ef4; +rom_get_rate_fcc_index = 0x40000ef8; +rom_get_rate_target_power = 0x40000efc; +rom_write_wifi_dig_gain = 0x40000f00; +rom_bt_correct_rf_ana_gain = 0x40000f04; +rom_pkdet_vol_start = 0x40000f08; +rom_read_sar2_code = 0x40000f0c; +rom_get_sar2_vol = 0x40000f10; +rom_get_pll_vol = 0x40000f14; +rom_get_phy_target_power = 0x40000f18; +rom_temp_to_power = 0x40000f1c; +rom_phy_track_pll_cap = 0x40000f20; +rom_phy_pwdet_always_en = 0x40000f24; +rom_phy_pwdet_onetime_en = 0x40000f28; +rom_get_i2c_mst0_mask = 0x40000f2c; +rom_get_i2c_hostid = 0x40000f30; +rom_enter_critical_phy = 0x40000f34; +rom_exit_critical_phy = 0x40000f38; +rom_chip_i2c_readReg_org = 0x40000f3c; +rom_i2c_paral_set_mst0 = 0x40000f40; +rom_i2c_paral_set_read = 0x40000f44; +rom_i2c_paral_read = 0x40000f48; +rom_i2c_paral_write = 0x40000f4c; +rom_i2c_paral_write_num = 0x40000f50; +rom_i2c_paral_write_mask = 0x40000f54; +rom_bb_bss_cbw40_ana = 0x40000f58; +rom_chan_to_freq = 0x40000f5c; +rom_open_i2c_xpd = 0x40000f60; +rom_dac_rate_set = 0x40000f64; +rom_tsens_read_init = 0x40000f68; +rom_tsens_code_read = 0x40000f6c; +rom_tsens_index_to_dac = 0x40000f70; +rom_tsens_index_to_offset = 0x40000f74; +rom_tsens_dac_cal = 0x40000f78; +rom_code_to_temp = 0x40000f7c; +rom_write_pll_cap_mem = 0x40000f80; +rom_pll_correct_dcap = 0x40000f84; +rom_phy_en_hw_set_freq = 0x40000f88; +rom_phy_dis_hw_set_freq = 0x40000f8c; +rom_pll_vol_cal = 0x40000f90; +rom_wrtie_pll_cap = 0x40000f94; +rom_set_tx_gain_mem = 0x40000f98; +rom_bt_tx_dig_gain = 0x40000f9c; +rom_bt_get_tx_gain = 0x40000fa0; +rom_get_chan_target_power = 0x40000fa4; +rom_get_tx_gain_value = 0x40000fa8; +rom_wifi_tx_dig_gain = 0x40000fac; +rom_wifi_get_tx_gain = 0x40000fb0; +rom_fe_i2c_reg_renew = 0x40000fb4; +rom_wifi_agc_sat_gain = 0x40000fb8; +rom_i2c_master_reset = 0x40000fbc; +rom_bt_filter_reg = 0x40000fc0; +rom_phy_bbpll_cal = 0x40000fc4; +rom_i2c_sar2_init_code = 0x40000fc8; +rom_phy_param_addr = 0x40000fcc; +rom_phy_reg_init = 0x40000fd0; +rom_set_chan_reg = 0x40000fd4; +rom_phy_wakeup_init = 0x40000fd8; +rom_phy_i2c_init1 = 0x40000fdc; +rom_tsens_temp_read = 0x40000fe0; +rom_bt_track_pll_cap = 0x40000fe4; +rom_wifi_track_pll_cap = 0x40000fe8; +rom_wifi_set_tx_gain = 0x40000fec; +rom_txpwr_cal_track = 0x40000ff0; +rom_tx_pwctrl_background = 0x40000ff4; +rom_bt_set_tx_gain = 0x40000ff8; +rom_noise_check_loop = 0x40000ffc; +rom_phy_close_rf = 0x40001000; +rom_phy_xpd_tsens = 0x40001004; +rom_phy_freq_mem_backup = 0x40001008; +rom_phy_ant_init = 0x4000100c; +rom_bt_track_tx_power = 0x40001010; +rom_wifi_track_tx_power = 0x40001014; +rom_phy_dig_reg_backup = 0x40001018; +chip726_phyrom_version_num = 0x4000101c; +/* Data (.data, .bss, .rodata) */ +phy_param_rom = 0x4084fcd8; diff --git a/components/esp_rom/esp32c61/ld/esp32c61.rom.pp.ld b/components/esp_rom/esp32c61/ld/esp32c61.rom.pp.ld new file mode 100644 index 0000000000..b69157baae --- /dev/null +++ b/components/esp_rom/esp32c61/ld/esp32c61.rom.pp.ld @@ -0,0 +1,263 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +/* ROM function interface esp32c6lite.rom.pp.ld for esp32c6lite + * + * + * Generated from ./target/esp32c6lite/interface-esp32c6lite.yml md5sum d875746dfc29a51e6d327cc923b7a095 + * + * Compatible with ROM where ECO version equal or greater to 0. + * + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + */ + +/*************************************** + Group rom_pp + ***************************************/ + +/* Functions */ +esp_pp_rom_version_get = 0x40000af8; +RC_GetBlockAckTime = 0x40000afc; +ebuf_list_remove = 0x40000b00; +esf_buf_alloc = 0x40000b04; +esf_buf_alloc_dynamic = 0x40000b08; +esf_buf_recycle = 0x40000b0c; +GetAccess = 0x40000b10; +hal_mac_is_low_rate_enabled = 0x40000b14; +hal_mac_tx_get_blockack = 0x40000b18; +hal_mac_tx_set_ppdu = 0x40000b1c; +ic_get_trc = 0x40000b20; +ic_mac_deinit = 0x40000b24; +ic_mac_init = 0x40000b28; +ic_interface_enabled = 0x40000b2c; +is_lmac_idle = 0x40000b30; +lmacAdjustTimestamp = 0x40000b34; +lmacDiscardAgedMSDU = 0x40000b38; +lmacDiscardMSDU = 0x40000b3c; +lmacEndFrameExchangeSequence = 0x40000b40; +lmacIsIdle = 0x40000b44; +lmacIsLongFrame = 0x40000b48; +lmacMSDUAged = 0x40000b4c; +lmacPostTxComplete = 0x40000b50; +lmacProcessAllTxTimeout = 0x40000b54; +lmacProcessCollisions = 0x40000b58; +lmacProcessRxSucData = 0x40000b5c; +lmacReachLongLimit = 0x40000b60; +lmacReachShortLimit = 0x40000b64; +lmacRecycleMPDU = 0x40000b68; +lmacRxDone = 0x40000b6c; +lmacSetTxFrame = 0x40000b70; +lmacTxDone = 0x40000b74; +lmacTxFrame = 0x40000b78; +mac_tx_set_duration = 0x40000b7c; +mac_tx_set_plcp0 = 0x40000b80; +mac_tx_set_plcp1 = 0x40000b84; +mac_tx_set_plcp2 = 0x40000b88; +pm_check_state = 0x40000b8c; +pm_disable_dream_timer = 0x40000b90; +pm_disable_sleep_delay_timer = 0x40000b94; +pm_dream = 0x40000b98; +pm_mac_wakeup = 0x40000b9c; +pm_mac_sleep = 0x40000ba0; +pm_enable_active_timer = 0x40000ba4; +pm_enable_sleep_delay_timer = 0x40000ba8; +pm_local_tsf_process = 0x40000bac; +pm_set_beacon_filter = 0x40000bb0; +pm_is_in_wifi_slice_threshold = 0x40000bb4; +pm_is_waked = 0x40000bb8; +pm_keep_alive = 0x40000bbc; +pm_on_beacon_rx = 0x40000bc0; +pm_on_data_rx = 0x40000bc4; +pm_on_tbtt = 0x40000bc8; +pm_parse_beacon = 0x40000bcc; +pm_process_tim = 0x40000bd0; +pm_rx_beacon_process = 0x40000bd4; +pm_rx_data_process = 0x40000bd8; +pm_sleep = 0x40000bdc; +pm_sleep_for = 0x40000be0; +pm_tbtt_process = 0x40000be4; +ppAMPDU2Normal = 0x40000be8; +ppAssembleAMPDU = 0x40000bec; +ppCalFrameTimes = 0x40000bf0; +ppCalSubFrameLength = 0x40000bf4; +ppCalTxAMPDULength = 0x40000bf8; +ppCheckTxAMPDUlength = 0x40000bfc; +ppDequeueRxq_Locked = 0x40000c00; +ppDequeueTxQ = 0x40000c04; +ppEmptyDelimiterLength = 0x40000c08; +ppEnqueueRxq = 0x40000c0c; +ppEnqueueTxDone = 0x40000c10; +ppGetTxframe = 0x40000c14; +ppMapTxQueue = 0x40000c18; +ppProcTxSecFrame = 0x40000c1c; +ppProcessRxPktHdr = 0x40000c20; +ppProcessTxQ = 0x40000c24; +ppRecordBarRRC = 0x40000c28; +ppRecycleAmpdu = 0x40000c2c; +ppRecycleRxPkt = 0x40000c30; +ppResortTxAMPDU = 0x40000c34; +ppResumeTxAMPDU = 0x40000c38; +ppRxFragmentProc = 0x40000c3c; +ppRxPkt = 0x40000c40; +ppRxProtoProc = 0x40000c44; +ppSearchTxQueue = 0x40000c48; +ppSearchTxframe = 0x40000c4c; +ppSelectNextQueue = 0x40000c50; +ppSubFromAMPDU = 0x40000c54; +ppTask = 0x40000c58; +ppTxPkt = 0x40000c5c; +ppTxProtoProc = 0x40000c60; +ppTxqUpdateBitmap = 0x40000c64; +pp_coex_tx_request = 0x40000c68; +pp_hdrsize = 0x40000c6c; +pp_post = 0x40000c70; +pp_process_hmac_waiting_txq = 0x40000c74; +rcGetAmpduSched = 0x40000c78; +rcUpdateRxDone = 0x40000c7c; +rc_get_trc = 0x40000c80; +rc_get_trc_by_index = 0x40000c84; +rcAmpduLowerRate = 0x40000c88; +rcampduuprate = 0x40000c8c; +rcClearCurAMPDUSched = 0x40000c90; +rcClearCurSched = 0x40000c94; +rcClearCurStat = 0x40000c98; +rcGetSched = 0x40000c9c; +rcLowerSched = 0x40000ca0; +rcSetTxAmpduLimit = 0x40000ca4; +rcTxUpdatePer = 0x40000ca8; +rcUpdateAckSnr = 0x40000cac; +rcUpdateRate = 0x40000cb0; +rcUpdateTxDone = 0x40000cb4; +rcUpdateTxDoneAmpdu2 = 0x40000cb8; +rcUpSched = 0x40000cbc; +rssi_margin = 0x40000cc0; +rx11NRate2AMPDULimit = 0x40000cc4; +TRC_AMPDU_PER_DOWN_THRESHOLD = 0x40000cc8; +TRC_AMPDU_PER_UP_THRESHOLD = 0x40000ccc; +trc_calc_duration = 0x40000cd0; +trc_isTxAmpduOperational = 0x40000cd4; +trc_onAmpduOp = 0x40000cd8; +TRC_PER_IS_GOOD = 0x40000cdc; +trc_SetTxAmpduState = 0x40000ce0; +trc_tid_isTxAmpduOperational = 0x40000ce4; +trcAmpduSetState = 0x40000ce8; +wDevCheckBlockError = 0x40000cec; +wDev_AppendRxBlocks = 0x40000cf0; +wDev_DiscardFrame = 0x40000cf4; +wDev_GetNoiseFloor = 0x40000cf8; +wDev_IndicateAmpdu = 0x40000cfc; +wDev_IndicateFrame = 0x40000d00; +wdev_mac_reg_load = 0x40000d04; +wdev_mac_reg_store = 0x40000d08; +wdev_mac_special_reg_load = 0x40000d0c; +wdev_mac_special_reg_store = 0x40000d10; +wdev_mac_wakeup = 0x40000d14; +wdev_mac_sleep = 0x40000d18; +hal_mac_is_dma_enable = 0x40000d1c; +wDev_ProcessFiq = 0x40000d20; +wDev_ProcessRxSucData = 0x40000d24; +wdevProcessRxSucDataAll = 0x40000d28; +wdev_csi_len_align = 0x40000d2c; +ppDequeueTxDone_Locked = 0x40000d30; +ppProcTxDone = 0x40000d34; +pm_tx_data_done_process = 0x40000d38; +config_is_cache_tx_buf_enabled = 0x40000d3c; +ppMapWaitTxq = 0x40000d40; +ppProcessWaitingQueue = 0x40000d44; +ppDisableQueue = 0x40000d48; +pm_allow_tx = 0x40000d4c; +wdev_is_data_in_rxlist = 0x40000d50; +ppProcTxCallback = 0x40000d54; +mac_tx_set_hesig = 0x40000d58; +ppCalPreFecPaddingFactor = 0x40000d5c; +mac_tx_set_tb = 0x40000d60; +mac_tx_set_mplen = 0x40000d64; +/* Data (.data, .bss, .rodata) */ +our_instances_ptr = 0x4003ffe0; +pTxRx = 0x4084ff88; +lmacConfMib_ptr = 0x4084ff84; +our_wait_eb = 0x4084ff80; +our_tx_eb = 0x4084ff7c; +pp_wdev_funcs = 0x4084ff78; +g_osi_funcs_p = 0x4084ff74; +wDevCtrl_ptr = 0x4084ff70; +g_wdev_last_desc_reset_ptr = 0x4003ffdc; +wDevMacSleep_ptr = 0x4084ff6c; +g_lmac_cnt_ptr = 0x4084ff68; +our_controls_ptr = 0x4003ffd8; +pp_sig_cnt_ptr = 0x4084ff64; +g_eb_list_desc_ptr = 0x4084ff60; +s_fragment_ptr = 0x4084ff5c; +if_ctrl_ptr = 0x4084ff58; +g_intr_lock_mux = 0x4084ff54; +g_wifi_global_lock = 0x4084ff50; +s_wifi_queue = 0x4084ff4c; +pp_task_hdl = 0x4084ff48; +s_pp_task_create_sem = 0x4084ff44; +s_pp_task_del_sem = 0x4084ff40; +g_wifi_menuconfig_ptr = 0x4084ff3c; +xphyQueue = 0x4084ff38; +ap_no_lr_ptr = 0x4084ff34; +rc11BSchedTbl_ptr = 0x4084ff30; +rc11NSchedTbl_ptr = 0x4084ff2c; +rcLoRaSchedTbl_ptr = 0x4084ff28; +BasicOFDMSched_ptr = 0x4084ff24; +trc_ctl_ptr = 0x4084ff20; +g_pm_cnt_ptr = 0x4084ff1c; +g_pm_ptr = 0x4084ff18; +g_pm_cfg_ptr = 0x4084ff14; +g_esp_mesh_quick_funcs_ptr = 0x4084ff10; +g_txop_queue_status_ptr = 0x4084ff0c; +g_mac_sleep_en_ptr = 0x4084ff08; +g_mesh_is_root_ptr = 0x4084ff04; +g_mesh_topology_ptr = 0x4084ff00; +g_mesh_init_ps_type_ptr = 0x4084fefc; +g_mesh_is_started_ptr = 0x4084fef8; +g_config_func = 0x4084fef4; +g_net80211_tx_func = 0x4084fef0; +g_timer_func = 0x4084feec; +s_michael_mic_failure_cb = 0x4084fee8; +wifi_sta_rx_probe_req = 0x4084fee4; +g_tx_done_cb_func = 0x4084fee0; +g_per_conn_trc = 0x4084fe94; +s_encap_amsdu_func = 0x4084fe90; +s_mplen_high_bitmap = 0x4084fce8; +s_mplen_low_bitmap = 0x4084fcf8; +rx_beacon_count = 0x4084fe8c; +rx_beacon_sw_parse = 0x4084fe88; +rx_beacon_hw_parse = 0x4084fe84; +rx_beacon_tim_count = 0x4084fe80; +rx_beacon_tim_udata = 0x4084fe7c; +rx_beacon_tim_udata_bitmap = 0x4084fe78; +rx_beacon_tim_bdata = 0x4084fe74; +rx_beacon_tim_bdata_bitmapctl = 0x4084fe70; +rx_beacon_tim_bdata_bitmap_trans = 0x4084fe6c; +rx_beacon_tim_bdata_bitmap_mbssid_self = 0x4084fe68; +rx_beacon_tim_bdata_bitmap_mbssid_other = 0x4084fe64; +rx_beacon_dtim_tim = 0x4084fe60; +rx_beacon_dtim_tim_mcast = 0x4084fe5c; +amdpu_delay_time_ms = 0x4084fce4; +ampdu_delay_packet = 0x4084fce0; +ampdu_delay = 0x4084fe59; +first_ampdu = 0x4084fe58; +s_ht_ampdu_density_us = 0x4084fcde; +s_ht_ampdu_density = 0x4084fcdd; +s_running_phy_type = 0x4084fcdc; +complete_ena_tb_seqno = 0x4084fe54; +complete_ena_tb_final = 0x4084fe50; +complete_ena_tb_count = 0x4084fe4c; +s_itwt_state = 0x4084fe48; +g_dbg_interp_tsf = 0x4084fe44; +g_dbg_interp_tsf_end = 0x4084fe40; +g_dbg_closrf_tsf = 0x4084fe3c; +g_dbg_closrf_idx = 0x4084fe38; +g_dbg_closrf_blk = 0x4084fe34; +queue_history = 0x4084fd6c; +queue_history_idx = 0x4084fd68; +s_he_min_len_bytes = 0x4084fd2c; +s_he_dcm_min_len_bytes = 0x4084fd0c; +s_mplen_vi_bitmap = 0x4084fd08; +s_mplen_low_bitmap = 0x4084fcf8; +s_mplen_high_bitmap = 0x4084fce8; diff --git a/components/esp_rom/esp32c61/ld/esp32c61.rom.rvfp.ld b/components/esp_rom/esp32c61/ld/esp32c61.rom.rvfp.ld new file mode 100644 index 0000000000..4513c2e6c3 --- /dev/null +++ b/components/esp_rom/esp32c61/ld/esp32c61.rom.rvfp.ld @@ -0,0 +1,62 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +/* ROM function interface esp32c6lite.rom.rvfp.ld for esp32c6lite + * + * + * Generated from ./target/esp32c6lite/interface-esp32c6lite.yml md5sum d875746dfc29a51e6d327cc923b7a095 + * + * Compatible with ROM where ECO version equal or greater to 0. + * + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + */ + +/*************************************** + Group rvfplibsf + ***************************************/ + +/* Functions */ +_rvfp__addsf3 = 0x40000980; +_rvfp__eqsf2 = 0x40000984; +_rvfp__extendsfdf2 = 0x40000988; +_rvfp__fixsfsi = 0x4000098c; +_rvfp__fixunssfsi = 0x40000990; +_rvfp__floatdisf = 0x40000994; +_rvfp__floatsisf = 0x40000998; +_rvfp__floatundisf = 0x4000099c; +_rvfp__floatunsisf = 0x400009a0; +_rvfp__gesf2 = 0x400009a4; +_rvfp__gtsf2 = 0x400009a8; +_rvfp__lesf2 = 0x400009ac; +_rvfp__ltsf2 = 0x400009b0; +_rvfp__mulsf3 = 0x400009b4; +_rvfp__nesf2 = 0x400009b8; +_rvfp__subsf3 = 0x400009bc; +_rvfp__truncdfsf2 = 0x400009c0; + + +/*************************************** + Group rvfplibdf + ***************************************/ + +/* Functions */ +_rvfp__adddf3 = 0x400009c4; +_rvfp__eqdf2 = 0x400009c8; +_rvfp__fixdfdi = 0x400009cc; +_rvfp__fixdfsi = 0x400009d0; +_rvfp__fixsfdi = 0x400009d4; +_rvfp__fixunsdfsi = 0x400009d8; +_rvfp__fixunssfdi = 0x400009dc; +_rvfp__floatdidf = 0x400009e0; +_rvfp__floatsidf = 0x400009e4; +_rvfp__floatundidf = 0x400009e8; +_rvfp__floatunsidf = 0x400009ec; +_rvfp__gedf2 = 0x400009f0; +_rvfp__gtdf2 = 0x400009f4; +_rvfp__ledf2 = 0x400009f8; +_rvfp__ltdf2 = 0x400009fc; +_rvfp__muldf3 = 0x40000a00; +_rvfp__nedf2 = 0x40000a04; +_rvfp__subdf3 = 0x40000a08; diff --git a/components/esp_rom/esp32c61/ld/esp32c61.rom.spiflash.ld b/components/esp_rom/esp32c61/ld/esp32c61.rom.spiflash.ld new file mode 100644 index 0000000000..6dd9e34a98 --- /dev/null +++ b/components/esp_rom/esp32c61/ld/esp32c61.rom.spiflash.ld @@ -0,0 +1,165 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +/* ROM function interface esp32c6lite.rom.spiflash.ld for esp32c6lite + * + * + * Generated from ./target/esp32c6lite/interface-esp32c6lite.yml md5sum d875746dfc29a51e6d327cc923b7a095 + * + * Compatible with ROM where ECO version equal or greater to 0. + * + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + */ + +/*************************************** + Group spi_flash_cache + ***************************************/ + +/* Functions */ +spi_flash_disable_cache = 0x40000204; +spi_flash_restore_cache = 0x40000208; +spi_flash_cache_enabled = 0x4000020c; +spi_flash_enable_cache = 0x40000210; +esp_enable_cache_flash_wrap = 0x40000214; + + +/*************************************** + Group spi_flash_mmap + ***************************************/ + +/* Functions */ +spi_flash_mmap_os_func_set = 0x40000218; +spi_flash_mmap_page_num_init = 0x4000021c; +spi_flash_mmap = 0x40000220; +spi_flash_mmap_pages = 0x40000224; +spi_flash_munmap = 0x40000228; +spi_flash_mmap_dump = 0x4000022c; +spi_flash_check_and_flush_cache = 0x40000230; +spi_flash_mmap_get_free_pages = 0x40000234; +spi_flash_cache2phys = 0x40000238; +spi_flash_phys2cache = 0x4000023c; + + +/*************************************** + Group esp_flash + ***************************************/ + +/* Functions */ +esp_flash_chip_driver_initialized = 0x40000240; +esp_flash_read_id = 0x40000244; +esp_flash_get_size = 0x40000248; +esp_flash_erase_chip = 0x4000024c; +esp_flash_erase_region = 0x40000250; +esp_flash_get_chip_write_protect = 0x40000254; +esp_flash_set_chip_write_protect = 0x40000258; +esp_flash_get_protectable_regions = 0x4000025c; +esp_flash_get_protected_region = 0x40000260; +esp_flash_set_protected_region = 0x40000264; +esp_flash_read = 0x40000268; +esp_flash_write = 0x4000026c; +esp_flash_write_encrypted = 0x40000270; +esp_flash_read_encrypted = 0x40000274; +esp_flash_get_io_mode = 0x40000278; +esp_flash_set_io_mode = 0x4000027c; +spi_flash_boot_attach = 0x40000280; +esp_flash_read_chip_id = 0x40000284; +detect_spi_flash_chip = 0x40000288; +esp_flash_suspend_cmd_init = 0x4000028c; +/* Data (.data, .bss, .rodata) */ +esp_flash_default_chip = 0x4084ffe8; +esp_flash_api_funcs = 0x4084ffe4; + + +/*************************************** + Group spi_flash_chips + ***************************************/ + +/* Functions */ +spi_flash_chip_generic_probe = 0x40000290; +spi_flash_chip_generic_detect_size = 0x40000294; +spi_flash_chip_generic_write = 0x40000298; +spi_flash_chip_generic_write_encrypted = 0x4000029c; +spi_flash_chip_generic_set_write_protect = 0x400002a0; +spi_flash_common_write_status_16b_wrsr = 0x400002a4; +spi_flash_chip_generic_reset = 0x400002a8; +spi_flash_chip_generic_erase_chip = 0x400002ac; +spi_flash_chip_generic_erase_sector = 0x400002b0; +spi_flash_chip_generic_erase_block = 0x400002b4; +spi_flash_chip_generic_page_program = 0x400002b8; +spi_flash_chip_generic_get_write_protect = 0x400002bc; +spi_flash_common_read_status_16b_rdsr_rdsr2 = 0x400002c0; +spi_flash_chip_generic_read_reg = 0x400002c4; +spi_flash_chip_generic_yield = 0x400002c8; +spi_flash_generic_wait_host_idle = 0x400002cc; +spi_flash_chip_generic_wait_idle = 0x400002d0; +spi_flash_chip_generic_config_host_io_mode = 0x400002d4; +spi_flash_chip_generic_read = 0x400002d8; +spi_flash_common_read_status_8b_rdsr2 = 0x400002dc; +spi_flash_chip_generic_get_io_mode = 0x400002e0; +spi_flash_common_read_status_8b_rdsr = 0x400002e4; +spi_flash_common_write_status_8b_wrsr = 0x400002e8; +spi_flash_common_write_status_8b_wrsr2 = 0x400002ec; +spi_flash_common_set_io_mode = 0x400002f0; +spi_flash_chip_generic_set_io_mode = 0x400002f4; +spi_flash_chip_generic_read_unique_id = 0x400002f8; +spi_flash_chip_generic_get_caps = 0x400002fc; +spi_flash_chip_generic_suspend_cmd_conf = 0x40000300; +spi_flash_chip_gd_get_io_mode = 0x40000304; +spi_flash_chip_gd_probe = 0x40000308; +spi_flash_chip_gd_set_io_mode = 0x4000030c; +/* Data (.data, .bss, .rodata) */ +spi_flash_chip_generic_config_data = 0x4084ffe0; +spi_flash_encryption = 0x4084ffdc; + + +/*************************************** + Group memspi_host + ***************************************/ + +/* Functions */ +memspi_host_read_id_hs = 0x40000310; +memspi_host_read_status_hs = 0x40000314; +memspi_host_flush_cache = 0x40000318; +memspi_host_erase_chip = 0x4000031c; +memspi_host_erase_sector = 0x40000320; +memspi_host_erase_block = 0x40000324; +memspi_host_program_page = 0x40000328; +memspi_host_read = 0x4000032c; +memspi_host_set_write_protect = 0x40000330; +memspi_host_set_max_read_len = 0x40000334; +memspi_host_read_data_slicer = 0x40000338; +memspi_host_write_data_slicer = 0x4000033c; + + +/*************************************** + Group hal_spiflash + ***************************************/ + +/* Functions */ +spi_flash_hal_poll_cmd_done = 0x40000340; +spi_flash_hal_device_config = 0x40000344; +spi_flash_hal_configure_host_io_mode = 0x40000348; +spi_flash_hal_common_command = 0x4000034c; +spi_flash_hal_read = 0x40000350; +spi_flash_hal_erase_chip = 0x40000354; +spi_flash_hal_erase_sector = 0x40000358; +spi_flash_hal_erase_block = 0x4000035c; +spi_flash_hal_program_page = 0x40000360; +spi_flash_hal_set_write_protect = 0x40000364; +spi_flash_hal_host_idle = 0x40000368; +spi_flash_hal_check_status = 0x4000036c; +spi_flash_hal_setup_read_suspend = 0x40000370; +spi_flash_hal_setup_auto_suspend_mode = 0x40000374; +spi_flash_hal_setup_auto_resume_mode = 0x40000378; +spi_flash_hal_disable_auto_suspend_mode = 0x4000037c; +spi_flash_hal_disable_auto_resume_mode = 0x40000380; +spi_flash_hal_resume = 0x40000384; +spi_flash_hal_suspend = 0x40000388; +spi_flash_encryption_hal_enable = 0x4000038c; +spi_flash_encryption_hal_disable = 0x40000390; +spi_flash_encryption_hal_prepare = 0x40000394; +spi_flash_encryption_hal_done = 0x40000398; +spi_flash_encryption_hal_destroy = 0x4000039c; +spi_flash_encryption_hal_check = 0x400003a0; diff --git a/components/esp_rom/esp32c61/ld/esp32c61.rom.systimer.ld b/components/esp_rom/esp32c61/ld/esp32c61.rom.systimer.ld new file mode 100644 index 0000000000..7be47b1110 --- /dev/null +++ b/components/esp_rom/esp32c61/ld/esp32c61.rom.systimer.ld @@ -0,0 +1,26 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/*************************************** + Group hal_systimer + ***************************************/ + +/* Functions */ +systimer_hal_init = 0x400003d0; +systimer_hal_deinit = 0x400003d4; +systimer_hal_set_tick_rate_ops = 0x400003d8; +systimer_hal_get_counter_value = 0x400003dc; +systimer_hal_get_time = 0x400003e0; +systimer_hal_set_alarm_target = 0x400003e4; +systimer_hal_set_alarm_period = 0x400003e8; +systimer_hal_get_alarm_value = 0x400003ec; +systimer_hal_enable_alarm_int = 0x400003f0; +systimer_hal_on_apb_freq_update = 0x400003f4; +systimer_hal_counter_value_advance = 0x400003f8; +systimer_hal_enable_counter = 0x400003fc; +systimer_hal_select_alarm_mode = 0x40000400; +systimer_hal_connect_alarm_counter = 0x40000404; +systimer_hal_counter_can_stall_by_cpu = 0x40000408; diff --git a/components/esp_rom/esp32c61/ld/esp32c61.rom.version.ld b/components/esp_rom/esp32c61/ld/esp32c61.rom.version.ld new file mode 100644 index 0000000000..dad3a86c2f --- /dev/null +++ b/components/esp_rom/esp32c61/ld/esp32c61.rom.version.ld @@ -0,0 +1,13 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +/* ROM version variables for esp32c6lite + * + * These addresses should be compatible with any ROM version for this chip. + * + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + */ +_rom_chip_id = 0x40000010; +_rom_eco_version = 0x40000014; diff --git a/components/esp_rom/esp32c61/ld/esp32c61.rom.wdt.ld b/components/esp_rom/esp32c61/ld/esp32c61.rom.wdt.ld new file mode 100644 index 0000000000..588987ef32 --- /dev/null +++ b/components/esp_rom/esp32c61/ld/esp32c61.rom.wdt.ld @@ -0,0 +1,22 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/*************************************** + Group hal_wdt + ***************************************/ + +/* Functions */ +wdt_hal_init = 0x400003a4; +wdt_hal_deinit = 0x400003a8; +wdt_hal_config_stage = 0x400003ac; +wdt_hal_write_protect_disable = 0x400003b0; +wdt_hal_write_protect_enable = 0x400003b4; +wdt_hal_enable = 0x400003b8; +wdt_hal_disable = 0x400003bc; +wdt_hal_handle_intr = 0x400003c0; +wdt_hal_feed = 0x400003c4; +wdt_hal_set_flashboot_en = 0x400003c8; +wdt_hal_is_enabled = 0x400003cc; diff --git a/components/esp_rom/include/esp32c61/.gitkeep b/components/esp_rom/include/esp32c61/.gitkeep deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/components/esp_rom/include/esp32c61/rom/bigint.h b/components/esp_rom/include/esp32c61/rom/bigint.h new file mode 100644 index 0000000000..3c468ce7a3 --- /dev/null +++ b/components/esp_rom/include/esp32c61/rom/bigint.h @@ -0,0 +1,35 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ROM_BIGINT_H_ +#define _ROM_BIGINT_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +void ets_bigint_enable(void); + +void ets_bigint_disable(void); + +int ets_bigint_multiply(const uint32_t *x, const uint32_t *y, uint32_t len_words); + +int ets_bigint_modmult(const uint32_t *x, const uint32_t *y, const uint32_t *m, uint32_t m_dash, const uint32_t *rb, uint32_t len_words); + +int ets_bigint_modexp(const uint32_t *x, const uint32_t *y, const uint32_t *m, uint32_t m_dash, const uint32_t *rb, bool constant_time, uint32_t len_words); + +void ets_bigint_wait_finish(void); + +int ets_bigint_getz(uint32_t *z, uint32_t len_words); + +#ifdef __cplusplus +} +#endif + +#endif /* _ROM_BIGINT_H_ */ diff --git a/components/esp_rom/include/esp32c61/rom/cache.h b/components/esp_rom/include/esp32c61/rom/cache.h new file mode 100644 index 0000000000..5ed6740a62 --- /dev/null +++ b/components/esp_rom/include/esp32c61/rom/cache.h @@ -0,0 +1,626 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include "esp_bit_defs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** \defgroup cache_apis, cache operation related apis + * @brief cache apis + */ + +/** @addtogroup cache_apis + * @{ + */ +#define MIN_ICACHE_SIZE 16384 +#define MAX_ICACHE_SIZE 16384 +#define MIN_ICACHE_WAYS 8 +#define MAX_ICACHE_WAYS 8 +#define MAX_CACHE_WAYS 8 +#define MIN_CACHE_LINE_SIZE 32 +#define TAG_SIZE 4 +#define MIN_ICACHE_BANK_NUM 1 +#define MAX_ICACHE_BANK_NUM 1 +#define CACHE_MEMORY_BANK_NUM 1 +#define CACHE_MEMORY_IBANK_SIZE 0x4000 + +#define MAX_ITAG_BANK_ITEMS (MAX_ICACHE_SIZE / MAX_ICACHE_BANK_NUM / MIN_CACHE_LINE_SIZE) +#define MAX_ITAG_BLOCK_ITEMS (MAX_ICACHE_SIZE / MAX_ICACHE_BANK_NUM / MAX_ICACHE_WAYS / MIN_CACHE_LINE_SIZE) +#define MAX_ITAG_BANK_SIZE (MAX_ITAG_BANK_ITEMS * TAG_SIZE) +#define MAX_ITAG_BLOCK_SIZE (MAX_ITAG_BLOCK_ITEMS * TAG_SIZE) + +typedef enum { + CACHE_LOCK_LOCK = BIT(0), + CACHE_LOCK_UNLOCK = BIT(1), +} cache_lock_t; + +typedef enum { + CACHE_SYNC_INVALIDATE = BIT(0), + CACHE_SYNC_CLEAN = BIT(1), + CACHE_SYNC_WRITEBACK = BIT(2), + CACHE_SYNC_WRITEBACK_INVALIDATE = BIT(3), +} cache_sync_t; + +typedef enum { + CACHE_SIZE_HALF = 0, /*!< 8KB for icache and dcache */ + CACHE_SIZE_FULL = 1, /*!< 16KB for icache and dcache */ +} cache_size_t; + +typedef enum { + CACHE_4WAYS_ASSOC = 0, /*!< 4 way associated cache */ + CACHE_8WAYS_ASSOC = 1, /*!< 8 way associated cache */ +} cache_ways_t; + +typedef enum { + CACHE_LINE_SIZE_16B = 0, /*!< 16 Byte cache line size */ + CACHE_LINE_SIZE_32B = 1, /*!< 32 Byte cache line size */ + CACHE_LINE_SIZE_64B = 2, /*!< 64 Byte cache line size */ +} cache_line_size_t; + +typedef enum { + CACHE_AUTOLOAD_POSITIVE = 0, /*!< cache autoload step is positive */ + CACHE_AUTOLOAD_NEGATIVE = 1, /*!< cache autoload step is negative */ +} cache_autoload_order_t; + +#define CACHE_AUTOLOAD_STEP(i) ((i) - 1) + +typedef enum { + CACHE_AUTOLOAD_MISS_TRIGGER = 0, /*!< autoload only triggered by cache miss */ + CACHE_AUTOLOAD_HIT_TRIGGER = 1, /*!< autoload only triggered by cache hit */ + CACHE_AUTOLOAD_BOTH_TRIGGER = 2, /*!< autoload triggered both by cache miss and hit */ +} cache_autoload_trigger_t; + +typedef enum { + CACHE_FREEZE_ACK_BUSY = 0, /*!< in this mode, cache ack busy to CPU if a cache miss happens*/ + CACHE_FREEZE_ACK_ERROR = 1, /*!< in this mode, cache ack wrong data to CPU and trigger an error if a cache miss happens */ +} cache_freeze_mode_t; + +typedef enum { + MMU_PAGE_MODE_64KB = 0, + MMU_PAGE_MODE_32KB = 1, + MMU_PAGE_MODE_16KB = 2, + MMU_PAGE_MODE_8KB = 3, + MMU_PAGE_MODE_INVALID, +} mmu_page_mode_t; + +struct cache_mode { + uint32_t cache_size; /*!< cache size in byte */ + uint16_t cache_line_size; /*!< cache line size in byte */ + uint8_t cache_ways; /*!< cache ways, always 4 */ + uint8_t ibus; /*!< the cache index, 0 for dcache, 1 for icache */ +}; + +struct icache_tag_item { + uint32_t valid:1; /*!< the tag item is valid or not */ + uint32_t lock:1; /*!< the cache line is locked or not */ + uint32_t fifo_cnt:3; /*!< fifo cnt, 0 ~ 3 for 4 ways cache */ + uint32_t tag:13; /*!< the tag is the high part of the cache address, however is only 16MB (8MB Ibus + 8MB Dbus) range, and without low part */ + uint32_t reserved:14; +}; + +struct autoload_config { + uint8_t order; /*!< autoload step is positive or negative */ + uint8_t trigger; /*!< autoload trigger */ + uint8_t ena0; /*!< autoload region0 enable */ + uint8_t ena1; /*!< autoload region1 enable */ + uint32_t addr0; /*!< autoload region0 start address */ + uint32_t size0; /*!< autoload region0 size */ + uint32_t addr1; /*!< autoload region1 start address */ + uint32_t size1; /*!< autoload region1 size */ +}; + +struct tag_group_info { + struct cache_mode mode; /*!< cache and cache mode */ + uint32_t filter_addr; /*!< the address that used to generate the struct */ + uint32_t vaddr_offset; /*!< virtual address offset of the cache ways */ + uint32_t tag_addr[MAX_CACHE_WAYS]; /*!< tag memory address, only [0~mode.ways-1] is valid to use */ + uint32_t cache_memory_offset[MAX_CACHE_WAYS]; /*!< cache memory address, only [0~mode.ways-1] is valid to use */ +}; + +struct lock_config { + uint32_t addr; /*!< manual lock address*/ + uint16_t size; /*!< manual lock size*/ + uint16_t group; /*!< manual lock group, 0 or 1*/ +}; + +struct cache_internal_stub_table { + uint32_t (* cache_line_size)(void); + uint32_t (* cache_addr)(uint32_t addr); + void (* sync_cache_items)(uint32_t type, uint32_t addr, uint32_t items); + void (* lock_cache_items)(uint32_t lock, uint32_t addr, uint32_t items); + uint32_t (* suspend_cache_autoload)(void); + void (* resume_cache_autoload)(uint32_t autoload); + void (* freeze_cache_enable)(cache_freeze_mode_t mode); + void (* freeze_cache_disable)(void); + int (* op_addr)(uint32_t op_type, + uint32_t start_addr, + uint32_t size, + uint32_t cache_line_size, + uint32_t max_sync_num, + void(* cache_Iop)(uint32_t, uint32_t, uint32_t)); +}; + +/* Defined in the interface file, default value is rom_default_cache_internal_table */ +extern const struct cache_internal_stub_table* rom_cache_internal_table_ptr; + +typedef void (* cache_op_start)(void); +typedef void (* cache_op_end)(void); + +typedef struct { + cache_op_start start; + cache_op_end end; +} cache_op_cb_t; + +/* Defined in the interface file, default value is NULL */ +extern const cache_op_cb_t* rom_cache_op_cb; + +#define ESP_ROM_ERR_INVALID_ARG 1 +#define MMU_SET_ADDR_ALIGNED_ERROR 2 +#define MMU_SET_PASE_SIZE_ERROR 3 +#define MMU_SET_VADDR_OUT_RANGE 4 + +#define CACHE_OP_ICACHE_Y 1 +#define CACHE_OP_ICACHE_N 0 + +/** + * @brief Initialise cache mmu, mark all entries as invalid. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return None + */ +void Cache_MMU_Init(void); + +/** + * @brief Init Cache for ROM boot, including resetting the Icache, initializing MMU, Enabling ICache, unmasking bus. + * + * @param None + * + * @return None + */ +void ROM_Boot_Cache_Init(void); + +/** + * @brief Set ICache mmu mapping. + * Please do not call this function in your SDK application. + * + * @param uint32_t senitive : Config this page should apply flash encryption or not + * + * @param uint32_t ext_ram : DPORT_MMU_ACCESS_FLASH for flash, DPORT_MMU_INVALID for invalid. In + * esp32c61, external memory is always flash + * + * @param uint32_t vaddr : virtual address in CPU address space. + * Can be Iram0,Iram1,Irom0,Drom0 and AHB buses address. + * Should be aligned by psize. + * + * @param uint32_t paddr : physical address in external memory. + * Should be aligned by psize. + * + * @param uint32_t psize : page size of ICache, in kilobytes. Should be 64 here. + * + * @param uint32_t num : pages to be set. + * + * @param uint32_t fixed : 0 for physical pages grow with virtual pages, other for virtual pages map to same physical page. + * + * @return uint32_t: error status + * 0 : mmu set success + * 2 : vaddr or paddr is not aligned + * 3 : psize error + * 4 : vaddr is out of range + */ +int Cache_MSPI_MMU_Set(uint32_t sensitive, uint32_t ext_ram, uint32_t vaddr, uint32_t paddr, uint32_t psize, uint32_t num, uint32_t fixed); + +/** + * @brief Set DCache mmu mapping. + * Please do not call this function in your SDK application. + * + * @param uint32_t ext_ram : DPORT_MMU_ACCESS_FLASH for flash, DPORT_MMU_INVALID for invalid. In + * esp32c61, external memory is always flash + * + * @param uint32_t vaddr : virtual address in CPU address space. + * Can be DRam0, DRam1, DRom0, DPort and AHB buses address. + * Should be aligned by psize. + * + * @param uint32_t paddr : physical address in external memory. + * Should be aligned by psize. + * + * @param uint32_t psize : page size of DCache, in kilobytes. Should be 64 here. + * + * @param uint32_t num : pages to be set. + + * @param uint32_t fixed : 0 for physical pages grow with virtual pages, other for virtual pages map to same physical page. + * + * @return uint32_t: error status + * 0 : mmu set success + * 2 : vaddr or paddr is not aligned + * 3 : psize error + * 4 : vaddr is out of range + */ +int Cache_Dbus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr, uint32_t psize, uint32_t num, uint32_t fixed); + + +/** + * @brief Get cache mode of ICache or DCache. + * Please do not call this function in your SDK application. + * + * @param struct cache_mode * mode : the pointer of cache mode struct, caller should set the icache field + * + * return none + */ +void Cache_Get_Mode(struct cache_mode * mode); + +/** + * @brief Set cache page mode. + * + * @param mmu_page_mode_t + * + * @return None + */ +void MMU_Set_Page_Mode(mmu_page_mode_t pg_mode); + +/** + * @brief Get cache page mode. + * + * @param None + * + * @return page mode + */ +mmu_page_mode_t MMU_Get_Page_Mode(void); + +/** + * @brief Invalidate the cache items for ICache. + * Operation will be done CACHE_LINE_SIZE aligned. + * If the region is not in ICache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr: start address to invalidate + * + * @param uint32_t items: cache lines to invalidate, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB) + * + * @return None + */ +void Cache_Sync_Items(uint32_t type, uint32_t addr, uint32_t bytes); + +/** + * @brief Invalidate the Cache items in the region from ICache or DCache. + * If the region is not in Cache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr : invalidated region start address. + * + * @param uint32_t size : invalidated region size. + * + * @return 0 for success + * 1 for invalid argument + */ +int Cache_Invalidate_Addr(uint32_t addr, uint32_t size); + +int Cache_Clean_Addr(uint32_t addr, uint32_t size); + +int Cache_WriteBack_Addr(uint32_t addr, uint32_t size); + +int Cache_WriteBack_Invalidate_Addr(uint32_t addr, uint32_t size); + +/** + * @brief Invalidate all cache items in ICache. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return None + */ +void Cache_Invalidate_All(void); + +void Cache_Clean_All(void); + +void Cache_WriteBack_All(void); + +void Cache_WriteBack_Invalidate_All(void); + +/** + * @brief Mask all buses through ICache and DCache. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return None + */ +void Cache_Mask_All(void); + +/** + * @brief Suspend ICache auto preload operation, then you can resume it after some ICache operations. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return uint32_t : 0 for ICache not auto preload before suspend. + */ +uint32_t Cache_Suspend_Autoload(void); + +/** + * @brief Resume ICache auto preload operation after some ICache operations. + * Please do not call this function in your SDK application. + * + * @param uint32_t autoload : 0 for ICache not auto preload before suspend. + * + * @return None. + */ +void Cache_Resume_Autoload(uint32_t autoload); + +/** + * @brief Start an ICache manual preload, will suspend auto preload of ICache. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr : start address of the preload region. + * + * @param uint32_t size : size of the preload region, should not exceed the size of ICache. + * + * @param uint32_t order : the preload order, 0 for positive, other for negative + * + * @return uint32_t : 0 for ICache not auto preload before manual preload. + */ +uint32_t Cache_Start_Preload(uint32_t addr, uint32_t size, uint32_t order); + +/** + * @brief Return if the ICache manual preload done. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return uint32_t : 0 for ICache manual preload not done. + */ +uint32_t Cache_Preload_Done(void); + +/** + * @brief End the ICache manual preload to resume auto preload of ICache. + * Please do not call this function in your SDK application. + * + * @param uint32_t autoload : 0 for ICache not auto preload before manual preload. + * + * @return None + */ +void Cache_End_Preload(uint32_t autoload); + +/** + * @brief Config autoload parameters of ICache. + * Please do not call this function in your SDK application. + * + * @param struct autoload_config * config : autoload parameters. + * + * @return None + */ +void Cache_Config_Autoload(const struct autoload_config * config); + +/** + * @brief Enable auto preload for ICache. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return None + */ +void Cache_Enable_Autoload(void); + +/** + * @brief Disable auto preload for ICache. + * Please do not call this function in your SDK application. + * + * @param None + * + * @return None + */ +void Cache_Disable_Autoload(void); + +/** + * @brief Config a group of prelock parameters of ICache. + * Please do not call this function in your SDK application. + * + * @param struct lock_config * config : a group of lock parameters. + * + * @return None + */ + +void Cache_Enable_PreLock(const struct lock_config *config); + +/** + * @brief Disable a group of prelock parameters for ICache. + * However, the locked data will not be released. + * Please do not call this function in your SDK application. + * + * @param uint16_t group : 0 for group0, 1 for group1. + * + * @return None + */ +void Cache_Disable_PreLock(uint16_t group); + +/** + * @brief Lock the cache items for ICache. + * Operation will be done CACHE_LINE_SIZE aligned. + * If the region is not in ICache addr room, nothing will be done. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr: start address to lock + * + * @param uint32_t items: cache lines to lock, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB) + * + * @return None + */ +int Cache_Lock_Items(uint32_t lock, uint32_t addr, uint32_t items); + +/** + * @brief Lock the cache items in tag memory for ICache or DCache. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr : start address of lock region. + * + * @param uint32_t size : size of lock region. + * + * @return 0 for success + * 1 for invalid argument + */ +int Cache_Lock_Addr(uint32_t addr, uint32_t size); + +/** + * @brief Unlock the cache items in tag memory for ICache or DCache. + * Please do not call this function in your SDK application. + * + * @param uint32_t addr : start address of unlock region. + * + * @param uint32_t size : size of unlock region. + * + * @return 0 for success + * 1 for invalid argument + */ +int Cache_Unlock_Addr(uint32_t addr, uint32_t size); + +/** + * @brief Disable ICache access for the cpu. + * This operation will make all ICache tag memory invalid, CPU can't access ICache, ICache will keep idle. + * Please do not call this function in your SDK application. + * + * @return uint32_t : auto preload enabled before + */ +uint32_t Cache_Disable_Cache(void); + +/** + * @brief Enable ICache access for the cpu. + * Please do not call this function in your SDK application. + * + * @param uint32_t autoload : ICache will preload then. + * + * @return None + */ +void Cache_Enable_Cache(uint32_t autoload); + +/** + * @brief Suspend ICache access for the cpu. + * The ICache tag memory is still there, CPU can't access ICache, ICache will keep idle. + * Please do not change MMU, cache mode or tag memory(tag memory can be changed in some special case). + * Please do not call this function in your SDK application. + * + * @param None + * + * @return uint32_t : auto preload enabled before + */ +uint32_t Cache_Suspend_Cache(void); + +/** + * @brief Resume ICache access for the cpu. + * Please do not call this function in your SDK application. + * + * @param uint32_t autoload : ICache will preload then. + * + * @return None + */ +void Cache_Resume_Cache(uint32_t autoload); + +/** + * @brief Get ICache cache line size + * + * @param None + * + * @return uint32_t: 16, 32, 64 Byte + */ +uint32_t Cache_Get_Cache_Line_Size(void); + +/** + * @brief Enable freeze for ICache. + * Any miss request will be rejected, including cpu miss and preload/autoload miss. + * Please do not call this function in your SDK application. + * + * @param cache_freeze_mode_t mode : 0 for assert busy 1 for assert hit + * + * @return None + */ +void Cache_Freeze_Enable(cache_freeze_mode_t mode); + +/** + * @brief Disable freeze for ICache. + * Please do not call this function in your SDK application. + * + * @return None + */ +void Cache_Freeze_Disable(void); + +/** + * @brief Travel tag memory to run a call back function. + * ICache and DCache are suspend when doing this. + * The callback will get the parameter tag_group_info, which will include a group of tag memory addresses and cache memory addresses. + * Please do not call this function in your SDK application. + * + * @param struct cache_mode * mode : the cache to check and the cache mode. + * + * @param uint32_t filter_addr : only the cache lines which may include the filter_address will be returned to the call back function. + * 0 for do not filter, all cache lines will be returned. + * + * @param void (* process)(struct tag_group_info *) : call back function, which may be called many times, a group(the addresses in the group are in the same position in the cache ways) a time. + * + * @return None + */ +void Cache_Travel_Tag_Memory(struct cache_mode * mode, uint32_t filter_addr, void (* process)(struct tag_group_info *)); + +/** + * @brief Get the virtual address from cache mode, cache tag and the virtual address offset of cache ways. + * Please do not call this function in your SDK application. + * + * @param struct cache_mode * mode : the cache to calculate the virtual address and the cache mode. + * + * @param uint32_t tag : the tag part fo a tag item, 12-14 bits. + * + * @param uint32_t addr_offset : the virtual address offset of the cache ways. + * + * @return uint32_t : the virtual address. + */ +uint32_t Cache_Get_Virtual_Addr(struct cache_mode *mode, uint32_t tag, uint32_t vaddr_offset); + +/** + * @} + */ + +/** + * @brief Get the cache MMU IROM end address. + * Please do not call this function in your SDK application. + * + * @param void + * + * @return uint32_t : the word value of the address. + */ +uint32_t Cache_Get_IROM_MMU_End(void); + +/** + * @brief Get the cache MMU DROM end address. + * Please do not call this function in your SDK application. + * + * @param void + * + * @return uint32_t : the word value of the address. + */ +uint32_t Cache_Get_DROM_MMU_End(void); + +/** + * @brief Configure cache MMU page size according to instruction and rodata size + * + * @param irom_size The instruction cache MMU page size + * @param drom_size The rodata data cache MMU page size + */ +void Cache_Set_IDROM_MMU_Size(uint32_t irom_size, uint32_t drom_size); + +uint32_t Cache_Count_Flash_Pages(uint32_t * page0_mapped); + +uint32_t Cache_Flash_To_SPIRAM_Copy(uint32_t bus_start_addr, uint32_t start_page, uint32_t * page0_page); + +#define Cache_Dbus_MMU_Set(ext_ram, vaddr, paddr, psize, num, fixed) \ + Cache_MSPI_MMU_Set(ets_efuse_cache_encryption_enabled() ? SOC_MMU_SENSITIVE : 0, ext_ram, vaddr, paddr, psize, num, fixed) + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_rom/include/esp32c61/rom/crc.h b/components/esp_rom/include/esp32c61/rom/crc.h new file mode 100644 index 0000000000..e2b43000ae --- /dev/null +++ b/components/esp_rom/include/esp32c61/rom/crc.h @@ -0,0 +1,119 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ROM_CRC_H +#define ROM_CRC_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** \defgroup crc_apis, uart configuration and communication related apis + * @brief crc apis + */ + +/** @addtogroup crc_apis + * @{ + */ + + +/* Standard CRC8/16/32 algorithms. */ +// CRC-8 x8+x2+x1+1 0x07 +// CRC16-CCITT x16+x12+x5+1 1021 ISO HDLC, ITU X.25, V.34/V.41/V.42, PPP-FCS +// CRC32: +//G(x) = x32 +x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x1 + 1 +//If your buf is not continuous, you can use the first result to be the second parameter. + +/** + * @brief Crc32 value that is in little endian. + * + * @param uint32_t crc : init crc value, use 0 at the first use. + * + * @param uint8_t const *buf : buffer to start calculate crc. + * + * @param uint32_t len : buffer length in byte. + * + * @return None + */ +uint32_t crc32_le(uint32_t crc, uint8_t const *buf, uint32_t len); + +/** + * @brief Crc32 value that is in big endian. + * + * @param uint32_t crc : init crc value, use 0 at the first use. + * + * @param uint8_t const *buf : buffer to start calculate crc. + * + * @param uint32_t len : buffer length in byte. + * + * @return None + */ +uint32_t crc32_be(uint32_t crc, uint8_t const *buf, uint32_t len); + +/** + * @brief Crc16 value that is in little endian. + * + * @param uint16_t crc : init crc value, use 0 at the first use. + * + * @param uint8_t const *buf : buffer to start calculate crc. + * + * @param uint32_t len : buffer length in byte. + * + * @return None + */ +uint16_t crc16_le(uint16_t crc, uint8_t const *buf, uint32_t len); + +/** + * @brief Crc16 value that is in big endian. + * + * @param uint16_t crc : init crc value, use 0 at the first use. + * + * @param uint8_t const *buf : buffer to start calculate crc. + * + * @param uint32_t len : buffer length in byte. + * + * @return None + */ +uint16_t crc16_be(uint16_t crc, uint8_t const *buf, uint32_t len); + +/** + * @brief Crc8 value that is in little endian. + * + * @param uint8_t crc : init crc value, use 0 at the first use. + * + * @param uint8_t const *buf : buffer to start calculate crc. + * + * @param uint32_t len : buffer length in byte. + * + * @return None + */ +uint8_t crc8_le(uint8_t crc, uint8_t const *buf, uint32_t len); + +/** + * @brief Crc8 value that is in big endian. + * + * @param uint32_t crc : init crc value, use 0 at the first use. + * + * @param uint8_t const *buf : buffer to start calculate crc. + * + * @param uint32_t len : buffer length in byte. + * + * @return None + */ +uint8_t crc8_be(uint8_t crc, uint8_t const *buf, uint32_t len); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif diff --git a/components/esp_rom/include/esp32c61/rom/ecdsa.h b/components/esp_rom/include/esp32c61/rom/ecdsa.h new file mode 100644 index 0000000000..fbf5b06905 --- /dev/null +++ b/components/esp_rom/include/esp32c61/rom/ecdsa.h @@ -0,0 +1,26 @@ +/* + * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define ETS_DIGEST_LEN 32 /* SHA-256, bytes */ + +typedef enum { + ECDSA_CURVE_P192 = 1, + ECDSA_CURVE_P256 = 2 +} ECDSA_CURVE; + +int ets_ecdsa_verify(const uint8_t *key, const uint8_t *sig, ECDSA_CURVE curve_id, const uint8_t *digest, uint8_t *verified_digest); + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_rom/include/esp32c61/rom/efuse.h b/components/esp_rom/include/esp32c61/rom/efuse.h new file mode 100644 index 0000000000..2c95712579 --- /dev/null +++ b/components/esp_rom/include/esp32c61/rom/efuse.h @@ -0,0 +1,283 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ROM_EFUSE_H_ +#define _ROM_EFUSE_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +/** \defgroup efuse_APIs efuse APIs + * @brief ESP32 efuse read/write APIs + * @attention + * + */ + +/** @addtogroup efuse_APIs + * @{ + */ + +typedef enum { + ETS_EFUSE_KEY_PURPOSE_USER = 0, + ETS_EFUSE_KEY_PURPOSE_RESERVED = 1, + ETS_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY = 4, + ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL = 5, + ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG = 6, + ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE = 7, + ETS_EFUSE_KEY_PURPOSE_HMAC_UP = 8, + ETS_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST0 = 9, + ETS_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST1 = 10, + ETS_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST2 = 11, + ETS_EFUSE_KEY_PURPOSE_MAX, +} ets_efuse_purpose_t; + +typedef enum { + ETS_EFUSE_BLOCK0 = 0, + ETS_EFUSE_MAC_SPI_SYS_0 = 1, + ETS_EFUSE_BLOCK_SYS_DATA = 2, + ETS_EFUSE_BLOCK_USR_DATA = 3, + ETS_EFUSE_BLOCK_KEY0 = 4, + ETS_EFUSE_BLOCK_KEY1 = 5, + ETS_EFUSE_BLOCK_KEY2 = 6, + ETS_EFUSE_BLOCK_KEY3 = 7, + ETS_EFUSE_BLOCK_KEY4 = 8, + ETS_EFUSE_BLOCK_KEY5 = 9, + ETS_EFUSE_BLOCK_KEY6 = 10, + ETS_EFUSE_BLOCK_MAX, +} ets_efuse_block_t; + +/** + * @brief Efuse read operation: copies data from physical efuses to efuse read registers. + * + * @param null + * + * @return : 0 if success, others if apb clock is not accepted + */ +int ets_efuse_read(void); + +/** + * @brief Efuse write operation: Copies data from efuse write registers to efuse. Operates on a single block of efuses at a time. + * + * @note This function does not update read efuses, call ets_efuse_read() once all programming is complete. + * + * @return : 0 if success, others if apb clock is not accepted + */ +int ets_efuse_program(ets_efuse_block_t block); + +/** + * @brief Set all Efuse program registers to zero. + * + * Call this before writing new data to the program registers. + */ +void ets_efuse_clear_program_registers(void); + +/** + * @brief Program a block of key data to an efuse block + * + * @param key_block Block to read purpose for. Must be in range ETS_EFUSE_BLOCK_KEY0 to ETS_EFUSE_BLOCK_KEY6. Key block must be unused (@ref ets_efuse_key_block_unused). + * @param purpose Purpose to set for this key. Purpose must be already unset. + * @param data Pointer to data to write. + * @param data_len Length of data to write. + * + * @note This function also calls ets_efuse_program() for the specified block, and for block 0 (setting the purpose) + */ +int ets_efuse_write_key(ets_efuse_block_t key_block, ets_efuse_purpose_t purpose, const void *data, size_t data_len); + + +/* @brief Return the address of a particular efuse block's first read register + * + * @param block Index of efuse block to look up + * + * @return 0 if block is invalid, otherwise a numeric read register address + * of the first word in the block. + */ +uint32_t ets_efuse_get_read_register_address(ets_efuse_block_t block); + +/** + * @brief Return the current purpose set for an efuse key block + * + * @param key_block Block to read purpose for. Must be in range ETS_EFUSE_BLOCK_KEY0 to ETS_EFUSE_BLOCK_KEY6. + */ +ets_efuse_purpose_t ets_efuse_get_key_purpose(ets_efuse_block_t key_block); + +/** + * @brief Find a key block with the particular purpose set + * + * @param purpose Purpose to search for. + * @param[out] key_block Pointer which will be set to the key block if found. Can be NULL, if only need to test the key block exists. + * @return true if found, false if not found. If false, value at key_block pointer is unchanged. + */ +bool ets_efuse_find_purpose(ets_efuse_purpose_t purpose, ets_efuse_block_t *key_block); + +/** + * Return true if the key block is unused, false otherwise. + * + * An unused key block is all zero content, not read or write protected, + * and has purpose 0 (ETS_EFUSE_KEY_PURPOSE_USER) + * + * @param key_block key block to check. + * + * @return true if key block is unused, false if key block or used + * or the specified block index is not a key block. + */ +bool ets_efuse_key_block_unused(ets_efuse_block_t key_block); + + +/** + * @brief Search for an unused key block and return the first one found. + * + * See @ref ets_efuse_key_block_unused for a description of an unused key block. + * + * @return First unused key block, or ETS_EFUSE_BLOCK_MAX if no unused key block is found. + */ +ets_efuse_block_t ets_efuse_find_unused_key_block(void); + +/** + * @brief Return the number of unused efuse key blocks (0-6) + */ +unsigned ets_efuse_count_unused_key_blocks(void); + +/** + * @brief Calculate Reed-Solomon Encoding values for a block of efuse data. + * + * @param data Pointer to data buffer (length 32 bytes) + * @param rs_values Pointer to write encoded data to (length 12 bytes) + */ +void ets_efuse_rs_calculate(const void *data, void *rs_values); + +/** + * @brief Read if download mode disabled from Efuse + * + * @return + * - true for efuse disable download mode. + * - false for efuse doesn't disable download mode. + */ +bool ets_efuse_download_modes_disabled(void); + +/** + * @brief Read if uart print control value from Efuse + * + * @return + * - 0 for uart force print. + * - 1 for uart print when GPIO8 is low when digital reset. + * 2 for uart print when GPIO8 is high when digital reset. + * 3 for uart force slient + */ +uint32_t ets_efuse_get_uart_print_control(void); + +/** + * @brief Read if usb download mode disabled from Efuse + * + * (Also returns true if security download mode is enabled, as this mode + * disables USB download.) + * + * @return + * - true for efuse disable usb download mode. + * - false for efuse doesn't disable usb download mode. + */ +bool ets_efuse_usb_download_mode_disabled(void); + +/** + * @brief Read if security download modes enabled from Efuse + * + * @return + * - true for efuse enable security download mode. + * - false for efuse doesn't enable security download mode. + */ +bool ets_efuse_security_download_modes_enabled(void); + +/** + * @brief Return true if secure boot is enabled in EFuse + */ +bool ets_efuse_secure_boot_enabled(void); + +/** + * @brief Return true if secure boot aggressive revoke is enabled in EFuse + */ +bool ets_efuse_secure_boot_aggressive_revoke_enabled(void); + +/** + * @brief Return true if cache encryption (flash, etc) is enabled from boot via EFuse + */ +bool ets_efuse_cache_encryption_enabled(void); + +/** + * @brief Return true if EFuse indicates to send a flash resume command. + */ +bool ets_efuse_force_send_resume(void); + +/** + * @brief return the time in us ROM boot need wait flash to power on from Efuse + * + * @return + * - uint32_t the time in us. + */ +uint32_t ets_efuse_get_flash_delay_us(void); + +#define EFUSE_SPICONFIG_SPI_DEFAULTS 0 +#define EFUSE_SPICONFIG_HSPI_DEFAULTS 1 + +#define EFUSE_SPICONFIG_RET_SPICLK_MASK 0x3f +#define EFUSE_SPICONFIG_RET_SPICLK_SHIFT 0 +#define EFUSE_SPICONFIG_RET_SPICLK(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPICLK_SHIFT) & EFUSE_SPICONFIG_RET_SPICLK_MASK) + +#define EFUSE_SPICONFIG_RET_SPIQ_MASK 0x3f +#define EFUSE_SPICONFIG_RET_SPIQ_SHIFT 6 +#define EFUSE_SPICONFIG_RET_SPIQ(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPIQ_SHIFT) & EFUSE_SPICONFIG_RET_SPIQ_MASK) + +#define EFUSE_SPICONFIG_RET_SPID_MASK 0x3f +#define EFUSE_SPICONFIG_RET_SPID_SHIFT 12 +#define EFUSE_SPICONFIG_RET_SPID(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPID_SHIFT) & EFUSE_SPICONFIG_RET_SPID_MASK) + +#define EFUSE_SPICONFIG_RET_SPICS0_MASK 0x3f +#define EFUSE_SPICONFIG_RET_SPICS0_SHIFT 18 +#define EFUSE_SPICONFIG_RET_SPICS0(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPICS0_SHIFT) & EFUSE_SPICONFIG_RET_SPICS0_MASK) + + +#define EFUSE_SPICONFIG_RET_SPIHD_MASK 0x3f +#define EFUSE_SPICONFIG_RET_SPIHD_SHIFT 24 +#define EFUSE_SPICONFIG_RET_SPIHD(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPIHD_SHIFT) & EFUSE_SPICONFIG_RET_SPIHD_MASK) + +/** + * @brief Enable JTAG temporarily by writing a JTAG HMAC "key" into + * the JTAG_CTRL registers. + * + * Works if JTAG has been "soft" disabled by burning the EFUSE_SOFT_DIS_JTAG efuse. + * + * Will enable the HMAC module to generate a "downstream" HMAC value from a key already saved in efuse, and then write the JTAG HMAC "key" which will enable JTAG if the two keys match. + * + * @param jtag_hmac_key Pointer to a 32 byte array containing a valid key. Supplied by user. + * @param key_block Index of a key block containing the source for this key. + * + * @return ETS_FAILED if HMAC operation fails or invalid parameter, ETS_OK otherwise. ETS_OK doesn't necessarily mean that JTAG was enabled. + */ +int ets_jtag_enable_temporarily(const uint8_t *jtag_hmac_key, ets_efuse_block_t key_block); + +/** + * @brief A crc8 algorithm used for MAC addresses in efuse + * + * @param unsigned char const *p : Pointer to original data. + * + * @param unsigned int len : Data length in byte. + * + * @return unsigned char: Crc value. + */ +unsigned char esp_crc8(unsigned char const *p, unsigned int len); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* _ROM_EFUSE_H_ */ diff --git a/components/esp_rom/include/esp32c61/rom/esp_flash.h b/components/esp_rom/include/esp32c61/rom/esp_flash.h new file mode 100644 index 0000000000..6d48e4be2c --- /dev/null +++ b/components/esp_rom/include/esp32c61/rom/esp_flash.h @@ -0,0 +1,46 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "esp_err.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Note: Most of esp_flash APIs in ROM are compatible with headers in ESP-IDF, this function + just adds ROM-specific parts +*/ + +struct spi_flash_chip_t; +typedef struct esp_flash_t esp_flash_t; + +/* Structure to wrap "global" data used by esp_flash in ROM */ +typedef struct { + /* Default SPI flash chip, ie main chip attached to the MCU + This chip is used if the 'chip' argument passed to esp_flash_xxx API functions is ever NULL + */ + esp_flash_t *default_chip; + + /* Global API OS notification start/end/chip_check functions + + These are used by ROM if no other host functions are configured. + */ + struct { + esp_err_t (*start)(esp_flash_t *chip); + esp_err_t (*end)(esp_flash_t *chip, esp_err_t err); + esp_err_t (*chip_check)(esp_flash_t **inout_chip); + } api_funcs; +} esp_flash_rom_global_data_t; + +/** Access a pointer to the global data used by the ROM spi_flash driver + */ +esp_flash_rom_global_data_t *esp_flash_get_rom_global_data(void); + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_rom/include/esp32c61/rom/ets_sys.h b/components/esp_rom/include/esp32c61/rom/ets_sys.h new file mode 100644 index 0000000000..516a694fcd --- /dev/null +++ b/components/esp_rom/include/esp32c61/rom/ets_sys.h @@ -0,0 +1,432 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ROM_ETS_SYS_H_ +#define _ROM_ETS_SYS_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** \defgroup ets_sys_apis, ets system related apis + * @brief ets system apis + */ + +/** @addtogroup ets_sys_apis + * @{ + */ + +/************************************************************************ + * NOTE + * Many functions in this header files can't be run in FreeRTOS. + * Please see the comment of the Functions. + * There are also some functions that doesn't work on FreeRTOS + * without listed in the header, such as: + * xtos functions start with "_xtos_" in ld file. + * + *********************************************************************** + */ + +/** \defgroup ets_apis, Espressif Task Scheduler related apis + * @brief ets apis + */ + +/** @addtogroup ets_apis + * @{ + */ + +typedef enum { + ETS_OK = 0, /**< return successful in ets*/ + ETS_FAILED = 1, /**< return failed in ets*/ + ETS_PENDING = 2, + ETS_BUSY = 3, + ETS_CANCEL = 4, +} ETS_STATUS; + +typedef ETS_STATUS ets_status_t; + +typedef uint32_t ETSSignal; +typedef uint32_t ETSParam; + +typedef struct ETSEventTag ETSEvent; /**< Event transmit/receive in ets*/ + +struct ETSEventTag { + ETSSignal sig; /**< Event signal, in same task, different Event with different signal*/ + ETSParam par; /**< Event parameter, sometimes without usage, then will be set as 0*/ +}; + +typedef void (*ETSTask)(ETSEvent *e); /**< Type of the Task processer*/ +typedef void (* ets_idle_cb_t)(void *arg); /**< Type of the system idle callback*/ + + + + + +/** + * @} + */ + +/** \defgroup ets_boot_apis, Boot routing related apis + * @brief ets boot apis + */ + +/** @addtogroup ets_apis + * @{ + */ + +extern const char *const exc_cause_table[40]; ///**< excption cause that defined by the core.*/ + +/** + * @brief Set Pro cpu Entry code, code can be called in PRO CPU when booting is not completed. + * When Pro CPU booting is completed, Pro CPU will call the Entry code if not NULL. + * + * @param uint32_t start : the PRO Entry code address value in uint32_t + * + * @return None + */ +void ets_set_user_start(uint32_t start); + +/** + * @} + */ + +/** \defgroup ets_printf_apis, ets_printf related apis used in ets + * @brief ets printf apis + */ + +/** @addtogroup ets_printf_apis + * @{ + */ + +/** + * @brief Printf the strings to uart or other devices, similar with printf, simple than printf. + * Can not print float point data format, or longlong data format. + * So we maybe only use this in ROM. + * + * @param const char *fmt : See printf. + * + * @param ... : See printf. + * + * @return int : the length printed to the output device. + */ +int ets_printf(const char *fmt, ...); + +/** + * @brief Get the uart channel of ets_printf(uart_tx_one_char). + * + * @return uint8_t uart channel used by ets_printf(uart_tx_one_char). + */ +uint8_t ets_get_printf_channel(void); + +/** + * @brief Output a char to uart, which uart to output(which is in uart module in ROM) is not in scope of the function. + * Can not print float point data format, or longlong data format + * + * @param char c : char to output. + * + * @return None + */ +void ets_write_char_uart(char c); + +/** + * @brief Ets_printf have two output functions： putc1 and putc2, both of which will be called if need ouput. + * To install putc1, which is defaulted installed as ets_write_char_uart in none silent boot mode, as NULL in silent mode. + * + * @param void (*)(char) p: Output function to install. + * + * @return None + */ +void ets_install_putc1(void (*p)(char c)); + +/** + * @brief Ets_printf have two output functions： putc1 and putc2, both of which will be called if need ouput. + * To install putc2, which is defaulted installed as NULL. + * + * @param void (*)(char) p: Output function to install. + * + * @return None + */ +void ets_install_putc2(void (*p)(char c)); + +/** + * @brief Install putc1 as ets_write_char_uart. + * In silent boot mode(to void interfere the UART attached MCU), we can call this function, after booting ok. + * + * @param None + * + * @return None + */ +void ets_install_uart_printf(void); + +#define ETS_PRINTF(...) ets_printf(...) + +#define ETS_ASSERT(v) do { \ + if (!(v)) { \ + ets_printf("%s %u \n", __FILE__, __LINE__); \ + while (1) {}; \ + } \ +} while (0); + +/** + * @} + */ + +/** \defgroup ets_timer_apis, ets_timer related apis used in ets + * @brief ets timer apis + */ + +/** @addtogroup ets_timer_apis + * @{ + */ +typedef void ETSTimerFunc(void *timer_arg);/**< timer handler*/ + +typedef struct _ETSTIMER_ { + struct _ETSTIMER_ *timer_next; /**< timer linker*/ + uint32_t timer_expire; /**< abstruct time when timer expire*/ + uint32_t timer_period; /**< timer period, 0 means timer is not periodic repeated*/ + ETSTimerFunc *timer_func; /**< timer handler*/ + void *timer_arg; /**< timer handler argument*/ +} ETSTimer; + +/** + * @brief Init ets timer, this timer range is 640 us to 429496 ms + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param None + * + * @return None + */ +void ets_timer_init(void); + +/** + * @brief In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param None + * + * @return None + */ +void ets_timer_deinit(void); + +/** + * @brief Arm an ets timer, this timer range is 640 us to 429496 ms. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param ETSTimer *timer : Timer struct pointer. + * + * @param uint32_t tmout : Timer value in ms, range is 1 to 429496. + * + * @param bool repeat : Timer is periodic repeated. + * + * @return None + */ +void ets_timer_arm(ETSTimer *timer, uint32_t tmout, bool repeat); + +/** + * @brief Arm an ets timer, this timer range is 640 us to 429496 ms. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param ETSTimer *timer : Timer struct pointer. + * + * @param uint32_t tmout : Timer value in us, range is 1 to 429496729. + * + * @param bool repeat : Timer is periodic repeated. + * + * @return None + */ +void ets_timer_arm_us(ETSTimer *ptimer, uint32_t us, bool repeat); + +/** + * @brief Disarm an ets timer. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param ETSTimer *timer : Timer struct pointer. + * + * @return None + */ +void ets_timer_disarm(ETSTimer *timer); + +/** + * @brief Set timer callback and argument. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param ETSTimer *timer : Timer struct pointer. + * + * @param ETSTimerFunc *pfunction : Timer callback. + * + * @param void *parg : Timer callback argument. + * + * @return None + */ +void ets_timer_setfn(ETSTimer *ptimer, ETSTimerFunc *pfunction, void *parg); + +/** + * @brief Unset timer callback and argument to NULL. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param ETSTimer *timer : Timer struct pointer. + * + * @return None + */ +void ets_timer_done(ETSTimer *ptimer); + +/** + * @brief CPU do while loop for some time. + * In FreeRTOS task, please call FreeRTOS apis. + * + * @param uint32_t us : Delay time in us. + * + * @return None + */ +void ets_delay_us(uint32_t us); + +/** + * @brief Set the real CPU ticks per us to the ets, so that ets_delay_us will be accurate. + * Call this function when CPU frequency is changed. + * + * @param uint32_t ticks_per_us : CPU ticks per us. + * + * @return None + */ +void ets_update_cpu_frequency(uint32_t ticks_per_us); + + + +/** + * @brief Get the real CPU ticks per us to the ets. + * This function do not return real CPU ticks per us, just the record in ets. It can be used to check with the real CPU frequency. + * + * @param None + * + * @return uint32_t : CPU ticks per us record in ets. + */ +uint32_t ets_get_cpu_frequency(void); + +/** + * @} + */ + +/** \defgroup ets_intr_apis, ets interrupt configure related apis + * @brief ets intr apis + */ + +/** @addtogroup ets_intr_apis + * @{ + */ + +typedef void (* ets_isr_t)(void *);/**< interrupt handler type*/ + +/** + * @brief Attach a interrupt handler to a CPU interrupt number. + * This function equals to _xtos_set_interrupt_handler_arg(i, func, arg). + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param int i : CPU interrupt number. + * + * @param ets_isr_t func : Interrupt handler. + * + * @param void *arg : argument of the handler. + * + * @return None + */ +void ets_isr_attach(int i, ets_isr_t func, void *arg); + +/** + * @brief Mask the interrupts which show in mask bits. + * This function equals to _xtos_ints_off(mask). + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param uint32_t mask : BIT(i) means mask CPU interrupt number i. + * + * @return None + */ +void ets_isr_mask(uint32_t mask); + +/** + * @brief Unmask the interrupts which show in mask bits. + * This function equals to _xtos_ints_on(mask). + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param uint32_t mask : BIT(i) means mask CPU interrupt number i. + * + * @return None + */ +void ets_isr_unmask(uint32_t unmask); + +/** + * @brief Lock the interrupt to level 2. + * This function direct set the CPU registers. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param None + * + * @return None + */ +void ets_intr_lock(void); + +/** + * @brief Unlock the interrupt to level 0. + * This function direct set the CPU registers. + * In FreeRTOS, please call FreeRTOS apis, never call this api. + * + * @param None + * + * @return None + */ +void ets_intr_unlock(void); + + +/** + * @brief Attach an CPU interrupt to a hardware source. + * We have 4 steps to use an interrupt: + * 1.Attach hardware interrupt source to CPU. intr_matrix_set(0, ETS_WIFI_MAC_INTR_SOURCE, ETS_WMAC_INUM); + * 2.Set interrupt handler. xt_set_interrupt_handler(ETS_WMAC_INUM, func, NULL); + * 3.Enable interrupt for CPU. xt_ints_on(1 << ETS_WMAC_INUM); + * 4.Enable interrupt in the module. + * + * @param int cpu_no : The CPU which the interrupt number belongs. + * + * @param uint32_t model_num : The interrupt hardware source number, please see the interrupt hardware source table. + * + * @param uint32_t intr_num : The interrupt number CPU, please see the interrupt cpu using table. + * + * @return None + */ +void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num); + +/** + * @} + */ + +#ifndef MAC2STR +#define MAC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5] +#define MACSTR "%02x:%02x:%02x:%02x:%02x:%02x" +#endif + +#define ETS_MEM_BAR() asm volatile ( "" : : : "memory" ) + +#ifdef ESP_PLATFORM +// Remove in IDF v6.0 (IDF-7044) +typedef enum { + OK = 0, + FAIL, + PENDING, + BUSY, + CANCEL, +} STATUS __attribute__((deprecated("Use ETS_STATUS instead"))); +#endif + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* _ROM_ETS_SYS_H_ */ diff --git a/components/esp_rom/include/esp32c61/rom/gpio.h b/components/esp_rom/include/esp32c61/rom/gpio.h new file mode 100644 index 0000000000..e96264f1f1 --- /dev/null +++ b/components/esp_rom/include/esp32c61/rom/gpio.h @@ -0,0 +1,208 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include +#include "soc/gpio_reg.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** \defgroup gpio_apis, uart configuration and communication related apis + * @brief gpio apis + */ + +/** @addtogroup gpio_apis + * @{ + */ + +#define GPIO_REG_READ(reg) READ_PERI_REG(reg) +#define GPIO_REG_WRITE(reg, val) WRITE_PERI_REG(reg, val) +#define GPIO_ID_PIN0 0 +#define GPIO_ID_PIN(n) (GPIO_ID_PIN0+(n)) +#define GPIO_PIN_ADDR(i) (GPIO_PIN0_REG + i*4) + +#define GPIO_FUNC_IN_HIGH 0x38 +#define GPIO_FUNC_IN_LOW 0x3C + +#define GPIO_ID_IS_PIN_REGISTER(reg_id) \ + ((reg_id >= GPIO_ID_PIN0) && (reg_id <= GPIO_ID_PIN(GPIO_PIN_COUNT-1))) + +#define GPIO_REGID_TO_PINIDX(reg_id) ((reg_id) - GPIO_ID_PIN0) + +typedef enum { + GPIO_PIN_INTR_DISABLE = 0, + GPIO_PIN_INTR_POSEDGE = 1, + GPIO_PIN_INTR_NEGEDGE = 2, + GPIO_PIN_INTR_ANYEDGE = 3, + GPIO_PIN_INTR_LOLEVEL = 4, + GPIO_PIN_INTR_HILEVEL = 5 +} GPIO_INT_TYPE; + + +/** + * @brief Change GPIO(0-30) pin output by setting, clearing, or disabling pins, GPIO0<->BIT(0). + * There is no particular ordering guaranteed; so if the order of writes is significant, + * calling code should divide a single call into multiple calls. + * + * @param uint32_t set_mask : the gpios that need high level. + * + * @param uint32_t clear_mask : the gpios that need low level. + * + * @param uint32_t enable_mask : the gpios that need be changed. + * + * @param uint32_t disable_mask : the gpios that need diable output. + * + * @return None + */ +void gpio_output_set(uint32_t set_mask, uint32_t clear_mask, uint32_t enable_mask, uint32_t disable_mask); + +/** + * @brief Sample the value of GPIO input pins(0-30) and returns a bitmask. + * @param None + * + * @return uint32_t : bitmask for GPIO input pins, BIT(0) for GPIO0. + */ +uint32_t gpio_input_get(void); + +/** + * @brief Set GPIO to wakeup the ESP32. + * Please do not call this function in SDK. + * + * @param uint32_t i: gpio number. + * + * @param GPIO_INT_TYPE intr_state : only GPIO_PIN_INTR_LOLEVEL\GPIO_PIN_INTR_HILEVEL can be used + * + * @return None + */ +void gpio_pin_wakeup_enable(uint32_t i, GPIO_INT_TYPE intr_state); + +/** + * @brief disable GPIOs to wakeup the ESP32. + * Please do not call this function in SDK. + * + * @param None + * + * @return None + */ +void gpio_pin_wakeup_disable(void); + +/** + * @brief set gpio input to a signal, one gpio can input to several signals. + * + * @param uint32_t gpio : gpio number, 0~30 + * gpio == 0x3C, input 0 to signal + * gpio == 0x3A, input nothing to signal + * gpio == 0x38, input 1 to signal + * + * @param uint32_t signal_idx : signal index. + * + * @param bool inv : the signal is inv or not + * + * @return None + */ +void gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv); + +/** + * @brief set signal output to gpio, one signal can output to several gpios. + * + * @param uint32_t gpio : gpio number, 0~30 + * + * @param uint32_t signal_idx : signal index. + * signal_idx == 0x80, cancel output put to the gpio + * + * @param bool out_inv : the signal output is invert or not + * + * @param bool oen_inv : the signal output enable is invert or not + * + * @return None + */ +void gpio_matrix_out(uint32_t gpio, uint32_t signal_idx, bool out_inv, bool oen_inv); + +/** + * @brief Select pad as a gpio function from IOMUX. + * + * @param uint32_t gpio_num : gpio number, 0~30 + * + * @return None + */ +void gpio_pad_select_gpio(uint32_t gpio_num); + +/** + * @brief Set pad driver capability. + * + * @param uint32_t gpio_num : gpio number, 0~30 + * + * @param uint32_t drv : 0-3 + * + * @return None + */ +void gpio_pad_set_drv(uint32_t gpio_num, uint32_t drv); + +/** + * @brief Pull up the pad from gpio number. + * + * @param uint32_t gpio_num : gpio number, 0~30 + * + * @return None + */ +void gpio_pad_pullup(uint32_t gpio_num); + +/** + * @brief Pull down the pad from gpio number. + * + * @param uint32_t gpio_num : gpio number, 0~30 + * + * @return None + */ +void gpio_pad_pulldown(uint32_t gpio_num); + +/** + * @brief Unhold the pad from gpio number. + * + * @param uint32_t gpio_num : gpio number, 0~30 + * + * @return None + */ +void gpio_pad_unhold(uint32_t gpio_num); + +/** + * @brief Hold the pad from gpio number. + * + * @param uint32_t gpio_num : gpio number, 0~30 + * + * @return None + */ +void gpio_pad_hold(uint32_t gpio_num); + +/** + * @brief enable gpio pad input. + * + * @param uint32_t gpio_num : gpio number, 0~30 + * + * @return None + */ +void gpio_pad_input_enable(uint32_t gpio_num); + +/** + * @brief disable gpio pad input. + * + * @param uint32_t gpio_num : gpio number, 0~30 + * + * @return None + */ +void gpio_pad_input_disable(uint32_t gpio_num); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_rom/include/esp32c61/rom/libc_stubs.h b/components/esp_rom/include/esp32c61/rom/libc_stubs.h new file mode 100644 index 0000000000..6d9c31a938 --- /dev/null +++ b/components/esp_rom/include/esp32c61/rom/libc_stubs.h @@ -0,0 +1,83 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef _ROM_LIBC_STUBS_H_ +#define _ROM_LIBC_STUBS_H_ + +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* +ESP32-C6 ROM code contains implementations of some of C library functions. +Whenever a function in ROM needs to use a syscall, it calls a pointer to the corresponding syscall +implementation defined in the following struct. + +The table itself, by default, is not allocated in RAM. A global pointer syscall_table_ptr is used to +set the address + +So, before using any of the C library functions (except for pure functions and memcpy/memset functions), +application must allocate syscall table structure for each CPU being used, and populate it with pointers +to actual implementations of corresponding syscalls. +*/ + +struct syscall_stub_table { + struct _reent *(*__getreent)(void); + void *(*_malloc_r)(struct _reent *r, size_t); + void (*_free_r)(struct _reent *r, void *); + void *(*_realloc_r)(struct _reent *r, void *, size_t); + void *(*_calloc_r)(struct _reent *r, size_t, size_t); + void (*_abort)(void); + int (*_system_r)(struct _reent *r, const char *); + int (*_rename_r)(struct _reent *r, const char *, const char *); + clock_t (*_times_r)(struct _reent *r, struct tms *); + int (*_gettimeofday_r) (struct _reent *r, struct timeval *, void *); + void (*_raise_r)(struct _reent *r); + int (*_unlink_r)(struct _reent *r, const char *); + int (*_link_r)(struct _reent *r, const char *, const char *); + int (*_stat_r)(struct _reent *r, const char *, struct stat *); + int (*_fstat_r)(struct _reent *r, int, struct stat *); + void *(*_sbrk_r)(struct _reent *r, ptrdiff_t); + int (*_getpid_r)(struct _reent *r); + int (*_kill_r)(struct _reent *r, int, int); + void (*_exit_r)(struct _reent *r, int); + int (*_close_r)(struct _reent *r, int); + int (*_open_r)(struct _reent *r, const char *, int, int); + int (*_write_r)(struct _reent *r, int, const void *, int); + int (*_lseek_r)(struct _reent *r, int, int, int); + int (*_read_r)(struct _reent *r, int, void *, int); + void (*_retarget_lock_init)(_LOCK_T *lock); + void (*_retarget_lock_init_recursive)(_LOCK_T *lock); + void (*_retarget_lock_close)(_LOCK_T lock); + void (*_retarget_lock_close_recursive)(_LOCK_T lock); + void (*_retarget_lock_acquire)(_LOCK_T lock); + void (*_retarget_lock_acquire_recursive)(_LOCK_T lock); + int (*_retarget_lock_try_acquire)(_LOCK_T lock); + int (*_retarget_lock_try_acquire_recursive)(_LOCK_T lock); + void (*_retarget_lock_release)(_LOCK_T lock); + void (*_retarget_lock_release_recursive)(_LOCK_T lock); + int (*_printf_float)(struct _reent *data, void *pdata, FILE *fp, int (*pfunc) (struct _reent *, FILE *, const char *, size_t len), va_list *ap); + int (*_scanf_float) (struct _reent *rptr, void *pdata, FILE *fp, va_list *ap); + void (*__assert_func) (const char *file, int line, const char *func, const char *failedexpr) __attribute__((__noreturn__)); + void (*__sinit) (struct _reent *r); + void (*_cleanup_r) (struct _reent *r); +}; + +extern struct syscall_stub_table *syscall_table_ptr; + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif /* _ROM_LIBC_STUBS_H_ */ diff --git a/components/esp_rom/include/esp32c61/rom/lldesc.h b/components/esp_rom/include/esp32c61/rom/lldesc.h new file mode 100644 index 0000000000..afb86b27e9 --- /dev/null +++ b/components/esp_rom/include/esp32c61/rom/lldesc.h @@ -0,0 +1,139 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ROM_LLDESC_H_ +#define _ROM_LLDESC_H_ + +#include + +#include "sys/queue.h" +#include "esp_rom_lldesc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define LLDESC_TX_MBLK_SIZE 268 /* */ +#define LLDESC_RX_SMBLK_SIZE 64 /* small block size, for small mgmt frame */ +#define LLDESC_RX_MBLK_SIZE 524 /* rx is large sinec we want to contain mgmt frame in one block*/ +#define LLDESC_RX_AMPDU_ENTRY_MBLK_SIZE 64 /* it is a small buffer which is a cycle link*/ +#define LLDESC_RX_AMPDU_LEN_MBLK_SIZE 256 /*for ampdu entry*/ +#ifdef ESP_MAC_5 +#define LLDESC_TX_MBLK_NUM 116 /* 64K / 256 */ +#define LLDESC_RX_MBLK_NUM 82 /* 64K / 512 MAX 172*/ +#define LLDESC_RX_AMPDU_ENTRY_MBLK_NUM 4 +#define LLDESC_RX_AMPDU_LEN_MLBK_NUM 12 +#else +#ifdef SBUF_RXTX +#define LLDESC_TX_MBLK_NUM_MAX (2 * 48) /* 23K / 260 - 8 */ +#define LLDESC_RX_MBLK_NUM_MAX (2 * 48) /* 23K / 524 */ +#define LLDESC_TX_MBLK_NUM_MIN (2 * 16) /* 23K / 260 - 8 */ +#define LLDESC_RX_MBLK_NUM_MIN (2 * 16) /* 23K / 524 */ +#endif +#define LLDESC_TX_MBLK_NUM 10 //(2 * 32) /* 23K / 260 - 8 */ + +#ifdef IEEE80211_RX_AMPDU +#define LLDESC_RX_MBLK_NUM 30 +#else +#define LLDESC_RX_MBLK_NUM 10 +#endif /*IEEE80211_RX_AMPDU*/ + +#define LLDESC_RX_AMPDU_ENTRY_MBLK_NUM 4 +#define LLDESC_RX_AMPDU_LEN_MLBK_NUM 8 +#endif /* !ESP_MAC_5 */ + +typedef struct tx_ampdu_entry_s { + uint32_t sub_len : 12, + dili_num : 7, + : 1, + null_byte: 2, + data : 1, + enc : 1, + seq : 8; +} tx_ampdu_entry_t; + +typedef struct lldesc_chain_s { + lldesc_t *head; + lldesc_t *tail; +} lldesc_chain_t; + +#ifdef SBUF_RXTX +enum sbuf_mask_s { + SBUF_MOVE_NO = 0, + SBUF_MOVE_TX2RX, + SBUF_MOVE_RX2TX, +} ; + +#define SBUF_MOVE_STEP 8 +#endif +#define LLDESC_SIZE sizeof(struct lldesc_s) + +/* SLC Descriptor */ +#define LLDESC_OWNER_MASK 0x80000000 +#define LLDESC_OWNER_SHIFT 31 +#define LLDESC_SW_OWNED 0 +#define LLDESC_HW_OWNED 1 + +#define LLDESC_EOF_MASK 0x40000000 +#define LLDESC_EOF_SHIFT 30 + +#define LLDESC_SOSF_MASK 0x20000000 +#define LLDESC_SOSF_SHIFT 29 + +#define LLDESC_LENGTH_MASK 0x00fff000 +#define LLDESC_LENGTH_SHIFT 12 + +#define LLDESC_SIZE_MASK 0x00000fff +#define LLDESC_SIZE_SHIFT 0 + +#define LLDESC_ADDR_MASK 0x000fffff + +void lldesc_build_chain(uint8_t *descptr, uint32_t desclen, uint8_t *mblkptr, uint32_t buflen, uint32_t blksz, uint8_t owner, + lldesc_t **head, +#ifdef TO_HOST_RESTART + lldesc_t **one_before_tail, +#endif + lldesc_t **tail); + +static inline uint32_t lldesc_get_chain_length(lldesc_t *head) +{ + lldesc_t *ds = head; + uint32_t len = 0; + + while (ds) { + len += ds->length; + ds = STAILQ_NEXT(ds, qe); + } + + return len; +} + +static inline void lldesc_config(lldesc_t *ds, uint8_t owner, uint8_t eof, uint8_t sosf, uint16_t len) +{ + ds->owner = owner; + ds->eof = eof; + ds->sosf = sosf; + ds->length = len; +} + +#define LLDESC_CONFIG(_desc, _owner, _eof, _sosf, _len) do { \ + (_desc)->owner = (_owner); \ + (_desc)->eof = (_eof); \ + (_desc)->sosf = (_sosf); \ + (_desc)->length = (_len); \ +} while(0) + +#define LLDESC_FROM_HOST_CLEANUP(ds) LLDESC_CONFIG((ds), LLDESC_HW_OWNED, 0, 0, 0) + +#define LLDESC_MAC_RX_CLEANUP(ds) LLDESC_CONFIG((ds), LLDESC_HW_OWNED, 0, 0, (ds)->size) + +#define LLDESC_TO_HOST_CLEANUP(ds) LLDESC_CONFIG((ds), LLDESC_HW_OWNED, 0, 0, 0) + +#ifdef __cplusplus +} +#endif + +#endif /* _ROM_LLDESC_H_ */ diff --git a/components/esp_rom/include/esp32c61/rom/md5_hash.h b/components/esp_rom/include/esp32c61/rom/md5_hash.h new file mode 100644 index 0000000000..3e00ae28b3 --- /dev/null +++ b/components/esp_rom/include/esp32c61/rom/md5_hash.h @@ -0,0 +1,41 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * MD5 internal definitions + * Copyright (c) 2003-2005, Jouni Malinen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Alternatively, this software may be distributed under the terms of BSD + * license. + * + * See README and COPYING for more details. + */ + +#pragma once + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct MD5Context { + uint32_t buf[4]; + uint32_t bits[2]; + uint8_t in[64]; +}; + +void MD5Init(struct MD5Context *context); +void MD5Update(struct MD5Context *context, unsigned char const *buf, unsigned len); +void MD5Final(unsigned char digest[16], struct MD5Context *context); + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_rom/include/esp32c61/rom/miniz.h b/components/esp_rom/include/esp32c61/rom/miniz.h new file mode 100644 index 0000000000..357e60a9c1 --- /dev/null +++ b/components/esp_rom/include/esp32c61/rom/miniz.h @@ -0,0 +1,8 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#warning "{target}/rom/miniz.h is deprecated, please use (#include "miniz.h") instead" +#include "../../miniz.h" diff --git a/components/esp_rom/include/esp32c61/rom/opi_flash.h b/components/esp_rom/include/esp32c61/rom/opi_flash.h new file mode 100644 index 0000000000..e3412d1962 --- /dev/null +++ b/components/esp_rom/include/esp32c61/rom/opi_flash.h @@ -0,0 +1,321 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include +#include +#include +#include "spi_flash.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +typedef struct { + uint8_t mode; + uint8_t cmd_bit_len; + uint16_t cmd; + uint32_t addr; + uint8_t addr_bit_len; + uint8_t dummy_bit_len; + uint8_t data_bit_len; + uint8_t cs_sel: 4; + uint8_t is_pe: 4; +} esp_rom_opiflash_cmd_t; + +typedef struct { + uint8_t addr_bit_len; + uint8_t dummy_bit_len; + uint16_t cmd; + uint8_t cmd_bit_len; + uint8_t var_dummy_en; +} esp_rom_opiflash_spi0rd_t; + +typedef struct { + esp_rom_opiflash_cmd_t rdid; + esp_rom_opiflash_cmd_t rdsr; + esp_rom_opiflash_cmd_t wren; + esp_rom_opiflash_cmd_t se; + esp_rom_opiflash_cmd_t be64k; + esp_rom_opiflash_cmd_t read; + esp_rom_opiflash_cmd_t pp; + esp_rom_opiflash_spi0rd_t cache_rd_cmd; +} esp_rom_opiflash_def_t; + +typedef struct { + uint16_t cmd; /*!< Command value */ + uint16_t cmdBitLen; /*!< Command byte length*/ + uint32_t *addr; /*!< Point to address value*/ + uint32_t addrBitLen; /*!< Address byte length*/ + uint32_t *txData; /*!< Point to send data buffer*/ + uint32_t txDataBitLen; /*!< Send data byte length.*/ + uint32_t *rxData; /*!< Point to recevie data buffer*/ + uint32_t rxDataBitLen; /*!< Recevie Data byte length.*/ + uint32_t dummyBitLen; +} esp_rom_spi_cmd_t; + +#define ESP_ROM_OPIFLASH_MUX_TAKE() +#define ESP_ROM_OPIFLASH_MUX_GIVE() +#define ESP_ROM_OPIFLASH_SEL_CS0 (BIT(0)) +#define ESP_ROM_OPIFLASH_SEL_CS1 (BIT(1)) + +// Definition of MX25UM25645G Octa Flash +// SPI status register +#define ESP_ROM_SPIFLASH_BUSY_FLAG BIT0 +#define ESP_ROM_SPIFLASH_WRENABLE_FLAG BIT1 +#define ESP_ROM_SPIFLASH_BP0 BIT2 +#define ESP_ROM_SPIFLASH_BP1 BIT3 +#define ESP_ROM_SPIFLASH_BP2 BIT4 +#define ESP_ROM_SPIFLASH_WR_PROTECT (ESP_ROM_SPIFLASH_BP0|ESP_ROM_SPIFLASH_BP1|ESP_ROM_SPIFLASH_BP2) +#define ESP_ROM_SPIFLASH_QE BIT9 + +#define FLASH_OP_MODE_RDCMD_DOUT 0x3B +#define ESP_ROM_FLASH_SECTOR_SIZE 0x1000 +#define ESP_ROM_FLASH_BLOCK_SIZE_64K 0x10000 +#define ESP_ROM_FLASH_PAGE_SIZE 256 + +// FLASH commands +#define ROM_FLASH_CMD_RDID 0x9F +#define ROM_FLASH_CMD_WRSR 0x01 +#define ROM_FLASH_CMD_WRSR2 0x31 /* Not all SPI flash uses this command */ +#define ROM_FLASH_CMD_WREN 0x06 +#define ROM_FLASH_CMD_WRDI 0x04 +#define ROM_FLASH_CMD_RDSR 0x05 +#define ROM_FLASH_CMD_RDSR2 0x35 /* Not all SPI flash uses this command */ +#define ROM_FLASH_CMD_ERASE_SEC 0x20 +#define ROM_FLASH_CMD_ERASE_BLK_32K 0x52 +#define ROM_FLASH_CMD_ERASE_BLK_64K 0xD8 +#define ROM_FLASH_CMD_OTPEN 0x3A /* Enable OTP mode, not all SPI flash uses this command */ +#define ROM_FLASH_CMD_RSTEN 0x66 +#define ROM_FLASH_CMD_RST 0x99 + +#define ROM_FLASH_CMD_SE4B 0x21 +#define ROM_FLASH_CMD_SE4B_OCT 0xDE21 +#define ROM_FLASH_CMD_BE4B 0xDC +#define ROM_FLASH_CMD_BE4B_OCT 0x23DC +#define ROM_FLASH_CMD_RSTEN_OCT 0x9966 +#define ROM_FLASH_CMD_RST_OCT 0x6699 + +#define ROM_FLASH_CMD_FSTRD4B_STR 0x13EC +#define ROM_FLASH_CMD_FSTRD4B_DTR 0x11EE +#define ROM_FLASH_CMD_FSTRD4B 0x0C +#define ROM_FLASH_CMD_PP4B 0x12 +#define ROM_FLASH_CMD_PP4B_OCT 0xED12 + +#define ROM_FLASH_CMD_RDID_OCT 0x609F +#define ROM_FLASH_CMD_WREN_OCT 0xF906 +#define ROM_FLASH_CMD_RDSR_OCT 0xFA05 +#define ROM_FLASH_CMD_RDCR2 0x71 +#define ROM_FLASH_CMD_RDCR2_OCT 0x8E71 +#define ROM_FLASH_CMD_WRCR2 0x72 +#define ROM_FLASH_CMD_WRCR2_OCT 0x8D72 + +// Definitions for GigaDevice GD25LX256E Flash +#define ROM_FLASH_CMD_RDFSR_GD 0x70 +#define ROM_FLASH_CMD_RD_GD 0x03 +#define ROM_FLASH_CMD_RD4B_GD 0x13 +#define ROM_FLASH_CMD_FSTRD_GD 0x0B +#define ROM_FLASH_CMD_FSTRD4B_GD 0x0C +#define ROM_FLASH_CMD_FSTRD_OOUT_GD 0x8B +#define ROM_FLASH_CMD_FSTRD4B_OOUT_GD 0x7C +#define ROM_FLASH_CMD_FSTRD_OIOSTR_GD 0xCB +#define ROM_FLASH_CMD_FSTRD4B_OIOSTR_GD 0xCC +#define ROM_FLASH_CMD_FSTRD4B_OIODTR_GD 0xFD + +#define ROM_FLASH_CMD_PP_GD 0x02 +#define ROM_FLASH_CMD_PP4B_GD 0x12 +#define ROM_FLASH_CMD_PP_OOUT_GD 0x82 +#define ROM_FLASH_CMD_PP4B_OOUT_GD 0x84 +#define ROM_FLASH_CMD_PP_OIO_GD 0xC2 +#define ROM_FLASH_CMD_PP4B_OIOSTR_GD 0x8E + +#define ROM_FLASH_CMD_SE_GD 0x20 +#define ROM_FLASH_CMD_SE4B_GD 0x21 +#define ROM_FLASH_CMD_BE32K_GD 0x52 +#define ROM_FLASH_CMD_BE32K4B_GD 0x5C +#define ROM_FLASH_CMD_BE64K_GD 0xD8 +#define ROM_FLASH_CMD_BE64K4B_GD 0xDC + +#define ROM_FLASH_CMD_EN4B_GD 0xB7 +#define ROM_FLASH_CMD_DIS4B_GD 0xE9 + +extern const esp_rom_opiflash_def_t *rom_opiflash_cmd_def; + +/** + * @brief init legacy driver for Octal Flash + */ +void esp_rom_opiflash_legacy_driver_init(const esp_rom_opiflash_def_t *flash_cmd_def); + +// spi user mode command config +/** + * @brief Config the spi user command + * @param spi_num spi port + * @param pcmd pointer to accept the spi command struct + */ +void esp_rom_spi_cmd_config(int spi_num, esp_rom_spi_cmd_t* pcmd); + +/** + * @brief Start a spi user command sequence + * @param spi_num spi port + * @param rx_buf buffer pointer to receive data + * @param rx_len receive data length in byte + * @param cs_en_mask decide which cs to use, 0 for cs0, 1 for cs1 + * @param is_write_erase to indicate whether this is a write or erase operation, since the CPU would check permission + */ +void esp_rom_spi_cmd_start(int spi_num, uint8_t* rx_buf, uint16_t rx_len, uint8_t cs_en_mask, bool is_write_erase); + +/** + * @brief Config opi flash pads according to efuse settings. + */ +void esp_rom_opiflash_pin_config(void); + +// set SPI read/write mode +/** + * @brief Set SPI operation mode + * @param spi_num spi port + * @param mode Flash Read Mode + */ +void esp_rom_spi_set_op_mode(int spi_num, esp_rom_spiflash_read_mode_t mode); + +/** + * @brief Set data swap mode in DTR(DDR) mode + * @param spi_num spi port + * @param wr_swap to decide whether to swap fifo data in dtr write operation + * @param rd_swap to decide whether to swap fifo data in dtr read operation + */ +void esp_rom_spi_set_dtr_swap_mode(int spi, bool wr_swap, bool rd_swap); + + +/** + * @brief to send reset command in spi/opi-str/opi-dtr mode(for MX25UM25645G) + * @param spi_num spi port + */ +void esp_rom_opiflash_mode_reset(int spi_num); + +/** + * @brief To execute a flash operation command + * @param spi_num spi port + * @param mode Flash Read Mode + * @param cmd data to send in command field + * @param cmd_bit_len bit length of command field + * @param addr data to send in address field + * @param addr_bit_len bit length of address field + * @param dummy_bits bit length of dummy field + * @param mosi_data data buffer to be sent in mosi field + * @param mosi_bit_len bit length of data buffer to be sent in mosi field + * @param miso_data data buffer to accept data in miso field + * @param miso_bit_len bit length of data buffer to accept data in miso field + * @param cs_mark decide which cs pin to use. 0: cs0, 1: cs1 + * @param is_write_erase_operation to indicate whether this a write or erase flash operation + */ +void esp_rom_opiflash_exec_cmd(int spi_num, esp_rom_spiflash_read_mode_t mode, + uint32_t cmd, int cmd_bit_len, + uint32_t addr, int addr_bit_len, + int dummy_bits, + uint8_t* mosi_data, int mosi_bit_len, + uint8_t* miso_data, int miso_bit_len, + uint32_t cs_mask, + bool is_write_erase_operation); + +/** + * @brief send reset command to opi flash + * @param spi_num spi port + * @param mode Flash Operation Mode + */ +void esp_rom_opiflash_soft_reset(int spi_num, esp_rom_spiflash_read_mode_t mode); + + +/** + * @brief to read opi flash ID + * @note command format would be defined in initialization + * @param[out] out_id buffer to accept id + * @return flash operation result + */ +esp_rom_spiflash_result_t esp_rom_opiflash_read_id(uint8_t *out_id); + +/** + * @brief to read opi flash status register + * @note command format would be defined in initialization + * @return opi flash status value + */ +uint8_t esp_rom_opiflash_rdsr(void); + +/** + * @brief wait opi flash status register to be idle + * @note command format would be defined in initialization + * @return flash operation result + */ +esp_rom_spiflash_result_t esp_rom_opiflash_wait_idle(void); + +/** + * @brief to erase flash sector + * @note command format would be defined in initialization + * @param sector_num the sector to be erased + * @return flash operation result + */ +esp_rom_spiflash_result_t esp_rom_opiflash_erase_sector(uint32_t sector_num); + +/** + * @brief to erase flash block + * @note command format would be defined in initialization + * @param block_num the block to be erased + * @return flash operation result + */ +esp_rom_spiflash_result_t esp_rom_opiflash_erase_block_64k(uint32_t block_num); + +/** + * @brief to erase a flash area define by start address and length + * @note command format would be defined in initialization + * @param start_addr the start address to be erased + * @param area_len the erea length to be erased + * @return flash operation result + */ +esp_rom_spiflash_result_t esp_rom_opiflash_erase_area(uint32_t start_addr, uint32_t area_len); + +/** + * @brief to read data from opi flash + * @note command format would be defined in initialization + * @param flash_addr flash address to read data from + * @param data_addr data buffer to accept the data + * @param len data length to be read + * @return flash operation result + */ +esp_rom_spiflash_result_t esp_rom_opiflash_read(uint32_t flash_addr, void *data_addr, int len); + +/** + * @brief to write data to opi flash + * @note command format would be defined in initialization + * @param flash_addr flash address to write data to + * @param data_addr data buffer to write to flash + * @param len data length to write + * @return flash operation result + */ +esp_rom_spiflash_result_t esp_rom_opiflash_write(uint32_t flash_addr, const uint32_t *data_addr, int len); + +/** + * @brief send WREN command + * @note command format would be defined in initialization + * @param arg not used, set to NULL + * @return flash operation result + */ +esp_rom_spiflash_result_t esp_rom_opiflash_wren(void* arg); + +/** + * @brief to configure SPI0 read flash command format for cache + * @note command format would be defined in initialization + * + */ +void esp_rom_opiflash_cache_mode_config(esp_rom_spiflash_read_mode_t mode, const esp_rom_opiflash_spi0rd_t *cache); + +esp_rom_spiflash_result_t esp_rom_opiflash_read_raw(uint32_t flash_addr, uint8_t* buf, int len); + + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_rom/include/esp32c61/rom/rom_layout.h b/components/esp_rom/include/esp32c61/rom/rom_layout.h new file mode 100644 index 0000000000..a7ae4e0ff7 --- /dev/null +++ b/components/esp_rom/include/esp32c61/rom/rom_layout.h @@ -0,0 +1,102 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define SUPPORT_BTDM 0 +#define SUPPORT_BTBB 0 +#define SUPPORT_WIFI 1 +#define SUPPORT_USB_DWCOTG 0 +#define SUPPORT_COEXIST 1 +#define SUPPORT_MBEDTLS 0 + +/* Structure and functions for returning ROM global layout + * + * This is for address symbols defined in the linker script, which may change during ECOs. + */ +typedef struct { + void *dram0_stack_shared_mem_start; + void *dram0_rtos_reserved_start; + void *stack_sentry; + void *stack; + +#if SUPPORT_BTDM + void *data_start_btdm; + void *data_end_btdm; + void *bss_start_btdm; + void *bss_end_btdm; + void *data_start_btdm_rom; + void *data_start_interface_btdm; + void *data_end_interface_btdm; + void *bss_start_interface_btdm; + void *bss_end_interface_btdm; +#endif + +#if SUPPORT_BTBB + void *dram_start_btbbrom; + void *dram_end_btbbrom; +#endif + +#if SUPPORT_BTDM || SUPPORT_WIFI + void *dram_start_phyrom; + void *dram_end_phyrom; +#endif + +#if SUPPORT_WIFI + void *dram_start_net80211; + void *dram_end_net80211; + void *data_start_interface_net80211; + void *data_end_interface_net80211; + void *bss_start_interface_net80211; + void *bss_end_interface_net80211; + void *dram_start_pp; + void *dram_end_pp; + void *data_start_interface_pp; + void *data_end_interface_pp; + void *bss_start_interface_pp; + void *bss_end_interface_pp; +#endif + +#if SUPPORT_COEXIST + void *dram_start_coexist; + void *dram_end_coexist; + void *data_start_interface_coexist; + void *data_end_interface_coexist; + void *bss_start_interface_coexist; + void *bss_end_interface_coexist; +#endif + +#if SUPPORT_MBEDTLS + void *dram_start_mbedtls_rom; + void *dram_end_mbedtls_rom; +#endif + +#if SUPPORT_USB_DWCOTG + void *dram_start_usb_dwcotg_rom; + void *dram_end_usb_dwcotg_rom; +#else + //Two reserved members are defined here, so the structure will not be broken, + //please keep in mind that there is no memory can be released between + //dram_start_usb_reserved_rom ~ dram_end_usb_reserved_rom. + void *dram_start_usb_reserved_rom; + void *dram_end_usb_reserved_rom; +#endif + + void *dram_start_uart_rom; + void *dram_end_uart_rom; +} ets_rom_layout_t; + +extern const ets_rom_layout_t *const ets_rom_layout_p; + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_rom/include/esp32c61/rom/rtc.h b/components/esp_rom/include/esp32c61/rom/rtc.h new file mode 100644 index 0000000000..e0a775d302 --- /dev/null +++ b/components/esp_rom/include/esp32c61/rom/rtc.h @@ -0,0 +1,255 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include +#include +#include "esp_assert.h" + +#include "soc/soc.h" +#include "soc/lp_aon_reg.h" +#include "soc/reset_reasons.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** \defgroup rtc_apis, rtc registers and memory related apis + * @brief rtc apis + */ + +/** @addtogroup rtc_apis + * @{ + */ + +/************************************************************************************** + * Note: * + * Some Rtc memory and registers are used, in ROM or in internal library. * + * Please do not use reserved or used rtc memory or registers. * + * * + ************************************************************************************* + * LP Memory & Store Register usage + ************************************************************************************* + * rtc memory addr type size usage + * 0x3f421000(0x50000000) Slow SIZE_CP Co-Processor code/Reset Entry + * 0x3f421000+SIZE_CP Slow 8192-SIZE_CP + * + * 0x3ff80000(0x40070000) Fast 8192 deep sleep entry code + * + ************************************************************************************* + * RTC store registers usage + * LP_AON_STORE0_REG Reserved + * LP_AON_STORE1_REG RTC_SLOW_CLK calibration value + * LP_AON_STORE2_REG Boot time, low word + * LP_AON_STORE3_REG Boot time, high word + * LP_AON_STORE4_REG External XTAL frequency + * LP_AON_STORE5_REG FAST_RTC_MEMORY_LENGTH + * LP_AON_STORE6_REG FAST_RTC_MEMORY_ENTRY + * LP_AON_STORE7_REG FAST_RTC_MEMORY_CRC + * LP_AON_STORE8_REG Store light sleep wake stub addr + * LP_AON_STORE9_REG Store the sleep mode at bit[0] (0:light sleep 1:deep sleep) + ************************************************************************************* + */ + +#define RTC_SLOW_CLK_CAL_REG LP_AON_STORE1_REG +#define RTC_BOOT_TIME_LOW_REG LP_AON_STORE2_REG +#define RTC_BOOT_TIME_HIGH_REG LP_AON_STORE3_REG +#define RTC_XTAL_FREQ_REG LP_AON_STORE4_REG +#define RTC_ENTRY_LENGTH_REG LP_AON_STORE5_REG +#define RTC_ENTRY_ADDR_REG LP_AON_STORE6_REG +#define RTC_RESET_CAUSE_REG LP_AON_STORE6_REG +#define RTC_MEMORY_CRC_REG LP_AON_STORE7_REG +#define LIGHT_SLEEP_WAKE_STUB_ADDR_REG LP_AON_STORE8_REG +#define SLEEP_MODE_REG LP_AON_STORE9_REG + +#define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) //!< Disable logging from the ROM code. + +typedef enum { + AWAKE = 0, // +#include +#include "ets_sys.h" +#include "ecdsa.h" +#include "esp_assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if CONFIG_SECURE_BOOT_V2_ENABLED || CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT + +typedef struct ets_secure_boot_sig_block ets_secure_boot_sig_block_t; +typedef struct ets_secure_boot_signature ets_secure_boot_signature_t; +typedef struct ets_secure_boot_key_digests ets_secure_boot_key_digests_t; + +/* Anti-FI measure: use full words for success/fail, instead of + 0/non-zero +*/ +typedef enum { + SB_SUCCESS = 0x3A5A5AA5, + SB_FAILED = 0x7533885E, +} ets_secure_boot_status_t; + +/* Verify bootloader image (reconfigures cache to map), + with key digests provided as parameters.) + + Can be used to verify secure boot status before enabling + secure boot permanently. + + If stage_load parameter is true, bootloader is copied into staging + buffer in RAM at the same time. + + If result is SB_SUCCESS, the "simple hash" of the bootloader is + copied into verified_hash. +*/ +ets_secure_boot_status_t ets_secure_boot_verify_bootloader_with_keys(uint8_t *verified_hash, const ets_secure_boot_key_digests_t *trusted_keys, bool stage_load); + +/* Read key digests from efuse. Any revoked/missing digests will be + marked as NULL +*/ +ETS_STATUS ets_secure_boot_read_key_digests(ets_secure_boot_key_digests_t *trusted_keys); + +/* Verify supplied signature against supplied digest, using + supplied trusted key digests. + + Doesn't reconfigure cache or any other hardware access except for RSA peripheral. + + If result is SB_SUCCESS, the image_digest value is copied into verified_digest. +*/ +ets_secure_boot_status_t ets_secure_boot_verify_signature(const ets_secure_boot_signature_t *sig, const uint8_t *image_digest, const ets_secure_boot_key_digests_t *trusted_keys, uint8_t *verified_digest); + +/* Revoke a public key digest in efuse. + @param index Digest to revoke. Must be 0, 1 or 2. + */ +void ets_secure_boot_revoke_public_key_digest(int index); + +#define CRC_SIGN_BLOCK_LEN 1196 +#define SIG_BLOCK_PADDING 4096 +#define ETS_SECURE_BOOT_V2_SIGNATURE_MAGIC 0xE7 + +/* Secure Boot V2 signature block + + (Up to 3 in a signature sector are appended to the image) + */ +#if CONFIG_SECURE_SIGNED_APPS_RSA_SCHEME + +struct ets_secure_boot_sig_block { + uint8_t magic_byte; + uint8_t version; + uint8_t _reserved1; + uint8_t _reserved2; + uint8_t image_digest[32]; + ets_rsa_pubkey_t key; + uint8_t signature[384]; + uint32_t block_crc; + uint8_t _padding[16]; +}; + +#elif CONFIG_SECURE_SIGNED_APPS_ECDSA_V2_SCHEME + +struct __attribute((packed)) ets_secure_boot_sig_block { + uint8_t magic_byte; + uint8_t version; + uint8_t _reserved1; + uint8_t _reserved2; + uint8_t image_digest[32]; + struct { + struct { + uint8_t curve_id; /* ETS_ECDSA_CURVE_P192 / ETS_ECDSA_CURVE_P256 */ + uint8_t point[64]; /* X followed by Y (both little-endian), plus zero bytes if P192 */ + } key; + uint8_t signature[64]; /* r followed by s (both little-endian) */ + uint8_t padding[1031]; + } ecdsa; + uint32_t block_crc; /* note: crc covers all bytes in the structure before it, regardless of version field */ + uint8_t _padding[16]; +}; +#endif + +ESP_STATIC_ASSERT(sizeof(ets_secure_boot_sig_block_t) == 1216, "invalid sig block size"); + +#define SECURE_BOOT_NUM_BLOCKS 3 + +/* V2 Secure boot signature sector (up to 3 blocks) */ +struct ets_secure_boot_signature { + ets_secure_boot_sig_block_t block[SECURE_BOOT_NUM_BLOCKS]; + uint8_t _padding[4096 - (sizeof(ets_secure_boot_sig_block_t) * SECURE_BOOT_NUM_BLOCKS)]; +}; + +ESP_STATIC_ASSERT(sizeof(ets_secure_boot_signature_t) == 4096, "invalid sig sector size"); + +#define MAX_KEY_DIGESTS 3 + +struct ets_secure_boot_key_digests { + const void *key_digests[MAX_KEY_DIGESTS]; + bool allow_key_revoke; +}; + +#endif /* CONFIG_SECURE_BOOT_V2_ENABLED || CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT */ + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_rom/include/esp32c61/rom/sha.h b/components/esp_rom/include/esp32c61/rom/sha.h new file mode 100644 index 0000000000..4577f4349f --- /dev/null +++ b/components/esp_rom/include/esp32c61/rom/sha.h @@ -0,0 +1,53 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef _ROM_SHA_H_ +#define _ROM_SHA_H_ + +#include +#include +#include "ets_sys.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + SHA1 = 0, + SHA2_224, + SHA2_256, + SHA_TYPE_MAX +} SHA_TYPE; + +typedef struct SHAContext { + bool start; + bool in_hardware; // Is this context currently in peripheral? Needs to be manually cleared if multiple SHAs are interleaved + SHA_TYPE type; + uint32_t state[16]; // For SHA1/SHA224/SHA256, used 8, other used 16 + unsigned char buffer[128]; // For SHA1/SHA224/SHA256, used 64, other used 128 + uint32_t total_bits[4]; +} SHA_CTX; + +void ets_sha_enable(void); + +void ets_sha_disable(void); + +ets_status_t ets_sha_init(SHA_CTX *ctx, SHA_TYPE type); + +ets_status_t ets_sha_starts(SHA_CTX *ctx, uint16_t sha512_t); + +void ets_sha_get_state(SHA_CTX *ctx); + +void ets_sha_process(SHA_CTX *ctx, const unsigned char *input); + +void ets_sha_update(SHA_CTX *ctx, const unsigned char *input, uint32_t input_bytes, bool update_ctx); + +ets_status_t ets_sha_finish(SHA_CTX *ctx, unsigned char *output); + +#ifdef __cplusplus +} +#endif + +#endif /* _ROM_SHA_H_ */ diff --git a/components/esp_rom/include/esp32c61/rom/spi_flash.h b/components/esp_rom/include/esp32c61/rom/spi_flash.h new file mode 100644 index 0000000000..b3bcc37409 --- /dev/null +++ b/components/esp_rom/include/esp32c61/rom/spi_flash.h @@ -0,0 +1,458 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include +#include "esp_attr.h" +#include "esp_rom_spiflash.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define PERIPHS_SPI_FLASH_CMD SPI_MEM_CMD_REG(1) +#define PERIPHS_SPI_FLASH_ADDR SPI_MEM_ADDR_REG(1) +#define PERIPHS_SPI_FLASH_CTRL SPI_MEM_CTRL_REG(1) +#define PERIPHS_SPI_FLASH_CTRL1 SPI_MEM_CTRL1_REG(1) +#define PERIPHS_SPI_FLASH_STATUS SPI_MEM_RD_STATUS_REG(1) +#define PERIPHS_SPI_FLASH_USRREG SPI_MEM_USER_REG(1) +#define PERIPHS_SPI_FLASH_USRREG1 SPI_MEM_USER1_REG(1) +#define PERIPHS_SPI_FLASH_USRREG2 SPI_MEM_USER2_REG(1) +#define PERIPHS_SPI_FLASH_C0 SPI_MEM_W0_REG(1) +#define PERIPHS_SPI_FLASH_C1 SPI_MEM_W1_REG(1) +#define PERIPHS_SPI_FLASH_C2 SPI_MEM_W2_REG(1) +#define PERIPHS_SPI_FLASH_C3 SPI_MEM_W3_REG(1) +#define PERIPHS_SPI_FLASH_C4 SPI_MEM_W4_REG(1) +#define PERIPHS_SPI_FLASH_C5 SPI_MEM_W5_REG(1) +#define PERIPHS_SPI_FLASH_C6 SPI_MEM_W6_REG(1) +#define PERIPHS_SPI_FLASH_C7 SPI_MEM_W7_REG(1) +#define PERIPHS_SPI_FLASH_TX_CRC SPI_MEM_TX_CRC_REG(1) + +#define SPI0_R_QIO_DUMMY_CYCLELEN 5 +#define SPI0_R_QIO_ADDR_BITSLEN 23 +#define SPI0_R_FAST_DUMMY_CYCLELEN 7 +#define SPI0_R_DIO_DUMMY_CYCLELEN 3 +#define SPI0_R_FAST_ADDR_BITSLEN 23 +#define SPI0_R_SIO_ADDR_BITSLEN 23 + +#define SPI1_R_QIO_DUMMY_CYCLELEN 5 +#define SPI1_R_QIO_ADDR_BITSLEN 23 +#define SPI1_R_FAST_DUMMY_CYCLELEN 7 +#define SPI1_R_DIO_DUMMY_CYCLELEN 3 +#define SPI1_R_DIO_ADDR_BITSLEN 23 +#define SPI1_R_FAST_ADDR_BITSLEN 23 +#define SPI1_R_SIO_ADDR_BITSLEN 23 + +#define ESP_ROM_SPIFLASH_W_SIO_ADDR_BITSLEN 23 + +#define ESP_ROM_SPIFLASH_TWO_BYTE_STATUS_EN SPI_MEM_WRSR_2B + +//SPI address register +#define ESP_ROM_SPIFLASH_BYTES_LEN 24 +#define ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM 32 +#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM 16 +#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_BITS 0xf + +typedef void (* spi_flash_func_t)(void); +typedef esp_rom_spiflash_result_t (* spi_flash_op_t)(void); +typedef esp_rom_spiflash_result_t (* spi_flash_erase_t)(uint32_t); +typedef esp_rom_spiflash_result_t (* spi_flash_rd_t)(uint32_t, uint32_t*, int); +typedef esp_rom_spiflash_result_t (* spi_flash_wr_t)(uint32_t, const uint32_t*, int); +typedef esp_rom_spiflash_result_t (* spi_flash_ewr_t)(uint32_t, const void*, uint32_t); +typedef esp_rom_spiflash_result_t (* spi_flash_wren_t)(void*); +typedef esp_rom_spiflash_result_t (* spi_flash_erase_area_t)(uint32_t, uint32_t); + +typedef struct { + uint8_t pp_addr_bit_len; + uint8_t se_addr_bit_len; + uint8_t be_addr_bit_len; + uint8_t rd_addr_bit_len; + uint32_t read_sub_len; + uint32_t write_sub_len; + spi_flash_op_t unlock; + spi_flash_erase_t erase_sector; + spi_flash_erase_t erase_block; + spi_flash_rd_t read; + spi_flash_wr_t write; + spi_flash_ewr_t encrypt_write; + spi_flash_func_t check_sus; + spi_flash_wren_t wren; + spi_flash_op_t wait_idle; + spi_flash_erase_area_t erase_area; +} spiflash_legacy_funcs_t; + +typedef struct { + uint8_t data_length; + uint8_t read_cmd0; + uint8_t read_cmd1; + uint8_t write_cmd; + uint16_t data_mask; + uint16_t data; +} esp_rom_spiflash_common_cmd_t; + +/** + * @brief SPI Read Flash status register. We use CMD 0x05 (RDSR). + * Please do not call this function in SDK. + * + * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. + * + * @param uint32_t *status : The pointer to which to return the Flash status value. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : read OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : read error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_read_status(esp_rom_spiflash_chip_t *spi, uint32_t *status); + +/** + * @brief SPI Read Flash status register bits 8-15. We use CMD 0x35 (RDSR2). + * Please do not call this function in SDK. + * + * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. + * + * @param uint32_t *status : The pointer to which to return the Flash status value. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : read OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : read error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_read_statushigh(esp_rom_spiflash_chip_t *spi, uint32_t *status); + +/** + * @brief Write status to Flash status register. + * Please do not call this function in SDK. + * + * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. + * + * @param uint32_t status_value : Value to . + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : write OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : write error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : write timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_write_status(esp_rom_spiflash_chip_t *spi, uint32_t status_value); + +/** + * @brief Use a command to Read Flash status register. + * Please do not call this function in SDK. + * + * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. + * + * @param uint32_t*status : The pointer to which to return the Flash status value. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : read OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : read error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_read_user_cmd(uint32_t *status, uint8_t cmd); + +/** + * @brief Config SPI Flash read mode when init. + * Please do not call this function in SDK. + * + * @param esp_rom_spiflash_read_mode_t mode : QIO/QOUT/DIO/DOUT/FastRD/SlowRD. + * + * This function does not try to set the QIO Enable bit in the status register, caller is responsible for this. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : config OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : config error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_config_readmode(esp_rom_spiflash_read_mode_t mode); + +/** + * @brief Config SPI Flash clock divisor. + * Please do not call this function in SDK. + * + * @param uint8_t freqdiv: clock divisor. + * + * @param uint8_t spi: 0 for SPI0, 1 for SPI1. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : config OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : config error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_config_clk(uint8_t freqdiv, uint8_t spi); + +/** + * @brief Clear all SR bits except QE bit. + * Please do not call this function in SDK. + * + * @param None. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Unlock OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Unlock error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Unlock timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_clear_bp(void); + +/** + * @brief Clear all SR bits except QE bit. + * Please do not call this function in SDK. + * + * @param None. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Unlock OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Unlock error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Unlock timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_unlock(void); + +/** + * @brief Update SPI Flash parameter. + * Please do not call this function in SDK. + * + * @param uint32_t deviceId : Device ID read from SPI, the low 32 bit. + * + * @param uint32_t chip_size : The Flash size. + * + * @param uint32_t block_size : The Flash block size. + * + * @param uint32_t sector_size : The Flash sector size. + * + * @param uint32_t page_size : The Flash page size. + * + * @param uint32_t status_mask : The Mask used when read status from Flash(use single CMD). + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Update OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Update error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Update timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_config_param(uint32_t deviceId, uint32_t chip_size, uint32_t block_size, + uint32_t sector_size, uint32_t page_size, uint32_t status_mask); + +/** + * @brief Erase whole flash chip. + * Please do not call this function in SDK. + * + * @param None + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_erase_chip(void); + +/** + * @brief Erase a 64KB block of flash + * Uses SPI flash command D8H. + * Please do not call this function in SDK. + * + * @param uint32_t block_num : Which block to erase. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_erase_block(uint32_t block_num); + +/** + * @brief Erase a sector of flash. + * Uses SPI flash command 20H. + * Please do not call this function in SDK. + * + * @param uint32_t sector_num : Which sector to erase. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_erase_sector(uint32_t sector_num); + +/** + * @brief Erase some sectors. + * Please do not call this function in SDK. + * + * @param uint32_t start_addr : Start addr to erase, should be sector aligned. + * + * @param uint32_t area_len : Length to erase, should be sector aligned. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_erase_area(uint32_t start_addr, uint32_t area_len); + +/** + * @brief Write Data to Flash, you should Erase it yourself if need. + * Please do not call this function in SDK. + * + * @param uint32_t dest_addr : Address to write, should be 4 bytes aligned. + * + * @param const uint32_t *src : The pointer to data which is to write. + * + * @param uint32_t len : Length to write, should be 4 bytes aligned. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Write OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Write error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Write timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_write(uint32_t dest_addr, const uint32_t *src, int32_t len); + +/** + * @brief Read Data from Flash, you should Erase it yourself if need. + * Please do not call this function in SDK. + * + * @param uint32_t src_addr : Address to read, should be 4 bytes aligned. + * + * @param uint32_t *dest : The buf to read the data. + * + * @param uint32_t len : Length to read, should be 4 bytes aligned. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Read OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Read error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Read timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_read(uint32_t src_addr, uint32_t *dest, int32_t len); + +/** + * @brief SPI1 go into encrypto mode. + * Please do not call this function in SDK. + * + * @param None + * + * @return None + */ +void esp_rom_spiflash_write_encrypted_enable(void); + +/** + * @brief SPI1 go out of encrypto mode. + * Please do not call this function in SDK. + * + * @param None + * + * @return None + */ +void esp_rom_spiflash_write_encrypted_disable(void); + +/** + * @brief Write data to flash with transparent encryption. + * @note Sectors to be written should already be erased. + * + * @note Please do not call this function in SDK. + * + * @param uint32_t flash_addr : Address to write, should be 32 byte aligned. + * + * @param uint32_t *data : The pointer to data to write. Note, this pointer must + * be 32 bit aligned and the content of the data will be + * modified by the encryption function. + * + * @param uint32_t len : Length to write, should be 32 bytes aligned. + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Data written successfully. + * ESP_ROM_SPIFLASH_RESULT_ERR : Encryption write error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Encrypto write timeout. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_write_encrypted(uint32_t flash_addr, uint32_t *data, uint32_t len); + + +/** @brief Wait until SPI flash write operation is complete + * + * @note Please do not call this function in SDK. + * + * Reads the Write In Progress bit of the SPI flash status register, + * repeats until this bit is zero (indicating write complete). + * + * @return ESP_ROM_SPIFLASH_RESULT_OK : Write is complete + * ESP_ROM_SPIFLASH_RESULT_ERR : Error while reading status. + */ +esp_rom_spiflash_result_t esp_rom_spiflash_wait_idle(esp_rom_spiflash_chip_t *spi); + + +/** @brief Enable Quad I/O pin functions + * + * @note Please do not call this function in SDK. + * + * Sets the HD & WP pin functions for Quad I/O modes, based on the + * efuse SPI pin configuration. + * + * @param wp_gpio_num - Number of the WP pin to reconfigure for quad I/O. + * + * @param spiconfig - Pin configuration, as returned from ets_efuse_get_spiconfig(). + * - If this parameter is 0, default SPI pins are used and wp_gpio_num parameter is ignored. + * - If this parameter is 1, default HSPI pins are used and wp_gpio_num parameter is ignored. + * - For other values, this parameter encodes the HD pin number and also the CLK pin number. CLK pin selection is used + * to determine if HSPI or SPI peripheral will be used (use HSPI if CLK pin is the HSPI clock pin, otherwise use SPI). + * Both HD & WP pins are configured via GPIO matrix to map to the selected peripheral. + */ +void esp_rom_spiflash_select_qio_pins(uint8_t wp_gpio_num, uint32_t spiconfig); + +/** + * @brief Clear WEL bit unconditionally. + * + * @return always ESP_ROM_SPIFLASH_RESULT_OK + */ +esp_rom_spiflash_result_t esp_rom_spiflash_write_disable(void); + +/** + * @brief Set WREN bit. + * + * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. + * + * @return always ESP_ROM_SPIFLASH_RESULT_OK + */ +esp_rom_spiflash_result_t esp_rom_spiflash_write_enable(esp_rom_spiflash_chip_t *spi); + +/** + * @brief Fix the bug in SPI hardware communication with Flash/Ext-SRAM in High Speed. + * Please do not call this function in SDK. + * + * @param uint8_t spi: 0 for SPI0(Cache Access), 1 for SPI1(Flash read/write). + * + * @param uint8_t freqdiv: Pll is 80M, 4 for 20M, 3 for 26.7M, 2 for 40M, 1 for 80M. + * + * @return None + */ +void esp_rom_spiflash_fix_dummylen(uint8_t spi, uint8_t freqdiv); + +/** + * @brief Set SPI Flash pad drivers. + * Please do not call this function in SDK. + * + * @param uint8_t wp_gpio_num: WP gpio number. + * + * @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping + * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd + * + * @param uint8_t *drvs: drvs[0]-bit[3:0] for cpiclk, bit[7:4] for spiq, drvs[1]-bit[3:0] for spid, drvs[1]-bit[7:4] for spid + * drvs[2]-bit[3:0] for spihd, drvs[2]-bit[7:4] for spiwp. + * Values usually read from falsh by rom code, function usually callde by rom code. + * if value with bit(3) set, the value is valid, bit[2:0] is the real value. + * + * @return None + */ +void esp_rom_spiflash_set_drvs(uint8_t wp_gpio_num, uint32_t ishspi, uint8_t *drvs); + +/** + * @brief Select SPI Flash function for pads. + * Please do not call this function in SDK. + * + * @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping + * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd + * + * @return None + */ +void esp_rom_spiflash_select_padsfunc(uint32_t ishspi); + +/** + * @brief Send CommonCmd to Flash so that is can go into QIO mode, some Flash use different CMD. + * Please do not call this function in SDK. + * + * @param esp_rom_spiflash_common_cmd_t *cmd : A struct to show the action of a command. + * + * @return uint16_t 0 : do not send command any more. + * 1 : go to the next command. + * n > 1 : skip (n - 1) commands. + */ +uint16_t esp_rom_spiflash_common_cmd(esp_rom_spiflash_common_cmd_t *cmd); + +extern const spiflash_legacy_funcs_t *rom_spiflash_legacy_funcs; + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_rom/include/esp32c61/rom/tjpgd.h b/components/esp_rom/include/esp32c61/rom/tjpgd.h new file mode 100644 index 0000000000..b993c2f532 --- /dev/null +++ b/components/esp_rom/include/esp32c61/rom/tjpgd.h @@ -0,0 +1,104 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +/*----------------------------------------------------------------------------/ +/ TJpgDec - Tiny JPEG Decompressor include file (C)ChaN, 2012 +/----------------------------------------------------------------------------*/ +#ifndef _TJPGDEC +#define _TJPGDEC +/*---------------------------------------------------------------------------*/ +/* System Configurations */ + +#define JD_SZBUF 512 /* Size of stream input buffer */ +#define JD_FORMAT 0 /* Output pixel format 0:RGB888 (3 BYTE/pix), 1:RGB565 (1 WORD/pix) */ +#define JD_USE_SCALE 1 /* Use descaling feature for output */ +#define JD_TBLCLIP 1 /* Use table for saturation (might be a bit faster but increases 1K bytes of code size) */ + +/*---------------------------------------------------------------------------*/ + +#ifdef __cplusplus +extern "C" { +#endif + +/* These types must be 16-bit, 32-bit or larger integer */ +typedef int INT; +typedef unsigned int UINT; + +/* These types must be 8-bit integer */ +typedef char CHAR; +typedef unsigned char UCHAR; +typedef unsigned char BYTE; + +/* These types must be 16-bit integer */ +typedef short SHORT; +typedef unsigned short USHORT; +typedef unsigned short WORD; +typedef unsigned short WCHAR; + +/* These types must be 32-bit integer */ +typedef long LONG; +typedef unsigned long ULONG; +typedef unsigned long DWORD; + + +/* Error code */ +typedef enum { + JDR_OK = 0, /* 0: Succeeded */ + JDR_INTR, /* 1: Interrupted by output function */ + JDR_INP, /* 2: Device error or wrong termination of input stream */ + JDR_MEM1, /* 3: Insufficient memory pool for the image */ + JDR_MEM2, /* 4: Insufficient stream input buffer */ + JDR_PAR, /* 5: Parameter error */ + JDR_FMT1, /* 6: Data format error (may be damaged data) */ + JDR_FMT2, /* 7: Right format but not supported */ + JDR_FMT3 /* 8: Not supported JPEG standard */ +} JRESULT; + + + +/* Rectangular structure */ +typedef struct { + WORD left, right, top, bottom; +} JRECT; + + + +/* Decompressor object structure */ +typedef struct JDEC JDEC; +struct JDEC { + UINT dctr; /* Number of bytes available in the input buffer */ + BYTE *dptr; /* Current data read ptr */ + BYTE *inbuf; /* Bit stream input buffer */ + BYTE dmsk; /* Current bit in the current read byte */ + BYTE scale; /* Output scaling ratio */ + BYTE msx, msy; /* MCU size in unit of block (width, height) */ + BYTE qtid[3]; /* Quantization table ID of each component */ + SHORT dcv[3]; /* Previous DC element of each component */ + WORD nrst; /* Restart inverval */ + UINT width, height; /* Size of the input image (pixel) */ + BYTE *huffbits[2][2]; /* Huffman bit distribution tables [id][dcac] */ + WORD *huffcode[2][2]; /* Huffman code word tables [id][dcac] */ + BYTE *huffdata[2][2]; /* Huffman decoded data tables [id][dcac] */ + LONG *qttbl[4]; /* Dequaitizer tables [id] */ + void *workbuf; /* Working buffer for IDCT and RGB output */ + BYTE *mcubuf; /* Working buffer for the MCU */ + void *pool; /* Pointer to available memory pool */ + UINT sz_pool; /* Size of momory pool (bytes available) */ + UINT (*infunc)(JDEC *, BYTE *, UINT); /* Pointer to jpeg stream input function */ + void *device; /* Pointer to I/O device identifiler for the session */ +}; + + + +/* TJpgDec API functions */ +JRESULT jd_prepare (JDEC *, UINT(*)(JDEC *, BYTE *, UINT), void *, UINT, void *); +JRESULT jd_decomp (JDEC *, UINT(*)(JDEC *, void *, JRECT *), BYTE); + + +#ifdef __cplusplus +} +#endif + +#endif /* _TJPGDEC */ diff --git a/components/esp_rom/include/esp32c61/rom/uart.h b/components/esp_rom/include/esp32c61/rom/uart.h new file mode 100644 index 0000000000..57e3cf6618 --- /dev/null +++ b/components/esp_rom/include/esp32c61/rom/uart.h @@ -0,0 +1,353 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ROM_UART_H_ +#define _ROM_UART_H_ + +#include "esp_types.h" +#include "esp_attr.h" +#include "ets_sys.h" +#include "soc/soc.h" +#include "soc/uart_reg.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** \defgroup uart_apis, uart configuration and communication related apis + * @brief uart apis + */ + +/** @addtogroup uart_apis + * @{ + */ + +#define RX_BUFF_SIZE 0x400 +#define TX_BUFF_SIZE 100 + +//uart int enalbe register ctrl bits +#define UART_RCV_INTEN BIT0 +#define UART_TRX_INTEN BIT1 +#define UART_LINE_STATUS_INTEN BIT2 + +//uart int identification ctrl bits +#define UART_INT_FLAG_MASK 0x0E + +//uart fifo ctrl bits +#define UART_CLR_RCV_FIFO BIT1 +#define UART_CLR_TRX_FIFO BIT2 +#define UART_RCVFIFO_TRG_LVL_BITS BIT6 + +//uart line control bits +#define UART_DIV_LATCH_ACCESS_BIT BIT7 + +//uart line status bits +#define UART_RCV_DATA_RDY_FLAG BIT0 +#define UART_RCV_OVER_FLOW_FLAG BIT1 +#define UART_RCV_PARITY_ERR_FLAG BIT2 +#define UART_RCV_FRAME_ERR_FLAG BIT3 +#define UART_BRK_INT_FLAG BIT4 +#define UART_TRX_FIFO_EMPTY_FLAG BIT5 +#define UART_TRX_ALL_EMPTY_FLAG BIT6 // include fifo and shift reg +#define UART_RCV_ERR_FLAG BIT7 + +//send and receive message frame head +#define FRAME_FLAG 0x7E + +typedef enum { + UART_LINE_STATUS_INT_FLAG = 0x06, + UART_RCV_FIFO_INT_FLAG = 0x04, + UART_RCV_TMOUT_INT_FLAG = 0x0C, + UART_TXBUFF_EMPTY_INT_FLAG = 0x02 +} UartIntType; //consider bit0 for int_flag + +typedef enum { + RCV_ONE_BYTE = 0x0, + RCV_FOUR_BYTE = 0x1, + RCV_EIGHT_BYTE = 0x2, + RCV_FOURTEEN_BYTE = 0x3 +} UartRcvFifoTrgLvl; + +typedef enum { + FIVE_BITS = 0x0, + SIX_BITS = 0x1, + SEVEN_BITS = 0x2, + EIGHT_BITS = 0x3 +} UartBitsNum4Char; + +typedef enum { + ONE_STOP_BIT = 1, + ONE_HALF_STOP_BIT = 2, + TWO_STOP_BIT = 3 +} UartStopBitsNum; + +typedef enum { + NONE_BITS = 0, + ODD_BITS = 2, + EVEN_BITS = 3 + +} UartParityMode; + +typedef enum { + STICK_PARITY_DIS = 0, + STICK_PARITY_EN = 2 +} UartExistParity; + +typedef enum { + BIT_RATE_9600 = 9600, + BIT_RATE_19200 = 19200, + BIT_RATE_38400 = 38400, + BIT_RATE_57600 = 57600, + BIT_RATE_115200 = 115200, + BIT_RATE_230400 = 230400, + BIT_RATE_460800 = 460800, + BIT_RATE_921600 = 921600 +} UartBautRate; + +typedef enum { + NONE_CTRL, + HARDWARE_CTRL, + XON_XOFF_CTRL +} UartFlowCtrl; + +typedef enum { + EMPTY, + UNDER_WRITE, + WRITE_OVER +} RcvMsgBuffState; + +typedef struct { + uint8_t *pRcvMsgBuff; + uint8_t *pWritePos; + uint8_t *pReadPos; + uint8_t TrigLvl; + RcvMsgBuffState BuffState; +} RcvMsgBuff; + +typedef struct { + uint32_t TrxBuffSize; + uint8_t *pTrxBuff; +} TrxMsgBuff; + +typedef enum { + BAUD_RATE_DET, + WAIT_SYNC_FRM, + SRCH_MSG_HEAD, + RCV_MSG_BODY, + RCV_ESC_CHAR, +} RcvMsgState; + +typedef struct { + UartBautRate baut_rate; + UartBitsNum4Char data_bits; + UartExistParity exist_parity; + UartParityMode parity; // chip size in byte + UartStopBitsNum stop_bits; + UartFlowCtrl flow_ctrl; + uint8_t buff_uart_no; //indicate which uart use tx/rx buffer + RcvMsgBuff rcv_buff; +// TrxMsgBuff trx_buff; + RcvMsgState rcv_state; + int received; +} UartDevice; + +/** + * @brief Init uart device struct value and reset uart0/uart1 rx. + * Please do not call this function in SDK. + * + * @param rxBuffer, must be a pointer to RX_BUFF_SIZE bytes or NULL + * + * @return None + */ +void uartAttach(void *rxBuffer); + +/** + * @brief Init uart0 or uart1 for UART download booting mode. + * Please do not call this function in SDK. + * + * @param uint8_t uart_no : 0 for UART0, else for UART1. + * + * @param uint32_t clock : clock used by uart module, to adjust baudrate. + * + * @return None + */ +void Uart_Init(uint8_t uart_no, uint32_t clock); + +/** + * @brief Modify uart baudrate. + * This function will reset RX/TX fifo for uart. + * + * @param uint8_t uart_no : 0 for UART0, 1 for UART1. + * + * @param uint32_t DivLatchValue : (clock << 4)/baudrate. + * + * @return None + */ +void uart_div_modify(uint8_t uart_no, uint32_t DivLatchValue); + +/** + * @brief Switch printf channel of uart_tx_one_char. + * Please do not call this function when printf. + * + * @param uint8_t uart_no : 0 for UART0, 1 for UART1. + * + * @return None + */ +void uart_tx_switch(uint8_t uart_no); + +/** + * @brief Output a char to printf channel, wait until fifo not full. + * + * @param None + * + * @return OK. + */ +ETS_STATUS uart_tx_one_char(uint8_t TxChar); + +/** + * @brief Output a char to message exchange channel, wait until fifo not full. + * Please do not call this function in SDK. + * + * @param None + * + * @return OK. + */ +ETS_STATUS uart_tx_one_char2(uint8_t TxChar); + +/** + * @brief Wait until uart tx full empty. + * + * @param uint8_t uart_no : 0 for UART0, 1 for UART1. + * + * @return None. + */ +void uart_tx_flush(uint8_t uart_no); + +/** + * @brief Wait until uart tx full empty and the last char send ok. + * + * @param uart_no : 0 for UART0, 1 for UART1 + * + * The function defined in ROM code has a bug, so we define the correct version + * here for compatibility. + */ +void uart_tx_wait_idle(uint8_t uart_no); + +/** + * @brief Get an input char from message channel. + * Please do not call this function in SDK. + * + * @param uint8_t *pRxChar : the pointer to store the char. + * + * @return OK for successful. + * FAIL for failed. + */ +ETS_STATUS uart_rx_one_char(uint8_t *pRxChar); + +/** + * @brief Get an input char from message channel, wait until successful. + * Please do not call this function in SDK. + * + * @param None + * + * @return char : input char value. + */ +char uart_rx_one_char_block(void); + +/** + * @brief Get an input string line from message channel. + * Please do not call this function in SDK. + * + * @param uint8_t *pString : the pointer to store the string. + * + * @param uint8_t MaxStrlen : the max string length, incude '\0'. + * + * @return OK. + */ +ETS_STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen); + +/** + * @brief Process uart recevied information in the interrupt handler. + * Please do not call this function in SDK. + * + * @param void *para : the message receive buffer. + * + * @return None + */ +void uart_rx_intr_handler(void *para); + +/** + * @brief Get an char from receive buffer. + * Please do not call this function in SDK. + * + * @param RcvMsgBuff *pRxBuff : the pointer to the struct that include receive buffer. + * + * @param uint8_t *pRxByte : the pointer to store the char. + * + * @return OK for successful. + * FAIL for failed. + */ +ETS_STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte); + +/** + * @brief Get all chars from receive buffer. + * Please do not call this function in SDK. + * + * @param uint8_t *pCmdLn : the pointer to store the string. + * + * @return OK for successful. + * FAIL for failed. + */ +ETS_STATUS UartGetCmdLn(uint8_t *pCmdLn); + +/** + * @brief Get uart configuration struct. + * Please do not call this function in SDK. + * + * @param None + * + * @return UartDevice * : uart configuration struct pointer. + */ +UartDevice *GetUartDevice(void); + +/** + * @brief Send an packet to download tool, with SLIP escaping. + * Please do not call this function in SDK. + * + * @param uint8_t *p : the pointer to output string. + * + * @param int len : the string length. + * + * @return None. + */ +void send_packet(uint8_t *p, int len); + +/** + * @brief Receive an packet from download tool, with SLIP escaping. + * Please do not call this function in SDK. + * + * @param uint8_t *p : the pointer to input string. + * + * @param int len : If string length > len, the string will be truncated. + * + * @param uint8_t is_sync : 0, only one UART module; + * 1, two UART modules. + * + * @return int : the length of the string. + */ +int recv_packet(uint8_t *p, int len, uint8_t is_sync); + +extern UartDevice UartDev; + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* _ROM_UART_H_ */ diff --git a/tools/ci/check_public_headers_exceptions.txt b/tools/ci/check_public_headers_exceptions.txt index 1d27a99b0a..1d42a1dd06 100644 --- a/tools/ci/check_public_headers_exceptions.txt +++ b/tools/ci/check_public_headers_exceptions.txt @@ -103,6 +103,7 @@ components/esp_rom/include/esp32c5/mp/esp32c5/rom/rtc.h components/esp_rom/include/esp32c6/rom/rtc.h components/esp_rom/include/esp32h2/rom/rtc.h components/esp_rom/include/esp32p4/rom/rtc.h +components/esp_rom/include/esp32c61/rom/rtc.h components/esp_rom/include/esp32/rom/sha.h components/esp_rom/include/esp32/rom/secure_boot.h components/esp_rom/include/esp32c3/rom/spi_flash.h