feat(system): add option to allow user disable USJ module to save power

components/esp_driver_usb_serial_jtag/Kconfig

@@ -1,8 +1,20 @@
 menu "ESP-Driver:USB Serial/JTAG Configuration"
     depends on SOC_USB_SERIAL_JTAG_SUPPORTED
+
+    config USJ_ENABLE_USB_SERIAL_JTAG
+        bool "Enable USB-Serial-JTAG Module"
+        default y
+        help
+            The USB-Serial-JTAG module on ESP chips is turned on by default after power-on.
+            If your application does not need it and not rely on it to be used as system
+            console or use the built-in JTAG for debugging, you can disable this option,
+            then the clock of this module will be disabled at startup, which will save
+            some power consumption.
+
     config USJ_NO_AUTO_LS_ON_CONNECTION
         bool "Don't enter the automatic light sleep when USB Serial/JTAG port is connected"
-        depends on PM_ENABLE && ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED && !SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP
+        depends on PM_ENABLE && ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED && !SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP \
+            && USJ_ENABLE_USB_SERIAL_JTAG
         default n
         help
             If enabled, the chip will constantly monitor the connection status of the USB Serial/JTAG port. As long

components/esp_system/Kconfig

@@ -269,6 +269,7 @@ menu "ESP System Settings"
         # Internal option, indicates that console USB SERIAL JTAG is used
         bool
         default y if ESP_CONSOLE_USB_SERIAL_JTAG || ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG
+        select USJ_ENABLE_USB_SERIAL_JTAG
 
     config ESP_CONSOLE_UART
         # Internal option, indicates that console UART is used (and not USB, for example)

components/esp_system/port/soc/esp32c3/clk.c

@@ -21,6 +21,8 @@
 #include "soc/rtc_periph.h"
 #include "soc/i2s_reg.h"
 #include "hal/wdt_hal.h"
+#include "hal/usb_serial_jtag_ll.h"
+#include "hal/usb_fsls_phy_ll.h"
 #include "esp_private/periph_ctrl.h"
 #include "esp_private/esp_clk.h"
 #include "soc/syscon_reg.h"
@@ -241,6 +243,12 @@ __attribute__((weak)) void esp_perip_clk_init(void)
                            SYSTEM_WIFI_CLK_BT_EN_M |
                            SYSTEM_WIFI_CLK_I2C_CLK_EN |
                            SYSTEM_WIFI_CLK_UNUSED_BIT12;
+
+#if !CONFIG_USJ_ENABLE_USB_SERIAL_JTAG && !CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED
+        // Disable USB-Serial-JTAG clock and it's pad if not used
+        usb_fsls_phy_ll_int_jtag_disable(&USB_SERIAL_JTAG);
+        _usb_serial_jtag_ll_enable_bus_clock(false);
+#endif
     }
 
     //Reset the communication peripherals like I2C, SPI, UART, I2S and bring them to known state.

components/esp_system/port/soc/esp32c6/clk.c

@@ -38,6 +38,8 @@
 #include "hal/clk_gate_ll.h"
 #include "hal/lp_core_ll.h"
 #include "hal/temperature_sensor_ll.h"
+#include "hal/usb_serial_jtag_ll.h"
+#include "hal/usb_fsls_phy_ll.h"
 #include "esp_private/esp_modem_clock.h"
 #include "esp_private/periph_ctrl.h"
 #include "esp_private/esp_clk.h"
@@ -273,6 +275,12 @@ __attribute__((weak)) void esp_perip_clk_init(void)
         REG_CLR_BIT(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_CLK_EN);
         REG_CLR_BIT(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_EN);
         WRITE_PERI_REG(PCR_CTRL_CLK_OUT_EN_REG, 0);
+
+#if !CONFIG_USJ_ENABLE_USB_SERIAL_JTAG && !CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED
+        // Disable USB-Serial-JTAG clock and it's pad if not used
+        usb_fsls_phy_ll_int_jtag_disable(&USB_SERIAL_JTAG);
+        usb_serial_jtag_ll_enable_bus_clock(false);
+#endif
     }
 
     if (rst_reason == RESET_REASON_CHIP_POWER_ON || rst_reason == RESET_REASON_CHIP_BROWN_OUT \

components/esp_system/port/soc/esp32h2/clk.c

@@ -39,6 +39,8 @@
 #include "hal/spi_ll.h"
 #include "hal/clk_gate_ll.h"
 #include "hal/temperature_sensor_ll.h"
+#include "hal/usb_serial_jtag_ll.h"
+#include "hal/usb_fsls_phy_ll.h"
 #include "esp_private/periph_ctrl.h"
 #include "esp_private/esp_clk.h"
 #include "esp_private/esp_pmu.h"
@@ -263,6 +265,12 @@ __attribute__((weak)) void esp_perip_clk_init(void)
         REG_CLR_BIT(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_CLK_EN);
         REG_CLR_BIT(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_EN);
         WRITE_PERI_REG(PCR_CTRL_CLK_OUT_EN_REG, 0);
+
+#if !CONFIG_USJ_ENABLE_USB_SERIAL_JTAG && !CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED
+        // Disable USB-Serial-JTAG clock and it's pad if not used
+        usb_fsls_phy_ll_int_jtag_disable(&USB_SERIAL_JTAG);
+        usb_serial_jtag_ll_enable_bus_clock(false);
+#endif
     }
 
     if (rst_reason == RESET_REASON_CHIP_POWER_ON || rst_reason == RESET_REASON_CHIP_BROWN_OUT \

components/esp_system/port/soc/esp32s3/clk.c

@@ -21,6 +21,8 @@
 #include "soc/rtc_periph.h"
 #include "soc/i2s_reg.h"
 #include "hal/wdt_hal.h"
+#include "hal/usb_serial_jtag_ll.h"
+#include "hal/usb_fsls_phy_ll.h"
 #include "esp_private/periph_ctrl.h"
 #include "esp_private/esp_clk.h"
 #include "bootloader_clock.h"
@@ -260,6 +262,12 @@ __attribute__((weak)) void esp_perip_clk_init(void)
                            SYSTEM_WIFI_CLK_I2C_CLK_EN |
                            SYSTEM_WIFI_CLK_UNUSED_BIT12 |
                            SYSTEM_WIFI_CLK_SDIO_HOST_EN;
+
+#if !CONFIG_USJ_ENABLE_USB_SERIAL_JTAG && !CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED
+        // Disable USB-Serial-JTAG clock and it's pad if not used
+        usb_fsls_phy_ll_int_jtag_disable(&USB_SERIAL_JTAG);
+        usb_serial_jtag_ll_enable_bus_clock(false);
+#endif
     }
 
     //Reset the communication peripherals like I2C, SPI, UART, I2S and bring them to known state.

components/hal/esp32c3/include/hal/usb_fsls_phy_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -29,6 +29,19 @@ static inline void usb_fsls_phy_ll_int_jtag_enable(usb_serial_jtag_dev_t *hw)
     hw->conf0.usb_pad_enable = 1;
 }
 
+/**
+ * @brief Disable the internal PHY for USB_Serial_JTAG
+ *
+ * @param hw Start address of the USB Serial_JTAG registers
+ */
+static inline void usb_fsls_phy_ll_int_jtag_disable(usb_serial_jtag_dev_t *hw)
+{
+    // Disable USB D+ pullup
+    hw->conf0.dp_pullup = 0;
+    // Disable USB pad function
+    hw->conf0.usb_pad_enable = 0;
+}
+
 #ifdef __cplusplus
 }
 #endif

components/hal/esp32c3/include/hal/usb_serial_jtag_ll.h

@@ -206,13 +206,13 @@ FORCE_INLINE_ATTR void usb_serial_jtag_ll_enable_pad(bool enable_pad)
  * @brief Enable the bus clock for  USB Serial_JTAG module
  * @param clk_en True if enable the clock of USB Serial_JTAG module
  */
-FORCE_INLINE_ATTR void usb_serial_jtag_ll_enable_bus_clock(bool clk_en)
+FORCE_INLINE_ATTR void _usb_serial_jtag_ll_enable_bus_clock(bool clk_en)
 {
     SYSTEM.perip_clk_en0.reg_usb_device_clk_en = clk_en;
 }
 
 // SYSTEM.perip_clk_enx are shared registers, so this function must be used in an atomic way
-#define usb_serial_jtag_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; usb_serial_jtag_ll_enable_bus_clock(__VA_ARGS__)
+#define usb_serial_jtag_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _usb_serial_jtag_ll_enable_bus_clock(__VA_ARGS__)
 
 /**
  * @brief Reset the usb serial jtag module

components/hal/esp32c6/include/hal/usb_fsls_phy_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -29,6 +29,19 @@ static inline void usb_fsls_phy_ll_int_jtag_enable(usb_serial_jtag_dev_t *hw)
     hw->conf0.usb_pad_enable = 1;
 }
 
+/**
+ * @brief Disable the internal PHY for USB_Serial_JTAG
+ *
+ * @param hw Start address of the USB Serial_JTAG registers
+ */
+static inline void usb_fsls_phy_ll_int_jtag_disable(usb_serial_jtag_dev_t *hw)
+{
+    // Disable USB D+ pullup
+    hw->conf0.dp_pullup = 0;
+    // Disable USB pad function
+    hw->conf0.usb_pad_enable = 0;
+}
+
 #ifdef __cplusplus
 }
 #endif

components/hal/esp32h2/include/hal/usb_fsls_phy_ll.h

@@ -29,6 +29,19 @@ static inline void usb_fsls_phy_ll_int_jtag_enable(usb_serial_jtag_dev_t *hw)
     hw->conf0.usb_pad_enable = 1;
 }
 
+/**
+ * @brief Disable the internal PHY for USB_Serial_JTAG
+ *
+ * @param hw Start address of the USB Serial_JTAG registers
+ */
+static inline void usb_fsls_phy_ll_int_jtag_disable(usb_serial_jtag_dev_t *hw)
+{
+    // Disable USB D+ pullup
+    hw->conf0.dp_pullup = 0;
+    // Disable USB pad function
+    hw->conf0.usb_pad_enable = 0;
+}
+
 #ifdef __cplusplus
 }
 #endif

components/hal/esp32s3/include/hal/usb_fsls_phy_ll.h

@@ -69,6 +69,19 @@ static inline void usb_fsls_phy_ll_int_jtag_enable(usb_serial_jtag_dev_t *hw)
     RTCCNTL.usb_conf.sw_usb_phy_sel = 0;
 }
 
+/**
+ * @brief Disable the internal PHY for USB_Serial_JTAG
+ *
+ * @param hw Start address of the USB Serial_JTAG registers
+ */
+static inline void usb_fsls_phy_ll_int_jtag_disable(usb_serial_jtag_dev_t *hw)
+{
+    // Disable USB D+ pullup
+    hw->conf0.dp_pullup = 0;
+    // Disable USB pad function
+    hw->conf0.usb_pad_enable = 0;
+}
+
 /**
  * @brief Configures the external PHY for USB_Serial_JTAG
  *

components/hal/esp32s3/include/hal/usb_serial_jtag_ll.h

@@ -206,13 +206,13 @@ FORCE_INLINE_ATTR void usb_serial_jtag_ll_enable_pad(bool enable_pad)
  * @brief Enable the bus clock for  USB Serial_JTAG module
  * @param clk_en True if enable the clock of USB Serial_JTAG module
  */
-FORCE_INLINE_ATTR void usb_serial_jtag_ll_enable_bus_clock(bool clk_en)
+FORCE_INLINE_ATTR void _usb_serial_jtag_ll_enable_bus_clock(bool clk_en)
 {
     SYSTEM.perip_clk_en1.usb_device_clk_en = clk_en;
 }
 
 // SYSTEM.perip_clk_enx are shared registers, so this function must be used in an atomic way
-#define usb_serial_jtag_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; usb_serial_jtag_ll_enable_bus_clock(__VA_ARGS__)
+#define usb_serial_jtag_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _usb_serial_jtag_ll_enable_bus_clock(__VA_ARGS__)
 
 /**
  * @brief Reset the usb serial jtag module