refactor(hal/usb): Remove usb_fsls_phy_ll.h

For targets that only contain a USJ peripheral (and not a DWC OTG), their 'usb_fsls_phy_ll.h' headers only contain a single function ('usb_fsls_phy_ll_int_jtag_enable()') whose feature is already covered by functions in 'usb_serial_jtag_ll.h'. Thus, this header is redundant. This commit does the following: - Remove 'usb_fsls_phy_ll.h' for targets that only contain a USJ peripheral - Rename 'usb_fsls_phy_[hal|ll].[h|c]' to `usb_wrap_[hal|ll].[h|c]` for targets that contain a DWC OTG peripheral. This better reflects the underlying peripheral that the LL header accesses.
2024-03-14 21:20:33 +08:00 · 2024-03-14 21:20:33 +08:00 · a77e5cc718
commit a77e5cc718
--- a/components/bootloader_support/src/bootloader_console.c
+++ b/components/bootloader_support/src/bootloader_console.c
@ -6,6 +6,7 @@

 #include "sdkconfig.h"
 #include "bootloader_console.h"
+#include "soc/soc_caps.h"
 #include "soc/uart_periph.h"
 #include "soc/uart_channel.h"
 #include "soc/io_mux_reg.h"
@ -18,8 +19,8 @@
 #include "esp32s2/rom/usb/cdc_acm.h"
 #include "esp32s2/rom/usb/usb_common.h"
 #endif
-#if SOC_USB_SERIAL_JTAG_SUPPORTED
-#include "hal/usb_fsls_phy_ll.h"
+#if CONFIG_ESP_CONSOLE_USB_CDC && SOC_USB_SERIAL_JTAG_SUPPORTED
+#include "hal/usb_wrap_ll.h"
 #endif
 #include "esp_rom_gpio.h"
 #include "esp_rom_uart.h"
--- a/components/esp_driver_usb_serial_jtag/src/usb_serial_jtag.c
+++ b/components/esp_driver_usb_serial_jtag/src/usb_serial_jtag.c
@ -9,7 +9,6 @@
 #include <stdatomic.h>
 #include "esp_log.h"
 #include "hal/usb_serial_jtag_ll.h"
-#include "hal/usb_fsls_phy_ll.h"
 #include "freertos/FreeRTOS.h"
 #include "freertos/semphr.h"
 #include "freertos/ringbuf.h"
@ -187,7 +186,8 @@ esp_err_t usb_serial_jtag_driver_install(usb_serial_jtag_driver_config_t *usb_se
    atomic_store(&p_usb_serial_jtag_obj->fifo_status, FIFO_IDLE);

    // Configure PHY
-    usb_fsls_phy_ll_int_jtag_enable(&USB_SERIAL_JTAG);
+    usb_serial_jtag_ll_phy_enable_external(false);  // Use internal PHY
+    usb_serial_jtag_ll_phy_enable_pad(true);        // Enable USB PHY pads

    usb_serial_jtag_ll_clr_intsts_mask(USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY |
                                       USB_SERIAL_JTAG_INTR_SERIAL_OUT_RECV_PKT);
--- a/components/esp_system/port/soc/esp32c3/clk.c
+++ b/components/esp_system/port/soc/esp32c3/clk.c
@ -22,7 +22,6 @@
 #include "soc/i2s_reg.h"
 #include "hal/wdt_hal.h"
 #include "hal/usb_serial_jtag_ll.h"
-#include "hal/usb_fsls_phy_ll.h"
 #include "esp_private/periph_ctrl.h"
 #include "esp_private/esp_clk.h"
 #include "soc/syscon_reg.h"
@ -246,7 +245,7 @@ __attribute__((weak)) void esp_perip_clk_init(void)

 #if !CONFIG_USJ_ENABLE_USB_SERIAL_JTAG && !CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED
        // Disable USB-Serial-JTAG clock and it's pad if not used
-        usb_fsls_phy_ll_int_jtag_disable(&USB_SERIAL_JTAG);
+        usb_serial_jtag_ll_phy_enable_pad(false);
        _usb_serial_jtag_ll_enable_bus_clock(false);
 #endif
    }
--- a/components/esp_system/port/soc/esp32c6/clk.c
+++ b/components/esp_system/port/soc/esp32c6/clk.c
@ -40,7 +40,6 @@
 #include "hal/lp_core_ll.h"
 #include "hal/temperature_sensor_ll.h"
 #include "hal/usb_serial_jtag_ll.h"
-#include "hal/usb_fsls_phy_ll.h"
 #include "esp_private/esp_modem_clock.h"
 #include "esp_private/periph_ctrl.h"
 #include "esp_private/esp_clk.h"
@ -282,7 +281,7 @@ __attribute__((weak)) void esp_perip_clk_init(void)

 #if !CONFIG_USJ_ENABLE_USB_SERIAL_JTAG && !CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED
        // Disable USB-Serial-JTAG clock and it's pad if not used
-        usb_fsls_phy_ll_int_jtag_disable(&USB_SERIAL_JTAG);
+        usb_serial_jtag_ll_phy_enable_pad(false);
        usb_serial_jtag_ll_enable_bus_clock(false);
 #endif
    }
--- a/components/esp_system/port/soc/esp32h2/clk.c
+++ b/components/esp_system/port/soc/esp32h2/clk.c
@ -41,7 +41,6 @@
 #include "hal/clk_gate_ll.h"
 #include "hal/temperature_sensor_ll.h"
 #include "hal/usb_serial_jtag_ll.h"
-#include "hal/usb_fsls_phy_ll.h"
 #include "esp_private/periph_ctrl.h"
 #include "esp_private/esp_clk.h"
 #include "esp_private/esp_pmu.h"
@ -273,7 +272,7 @@ __attribute__((weak)) void esp_perip_clk_init(void)

 #if !CONFIG_USJ_ENABLE_USB_SERIAL_JTAG && !CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED
        // Disable USB-Serial-JTAG clock and it's pad if not used
-        usb_fsls_phy_ll_int_jtag_disable(&USB_SERIAL_JTAG);
+        usb_serial_jtag_ll_phy_enable_pad(false);
        usb_serial_jtag_ll_enable_bus_clock(false);
 #endif
    }
--- a/components/esp_system/port/soc/esp32s3/clk.c
+++ b/components/esp_system/port/soc/esp32s3/clk.c
@ -22,7 +22,6 @@
 #include "soc/i2s_reg.h"
 #include "hal/wdt_hal.h"
 #include "hal/usb_serial_jtag_ll.h"
-#include "hal/usb_fsls_phy_ll.h"
 #include "esp_private/periph_ctrl.h"
 #include "esp_private/esp_clk.h"
 #include "bootloader_clock.h"
@ -265,7 +264,7 @@ __attribute__((weak)) void esp_perip_clk_init(void)

 #if !CONFIG_USJ_ENABLE_USB_SERIAL_JTAG && !CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED
        // Disable USB-Serial-JTAG clock and it's pad if not used
-        usb_fsls_phy_ll_int_jtag_disable(&USB_SERIAL_JTAG);
+        usb_serial_jtag_ll_phy_enable_pad(false);
        usb_serial_jtag_ll_enable_bus_clock(false);
 #endif
    }
--- a/components/hal/CMakeLists.txt
+++ b/components/hal/CMakeLists.txt
@ -258,7 +258,7 @@ if(NOT BOOTLOADER_BUILD)
    if(CONFIG_SOC_USB_OTG_SUPPORTED)
        list(APPEND srcs "usb_dwc_hal.c")
        if(NOT ${target} STREQUAL "esp32p4")
-            list(APPEND srcs "usb_fsls_phy_hal.c")
+            list(APPEND srcs "usb_wrap_hal.c")
        endif()
    endif()

--- a/components/hal/esp32c3/include/hal/usb_fsls_phy_ll.h
+++ b/components/hal/esp32c3/include/hal/usb_fsls_phy_ll.h
@ -1,47 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-#include "soc/usb_serial_jtag_struct.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @brief Configures the internal PHY for USB_Serial_JTAG
- *
- * @param hw Start address of the USB Serial_JTAG registers
- */
-static inline void usb_fsls_phy_ll_int_jtag_enable(usb_serial_jtag_dev_t *hw)
-{
-    // USB_Serial_JTAG use internal PHY
-    hw->conf0.phy_sel = 0;
-    // Disable software control USB D+ D- pullup pulldown (Device FS: dp_pullup = 1)
-    hw->conf0.pad_pull_override = 0;
-    // Enable USB D+ pullup
-    hw->conf0.dp_pullup = 1;
-    // Enable USB pad function
-    hw->conf0.usb_pad_enable = 1;
-}
-
-/**
- * @brief Disable the internal PHY for USB_Serial_JTAG
- *
- * @param hw Start address of the USB Serial_JTAG registers
- */
-static inline void usb_fsls_phy_ll_int_jtag_disable(usb_serial_jtag_dev_t *hw)
-{
-    // Disable USB D+ pullup
-    hw->conf0.dp_pullup = 0;
-    // Disable USB pad function
-    hw->conf0.usb_pad_enable = 0;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/components/hal/esp32c6/include/hal/usb_fsls_phy_ll.h
+++ b/components/hal/esp32c6/include/hal/usb_fsls_phy_ll.h
@ -1,47 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-#include "soc/usb_serial_jtag_struct.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @brief Configures the internal PHY for USB_Serial_JTAG
- *
- * @param hw Start address of the USB Serial_JTAG registers
- */
-static inline void usb_fsls_phy_ll_int_jtag_enable(usb_serial_jtag_dev_t *hw)
-{
-    // USB_Serial_JTAG use internal PHY
-    hw->conf0.phy_sel = 0;
-    // Disable software control USB D+ D- pullup pulldown (Device FS: dp_pullup = 1)
-    hw->conf0.pad_pull_override = 0;
-    // Enable USB D+ pullup
-    hw->conf0.dp_pullup = 1;
-    // Enable USB pad function
-    hw->conf0.usb_pad_enable = 1;
-}
-
-/**
- * @brief Disable the internal PHY for USB_Serial_JTAG
- *
- * @param hw Start address of the USB Serial_JTAG registers
- */
-static inline void usb_fsls_phy_ll_int_jtag_disable(usb_serial_jtag_dev_t *hw)
-{
-    // Disable USB D+ pullup
-    hw->conf0.dp_pullup = 0;
-    // Disable USB pad function
-    hw->conf0.usb_pad_enable = 0;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/components/hal/esp32h2/include/hal/usb_fsls_phy_ll.h
+++ b/components/hal/esp32h2/include/hal/usb_fsls_phy_ll.h
@ -1,47 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-#include "soc/usb_serial_jtag_struct.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @brief Configures the internal PHY for USB_Serial_JTAG
- *
- * @param hw Start address of the USB Serial_JTAG registers
- */
-static inline void usb_fsls_phy_ll_int_jtag_enable(usb_serial_jtag_dev_t *hw)
-{
-    // USB_Serial_JTAG use internal PHY
-    hw->conf0.phy_sel = 0;
-    // Disable software control USB D+ D- pullup pulldown (Device FS: dp_pullup = 1)
-    hw->conf0.pad_pull_override = 0;
-    // Enable USB D+ pullup
-    hw->conf0.dp_pullup = 1;
-    // Enable USB pad function
-    hw->conf0.usb_pad_enable = 1;
-}
-
-/**
- * @brief Disable the internal PHY for USB_Serial_JTAG
- *
- * @param hw Start address of the USB Serial_JTAG registers
- */
-static inline void usb_fsls_phy_ll_int_jtag_disable(usb_serial_jtag_dev_t *hw)
-{
-    // Disable USB D+ pullup
-    hw->conf0.dp_pullup = 0;
-    // Disable USB pad function
-    hw->conf0.usb_pad_enable = 0;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/components/hal/esp32s2/include/hal/usb_fsls_phy_ll.h
+++ b/components/hal/esp32s2/include/hal/usb_fsls_phy_ll.h
--- a/components/hal/esp32s3/include/hal/usb_fsls_phy_ll.h
+++ b/components/hal/esp32s3/include/hal/usb_fsls_phy_ll.h
--- a/components/hal/include/hal/usb_fsls_phy_hal.h
+++ b/components/hal/include/hal/usb_fsls_phy_hal.h
--- a/components/hal/usb_fsls_phy_hal.c
+++ b/components/hal/usb_fsls_phy_hal.c
@ -4,8 +4,13 @@
 * SPDX-License-Identifier: Apache-2.0
 */

-#include "hal/usb_fsls_phy_ll.h"
-#include "hal/usb_fsls_phy_hal.h"
+#include "soc/soc_caps.h"
+#include "soc/rtc_cntl_struct.h"
+#if SOC_USB_SERIAL_JTAG_SUPPORTED
+#include "hal/usb_serial_jtag_ll.h"
+#endif
+#include "hal/usb_wrap_ll.h"
+#include "hal/usb_wrap_hal.h"

 void usb_fsls_phy_hal_init(usb_fsls_phy_hal_context_t *hal)
 {
@ -29,9 +34,18 @@ void usb_fsls_phy_hal_otg_conf(usb_fsls_phy_hal_context_t *hal, usb_phy_target_t
 void usb_fsls_phy_hal_jtag_conf(usb_fsls_phy_hal_context_t *hal, usb_phy_target_t phy_target)
 {
    if (phy_target == USB_PHY_TARGET_EXT) {
-        usb_fsls_phy_ll_ext_jtag_enable(hal->jtag_dev);
+        usb_serial_jtag_ll_phy_enable_external(true);   // USJ uses external PHY
+        // Enable SW control of muxing USB OTG vs USJ to the internal USB FSLS PHY
+        RTCCNTL.usb_conf.sw_hw_usb_phy_sel = 1;
+        // Internal USB FSLS PHY is mapped to the USJ
+        RTCCNTL.usb_conf.sw_usb_phy_sel = 1;
    } else if (phy_target == USB_PHY_TARGET_INT) {
-        usb_fsls_phy_ll_int_jtag_enable(hal->jtag_dev);
+        usb_serial_jtag_ll_phy_enable_external(true);   // USJ uses internal PHY
+        usb_serial_jtag_ll_phy_enable_pad(true);        // Enable USB PHY pads
+        // Enable SW control of muxing USB OTG vs USJ to the internal USB FSLS PHY
+        RTCCNTL.usb_conf.sw_hw_usb_phy_sel = 1;
+        // Internal USB FSLS PHY is mapped to the USJ
+        RTCCNTL.usb_conf.sw_usb_phy_sel = 0;
    }
 }
 #endif
--- a/components/usb/usb_phy.c
+++ b/components/usb/usb_phy.c
@ -12,8 +12,8 @@
 #include "esp_private/periph_ctrl.h"
 #include "esp_private/usb_phy.h"
 #include "soc/usb_dwc_periph.h"
-#include "hal/usb_fsls_phy_hal.h"
-#include "hal/usb_fsls_phy_ll.h"
+#include "hal/usb_wrap_hal.h"
+#include "hal/usb_wrap_ll.h"
 #include "esp_rom_gpio.h"
 #include "driver/gpio.h"
 #include "hal/gpio_ll.h"