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fix(esp_pm): fix PM_SLP_IRAM_OPT/PM_RTOS_IDLE_OPT feature 

- Fix flash accessed code to resolve issues with PM_SLP_IRAM_OPT/PM_RTOS_IDLE_OPT enabled
pull/11836/head
wuzhenghui 2023-06-25 17:12:43 +08:00
rodzic 4e9cc65763
commit a5c992c8af
19 zmienionych plików z 81 dodań i 52 usunięć
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7
components/esp_hw_support/Kconfig
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@ -72,8 +72,7 @@ menu "Hardware Settings"
config ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND
bool "Pull-up Flash CS pin in light sleep"
depends on !APP_BUILD_TYPE_PURE_RAM_APP && !ESP_SLEEP_POWER_DOWN_FLASH \
&& !PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
depends on !APP_BUILD_TYPE_PURE_RAM_APP && !ESP_SLEEP_POWER_DOWN_FLASH
default y
help
All IOs will be set to isolate(floating) state by default during sleep.
@ -89,7 +88,7 @@ menu "Hardware Settings"
config ESP_SLEEP_PSRAM_LEAKAGE_WORKAROUND
bool "Pull-up PSRAM CS pin in light sleep"
depends on SPIRAM && !PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
depends on SPIRAM
default y
help
All IOs will be set to isolate(floating) state by default during sleep.
@ -105,7 +104,7 @@ menu "Hardware Settings"
config ESP_SLEEP_MSPI_NEED_ALL_IO_PU
bool "Pull-up all SPI pins in light sleep"
depends on !ESP_SLEEP_POWER_DOWN_FLASH && !PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP \
depends on !ESP_SLEEP_POWER_DOWN_FLASH \
&& (ESP_SLEEP_PSRAM_LEAKAGE_WORKAROUND || ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND)
default y if IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32S3
help

4
components/esp_hw_support/intr_alloc.c
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@ -893,12 +893,12 @@ void IRAM_ATTR ets_isr_mask(uint32_t mask) {
esp_cpu_intr_disable(mask);
}
void esp_intr_enable_source(int inum)
void IRAM_ATTR esp_intr_enable_source(int inum)
{
esp_cpu_intr_enable(1 << inum);
}
void esp_intr_disable_source(int inum)
void IRAM_ATTR esp_intr_disable_source(int inum)
{
esp_cpu_intr_disable(1 << inum);
}

8
components/esp_hw_support/linker.lf
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@ -23,8 +23,6 @@ entries:
rtc_time (noflash_text)
if SOC_PMU_SUPPORTED = y:
pmu_sleep (noflash)
if PM_SLP_IRAM_OPT = y && IDF_TARGET_ESP32 = n:
sleep_modem:periph_inform_out_light_sleep_overhead (noflash)
if IDF_TARGET_ESP32 = y || IDF_TARGET_ESP32S2 = y:
rtc_wdt (noflash_text)
if PERIPH_CTRL_FUNC_IN_IRAM = y:
@ -44,3 +42,9 @@ entries:
sar_periph_ctrl (noflash)
else:
sar_periph_ctrl: sar_periph_ctrl_power_enable (noflash)
[mapping:soc_pm]
archive: libsoc.a
entries:
if PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND:
gpio_periph: GPIO_HOLD_MASK (noflash)

2
components/esp_hw_support/modem_clock.c
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@ -283,7 +283,7 @@ void IRAM_ATTR modem_clock_module_mac_reset(periph_module_t module)
#define COEXIST_CLOCK_DEPS (BIT(MODEM_CLOCK_COEXIST))
#define PHY_CLOCK_DEPS (BIT(MODEM_CLOCK_I2C_MASTER) | BIT(MODEM_CLOCK_FE))
static inline uint32_t modem_clock_get_module_deps(periph_module_t module)
static IRAM_ATTR uint32_t modem_clock_get_module_deps(periph_module_t module)
{
uint32_t deps = 0;
if (module == PERIPH_PHY_MODULE) {deps = PHY_CLOCK_DEPS;}

7
components/esp_hw_support/port/esp32c2/rtc_sleep.c
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@ -1,11 +1,12 @@
/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdint.h>
#include <stdlib.h>
#include "esp_attr.h"
#include "soc/soc.h"
#include "soc/rtc.h"
#include "soc/rtc_cntl_reg.h"
@ -21,6 +22,8 @@
#include "soc/regi2c_lp_bias.h"
#include "soc/regi2c_dig_reg.h"
static const DRAM_ATTR rtc_sleep_pu_config_t pu_cfg = RTC_SLEEP_PU_CONFIG_ALL(1);
/**
* Configure whether certain peripherals are powered down in deep sleep
* @param cfg power down flags as rtc_sleep_pu_config_t structure
@ -143,7 +146,6 @@ void rtc_sleep_get_default_config(uint32_t sleep_flags, rtc_sleep_config_t *out_
void rtc_sleep_init(rtc_sleep_config_t cfg)
{
if (cfg.lslp_mem_inf_fpu) {
rtc_sleep_pu_config_t pu_cfg = RTC_SLEEP_PU_CONFIG_ALL(1);
rtc_sleep_pu(pu_cfg);
}
@ -229,7 +231,6 @@ static uint32_t rtc_sleep_finish(uint32_t lslp_mem_inf_fpu)
/* restore config if it is a light sleep */
if (lslp_mem_inf_fpu) {
rtc_sleep_pu_config_t pu_cfg = RTC_SLEEP_PU_CONFIG_ALL(1);
rtc_sleep_pu(pu_cfg);
}
return reject;

7
components/esp_hw_support/port/esp32c3/rtc_sleep.c
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@ -1,11 +1,12 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdint.h>
#include <stdlib.h>
#include "esp_attr.h"
#include "soc/soc.h"
#include "soc/rtc.h"
#include "soc/rtc_cntl_reg.h"
@ -27,6 +28,8 @@
#include "soc/systimer_reg.h"
#endif
static const DRAM_ATTR rtc_sleep_pu_config_t pu_cfg = RTC_SLEEP_PU_CONFIG_ALL(1);
/**
* Configure whether certain peripherals are powered down in deep sleep
* @param cfg power down flags as rtc_sleep_pu_config_t structure
@ -168,7 +171,6 @@ void rtc_sleep_get_default_config(uint32_t sleep_flags, rtc_sleep_config_t *out_
void rtc_sleep_init(rtc_sleep_config_t cfg)
{
if (cfg.lslp_mem_inf_fpu) {
rtc_sleep_pu_config_t pu_cfg = RTC_SLEEP_PU_CONFIG_ALL(1);
rtc_sleep_pu(pu_cfg);
}
if (cfg.wifi_pd_en) {
@ -368,7 +370,6 @@ static uint32_t rtc_sleep_finish(uint32_t lslp_mem_inf_fpu)
/* restore config if it is a light sleep */
if (lslp_mem_inf_fpu) {
rtc_sleep_pu_config_t pu_cfg = RTC_SLEEP_PU_CONFIG_ALL(1);
rtc_sleep_pu(pu_cfg);
}
return reject;

7
components/esp_hw_support/port/esp32s3/rtc_sleep.c
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@ -1,10 +1,11 @@
/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdint.h>
#include "esp_attr.h"
#include "soc/soc.h"
#include "soc/rtc.h"
#include "soc/rtc_cntl_reg.h"
@ -20,6 +21,8 @@
#define RTC_CNTL_MEM_FOLW_CPU (RTC_CNTL_SLOWMEM_FOLW_CPU | RTC_CNTL_FASTMEM_FOLW_CPU)
static const DRAM_ATTR rtc_sleep_pu_config_t pu_cfg = RTC_SLEEP_PU_CONFIG_ALL(1);
/**
* Configure whether certain peripherals are powered up in sleep
* @param cfg power down flags as rtc_sleep_pu_config_t structure
@ -171,7 +174,6 @@ void rtc_sleep_get_default_config(uint32_t sleep_flags, rtc_sleep_config_t *out_
void rtc_sleep_init(rtc_sleep_config_t cfg)
{
if (cfg.lslp_mem_inf_fpu) {
rtc_sleep_pu_config_t pu_cfg = RTC_SLEEP_PU_CONFIG_ALL(1);
rtc_sleep_pu(pu_cfg);
}
@ -289,7 +291,6 @@ static uint32_t rtc_sleep_finish(uint32_t lslp_mem_inf_fpu)
/* restore config if it is a light sleep */
if (lslp_mem_inf_fpu) {
rtc_sleep_pu_config_t pu_cfg = RTC_SLEEP_PU_CONFIG_ALL(1);
rtc_sleep_pu(pu_cfg);
}

2
components/esp_hw_support/sleep_clock.c
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@ -76,7 +76,7 @@ void sleep_clock_modem_retention_deinit(void)
sleep_retention_entries_destroy(SLEEP_RETENTION_MODULE_CLOCK_MODEM);
}
bool IRAM_ATTR clock_domain_pd_allowed(void)
bool clock_domain_pd_allowed(void)
{
const uint32_t modules = sleep_retention_get_modules();
const uint32_t mask = (const uint32_t) (

2
components/esp_hw_support/sleep_modem.c
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@ -275,7 +275,7 @@ inline __attribute__((always_inline)) bool sleep_modem_wifi_modem_link_done(void
#endif /* SOC_PM_SUPPORT_PMU_MODEM_STATE */
bool IRAM_ATTR modem_domain_pd_allowed(void)
bool modem_domain_pd_allowed(void)
{
#if SOC_PM_MODEM_RETENTION_BY_REGDMA
const uint32_t modules = sleep_retention_get_modules();

34
components/esp_hw_support/sleep_modes.c
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@ -400,10 +400,11 @@ void esp_deep_sleep_deregister_hook(esp_deep_sleep_cb_t old_dslp_cb)
portEXIT_CRITICAL(&spinlock_rtc_deep_sleep);
}
#if (CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND) \
#if (CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND && !CONFIG_IDF_TARGET_ESP32H2) \
|| CONFIG_ESP_SLEEP_CACHE_SAFE_ASSERTION
static int s_cache_suspend_cnt = 0;
// Must be called from critical sections.
static void IRAM_ATTR suspend_cache(void) {
s_cache_suspend_cnt++;
if (s_cache_suspend_cnt == 1) {
@ -411,9 +412,10 @@ static void IRAM_ATTR suspend_cache(void) {
}
}
// Must be called from critical sections.
static void IRAM_ATTR resume_cache(void) {
s_cache_suspend_cnt--;
assert(s_cache_suspend_cnt >= 0 && "cache resume doesn't match suspend ops");
assert(s_cache_suspend_cnt >= 0 && DRAM_STR("cache resume doesn't match suspend ops"));
if (s_cache_suspend_cnt == 0) {
cache_hal_resume(CACHE_TYPE_ALL);
}
@ -427,7 +429,7 @@ static void IRAM_ATTR flush_uarts(void)
#ifdef CONFIG_IDF_TARGET_ESP32
esp_rom_uart_tx_wait_idle(i);
#else
if (periph_ll_periph_enabled(PERIPH_UART0_MODULE + i)) {
if (periph_ll_uart_enabled(i)) {
esp_rom_uart_tx_wait_idle(i);
}
#endif
@ -437,14 +439,15 @@ static void IRAM_ATTR flush_uarts(void)
static uint32_t s_suspended_uarts_bmap = 0;
/**
* Suspend enabled uarts and return suspended uarts bit map
* Suspend enabled uarts and return suspended uarts bit map.
* Must be called from critical sections.
*/
static IRAM_ATTR void suspend_uarts(void)
FORCE_INLINE_ATTR void suspend_uarts(void)
{
s_suspended_uarts_bmap = 0;
for (int i = 0; i < SOC_UART_HP_NUM; ++i) {
#ifndef CONFIG_IDF_TARGET_ESP32
if (!periph_ll_periph_enabled(PERIPH_UART0_MODULE + i)) {
if (!periph_ll_uart_enabled(i)) {
continue;
}
#endif
@ -461,7 +464,8 @@ static IRAM_ATTR void suspend_uarts(void)
}
}
static void IRAM_ATTR resume_uarts(void)
// Must be called from critical sections
FORCE_INLINE_ATTR void resume_uarts(void)
{
for (int i = 0; i < SOC_UART_HP_NUM; ++i) {
if (s_suspended_uarts_bmap & 0x1) {
@ -487,7 +491,7 @@ static void IRAM_ATTR resume_uarts(void)
completion time has exceeded the wakeup time, we should abandon the flush, skip the sleep and
return ESP_ERR_SLEEP_REJECT.
*/
static bool light_sleep_uart_prepare(uint32_t pd_flags, int64_t sleep_duration)
FORCE_INLINE_ATTR bool light_sleep_uart_prepare(uint32_t pd_flags, int64_t sleep_duration)
{
bool should_skip_sleep = false;
#if !SOC_PM_SUPPORT_TOP_PD
@ -513,7 +517,7 @@ static bool light_sleep_uart_prepare(uint32_t pd_flags, int64_t sleep_duration)
/**
* These save-restore workaround should be moved to lower layer
*/
inline static void IRAM_ATTR misc_modules_sleep_prepare(bool deep_sleep)
FORCE_INLINE_ATTR void misc_modules_sleep_prepare(bool deep_sleep)
{
if (deep_sleep){
for (int n = 0; n < MAX_DSLP_HOOKS; n++) {
@ -548,7 +552,7 @@ inline static void IRAM_ATTR misc_modules_sleep_prepare(bool deep_sleep)
/**
* These save-restore workaround should be moved to lower layer
*/
inline static void IRAM_ATTR misc_modules_wake_prepare(void)
FORCE_INLINE_ATTR void misc_modules_wake_prepare(void)
{
#if SOC_PM_RETENTION_HAS_REGDMA_POWER_BUG
sleep_retention_do_system_retention(false);
@ -746,7 +750,7 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t m
In order to avoid the leakage of the SPI cs pin, hold it here */
#if (CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND)
#if !CONFIG_IDF_TARGET_ESP32H2 // ESP32H2 TODO IDF-7359: related rtcio ll func not supported yet
if(!(pd_flags & PMU_SLEEP_PD_VDDSDIO)) {
if(!(pd_flags & RTC_SLEEP_PD_VDDSDIO)) {
/* Cache Suspend 1: will wait cache idle in cache suspend, also means SPI bus IDLE, then we can hold SPI CS pin safely*/
suspend_cache();
gpio_ll_hold_en(&GPIO, SPI_CS0_GPIO_NUM);
@ -769,7 +773,7 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t m
/* Unhold the SPI CS pin */
#if (CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND)
#if !CONFIG_IDF_TARGET_ESP32H2 // ESP32H2 TODO IDF-7359: related rtcio ll func not supported yet
if(!(pd_flags & PMU_SLEEP_PD_VDDSDIO)) {
if(!(pd_flags & RTC_SLEEP_PD_VDDSDIO)) {
gpio_ll_hold_dis(&GPIO, SPI_CS0_GPIO_NUM);
/* Cache Resume 1: Resume cache for continue running*/
resume_cache();
@ -949,7 +953,7 @@ static esp_err_t esp_light_sleep_inner(uint32_t pd_flags,
* x | 1 | pd flash with relaxed conditions(force_pd)
* 1 | 0 | pd flash with strict conditions(safe_pd)
*/
static inline bool can_power_down_vddsdio(uint32_t pd_flags, const uint32_t vddsdio_pd_sleep_duration)
FORCE_INLINE_ATTR bool can_power_down_vddsdio(uint32_t pd_flags, const uint32_t vddsdio_pd_sleep_duration)
{
bool force_pd = !(s_config.wakeup_triggers & RTC_TIMER_TRIG_EN) || (s_config.sleep_duration > vddsdio_pd_sleep_duration);
bool safe_pd = (s_config.wakeup_triggers == RTC_TIMER_TRIG_EN) && (s_config.sleep_duration > vddsdio_pd_sleep_duration);
@ -1702,7 +1706,7 @@ esp_err_t esp_sleep_pd_config(esp_sleep_pd_domain_t domain, esp_sleep_pd_option_
* the XTAL clock control of some chips(esp32c6/esp32h2) depends on the top domain.
*/
#if SOC_PM_SUPPORT_TOP_PD
static inline bool top_domain_pd_allowed(void) {
FORCE_INLINE_ATTR bool top_domain_pd_allowed(void) {
return (cpu_domain_pd_allowed() && \
clock_domain_pd_allowed() && \
peripheral_domain_pd_allowed() && \
@ -1794,7 +1798,7 @@ static uint32_t get_power_down_flags(void)
s_config.domain[ESP_PD_DOMAIN_XTAL].pd_option = ESP_PD_OPTION_OFF;
#endif
const __attribute__((unused)) char *option_str[] = {"OFF", "ON", "AUTO(OFF)" /* Auto works as OFF */};
const __attribute__((unused)) char *option_str[] = {DRAM_STR("OFF"), DRAM_STR("ON"), DRAM_STR("AUTO(OFF)") /* Auto works as OFF */};
/* This function is called from a critical section, log with ESP_EARLY_LOGD. */
#if SOC_PM_SUPPORT_RTC_PERIPH_PD
ESP_EARLY_LOGD(TAG, "RTC_PERIPH: %s", option_str[s_config.domain[ESP_PD_DOMAIN_RTC_PERIPH].pd_option]);

2
components/esp_hw_support/sleep_system_peripheral.c
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@ -236,7 +236,7 @@ error:
return err;
}
bool IRAM_ATTR peripheral_domain_pd_allowed(void)
bool peripheral_domain_pd_allowed(void)
{
const uint32_t modules = sleep_retention_get_modules();
const uint32_t mask = (const uint32_t) (

8
components/esp_pm/Kconfig
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@ -51,8 +51,8 @@ menu "Power Management"
bool "Put lightsleep related codes in internal RAM"
depends on FREERTOS_USE_TICKLESS_IDLE
help
If enabled, about 1.8KB of lightsleep related source code would be in IRAM and chip would sleep
longer for 760us at most each time.
If enabled, about 2.1KB of lightsleep related source code would be in IRAM and chip would sleep
longer for 310us at 160MHz CPU frequency most each time.
This feature is intended to be used when lower power consumption is needed
while there is enough place in IRAM to place source code.
@ -60,8 +60,8 @@ menu "Power Management"
bool "Put RTOS IDLE related codes in internal RAM"
depends on FREERTOS_USE_TICKLESS_IDLE
help
If enabled, about 260B of RTOS_IDLE related source code would be in IRAM and chip would sleep
longer for 40us at most each time.
If enabled, about 180Bytes of RTOS_IDLE related source code would be in IRAM and chip would sleep
longer for 20us at 160MHz CPU frequency most each time.
This feature is intended to be used when lower power consumption is needed
while there is enough place in IRAM to place source code.

17
components/esp_pm/linker.lf
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@ -5,6 +5,9 @@ entries:
pm_impl:esp_pm_impl_idle_hook (noflash)
pm_impl:esp_pm_impl_waiti (noflash)
if PM_SLP_IRAM_OPT = y:
pm_impl:esp_pm_impl_get_cpu_freq (noflash)
[mapping:esp_hw_support_pm]
archive: libesp_hw_support.a
entries:
@ -16,12 +19,24 @@ entries:
esp_clk:esp_clk_slowclk_cal_set (noflash)
esp_clk:esp_clk_slowclk_cal_get (noflash)
esp_clk:esp_rtc_get_time_us (noflash)
esp_clk:esp_clk_private_lock (noflash)
esp_clk:esp_clk_private_unlock (noflash)
if SOC_RTC_MEM_SUPPORTED = y:
esp_clk:calc_checksum (noflash)
if SOC_SYSTIMER_SUPPORTED = y:
systimer (noflash)
if GPIO_ESP32_SUPPORT_SWITCH_SLP_PULL = y:
sleep_gpio:gpio_sleep_mode_config_apply (noflash)
if SOC_PM_CPU_RETENTION_BY_RTCCNTL = y && (SOC_PM_SUPPORT_CPU_PD = y || SOC_PM_SUPPORT_TAGMEM_PD = y):
sleep_cpu:sleep_enable_cpu_retention (noflash)
if SOC_PM_SUPPORT_CPU_PD = y:
sleep_cpu:cpu_domain_pd_allowed (noflash)
if SOC_PM_SUPPORT_TOP_PD = y:
sleep_clock:clock_domain_pd_allowed (noflash)
sleep_system_peripheral:peripheral_domain_pd_allowed (noflash)
sleep_modem:modem_domain_pd_allowed (noflash)
sleep_modem:periph_inform_out_light_sleep_overhead (noflash)
sar_periph_ctrl:sar_periph_ctrl_power_disable (noflash)
[mapping:esp_system_pm]
archive: libesp_system.a
@ -48,10 +63,12 @@ entries:
esp_timer_impl_lac:esp_timer_impl_lock (noflash)
esp_timer_impl_lac:esp_timer_impl_unlock (noflash)
esp_timer_impl_lac:esp_timer_impl_advance (noflash)
esp_timer_impl_lac:esp_timer_impl_set (noflash)
elif ESP_TIMER_IMPL_SYSTIMER = y:
esp_timer_impl_systimer:esp_timer_impl_lock (noflash)
esp_timer_impl_systimer:esp_timer_impl_unlock (noflash)
esp_timer_impl_systimer:esp_timer_impl_advance (noflash)
esp_timer_impl_systimer:esp_timer_impl_set (noflash)
[mapping:newlib_pm]
archive: libnewlib.a

4
components/hal/esp32c6/modem_clock_hal.c
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@ -19,7 +19,7 @@ typedef enum {
MODEM_CLOCK_EXT32K_CODE = 2
} modem_clock_32k_clk_src_code_t;
void modem_clock_hal_set_clock_domain_icg_bitmap(modem_clock_hal_context_t *hal, modem_clock_domain_t domain, uint32_t bitmap)
void IRAM_ATTR modem_clock_hal_set_clock_domain_icg_bitmap(modem_clock_hal_context_t *hal, modem_clock_domain_t domain, uint32_t bitmap)
{
HAL_ASSERT(domain < MODEM_CLOCK_DOMAIN_MAX);
switch (domain)
@ -101,7 +101,7 @@ uint32_t modem_clock_hal_get_clock_domain_icg_bitmap(modem_clock_hal_context_t *
return bitmap;
}
void modem_clock_hal_enable_fe_clock(modem_clock_hal_context_t *hal, bool enable)
void IRAM_ATTR modem_clock_hal_enable_fe_clock(modem_clock_hal_context_t *hal, bool enable)
{
if (enable) {
modem_syscon_ll_enable_fe_apb_clock(hal->syscon_dev, enable);

8
components/hal/esp32c6/pmu_hal.c
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@ -11,26 +11,26 @@
#include "hal/pmu_hal.h"
#include "hal/pmu_types.h"
void IRAM_ATTR pmu_hal_hp_set_digital_power_up_wait_cycle(pmu_hal_context_t *hal, uint32_t power_supply_wait_cycle, uint32_t power_up_wait_cycle)
void pmu_hal_hp_set_digital_power_up_wait_cycle(pmu_hal_context_t *hal, uint32_t power_supply_wait_cycle, uint32_t power_up_wait_cycle)
{
pmu_ll_hp_set_digital_power_supply_wait_cycle(hal->dev, power_supply_wait_cycle);
pmu_ll_hp_set_digital_power_up_wait_cycle(hal->dev, power_up_wait_cycle);
}
uint32_t IRAM_ATTR pmu_hal_hp_get_digital_power_up_wait_cycle(pmu_hal_context_t *hal)
uint32_t pmu_hal_hp_get_digital_power_up_wait_cycle(pmu_hal_context_t *hal)
{
uint32_t power_supply_wait_cycle = pmu_ll_hp_get_digital_power_supply_wait_cycle(hal->dev);
uint32_t power_up_wait_cycle = pmu_ll_hp_get_digital_power_up_wait_cycle(hal->dev);
return power_supply_wait_cycle + power_up_wait_cycle;
}
void IRAM_ATTR pmu_hal_lp_set_digital_power_up_wait_cycle(pmu_hal_context_t *hal, uint32_t power_supply_wait_cycle, uint32_t power_up_wait_cycle)
void pmu_hal_lp_set_digital_power_up_wait_cycle(pmu_hal_context_t *hal, uint32_t power_supply_wait_cycle, uint32_t power_up_wait_cycle)
{
pmu_ll_lp_set_digital_power_supply_wait_cycle(hal->dev, power_supply_wait_cycle);
pmu_ll_lp_set_digital_power_up_wait_cycle(hal->dev, power_up_wait_cycle);
}
uint32_t IRAM_ATTR pmu_hal_lp_get_digital_power_up_wait_cycle(pmu_hal_context_t *hal)
uint32_t pmu_hal_lp_get_digital_power_up_wait_cycle(pmu_hal_context_t *hal)
{
uint32_t power_supply_wait_cycle = pmu_ll_lp_get_digital_power_supply_wait_cycle(hal->dev);
uint32_t power_up_wait_cycle = pmu_ll_lp_get_digital_power_up_wait_cycle(hal->dev);

2
components/hal/esp32h2/modem_clock_hal.c
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@ -19,7 +19,7 @@ typedef enum {
MODEM_CLOCK_EXT32K_CODE = 2
} modem_clock_32k_clk_src_code_t;
void modem_clock_hal_enable_fe_clock(modem_clock_hal_context_t *hal, bool enable)
void IRAM_ATTR modem_clock_hal_enable_fe_clock(modem_clock_hal_context_t *hal, bool enable)
{
modem_lpcon_ll_enable_fe_mem_clock(hal->lpcon_dev, enable);
modem_syscon_ll_enable_fe_sdm_clock(hal->syscon_dev, enable);

8
components/hal/esp32h2/pmu_hal.c
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@ -11,26 +11,26 @@
#include "hal/pmu_hal.h"
#include "hal/pmu_types.h"
void IRAM_ATTR pmu_hal_hp_set_digital_power_up_wait_cycle(pmu_hal_context_t *hal, uint32_t power_supply_wait_cycle, uint32_t power_up_wait_cycle)
void pmu_hal_hp_set_digital_power_up_wait_cycle(pmu_hal_context_t *hal, uint32_t power_supply_wait_cycle, uint32_t power_up_wait_cycle)
{
pmu_ll_hp_set_digital_power_supply_wait_cycle(hal->dev, power_supply_wait_cycle);
pmu_ll_hp_set_digital_power_up_wait_cycle(hal->dev, power_up_wait_cycle);
}
uint32_t IRAM_ATTR pmu_hal_hp_get_digital_power_up_wait_cycle(pmu_hal_context_t *hal)
uint32_t pmu_hal_hp_get_digital_power_up_wait_cycle(pmu_hal_context_t *hal)
{
uint32_t power_supply_wait_cycle = pmu_ll_hp_get_digital_power_supply_wait_cycle(hal->dev);
uint32_t power_up_wait_cycle = pmu_ll_hp_get_digital_power_up_wait_cycle(hal->dev);
return power_supply_wait_cycle + power_up_wait_cycle;
}
void IRAM_ATTR pmu_hal_lp_set_digital_power_up_wait_cycle(pmu_hal_context_t *hal, uint32_t power_supply_wait_cycle, uint32_t power_up_wait_cycle)
void pmu_hal_lp_set_digital_power_up_wait_cycle(pmu_hal_context_t *hal, uint32_t power_supply_wait_cycle, uint32_t power_up_wait_cycle)
{
pmu_ll_lp_set_digital_power_supply_wait_cycle(hal->dev, power_supply_wait_cycle);
pmu_ll_lp_set_digital_power_up_wait_cycle(hal->dev, power_up_wait_cycle);
}
uint32_t IRAM_ATTR pmu_hal_lp_get_digital_power_up_wait_cycle(pmu_hal_context_t *hal)
uint32_t pmu_hal_lp_get_digital_power_up_wait_cycle(pmu_hal_context_t *hal)
{
uint32_t power_supply_wait_cycle = pmu_ll_lp_get_digital_power_supply_wait_cycle(hal->dev);
uint32_t power_up_wait_cycle = pmu_ll_lp_get_digital_power_up_wait_cycle(hal->dev);

2
components/hal/esp32s3/include/hal/uart_ll.h
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@ -934,7 +934,7 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_low_pulse_cnt(uart_dev_t *hw)
*
* @return None.
*/
static inline void uart_ll_force_xoff(uart_port_t uart_num)
FORCE_INLINE_ATTR void uart_ll_force_xoff(uart_port_t uart_num)
{
REG_CLR_BIT(UART_FLOW_CONF_REG(uart_num), UART_FORCE_XON);
REG_SET_BIT(UART_FLOW_CONF_REG(uart_num), UART_SW_FLOW_CON_EN | UART_FORCE_XOFF);

2
components/hal/linker.lf
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@ -50,3 +50,5 @@ entries:
adc_hal: adc_hal_check_event (noflash)
adc_hal: adc_hal_digi_clr_intr (noflash)
adc_hal: adc_hal_get_desc_addr (noflash)
if SOC_PMU_SUPPORTED = y:
pmu_hal (noflash)