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Merge branch 'feature/esp32c5_beta3_mmap' into 'master' 

cache / mmu: c5 support

Closes IDF-8646 and IDF-8658

See merge request espressif/esp-idf!29693
pull/13431/head
Armando (Dou Yiwen) 2024-03-18 18:05:36 +08:00
rodzic 30ab38c791 5efcd8979e
commit 9ffebf3cf2
3 zmienionych plików z 39 dodań i 97 usunięć
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96
components/hal/esp32c5/include/hal/cache_ll.h
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@ -9,12 +9,9 @@
#pragma once
#include <stdbool.h>
#include "sdkconfig.h" // TODO: remove
#include "soc/cache_reg.h"
#if CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
#include "soc/ext_mem_defs.h"
#include "rom/cache.h"
#endif
#include "hal/cache_types.h"
#include "hal/assert.h"
#include "esp32c5/rom/cache.h"
@ -49,7 +46,6 @@ extern "C" {
__attribute__((always_inline))
static inline bool cache_ll_is_cache_autoload_enabled(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
{
// TODO: [ESP32C5] IDF-8646 (inherit from C6)
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
bool enabled = false;
if (REG_GET_BIT(CACHE_L1_CACHE_AUTOLOAD_CTRL_REG, CACHE_L1_CACHE_AUTOLOAD_ENA)) {
@ -68,7 +64,6 @@ static inline bool cache_ll_is_cache_autoload_enabled(uint32_t cache_level, cach
__attribute__((always_inline))
static inline void cache_ll_disable_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
{
// TODO: [ESP32C5] IDF-8646 (inherit from C6)
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
(void) type;
Cache_Disable_ICache();
@ -90,7 +85,6 @@ static inline void cache_ll_disable_cache(uint32_t cache_level, cache_type_t typ
__attribute__((always_inline))
static inline void cache_ll_enable_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id, bool inst_autoload_en, bool data_autoload_en)
{
// TODO: [ESP32C5] IDF-8646 (inherit from C6)
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
Cache_Enable_ICache(inst_autoload_en ? CACHE_LL_L1_ICACHE_AUTOLOAD : 0);
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
@ -108,7 +102,6 @@ static inline void cache_ll_enable_cache(uint32_t cache_level, cache_type_t type
__attribute__((always_inline))
static inline void cache_ll_suspend_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
{
// TODO: [ESP32C5] IDF-8646 (inherit from C6)
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
Cache_Suspend_ICache();
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
@ -128,7 +121,6 @@ static inline void cache_ll_suspend_cache(uint32_t cache_level, cache_type_t typ
__attribute__((always_inline))
static inline void cache_ll_resume_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id, bool inst_autoload_en, bool data_autoload_en)
{
// TODO: [ESP32C5] IDF-8646 (inherit from C6)
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
Cache_Resume_ICache(inst_autoload_en ? CACHE_LL_L1_ICACHE_AUTOLOAD : 0);
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
@ -150,7 +142,6 @@ static inline void cache_ll_resume_cache(uint32_t cache_level, cache_type_t type
__attribute__((always_inline))
static inline void cache_ll_invalidate_addr(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size)
{
// TODO: [ESP32C5] IDF-8646 (inherit from C6)
Cache_Invalidate_Addr(vaddr, size);
}
@ -164,7 +155,6 @@ static inline void cache_ll_invalidate_addr(uint32_t cache_level, cache_type_t t
__attribute__((always_inline))
static inline void cache_ll_freeze_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
{
// TODO: [ESP32C5] IDF-8646 (inherit from C6)
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
Cache_Freeze_ICache_Enable(CACHE_FREEZE_ACK_BUSY);
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
@ -182,7 +172,6 @@ static inline void cache_ll_freeze_cache(uint32_t cache_level, cache_type_t type
__attribute__((always_inline))
static inline void cache_ll_unfreeze_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
{
// TODO: [ESP32C5] IDF-8646 (inherit from C6)
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
Cache_Freeze_ICache_Disable();
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
@ -202,7 +191,6 @@ static inline void cache_ll_unfreeze_cache(uint32_t cache_level, cache_type_t ty
__attribute__((always_inline))
static inline uint32_t cache_ll_get_line_size(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
{
// TODO: [ESP32C5] IDF-8646 (inherit from C6)
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
uint32_t size = 0;
size = Cache_Get_ICache_Line_Size();
@ -229,26 +217,24 @@ __attribute__((always_inline))
#endif
static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len)
{
// TODO: [ESP32C5] IDF-8646 (inherit from C6)
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
// HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
// cache_bus_mask_t mask = (cache_bus_mask_t)0;
// // uint32_t vaddr_end = vaddr_start + len - 1;
// if (vaddr_start >= SOC_IRAM0_CACHE_ADDRESS_LOW && vaddr_end < SOC_IRAM0_CACHE_ADDRESS_HIGH) {
// //c5 the I/D bus memory are shared, so we always return `CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0`
// mask = (cache_bus_mask_t)(mask | (CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0));
// } else {
// HAL_ASSERT(0); //Out of region
// }
// // return mask;
return (cache_bus_mask_t)0;
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
cache_bus_mask_t mask = (cache_bus_mask_t)0;
uint32_t vaddr_end = vaddr_start + len - 1;
if (vaddr_start >= SOC_IRAM0_CACHE_ADDRESS_LOW && vaddr_end < SOC_IRAM0_CACHE_ADDRESS_HIGH) {
//c5 the I/D bus memory are shared, so we always return `CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0`
mask = (cache_bus_mask_t)(mask | (CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0));
} else {
HAL_ASSERT(0); //Out of region
}
return mask;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
cache_bus_mask_t mask = (cache_bus_mask_t)0;
uint32_t vaddr_end = vaddr_start + len - 1;
if (vaddr_start >= SOC_IRAM0_CACHE_ADDRESS_LOW && vaddr_end < SOC_IRAM0_CACHE_ADDRESS_HIGH) {
//c6 the I/D bus memory are shared, so we always return `CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0`
//c5 the I/D bus memory are shared, so we always return `CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0`
mask = (cache_bus_mask_t)(mask | (CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0));
} else {
HAL_ASSERT(0); //Out of region
@ -269,17 +255,16 @@ __attribute__((always_inline))
#endif
static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask)
{
// TODO: [ESP32C5] IDF-8646 (inherit from C6)
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
// HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
// //On esp32c5, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
// HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
// // uint32_t ibus_mask = 0;
// ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? EXTMEM_L1_CACHE_SHUT_IBUS : 0);
// REG_CLR_BIT(EXTMEM_L1_CACHE_CTRL_REG, ibus_mask);
// // uint32_t dbus_mask = 0;
// dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? EXTMEM_L1_CACHE_SHUT_DBUS : 0);
// REG_CLR_BIT(EXTMEM_L1_CACHE_CTRL_REG, dbus_mask);
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
//On esp32c5, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
uint32_t ibus_mask = 0;
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? CACHE_L1_CACHE_SHUT_BUS0 : 0);
REG_CLR_BIT(CACHE_L1_CACHE_CTRL_REG, ibus_mask);
uint32_t dbus_mask = 0;
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? CACHE_L1_CACHE_SHUT_BUS1 : 0);
REG_CLR_BIT(CACHE_L1_CACHE_CTRL_REG, dbus_mask);
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
//On esp32c5, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
@ -304,18 +289,16 @@ static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t ma
__attribute__((always_inline))
static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask)
{
abort();
// TODO: [ESP32C5] IDF-8646 (inherit from C6)
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
// HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
// //On esp32c5, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
// HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
// // uint32_t ibus_mask = 0;
// ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? EXTMEM_L1_CACHE_SHUT_IBUS : 0);
// REG_SET_BIT(EXTMEM_L1_CACHE_CTRL_REG, ibus_mask);
// // uint32_t dbus_mask = 0;
// dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? EXTMEM_L1_CACHE_SHUT_DBUS : 0);
// REG_SET_BIT(EXTMEM_L1_CACHE_CTRL_REG, dbus_mask);
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
//On esp32c5, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
uint32_t ibus_mask = 0;
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? CACHE_L1_CACHE_SHUT_BUS0 : 0);
REG_SET_BIT(CACHE_L1_CACHE_CTRL_REG, ibus_mask);
uint32_t dbus_mask = 0;
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? CACHE_L1_CACHE_SHUT_BUS1 : 0);
REG_SET_BIT(CACHE_L1_CACHE_CTRL_REG, dbus_mask);
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
//On esp32c5, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
@ -344,19 +327,16 @@ static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t m
__attribute__((always_inline))
static inline bool cache_ll_vaddr_to_cache_level_id(uint32_t vaddr_start, uint32_t len, uint32_t *out_level, uint32_t *out_id)
{
abort();
// TODO: [ESP32C5] IDF-8646 (inherit from C6)
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
// bool valid = false;
// uint32_t vaddr_end = vaddr_start + len - 1;
// // valid |= (SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_end));
// valid |= (SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_end));
// // if (valid) {
// *out_level = 1;
// *out_id = 0;
// }
// // return valid;
return (bool)0;
bool valid = false;
uint32_t vaddr_end = vaddr_start + len - 1;
valid |= (SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_end));
valid |= (SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_end));
if (valid) {
*out_level = 1;
*out_id = 0;
}
return valid;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
bool valid = false;
uint32_t vaddr_end = vaddr_start + len - 1;

18
components/hal/esp32c5/include/hal/mmu_ll.h
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@ -33,7 +33,6 @@ extern "C" {
*/
static inline uint32_t mmu_ll_vaddr_to_laddr(uint32_t vaddr)
{
// TODO: [ESP32C5] IDF-8658 (inherit from C6)
return vaddr & SOC_MMU_LINEAR_ADDR_MASK;
}
@ -48,7 +47,6 @@ static inline uint32_t mmu_ll_vaddr_to_laddr(uint32_t vaddr)
*/
static inline uint32_t mmu_ll_laddr_to_vaddr(uint32_t laddr, mmu_vaddr_t vaddr_type, mmu_target_t target)
{
// TODO: [ESP32C5] IDF-8658 (inherit from C6)
(void)target;
(void)vaddr_type;
//On ESP32C5, I/D share the same vaddr range
@ -57,7 +55,6 @@ static inline uint32_t mmu_ll_laddr_to_vaddr(uint32_t laddr, mmu_vaddr_t vaddr_t
__attribute__((always_inline)) static inline bool mmu_ll_cache_encryption_enabled(void)
{
// TODO: [ESP32C5] IDF-8658 (inherit from C6)
#if SOC_EFUSE_SUPPORTED
unsigned cnt = efuse_ll_get_flash_crypt_cnt();
// 3 bits wide, any odd number - 1 or 3 - bits set means encryption is on
@ -78,7 +75,6 @@ __attribute__((always_inline)) static inline bool mmu_ll_cache_encryption_enable
__attribute__((always_inline))
static inline mmu_page_size_t mmu_ll_get_page_size(uint32_t mmu_id)
{
// TODO: [ESP32C5] IDF-8658 (inherit from C6)
(void)mmu_id;
uint32_t page_size_code = REG_GET_FIELD(SPI_MEM_MMU_POWER_CTRL_REG(0), SPI_MMU_PAGE_SIZE);
return (page_size_code == 0) ? MMU_PAGE_64KB :
@ -95,7 +91,6 @@ static inline mmu_page_size_t mmu_ll_get_page_size(uint32_t mmu_id)
__attribute__((always_inline))
static inline void mmu_ll_set_page_size(uint32_t mmu_id, uint32_t size)
{
// TODO: [ESP32C5] IDF-8658 (inherit from C6)
uint8_t reg_val = (size == MMU_PAGE_64KB) ? 0 :
(size == MMU_PAGE_32KB) ? 1 :
(size == MMU_PAGE_16KB) ? 2 :
@ -117,7 +112,6 @@ static inline void mmu_ll_set_page_size(uint32_t mmu_id, uint32_t size)
__attribute__((always_inline))
static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t vaddr_start, uint32_t len, mmu_vaddr_t type)
{
// TODO: [ESP32C5] IDF-8658 (inherit from C6)
(void)mmu_id;
(void)type;
uint32_t vaddr_end = vaddr_start + len - 1;
@ -136,7 +130,6 @@ static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t
*/
static inline bool mmu_ll_check_valid_paddr_region(uint32_t mmu_id, uint32_t paddr_start, uint32_t len)
{
// TODO: [ESP32C5] IDF-8658 (inherit from C6)
(void)mmu_id;
return (paddr_start < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)) &&
(len < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)) &&
@ -155,7 +148,6 @@ static inline bool mmu_ll_check_valid_paddr_region(uint32_t mmu_id, uint32_t pad
__attribute__((always_inline))
static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr)
{
// TODO: [ESP32C5] IDF-8658 (inherit from C6)
(void)mmu_id;
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
uint32_t shift_code = 0;
@ -191,7 +183,6 @@ static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr)
__attribute__((always_inline))
static inline uint32_t mmu_ll_format_paddr(uint32_t mmu_id, uint32_t paddr, mmu_target_t target)
{
// TODO: [ESP32C5] IDF-8658 (inherit from C6)
(void)mmu_id;
(void)target;
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
@ -225,7 +216,6 @@ static inline uint32_t mmu_ll_format_paddr(uint32_t mmu_id, uint32_t paddr, mmu_
*/
__attribute__((always_inline)) static inline void mmu_ll_write_entry(uint32_t mmu_id, uint32_t entry_id, uint32_t mmu_val, mmu_target_t target)
{
// TODO: [ESP32C5] IDF-8658 (inherit from C6)
(void)mmu_id;
(void)target;
uint32_t mmu_raw_value;
@ -247,7 +237,6 @@ __attribute__((always_inline)) static inline void mmu_ll_write_entry(uint32_t mm
*/
__attribute__((always_inline)) static inline uint32_t mmu_ll_read_entry(uint32_t mmu_id, uint32_t entry_id)
{
// TODO: [ESP32C5] IDF-8658 (inherit from C6)
(void)mmu_id;
uint32_t mmu_raw_value;
uint32_t ret;
@ -271,7 +260,6 @@ __attribute__((always_inline)) static inline uint32_t mmu_ll_read_entry(uint32_t
*/
__attribute__((always_inline)) static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id)
{
// TODO: [ESP32C5] IDF-8658 (inherit from C6)
(void)mmu_id;
REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
REG_WRITE(SPI_MEM_MMU_ITEM_CONTENT_REG(0), SOC_MMU_INVALID);
@ -285,7 +273,6 @@ __attribute__((always_inline)) static inline void mmu_ll_set_entry_invalid(uint3
__attribute__((always_inline))
static inline void mmu_ll_unmap_all(uint32_t mmu_id)
{
// TODO: [ESP32C5] IDF-8658 (inherit from C6)
for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) {
mmu_ll_set_entry_invalid(mmu_id, i);
}
@ -301,7 +288,6 @@ static inline void mmu_ll_unmap_all(uint32_t mmu_id)
*/
static inline bool mmu_ll_check_entry_valid(uint32_t mmu_id, uint32_t entry_id)
{
// TODO: [ESP32C5] IDF-8658 (inherit from C6)
(void)mmu_id;
HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
@ -319,7 +305,6 @@ static inline bool mmu_ll_check_entry_valid(uint32_t mmu_id, uint32_t entry_id)
*/
static inline mmu_target_t mmu_ll_get_entry_target(uint32_t mmu_id, uint32_t entry_id)
{
// TODO: [ESP32C5] IDF-8658 (inherit from C6)
(void)mmu_id;
return MMU_TARGET_FLASH0;
}
@ -334,7 +319,6 @@ static inline mmu_target_t mmu_ll_get_entry_target(uint32_t mmu_id, uint32_t ent
*/
static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t entry_id)
{
// TODO: [ESP32C5] IDF-8658 (inherit from C6)
(void)mmu_id;
HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
@ -374,7 +358,6 @@ static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t e
*/
static inline int mmu_ll_find_entry_id_based_on_map_value(uint32_t mmu_id, uint32_t mmu_val, mmu_target_t target)
{
// TODO: [ESP32C5] IDF-8658 (inherit from C6)
(void)mmu_id;
for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) {
if (mmu_ll_check_entry_valid(mmu_id, i)) {
@ -399,7 +382,6 @@ static inline int mmu_ll_find_entry_id_based_on_map_value(uint32_t mmu_id, uint3
*/
static inline uint32_t mmu_ll_entry_id_to_vaddr_base(uint32_t mmu_id, uint32_t entry_id, mmu_vaddr_t type)
{
// TODO: [ESP32C5] IDF-8658 (inherit from C6)
(void)mmu_id;
mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
uint32_t shift_code = 0;

22
components/soc/esp32c5/beta3/include/soc/ext_mem_defs.h
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -127,26 +127,6 @@ extern "C" {
_Static_assert(SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW == SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW, "IRAM0 and DRAM0 linear address should be same");
#endif
/**
* ROM flash mmap driver needs below definitions
*/
#define CACHE_IROM_MMU_START 0
#define CACHE_IROM_MMU_END Cache_Get_IROM_MMU_End()
#define CACHE_IROM_MMU_SIZE (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
#define CACHE_DROM_MMU_START CACHE_IROM_MMU_END
#define CACHE_DROM_MMU_END Cache_Get_DROM_MMU_End()
#define CACHE_DROM_MMU_SIZE (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START)
#define CACHE_DROM_MMU_MAX_END 0x400
#define ICACHE_MMU_SIZE 0x200
#define DCACHE_MMU_SIZE 0x200
#define MMU_BUS_START(i) 0
#define MMU_BUS_SIZE(i) 0x200
#ifdef __cplusplus
}
#endif