kopia lustrzana https://github.com/espressif/esp-idf
Merge branch 'feat/lp_i2s_ll_support' into 'master'
lp_i2s: added lp_i2s ll layer See merge request espressif/esp-idf!30158pull/13651/head
Armando (Dou Yiwen)
commit
9e9f76d88d
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@ -0,0 +1,460 @@
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/*
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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// The LL layer for LP I2S register operations
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/*******************************************************************************
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* NOTICE
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* The hal is not public api, don't use in application code.
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* See readme.md in hal/include/hal/readme.md
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******************************************************************************/
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#pragma once
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#include <stdbool.h>
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#include <math.h>
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#include "hal/misc.h"
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#include "hal/assert.h"
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#include "soc/lp_i2s_struct.h"
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#include "soc/lpperi_struct.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define I2S_LL_GET_HW(num) (((num) == 0)? (&LP_I2S) : NULL)
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#define LP_I2S_LL_EVENT_RX_DONE_INT (1<<0)
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#define LP_I2S_LL_EVENT_RX_HUNG_INT_INT (1<<1)
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#define LP_I2S_LL_EVENT_RX_FIFOMEM_UDF_INT (1<<2)
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#define LP_I2S_LL_EVENT_RX_MEM_THRESHOLD_INT (1<<5)
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#define LP_I2S_LL_TDM_CH_MASK (0x03UL)
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/**
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* @brief LP I2S rx stop mode enum type
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*/
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typedef enum {
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LP_I2S_LL_RX_STOP_MODE_START_CLEAR,
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LP_I2S_LL_RX_STOP_MODE_START_CLEAR_EOF_NUM,
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} lp_i2s_ll_rx_stop_mode_t;
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/**
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* @brief LP I2S rx polarity mode enum type
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*/
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typedef enum {
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LP_I2S_LL_RX_WS_POL_NEGATIVE,
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LP_I2S_LL_RX_WS_POL_POSITIVE,
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} lp_i2s_ll_rx_ws_pol_t;
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/**
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* @brief LP I2S rx bit order enum type
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*/
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typedef enum {
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LP_I2S_LL_RX_BIT_ORDER_BIG_ENDIAN,
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LP_I2S_LL_RX_BIT_ORDER_SMALL_ENDIAN,
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} lp_i2s_ll_rx_bit_order_t;
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/**
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* @brief LP I2S rx align enum type
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*/
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typedef enum {
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LP_I2S_LL_RX_RIGHT_ALIGN,
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LP_I2S_LL_RX_LEFT_ALIGN,
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} lp_i2s_ll_rx_alignment_t;
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/**
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* @brief LP I2S rx endian enum type
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*/
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typedef enum {
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LP_I2S_LL_RX_SMALL_ENDIAN,
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LP_I2S_LL_RX_BIG_ENDIAN,
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} lp_i2s_ll_rx_endian_t;
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/*---------------------------------------------------------------
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Clock
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---------------------------------------------------------------*/
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/**
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* @brief Enable the bus clock for LP I2S module
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*
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* @param id Instance id
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* @param en enable / disable
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*/
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static inline void lp_i2s_ll_enable_module_clock(int id, bool en)
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{
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LPPERI.clk_en.ck_en_lp_i2s = en;
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}
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/// use a macro to wrap the function, force the caller to use it in a critical section
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/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
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#define lp_i2s_ll_enable_module_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; lp_i2s_ll_enable_module_clock(__VA_ARGS__)
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/**
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* @brief Reset the LP I2S module
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*
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* @param hw Hardware instance address
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*/
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static inline void lp_i2s_ll_reset_module_clock(int id)
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{
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LPPERI.reset_en.rst_en_lp_i2s = 1;
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LPPERI.reset_en.rst_en_lp_i2s = 0;
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}
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/// use a macro to wrap the function, force the caller to use it in a critical section
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/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
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#define lp_i2s_ll_reset_module_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; lp_i2s_ll_reset_module_clock(__VA_ARGS__)
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/**
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* @brief Enable the bus clock for LP I2S RX module
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*
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* @param id Instance id
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* @param en enable / disable
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*/
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static inline void lp_i2s_ll_enable_rx_module_clock(int id, bool en)
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{
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LPPERI.clk_en.ck_en_lp_i2s_rx = en;
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}
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/// use a macro to wrap the function, force the caller to use it in a critical section
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/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
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#define lp_i2s_ll_enable_rx_module_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; lp_i2s_ll_enable_rx_module_clock(__VA_ARGS__)
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/**
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* @brief Set LP I2S clock source div num
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*
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* @note f_LP_I2S_CLK_S / (N + b / a) = f_LP_I2S_RX_CLK
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*
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* @param id Instance id
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* @param val value to set div num
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*/
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static inline void lp_i2s_ll_clk_source_div_num(int id, uint32_t val)
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{
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if (val == 256) {
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HAL_FORCE_MODIFY_U32_REG_FIELD(LPPERI.lp_i2s_rxclk_div_num, lp_i2s_rx_clkm_div_num, 0);
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} else if (val == 2) {
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HAL_FORCE_MODIFY_U32_REG_FIELD(LPPERI.lp_i2s_rxclk_div_num, lp_i2s_rx_clkm_div_num, 1);
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} else {
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HAL_FORCE_MODIFY_U32_REG_FIELD(LPPERI.lp_i2s_rxclk_div_num, lp_i2s_rx_clkm_div_num, val);
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}
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}
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/**
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* @brief Set LP I2S rx raw clock division
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*
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* @param id Instance id
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* @param a div a
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* @param b div b
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*/
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static inline void i2s_ll_tx_set_raw_clk_div(int id, uint32_t a, uint32_t b)
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{
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if (b <= a / 2) {
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LPPERI.lp_i2s_rxclk_div_xyz.lp_i2s_rx_clkm_div_yn1 = 0;
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LPPERI.lp_i2s_rxclk_div_xyz.lp_i2s_rx_clkm_div_x = floor(a / b) - 1;
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LPPERI.lp_i2s_rxclk_div_xyz.lp_i2s_rx_clkm_div_y = a % b;
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LPPERI.lp_i2s_rxclk_div_xyz.lp_i2s_rx_clkm_div_z = b;
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} else {
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LPPERI.lp_i2s_rxclk_div_xyz.lp_i2s_rx_clkm_div_yn1 = 1;
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LPPERI.lp_i2s_rxclk_div_xyz.lp_i2s_rx_clkm_div_x = floor(a / (a - b)) - 1;
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LPPERI.lp_i2s_rxclk_div_xyz.lp_i2s_rx_clkm_div_y = a % (a - b);
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LPPERI.lp_i2s_rxclk_div_xyz.lp_i2s_rx_clkm_div_z = a - b;
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}
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if (a == 0 && b == 0) {
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LPPERI.lp_i2s_rxclk_div_xyz.lp_i2s_rx_clkm_div_x = 0;
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LPPERI.lp_i2s_rxclk_div_xyz.lp_i2s_rx_clkm_div_z = 0;
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LPPERI.lp_i2s_rxclk_div_xyz.lp_i2s_rx_clkm_div_y = 1;
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}
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}
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/**
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* @brief Set LP I2S rx bck div num
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*
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* @param id Instance id
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* @param val value to set rx bck div num
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*/
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static inline void lp_i2s_ll_rx_set_bck_div_num(lp_i2s_dev_t *hw, uint32_t val)
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{
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hw->rx_conf1.rx_bck_div_num = val - 1;
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}
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/*---------------------------------------------------------------
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Reset
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---------------------------------------------------------------*/
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/**
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* @brief Reset LP I2S RX module
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*
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* @param id Instance id
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*/
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static inline void lp_i2s_ll_rx_reset(lp_i2s_dev_t *hw)
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{
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hw->rx_conf.rx_reset = 1;
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hw->rx_conf.rx_reset = 0;
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}
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/**
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* @brief Reset LP I2S RX FIFO
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*
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* @param id Instance id
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*/
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static inline void lp_i2s_ll_rx_reset_fifo(lp_i2s_dev_t *hw)
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{
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hw->rx_conf.rx_fifo_reset = 1;
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hw->rx_conf.rx_fifo_reset = 0;
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}
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/*---------------------------------------------------------------
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Master/Slave
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---------------------------------------------------------------*/
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/**
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* @brief Start LP I2S RX
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*
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* @param id Instance id
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*/
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static inline void lp_i2s_ll_rx_start(lp_i2s_dev_t *hw)
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{
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hw->rx_conf.rx_update = 1;
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while (hw->rx_conf.rx_update);
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hw->rx_conf.rx_start = 1;
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}
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/**
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* @brief Set LP I2S RX stop mode
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*
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* @param id Instance id
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*/
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static inline void lp_i2s_ll_set_rx_stop_mode(lp_i2s_dev_t *hw, lp_i2s_ll_rx_stop_mode_t rx_stop_mode)
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{
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hw->rx_conf.rx_stop_mode = rx_stop_mode;
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}
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/**
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* @brief Configure the received length to trigger in_suc_eof interrupt
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*
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* @param id Instance id
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* @param eof_num the byte length to trigger in_suc_eof interrupt
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*/
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static inline void lp_i2s_ll_rx_set_eof_num(lp_i2s_dev_t *hw, int eof_num)
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{
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hw->rxeof_num.rx_eof_num = eof_num;
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}
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/**
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* @brief Stop LP I2S RX
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*
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* @param id Instance id
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*/
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static inline void lp_i2s_ll_rx_stop(lp_i2s_dev_t *hw)
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{
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hw->rx_conf.rx_start = 0;
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}
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/*---------------------------------------------------------------
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Receive
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---------------------------------------------------------------*/
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/*--------------------------------------------------
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TDM
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--------------------------------------------------*/
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/**
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* @brief Enable LP I2S RX TDM mode
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*
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* @param hw LP I2S hardware instance
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*/
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static inline void lp_i2s_ll_rx_enable_tdm(lp_i2s_dev_t *hw)
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{
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hw->rx_conf.rx_pdm_en = false;
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hw->rx_conf.rx_tdm_en = true;
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}
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/**
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* @brief Configure RX total chan number under TDM mode
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*
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* @param hw LP I2S hardware instance
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* @param total_num Total chan number
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*/
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static inline void lp_i2s_ll_rx_set_tdm_chan_num(lp_i2s_dev_t *hw, int total_num)
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{
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hw->rx_tdm_ctrl.rx_tdm_tot_chan_num = total_num - 1;
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}
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/*--------------------------------------------------
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PDM
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--------------------------------------------------*/
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/**
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* @brief Enable LP RX PDM mode.
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*
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* @param hw LP I2S hardware instance
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*/
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static inline void lp_i2s_ll_rx_enable_pdm(lp_i2s_dev_t *hw)
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{
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hw->rx_conf.rx_pdm_en = 1;
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hw->rx_conf.rx_tdm_en = 0;
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}
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/*---------------------------------------------------------------
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General
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---------------------------------------------------------------*/
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/**
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* @brief Configure LP I2S rx channel bits and bits mode
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*/
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static inline void i2s_ll_rx_set_sample_bit(lp_i2s_dev_t *hw, int chan_bits, int bits_mode)
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{
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hw->rx_conf1.rx_tdm_chan_bits = chan_bits - 1;
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hw->rx_conf1.rx_bits_mod = bits_mode - 1;
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}
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/**
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* @brief Set LP I2S rx ws polarity
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*
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* @param hw LP I2S hardware instance
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* @param pol ws polarity
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*/
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static inline void lp_i2s_ll_rx_set_ws_pol(lp_i2s_dev_t *hw, lp_i2s_ll_rx_ws_pol_t pol)
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{
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hw->rx_conf.rx_ws_idle_pol = pol;
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}
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/**
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* @brief Set LP I2S rx ws width
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*
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* @param hw LP I2S hardware instance
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* @param width ws width
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*/
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static inline void lp_i2s_ll_rx_set_ws_width(lp_i2s_dev_t *hw, int width)
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{
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hw->rx_conf1.rx_tdm_ws_width = width - 1;
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}
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/**
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* @brief Set LP I2S rx half sample bits
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*
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* @param hw LP I2S hardware instance
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* @param half_sample_bits Half sample bits
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*/
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static inline void lp_i2s_ll_rx_set_half_sample_bits(lp_i2s_dev_t *hw, int half_sample_bits)
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{
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hw->rx_conf1.rx_half_sample_bits = half_sample_bits - 1;
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}
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/**
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* @brief Enable LP I2S RX set active channul
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*
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* @param hw LP I2S hardware instance
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* @param chanid channel id
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* @param enable enable or disable
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*/
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static inline void lp_i2s_ll_rx_set_active_chan(lp_i2s_dev_t *hw, uint32_t chan_mask)
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{
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uint32_t tdm_ctrl = hw->rx_tdm_ctrl.val;
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tdm_ctrl &= ~LP_I2S_LL_TDM_CH_MASK;
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tdm_ctrl |= (chan_mask & LP_I2S_LL_TDM_CH_MASK);
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hw->rx_tdm_ctrl.val = tdm_ctrl;
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}
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/**
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* @brief Set LP I2S rx pdm2pcm enable
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*
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* @param hw LP I2S hardware instance
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* @param en enable or disable
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*/
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static inline void lp_i2s_ll_rx_set_pdm2pcm_en(lp_i2s_dev_t *hw, bool en)
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{
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hw->rx_pdm_conf.rx_pdm2pcm_en = en;
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}
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/**
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* @brief Set LP I2S rx bit order
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*
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* @param hw LP I2S hardware instance
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* @param bit_order bit order
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*/
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static inline void lp_i2s_ll_rx_set_bit_order(lp_i2s_dev_t *hw, lp_i2s_ll_rx_bit_order_t bit_order)
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{
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hw->rx_conf.rx_bit_order = bit_order;
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}
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/**
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* @brief Enable LP I2S 24 fill
|
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*
|
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* @param hw LP I2S hardware instance
|
||||
* @param en enable or disable
|
||||
*/
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static inline void lp_i2s_ll_rx_enable_24_fill(lp_i2s_dev_t *hw, bool en)
|
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{
|
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hw->rx_conf.rx_24_fill_en = en;
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}
|
||||
|
||||
/**
|
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* @brief Set LP I2S rx alignment mode
|
||||
*
|
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* @param hw LP I2S hardware instance
|
||||
* @param align align
|
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*/
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static inline void lp_i2s_ll_rx_set_alignment_mode(lp_i2s_dev_t *hw, lp_i2s_ll_rx_alignment_t align)
|
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{
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hw->rx_conf.rx_left_align = align;
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}
|
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|
||||
/**
|
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* @brief Set LP I2S rx endian
|
||||
*
|
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* @param hw LP I2S hardware instance
|
||||
* @param endian endian
|
||||
*/
|
||||
static inline void lp_i2s_ll_rx_set_endian(lp_i2s_dev_t *hw, lp_i2s_ll_rx_endian_t endian)
|
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{
|
||||
hw->rx_conf.rx_big_endian = endian;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
Interrupt
|
||||
---------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief Get LP I2S RX interrupt status word
|
||||
*
|
||||
* @param hw LP I2S hardware instance
|
||||
* @param raw raw or status
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t lp_i2s_ll_rx_get_interrupt_status(lp_i2s_dev_t *hw, bool raw)
|
||||
{
|
||||
if (raw) {
|
||||
return hw->int_raw.val;
|
||||
} else {
|
||||
return hw->int_st.val;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable LP I2S RX channel interrupt
|
||||
*
|
||||
* @param hw LP I2S hardware instance
|
||||
* @param mask mask
|
||||
* @param enable enable or disable
|
||||
*/
|
||||
static inline void lp_i2s_ll_rx_enable_interrupt(lp_i2s_dev_t *hw, uint32_t mask, bool enable)
|
||||
{
|
||||
uint32_t int_ena = hw->int_ena.val;
|
||||
if (enable) {
|
||||
int_ena |= mask;
|
||||
} else {
|
||||
int_ena &= ~mask;
|
||||
}
|
||||
hw->int_ena.val = int_ena;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear LP I2S RX channel interrupt
|
||||
*
|
||||
* @param hw LP I2S hardware instance
|
||||
* @param mask mask
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void lp_i2s_ll_rx_clear_interrupt_status(lp_i2s_dev_t *hw, uint32_t mask)
|
||||
{
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||||
hw->int_clr.val = mask;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -21,7 +21,7 @@ extern "C" {
|
|||
*
|
||||
* 2) External 40MHz Crystal Clock: XTAL
|
||||
*
|
||||
* 3) Internal 136kHz RC Oscillator: RC_SLOW (may also referrred as SOSC in TRM or reg. description)
|
||||
* 3) Internal 136kHz RC Oscillator: RC_SLOW (may also referred as SOSC in TRM or reg. description)
|
||||
*
|
||||
* This RC oscillator generates a ~136kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock
|
||||
* can be computed in runtime through calibration.
|
||||
|
|
@ -342,6 +342,20 @@ typedef enum {
|
|||
I2S_CLK_SRC_EXTERNAL = -1, /*!< Select external clock as source clock */
|
||||
} soc_periph_i2s_clk_src_t;
|
||||
|
||||
/**
|
||||
* @brief Array initializer for all supported clock sources of LP I2S
|
||||
*/
|
||||
#define SOC_LP_I2S_CLKS {SOC_MOD_CLK_LP_PERI, SOC_MOD_CLK_XTAL_D2}
|
||||
|
||||
/**
|
||||
* @brief LP I2S clock source enum
|
||||
*/
|
||||
typedef enum {
|
||||
LP_I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_LP_PERI, /*!< Select LP_PERI as the default source clock */
|
||||
LP_I2S_CLK_SRC_LP_PERI = SOC_MOD_CLK_LP_PERI, /*!< Select LP_PERI as the source clock */
|
||||
LP_I2S_CLK_SRC_XTAL_D2 = SOC_MOD_CLK_XTAL_D2, /*!< LP_I2S source clock is XTAL_D2 */
|
||||
} soc_periph_lp_i2s_clk_src_t;
|
||||
|
||||
//////////////////////////////////////////////////LCD///////////////////////////////////////////////////////////////////
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -938,6 +938,7 @@ typedef struct {
|
|||
volatile lp_i2s_date_reg_t date;
|
||||
} lp_i2s_dev_t;
|
||||
|
||||
extern lp_i2s_dev_t LP_I2S;
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(lp_i2s_dev_t) == 0x100, "Invalid size of lp_i2s_dev_t structure");
|
||||
|
|
|
|||
Ładowanie…
Reference in New Issue