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feat(hal/sha): use RCC atomic block to enable/reset the SHA peripheral

pull/13550/head
harshal.patil 2024-03-08 00:40:26 +05:30
rodzic 211a2a5477
commit 9cd10e196b
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ID klucza GPG: 5B5EC97C35B9A2E5
18 zmienionych plików z 375 dodań i 55 usunięć
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19
components/esp_hw_support/esp_ds.c
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@ -29,6 +29,7 @@
#include "hal/ds_ll.h"
#include "hal/hmac_hal.h"
#include "hal/hmac_ll.h"
#include "hal/sha_ll.h"
#endif /* !CONFIG_IDF_TARGET_ESP32S2 */
#if CONFIG_IDF_TARGET_ESP32S2
@ -270,7 +271,10 @@ static void ds_acquire_enable(void)
hmac_ll_reset_register();
}
periph_module_enable(PERIPH_SHA_MODULE);
SHA_RCC_ATOMIC() {
sha_ll_enable_bus_clock(true);
sha_ll_reset_register();
}
DS_RCC_ATOMIC() {
ds_ll_enable_bus_clock(true);
@ -288,7 +292,9 @@ static void ds_disable_release(void)
ds_ll_enable_bus_clock(false);
}
periph_module_disable(PERIPH_SHA_MODULE);
SHA_RCC_ATOMIC() {
sha_ll_enable_bus_clock(false);
}
HMAC_RCC_ATOMIC() {
hmac_ll_enable_bus_clock(false);
@ -445,7 +451,10 @@ esp_err_t esp_ds_encrypt_params(esp_ds_data_t *data,
aes_ll_reset_register();
}
periph_module_enable(PERIPH_SHA_MODULE);
SHA_RCC_ATOMIC() {
sha_ll_enable_bus_clock(true);
sha_ll_reset_register();
}
ets_ds_data_t *ds_data = (ets_ds_data_t *) data;
const ets_ds_p_data_t *ds_plain_data = (const ets_ds_p_data_t *) p_data;
@ -456,7 +465,9 @@ esp_err_t esp_ds_encrypt_params(esp_ds_data_t *data,
result = ESP_ERR_INVALID_ARG;
}
periph_module_disable(PERIPH_SHA_MODULE);
SHA_RCC_ATOMIC() {
sha_ll_enable_bus_clock(false);
}
AES_RCC_ATOMIC() {
aes_ll_enable_bus_clock(false);

10
components/esp_hw_support/esp_hmac.c
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@ -21,6 +21,7 @@
#include "hal/ds_ll.h"
#include "hal/hmac_hal.h"
#include "hal/hmac_ll.h"
#include "hal/sha_ll.h"
#include "esp_private/periph_ctrl.h"
#endif
@ -75,7 +76,10 @@ esp_err_t esp_hmac_calculate(hmac_key_id_t key_id,
hmac_ll_reset_register();
}
periph_module_enable(PERIPH_SHA_MODULE);
SHA_RCC_ATOMIC() {
sha_ll_enable_bus_clock(true);
sha_ll_reset_register();
}
DS_RCC_ATOMIC() {
ds_ll_enable_bus_clock(true);
@ -146,7 +150,9 @@ esp_err_t esp_hmac_calculate(hmac_key_id_t key_id,
ds_ll_enable_bus_clock(false);
}
periph_module_disable(PERIPH_SHA_MODULE);
SHA_RCC_ATOMIC() {
sha_ll_enable_bus_clock(false);
}
HMAC_RCC_ATOMIC() {
hmac_ll_enable_bus_clock(false);

2
components/esp_hw_support/include/esp_private/esp_crypto_lock_internal.h
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@ -20,6 +20,7 @@ extern "C" {
#define DS_RCC_ATOMIC()
#define ECDSA_RCC_ATOMIC()
#define AES_RCC_ATOMIC()
#define SHA_RCC_ATOMIC()
#else /* !SOC_RCC_IS_INDEPENDENT */
#define MPI_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
#define ECC_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
@ -27,6 +28,7 @@ extern "C" {
#define DS_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
#define ECDSA_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
#define AES_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
#define SHA_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
#endif /* SOC_RCC_IS_INDEPENDENT */
#ifdef __cplusplus

37
components/hal/esp32/include/hal/sha_ll.h
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -7,6 +7,7 @@
#include <stdbool.h>
#include "hal/sha_types.h"
#include "soc/dport_reg.h"
#include "soc/hwcrypto_reg.h"
#include "soc/dport_access.h"
#include "hal/misc.h"
@ -17,6 +18,40 @@ extern "C" {
#define SHA_LL_TYPE_OFFSET 0x10
/**
* @brief Enable the bus clock for SHA peripheral module
*
* @param enable true to enable the module, false to disable the module
*/
static inline void sha_ll_enable_bus_clock(bool enable)
{
if (enable) {
DPORT_SET_PERI_REG_MASK(DPORT_PERI_CLK_EN_REG, DPORT_PERI_EN_SHA);
} else {
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERI_CLK_EN_REG, DPORT_PERI_EN_SHA);
}
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define sha_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; sha_ll_enable_bus_clock(__VA_ARGS__)
/**
* @brief Reset the SHA peripheral module
*/
static inline void sha_ll_reset_register(void)
{
DPORT_SET_PERI_REG_MASK(DPORT_PERI_RST_EN_REG, DPORT_PERI_EN_SHA);
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERI_RST_EN_REG, DPORT_PERI_EN_SHA);
// Clear reset on secure boot also, otherwise SHA is held in reset
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERI_RST_EN_REG, DPORT_PERI_EN_SECUREBOOT);
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define sha_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; sha_ll_reset_register(__VA_ARGS__)
/**
* @brief Returns the LOAD_REG register address for the given sha type
*

30
components/hal/esp32c2/include/hal/sha_ll.h
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -7,6 +7,7 @@
#include <stdbool.h>
#include "soc/hwcrypto_reg.h"
#include "soc/system_struct.h"
#include "hal/sha_types.h"
#ifdef __cplusplus
@ -14,6 +15,33 @@ extern "C" {
#endif
/**
* @brief Enable the bus clock for SHA peripheral module
*
* @param enable true to enable the module, false to disable the module
*/
static inline void sha_ll_enable_bus_clock(bool enable)
{
SYSTEM.perip_clk_en1.crypto_sha_clk_en = enable;
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define sha_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; sha_ll_enable_bus_clock(__VA_ARGS__)
/**
* @brief Reset the SHA peripheral module
*/
static inline void sha_ll_reset_register(void)
{
SYSTEM.perip_rst_en1.crypto_sha_rst = 1;
SYSTEM.perip_rst_en1.crypto_sha_rst = 0;
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define sha_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; sha_ll_reset_register(__VA_ARGS__)
/**
* @brief Start a new SHA block conversions (no initial hash in HW)
*

33
components/hal/esp32c3/include/hal/sha_ll.h
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -7,12 +7,43 @@
#include <stdbool.h>
#include "soc/hwcrypto_reg.h"
#include "soc/system_struct.h"
#include "hal/sha_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Enable the bus clock for SHA peripheral module
*
* @param enable true to enable the module, false to disable the module
*/
static inline void sha_ll_enable_bus_clock(bool enable)
{
SYSTEM.perip_clk_en1.reg_crypto_sha_clk_en = enable;
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define sha_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; sha_ll_enable_bus_clock(__VA_ARGS__)
/**
* @brief Reset the SHA peripheral module
*/
static inline void sha_ll_reset_register(void)
{
SYSTEM.perip_rst_en1.reg_crypto_sha_rst = 1;
SYSTEM.perip_rst_en1.reg_crypto_sha_rst = 0;
// Clear reset on digital signature and hmac also, otherwise SHA is held in reset
SYSTEM.perip_rst_en1.reg_crypto_ds_rst = 0;
SYSTEM.perip_rst_en1.reg_crypto_hmac_rst = 0;
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define sha_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; sha_ll_reset_register(__VA_ARGS__)
/**
* @brief Start a new SHA block conversions (no initial hash in HW)

25
components/hal/esp32c6/include/hal/sha_ll.h
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -7,12 +7,35 @@
#include <stdbool.h>
#include "soc/hwcrypto_reg.h"
#include "soc/pcr_struct.h"
#include "hal/sha_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Enable the bus clock for SHA peripheral module
*
* @param enable true to enable the module, false to disable the module
*/
static inline void sha_ll_enable_bus_clock(bool enable)
{
PCR.sha_conf.sha_clk_en = enable;
}
/**
* @brief Reset the SHA peripheral module
*/
static inline void sha_ll_reset_register(void)
{
PCR.sha_conf.sha_rst_en = 1;
PCR.sha_conf.sha_rst_en = 0;
// Clear reset on digital signature and hmac also, otherwise SHA is held in reset
PCR.ds_conf.ds_rst_en = 0;
PCR.hmac_conf.hmac_rst_en = 0;
}
/**
* @brief Start a new SHA block conversions (no initial hash in HW)

26
components/hal/esp32h2/include/hal/sha_ll.h
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -7,12 +7,36 @@
#include <stdbool.h>
#include "soc/hwcrypto_reg.h"
#include "soc/pcr_struct.h"
#include "hal/sha_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Enable the bus clock for SHA peripheral module
*
* @param enable true to enable the module, false to disable the module
*/
static inline void sha_ll_enable_bus_clock(bool enable)
{
PCR.sha_conf.sha_clk_en = enable;
}
/**
* @brief Reset the SHA peripheral module
*/
static inline void sha_ll_reset_register(void)
{
PCR.sha_conf.sha_rst_en = 1;
PCR.sha_conf.sha_rst_en = 0;
// Clear reset on digital signature, hmac and ecdsa also, otherwise SHA is held in reset
PCR.ds_conf.ds_rst_en = 0;
PCR.hmac_conf.hmac_rst_en = 0;
PCR.ecdsa_conf.ecdsa_rst_en = 0;
}
/**
* @brief Start a new SHA block conversions (no initial hash in HW)

36
components/hal/esp32p4/include/hal/sha_ll.h
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@ -1,18 +1,50 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdbool.h>
#include "soc/hwcrypto_reg.h"
#include "hal/sha_types.h"
#include "soc/hp_sys_clkrst_struct.h"
#include "soc/hwcrypto_reg.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Enable the bus clock for SHA peripheral module
*
* @param enable true to enable the module, false to disable the module
*/
static inline void sha_ll_enable_bus_clock(bool enable)
{
HP_SYS_CLKRST.peri_clk_ctrl25.reg_crypto_sha_clk_en = enable;
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define sha_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; sha_ll_enable_bus_clock(__VA_ARGS__)
/**
* @brief Reset the SHA peripheral module
*/
static inline void sha_ll_reset_register(void)
{
HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_sha = 1;
HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_sha = 0;
// Clear reset on digital signature, hmac and ecdsa, otherwise SHA is held in reset
HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_ds = 0;
HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_hmac = 0;
HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_ecdsa = 0;
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define sha_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; sha_ll_reset_register(__VA_ARGS__)
/**
* @brief Start a new SHA block conversions (no initial hash in HW)

36
components/hal/esp32s2/include/hal/sha_ll.h
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -14,6 +14,40 @@
extern "C" {
#endif
/**
* @brief Enable the bus clock for SHA peripheral module
*
* @param enable true to enable the module, false to disable the module
*/
static inline void sha_ll_enable_bus_clock(bool enable)
{
if (enable) {
SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN1_REG, DPORT_CRYPTO_SHA_CLK_EN);
} else {
CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN1_REG, DPORT_CRYPTO_SHA_CLK_EN);
}
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define sha_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; sha_ll_enable_bus_clock(__VA_ARGS__)
/**
* @brief Reset the SHA peripheral module
*/
static inline void sha_ll_reset_register(void)
{
SET_PERI_REG_MASK(DPORT_PERIP_RST_EN1_REG, DPORT_CRYPTO_SHA_RST);
CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN1_REG, DPORT_CRYPTO_SHA_RST);
// Clear reset on digital signature and hmac also, otherwise SHA is held in reset
CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN1_REG, DPORT_CRYPTO_DS_RST);
CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN1_REG, DPORT_CRYPTO_HMAC_RST);
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define sha_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; sha_ll_reset_register(__VA_ARGS__)
/**
* @brief Start a new SHA block conversions (no initial hash in HW)

37
components/hal/esp32s3/include/hal/sha_ll.h
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@ -1,19 +1,50 @@
/*
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdbool.h>
#include "soc/hwcrypto_reg.h"
#include "hal/sha_types.h"
#include "soc/dport_reg.h"
#include "soc/hwcrypto_reg.h"
#include "soc/system_struct.h"
#include "hal/sha_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Enable the bus clock for SHA peripheral module
*
* @param enable true to enable the module, false to disable the module
*/
static inline void sha_ll_enable_bus_clock(bool enable)
{
SYSTEM.perip_clk_en1.crypto_sha_clk_en = enable;
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define sha_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; sha_ll_enable_bus_clock(__VA_ARGS__)
/**
* @brief Reset the SHA peripheral module
*/
static inline void sha_ll_reset_register(void)
{
SYSTEM.perip_rst_en1.crypto_sha_rst = 1;
SYSTEM.perip_rst_en1.crypto_sha_rst = 0;
// Clear reset on digital signature and hmac also, otherwise SHA is held in reset
SYSTEM.perip_rst_en1.crypto_ds_rst = 0;
SYSTEM.perip_rst_en1.crypto_hmac_rst = 0;
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define sha_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; sha_ll_reset_register(__VA_ARGS__)
/**
* @brief Start a new SHA block conversions (no initial hash in HW)

19
components/hal/test_apps/crypto/main/ds/test_ds.c
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@ -119,6 +119,7 @@ _Static_assert(NUM_RESULTS == NUM_MESSAGES, "expected_results size should be the
#include "hal/ds_ll.h"
#include "hal/hmac_hal.h"
#include "hal/hmac_ll.h"
#include "hal/sha_ll.h"
static void ds_acquire_enable(void)
@ -128,7 +129,10 @@ static void ds_acquire_enable(void)
hmac_ll_reset_register();
}
periph_module_enable(PERIPH_SHA_MODULE);
SHA_RCC_ATOMIC() {
sha_ll_enable_bus_clock(true);
sha_ll_reset_register();
}
DS_RCC_ATOMIC() {
ds_ll_enable_bus_clock(true);
@ -146,7 +150,9 @@ static void ds_disable_release(void)
ds_ll_enable_bus_clock(false);
}
periph_module_disable(PERIPH_SHA_MODULE);
SHA_RCC_ATOMIC() {
sha_ll_enable_bus_clock(false);
}
HMAC_RCC_ATOMIC() {
hmac_ll_enable_bus_clock(false);
@ -234,7 +240,10 @@ static esp_err_t esp_ds_encrypt_params(esp_ds_data_t *data,
aes_ll_reset_register();
}
periph_module_enable(PERIPH_SHA_MODULE);
SHA_RCC_ATOMIC() {
sha_ll_enable_bus_clock(true);
sha_ll_reset_register();
}
ets_ds_data_t *ds_data = (ets_ds_data_t *) data;
const ets_ds_p_data_t *ds_plain_data = (const ets_ds_p_data_t *) p_data;
@ -245,7 +254,9 @@ static esp_err_t esp_ds_encrypt_params(esp_ds_data_t *data,
result = ESP_ERR_INVALID_ARG;
}
periph_module_disable(PERIPH_SHA_MODULE);
SHA_RCC_ATOMIC() {
sha_ll_enable_bus_clock(false);
}
AES_RCC_ATOMIC() {
aes_ll_enable_bus_clock(false);

12
components/hal/test_apps/crypto/main/hmac/test_hmac.c
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -33,6 +33,7 @@ static esp_err_t hmac_jtag_disable(void)
#include "hal/hmac_hal.h"
#include "hal/hmac_ll.h"
#include "hal/ds_ll.h"
#include "hal/sha_ll.h"
#include "esp_private/periph_ctrl.h"
#define SHA256_BLOCK_SZ 64
@ -69,7 +70,10 @@ static esp_err_t hmac_calculate(uint32_t key_id, const void *message, size_t mes
hmac_ll_reset_register();
}
periph_module_enable(PERIPH_SHA_MODULE);
SHA_RCC_ATOMIC() {
sha_ll_enable_bus_clock(true);
sha_ll_reset_register();
}
DS_RCC_ATOMIC() {
ds_ll_enable_bus_clock(true);
@ -130,7 +134,9 @@ static esp_err_t hmac_calculate(uint32_t key_id, const void *message, size_t mes
ds_ll_enable_bus_clock(false);
}
periph_module_disable(PERIPH_SHA_MODULE);
SHA_RCC_ATOMIC() {
sha_ll_enable_bus_clock(false);
}
HMAC_RCC_ATOMIC() {
hmac_ll_enable_bus_clock(false);

32
components/hal/test_apps/crypto/main/sha/sha_block.c
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: CC0-1.0
*/
@ -12,8 +12,9 @@
#include "soc/periph_defs.h"
#include "esp_private/periph_ctrl.h"
#include "esp_private/esp_crypto_lock_internal.h"
#include "hal/sha_hal.h"
#include "hal/clk_gate_ll.h"
#include "hal/sha_ll.h"
#include "sha_block.h"
#if defined(SOC_SHA_SUPPORT_SHA1)
@ -43,7 +44,10 @@ static void sha1_update_block(sha1_ctx* ctx, esp_sha_type sha_type, const unsign
if ( (ilen >= 64) || local_len) {
/* Enable peripheral module */
periph_ll_enable_clk_clear_rst(PERIPH_SHA_MODULE);
SHA_RCC_ATOMIC() {
sha_ll_enable_bus_clock(true);
sha_ll_reset_register();
}
if (ctx->first_block == 0) {
/* Writes the message digest to the SHA engine */
@ -72,7 +76,9 @@ static void sha1_update_block(sha1_ctx* ctx, esp_sha_type sha_type, const unsign
sha_hal_read_digest(sha_type, ctx->state);
/* Disable peripheral module */
periph_ll_disable_clk_set_rst(PERIPH_SHA_MODULE);
SHA_RCC_ATOMIC() {
sha_ll_enable_bus_clock(false);
}
}
if ( ilen > 0 ) {
@ -139,7 +145,10 @@ static void sha256_update_block(sha256_ctx* ctx, esp_sha_type sha_type, const un
if ( (ilen >= 64) || local_len) {
/* Enable peripheral module */
periph_ll_enable_clk_clear_rst(PERIPH_SHA_MODULE);
SHA_RCC_ATOMIC() {
sha_ll_enable_bus_clock(true);
sha_ll_reset_register();
}
if (ctx->first_block == 0) {
/* Writes the message digest to the SHA engine */
@ -168,7 +177,9 @@ static void sha256_update_block(sha256_ctx* ctx, esp_sha_type sha_type, const un
sha_hal_read_digest(sha_type, ctx->state);
/* Disable peripheral module */
periph_ll_disable_clk_set_rst(PERIPH_SHA_MODULE);
SHA_RCC_ATOMIC() {
sha_ll_enable_bus_clock(false);
}
}
if ( ilen > 0 ) {
@ -280,7 +291,10 @@ static void sha512_update_block(sha512_ctx* ctx, esp_sha_type sha_type, const un
if ( (ilen >= 128) || local_len) {
/* Enable peripheral module */
periph_ll_enable_clk_clear_rst(PERIPH_SHA_MODULE);
SHA_RCC_ATOMIC() {
sha_ll_enable_bus_clock(true);
sha_ll_reset_register();
}
if (ctx->first_block && sha_type == SHA2_512T){
sha_512_t_init_hash_block(ctx->t_val);
@ -313,7 +327,9 @@ static void sha512_update_block(sha512_ctx* ctx, esp_sha_type sha_type, const un
sha_hal_read_digest(sha_type, ctx->state);
/* Disable peripheral module */
periph_ll_disable_clk_set_rst(PERIPH_SHA_MODULE);
SHA_RCC_ATOMIC() {
sha_ll_enable_bus_clock(false);
}
}
if ( ilen > 0 ) {

23
components/hal/test_apps/crypto/main/sha/sha_dma.c
Wyświetl plik

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: CC0-1.0
*/
@ -19,8 +19,9 @@
#include "soc/periph_defs.h"
#include "esp_private/periph_ctrl.h"
#include "esp_private/esp_crypto_lock_internal.h"
#include "hal/sha_hal.h"
#include "hal/clk_gate_ll.h"
#include "hal/sha_ll.h"
#include "sha_dma.h"
#if CONFIG_SOC_SHA_GDMA
@ -68,20 +69,26 @@ static esp_err_t esp_sha_dma_start(const lldesc_t *input)
static void acquire_hardware(void)
{
SHA_RCC_ATOMIC() {
sha_ll_enable_bus_clock(true);
#if SOC_AES_CRYPTO_DMA
periph_ll_enable_clk_clear_rst(PERIPH_SHA_DMA_MODULE);
#elif SOC_AES_GDMA
periph_ll_enable_clk_clear_rst(PERIPH_SHA_MODULE);
crypto_dma_ll_enable_bus_clock(true);
#endif
sha_ll_reset_register();
#if SOC_AES_CRYPTO_DMA
crypto_dma_ll_reset_register();
#endif
}
}
static void release_hardware(void)
{
SHA_RCC_ATOMIC() {
sha_ll_enable_bus_clock(false);
#if SOC_AES_CRYPTO_DMA
periph_ll_disable_clk_set_rst(PERIPH_SHA_DMA_MODULE);
#elif SOC_AES_GDMA
periph_ll_disable_clk_set_rst(PERIPH_SHA_MODULE);
crypto_dma_ll_enable_bus_clock(false);
#endif
}
}
static int esp_sha_dma_process(esp_sha_type sha_type, const void *input, uint32_t ilen,

15
components/mbedtls/port/sha/block/sha.c
Wyświetl plik

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -8,10 +8,12 @@
#include "soc/soc_caps.h"
#include "soc/periph_defs.h"
#include "esp_private/esp_crypto_lock_internal.h"
#include "esp_private/periph_ctrl.h"
#include "sha/sha_block.h"
#include "hal/sha_hal.h"
#include "hal/sha_ll.h"
static _lock_t s_sha_lock;
@ -56,13 +58,20 @@ inline static size_t block_length(esp_sha_type type)
void esp_sha_acquire_hardware()
{
_lock_acquire(&s_sha_lock); /* Released when releasing hw with esp_sha_release_hardware() */
periph_module_enable(PERIPH_SHA_MODULE);
SHA_RCC_ATOMIC() {
sha_ll_enable_bus_clock(true);
sha_ll_reset_register();
}
}
/* Disable SHA peripheral block and then release it */
void esp_sha_release_hardware()
{
periph_module_disable(PERIPH_SHA_MODULE);
SHA_RCC_ATOMIC() {
sha_ll_enable_bus_clock(false);
}
_lock_release(&s_sha_lock);
}

27
components/mbedtls/port/sha/dma/sha.c
Wyświetl plik

@ -30,6 +30,7 @@
#include <sys/lock.h>
#include "esp_dma_utils.h"
#include "esp_private/esp_crypto_lock_internal.h"
#include "esp_private/esp_cache_private.h"
#include "esp_log.h"
#include "esp_memory_utils.h"
@ -49,6 +50,7 @@
#include "sha/sha_dma.h"
#include "hal/sha_hal.h"
#include "hal/sha_ll.h"
#include "soc/soc_caps.h"
#include "esp_sha_dma_priv.h"
@ -58,6 +60,7 @@
#elif SOC_SHA_CRYPTO_DMA
#define SHA_LOCK() esp_crypto_dma_lock_acquire()
#define SHA_RELEASE() esp_crypto_dma_lock_release()
#include "hal/crypto_dma_ll.h"
#endif
const static char *TAG = "esp-sha";
@ -103,23 +106,27 @@ void esp_sha_acquire_hardware()
{
SHA_LOCK(); /* Released when releasing hw with esp_sha_release_hardware() */
/* Enable SHA and DMA hardware */
#if SOC_SHA_CRYPTO_DMA
periph_module_enable(PERIPH_SHA_DMA_MODULE);
#elif SOC_SHA_GDMA
periph_module_enable(PERIPH_SHA_MODULE);
SHA_RCC_ATOMIC() {
sha_ll_enable_bus_clock(true);
#if SOC_AES_CRYPTO_DMA
crypto_dma_ll_enable_bus_clock(true);
#endif
sha_ll_reset_register();
#if SOC_AES_CRYPTO_DMA
crypto_dma_ll_reset_register();
#endif
}
}
/* Disable SHA peripheral block and then release it */
void esp_sha_release_hardware()
{
/* Disable SHA and DMA hardware */
#if SOC_SHA_CRYPTO_DMA
periph_module_disable(PERIPH_SHA_DMA_MODULE);
#elif SOC_SHA_GDMA
periph_module_disable(PERIPH_SHA_MODULE);
SHA_RCC_ATOMIC() {
sha_ll_enable_bus_clock(false);
#if SOC_AES_CRYPTO_DMA
crypto_dma_ll_enable_bus_clock(false);
#endif
}
SHA_RELEASE();
}

11
components/mbedtls/port/sha/parallel_engine/sha.c
Wyświetl plik

@ -35,9 +35,11 @@
#include "esp_cpu.h"
#include "hal/sha_hal.h"
#include "hal/sha_ll.h"
#include "hal/sha_types.h"
#include "sha/sha_parallel_engine.h"
#include "soc/hwcrypto_periph.h"
#include "esp_private/esp_crypto_lock_internal.h"
#include "esp_private/periph_ctrl.h"
/*
@ -151,7 +153,10 @@ static bool esp_sha_lock_engine_common(esp_sha_type sha_type, TickType_t ticks_t
if (engines_in_use == 0) {
/* Just locked first engine,
so enable SHA hardware */
periph_module_enable(PERIPH_SHA_MODULE);
SHA_RCC_ATOMIC() {
sha_ll_enable_bus_clock(true);
sha_ll_reset_register();
}
}
engines_in_use++;
@ -174,7 +179,9 @@ void esp_sha_unlock_engine(esp_sha_type sha_type)
if (engines_in_use == 0) {
/* About to release last engine, so
disable SHA hardware */
periph_module_disable(PERIPH_SHA_MODULE);
SHA_RCC_ATOMIC() {
sha_ll_enable_bus_clock(false);
}
}
portEXIT_CRITICAL(&engines_in_use_lock);