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uart: Support LP_UART port with UART driver on esp32c6

pull/11692/head
Song Ruo Jing 2023-03-24 11:42:01 +08:00
rodzic b77540c285
commit 921713fff4
68 zmienionych plików z 1127 dodań i 401 usunięć
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2
components/bt/porting/transport/uart/hci_uart.c
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@ -122,7 +122,7 @@ int hci_uart_config(int port_num, int32_t baud_rate, uint8_t data_bits, uint8_t
.stop_bits = stop_bits,
.flow_ctrl = HCI_UART_FLOWCTRL,
.source_clk = UART_SCLK_DEFAULT,
.rx_flow_ctrl_thresh = UART_FIFO_LEN - 1,
.rx_flow_ctrl_thresh = UART_HW_FIFO_LEN(port_num) - 1,
};
hci_uart.port = port_num;
hci_uart.cfg = uart_cfg;

12
components/driver/gpio/include/driver/rtc_io.h
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@ -198,6 +198,18 @@ esp_err_t rtc_gpio_set_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t st
*/
esp_err_t rtc_gpio_get_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t* strength);
/**
* @brief Select a RTC IOMUX function for the RTC IO
*
* @param gpio_num GPIO number
* @param func Function to assign to the pin
*
* @return
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG Parameter error
*/
esp_err_t rtc_gpio_iomux_func_sel(gpio_num_t gpio_num, int func);
#endif // SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
#if SOC_RTCIO_HOLD_SUPPORTED

10
components/driver/gpio/rtc_io.c
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@ -145,6 +145,16 @@ esp_err_t rtc_gpio_pulldown_dis(gpio_num_t gpio_num)
return ESP_OK;
}
esp_err_t rtc_gpio_iomux_func_sel(gpio_num_t gpio_num, int func)
{
ESP_RETURN_ON_FALSE(rtc_gpio_is_valid_gpio(gpio_num), ESP_ERR_INVALID_ARG, RTCIO_TAG, "RTCIO number error");
RTCIO_ENTER_CRITICAL();
rtcio_hal_iomux_func_sel(rtc_io_number_get(gpio_num), func);
RTCIO_EXIT_CRITICAL();
return ESP_OK;
}
#endif // SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
#if SOC_RTCIO_HOLD_SUPPORTED

47
components/driver/uart/include/driver/uart.h
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@ -20,22 +20,37 @@ extern "C" {
#include "freertos/ringbuf.h"
#include "hal/uart_types.h"
// Valid UART port number
#define UART_NUM_0 (0) /*!< UART port 0 */
#define UART_NUM_1 (1) /*!< UART port 1 */
#if SOC_UART_NUM > 2
#define UART_NUM_2 (2) /*!< UART port 2 */
#endif
#define UART_NUM_MAX (SOC_UART_NUM) /*!< UART port max */
/* @brief When calling `uart_set_pin`, instead of GPIO number, `UART_PIN_NO_CHANGE`
* can be provided to keep the currently allocated pin.
*/
#define UART_PIN_NO_CHANGE (-1)
#define UART_FIFO_LEN SOC_UART_FIFO_LEN ///< Length of the UART HW FIFO
#define UART_FIFO_LEN _Pragma ("GCC warning \"'UART_FIFO_LEN' macro is deprecated, please use 'UART_HW_FIFO_LEN' instead\"") SOC_UART_FIFO_LEN ///< Length of the HP UART HW FIFO
#if (SOC_UART_LP_NUM >= 1)
#define UART_HW_FIFO_LEN(uart_num) ((uart_num < SOC_UART_HP_NUM) ? SOC_UART_FIFO_LEN : SOC_LP_UART_FIFO_LEN) ///< Length of the UART HW FIFO
#else
#define UART_HW_FIFO_LEN(uart_num) SOC_UART_FIFO_LEN ///< Length of the UART HW FIFO
#endif
#define UART_BITRATE_MAX SOC_UART_BITRATE_MAX ///< Maximum configurable bitrate
/**
* @brief UART configuration parameters for uart_param_config function
*/
typedef struct {
int baud_rate; /*!< UART baud rate*/
uart_word_length_t data_bits; /*!< UART byte size*/
uart_parity_t parity; /*!< UART parity mode*/
uart_stop_bits_t stop_bits; /*!< UART stop bits*/
uart_hw_flowcontrol_t flow_ctrl; /*!< UART HW flow control mode (cts/rts)*/
uint8_t rx_flow_ctrl_thresh; /*!< UART HW RTS threshold*/
union {
uart_sclk_t source_clk; /*!< UART source clock selection */
#if (SOC_UART_LP_NUM >= 1)
lp_uart_sclk_t lp_source_clk; /*!< LP_UART source clock selection */
#endif
};
} uart_config_t;
/**
* @brief UART interrupt configuration parameters for uart_intr_config function
*/
@ -81,7 +96,7 @@ typedef intr_handle_t uart_isr_handle_t;
*
* UART ISR handler will be attached to the same CPU core that this function is running on.
*
* @note Rx_buffer_size should be greater than UART_FIFO_LEN. Tx_buffer_size should be either zero or greater than UART_FIFO_LEN.
* @note Rx_buffer_size should be greater than UART_HW_FIFO_LEN(uart_num). Tx_buffer_size should be either zero or greater than UART_HW_FIFO_LEN(uart_num).
*
* @param uart_num UART port number, the max port number is (UART_NUM_MAX -1).
* @param rx_buffer_size UART RX ring buffer size.
@ -196,7 +211,7 @@ esp_err_t uart_set_parity(uart_port_t uart_num, uart_parity_t parity_mode);
esp_err_t uart_get_parity(uart_port_t uart_num, uart_parity_t* parity_mode);
/**
* @brief Get the frequency of a clock source for the UART
* @brief Get the frequency of a clock source for the HP UART port
*
* @param sclk Clock source
* @param[out] out_freq_hz Output of frequency, in Hz
@ -249,7 +264,7 @@ esp_err_t uart_set_line_inverse(uart_port_t uart_num, uint32_t inverse_mask);
*
* @param uart_num UART port number, the max port number is (UART_NUM_MAX -1).
* @param flow_ctrl Hardware flow control mode
* @param rx_thresh Threshold of Hardware RX flow control (0 ~ UART_FIFO_LEN).
* @param rx_thresh Threshold of Hardware RX flow control (0 ~ UART_HW_FIFO_LEN(uart_num)).
* Only when UART_HW_FLOWCTRL_RTS is set, will the rx_thresh value be set.
*
* @return
@ -261,7 +276,7 @@ esp_err_t uart_set_hw_flow_ctrl(uart_port_t uart_num, uart_hw_flowcontrol_t flow
/**
* @brief Set software flow control.
*
* @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2
* @param uart_num UART port number, the max port number is (UART_NUM_MAX -1)
* @param enable switch on or off
* @param rx_thresh_xon low water mark
* @param rx_thresh_xoff high water mark
@ -358,7 +373,7 @@ esp_err_t uart_disable_tx_intr(uart_port_t uart_num);
*
* @param uart_num UART port number, the max port number is (UART_NUM_MAX -1).
* @param enable 1: enable; 0: disable
* @param thresh Threshold of TX interrupt, 0 ~ UART_FIFO_LEN
* @param thresh Threshold of TX interrupt, 0 ~ UART_HW_FIFO_LEN(uart_num)
*
* @return
* - ESP_OK Success
@ -695,7 +710,7 @@ esp_err_t uart_set_mode(uart_port_t uart_num, uart_mode_t mode);
* @note If application is using higher baudrate and it is observed that bytes
* in hardware RX fifo are overwritten then this threshold can be reduced
*
* @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2
* @param uart_num UART port number, the max port number is (UART_NUM_MAX -1)
* @param threshold Threshold value above which RX fifo full interrupt is generated
*
* @return
@ -708,7 +723,7 @@ esp_err_t uart_set_rx_full_threshold(uart_port_t uart_num, int threshold);
/**
* @brief Set uart threshold values for TX fifo empty
*
* @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2
* @param uart_num UART port number, the max port number is (UART_NUM_MAX -1)
* @param threshold Threshold value below which TX fifo empty interrupt is generated
*
* @return

176
components/driver/uart/uart.c
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@ -22,8 +22,10 @@
#include "soc/uart_periph.h"
#include "driver/uart.h"
#include "driver/gpio.h"
#include "driver/rtc_io.h"
#include "driver/uart_select.h"
#include "esp_private/periph_ctrl.h"
#include "esp_private/lp_periph_ctrl.h"
#include "esp_clk_tree.h"
#include "sdkconfig.h"
#include "esp_rom_gpio.h"
@ -43,13 +45,21 @@
static const char *UART_TAG = "uart";
#define UART_EMPTY_THRESH_DEFAULT (10)
#define LP_UART_EMPTY_THRESH_DEFAULT (2)
#define UART_FULL_THRESH_DEFAULT (120)
#define LP_UART_FULL_THRESH_DEFAULT (10)
#define UART_TOUT_THRESH_DEFAULT (10)
#define UART_CLKDIV_FRAG_BIT_WIDTH (3)
#define UART_TX_IDLE_NUM_DEFAULT (0)
#define UART_PATTERN_DET_QLEN_DEFAULT (10)
#define UART_MIN_WAKEUP_THRESH (UART_LL_MIN_WAKEUP_THRESH)
#if (SOC_UART_LP_NUM >= 1)
#define UART_THRESHOLD_NUM(uart_num, field_name) ((uart_num < SOC_UART_HP_NUM) ? field_name : LP_##field_name)
#else
#define UART_THRESHOLD_NUM(uart_num, field_name) (field_name)
#endif
#if SOC_UART_SUPPORT_WAKEUP_INT
#define UART_INTR_CONFIG_FLAG ((UART_INTR_RXFIFO_FULL) \
| (UART_INTR_RXFIFO_TOUT) \
@ -112,7 +122,7 @@ typedef struct {
uint32_t rx_cur_remain; /*!< Data number that waiting to be read out in ring buffer item*/
uint8_t *rx_ptr; /*!< pointer to the current data in ring buffer*/
uint8_t *rx_head_ptr; /*!< pointer to the head of RX item*/
uint8_t rx_data_buf[SOC_UART_FIFO_LEN]; /*!< Data buffer to stash FIFO data*/
uint8_t *rx_data_buf; /*!< Data buffer to stash FIFO data*/
uint8_t rx_stash_len; /*!< stashed data length.(When using flow control, after reading out FIFO data, if we fail to push to buffer, we can just stash them.) */
uint32_t rx_int_usr_mask; /*!< RX interrupt status. Valid at any time, regardless of RX buffer status. */
uart_pat_rb_t rx_pattern_pos;
@ -160,9 +170,12 @@ static uart_obj_t *p_uart_obj[UART_NUM_MAX] = {0};
static uart_context_t uart_context[UART_NUM_MAX] = {
UART_CONTEX_INIT_DEF(UART_NUM_0),
UART_CONTEX_INIT_DEF(UART_NUM_1),
#if UART_NUM_MAX > 2
#if SOC_UART_HP_NUM > 2
UART_CONTEX_INIT_DEF(UART_NUM_2),
#endif
#if (SOC_UART_LP_NUM >= 1)
UART_CONTEX_INIT_DEF(LP_UART_NUM_0),
#endif
};
static portMUX_TYPE uart_selectlock = portMUX_INITIALIZER_UNLOCKED;
@ -171,18 +184,26 @@ static void uart_module_enable(uart_port_t uart_num)
{
UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
if (uart_context[uart_num].hw_enabled != true) {
periph_module_enable(uart_periph_signal[uart_num].module);
if (uart_num != CONFIG_ESP_CONSOLE_UART_NUM) {
// Workaround for ESP32C3/S3: enable core reset before enabling uart module clock to prevent uart output
// garbage value.
if (uart_num < SOC_UART_HP_NUM) {
periph_module_enable(uart_periph_signal[uart_num].module);
if (uart_num != CONFIG_ESP_CONSOLE_UART_NUM) {
// Workaround for ESP32C3/S3: enable core reset before enabling uart module clock to prevent uart output
// garbage value.
#if SOC_UART_REQUIRE_CORE_RESET
uart_hal_set_reset_core(&(uart_context[uart_num].hal), true);
periph_module_reset(uart_periph_signal[uart_num].module);
uart_hal_set_reset_core(&(uart_context[uart_num].hal), false);
uart_hal_set_reset_core(&(uart_context[uart_num].hal), true);
periph_module_reset(uart_periph_signal[uart_num].module);
uart_hal_set_reset_core(&(uart_context[uart_num].hal), false);
#else
periph_module_reset(uart_periph_signal[uart_num].module);
periph_module_reset(uart_periph_signal[uart_num].module);
#endif
}
}
#if (SOC_UART_LP_NUM >= 1)
else {
lp_periph_module_enable(uart_periph_signal[uart_num].lp_module);
lp_periph_module_reset(uart_periph_signal[uart_num].lp_module);
}
#endif
uart_context[uart_num].hw_enabled = true;
}
UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
@ -192,9 +213,14 @@ static void uart_module_disable(uart_port_t uart_num)
{
UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
if (uart_context[uart_num].hw_enabled != false) {
if (uart_num != CONFIG_ESP_CONSOLE_UART_NUM ) {
if (uart_num != CONFIG_ESP_CONSOLE_UART_NUM && uart_num < SOC_UART_HP_NUM) {
periph_module_disable(uart_periph_signal[uart_num].module);
}
#if (SOC_UART_LP_NUM >= 1)
else if (uart_num >= SOC_UART_HP_NUM) {
lp_periph_module_disable(uart_periph_signal[uart_num].lp_module);
}
#endif
uart_context[uart_num].hw_enabled = false;
}
UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
@ -263,11 +289,11 @@ esp_err_t uart_set_baudrate(uart_port_t uart_num, uint32_t baud_rate)
{
ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_FAIL, UART_TAG, "uart_num error");
uart_sclk_t src_clk;
soc_module_clk_t src_clk;
uint32_t sclk_freq;
uart_hal_get_sclk(&(uart_context[uart_num].hal), &src_clk);
ESP_RETURN_ON_ERROR(uart_get_sclk_freq(src_clk, &sclk_freq), UART_TAG, "Invalid src_clk");
ESP_RETURN_ON_ERROR(esp_clk_tree_src_get_freq_hz(src_clk, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &sclk_freq), UART_TAG, "Invalid src_clk");
UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
uart_hal_set_baudrate(&(uart_context[uart_num].hal), baud_rate, sclk_freq);
@ -279,11 +305,11 @@ esp_err_t uart_get_baudrate(uart_port_t uart_num, uint32_t *baudrate)
{
ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_FAIL, UART_TAG, "uart_num error");
uart_sclk_t src_clk;
soc_module_clk_t src_clk;
uint32_t sclk_freq;
uart_hal_get_sclk(&(uart_context[uart_num].hal), &src_clk);
ESP_RETURN_ON_ERROR(uart_get_sclk_freq(src_clk, &sclk_freq), UART_TAG, "Invalid src_clk");
ESP_RETURN_ON_ERROR(esp_clk_tree_src_get_freq_hz(src_clk, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &sclk_freq), UART_TAG, "Invalid src_clk");
UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
uart_hal_get_baudrate(&(uart_context[uart_num].hal), baudrate, sclk_freq);
@ -303,8 +329,8 @@ esp_err_t uart_set_line_inverse(uart_port_t uart_num, uint32_t inverse_mask)
esp_err_t uart_set_sw_flow_ctrl(uart_port_t uart_num, bool enable, uint8_t rx_thresh_xon, uint8_t rx_thresh_xoff)
{
ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_FAIL, UART_TAG, "uart_num error");
ESP_RETURN_ON_FALSE((rx_thresh_xon < SOC_UART_FIFO_LEN), ESP_FAIL, UART_TAG, "rx flow xon thresh error");
ESP_RETURN_ON_FALSE((rx_thresh_xoff < SOC_UART_FIFO_LEN), ESP_FAIL, UART_TAG, "rx flow xoff thresh error");
ESP_RETURN_ON_FALSE((rx_thresh_xon < UART_HW_FIFO_LEN(uart_num)), ESP_FAIL, UART_TAG, "rx flow xon thresh error");
ESP_RETURN_ON_FALSE((rx_thresh_xoff < UART_HW_FIFO_LEN(uart_num)), ESP_FAIL, UART_TAG, "rx flow xoff thresh error");
uart_sw_flowctrl_t sw_flow_ctl = {
.xon_char = XON,
.xoff_char = XOFF,
@ -320,7 +346,7 @@ esp_err_t uart_set_sw_flow_ctrl(uart_port_t uart_num, bool enable, uint8_t rx_t
esp_err_t uart_set_hw_flow_ctrl(uart_port_t uart_num, uart_hw_flowcontrol_t flow_ctrl, uint8_t rx_thresh)
{
ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_FAIL, UART_TAG, "uart_num error");
ESP_RETURN_ON_FALSE((rx_thresh < SOC_UART_FIFO_LEN), ESP_FAIL, UART_TAG, "rx flow thresh error");
ESP_RETURN_ON_FALSE((rx_thresh < UART_HW_FIFO_LEN(uart_num)), ESP_FAIL, UART_TAG, "rx flow thresh error");
ESP_RETURN_ON_FALSE((flow_ctrl < UART_HW_FLOWCTRL_MAX), ESP_FAIL, UART_TAG, "hw_flowctrl mode error");
UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
uart_hal_set_hw_flow_ctrl(&(uart_context[uart_num].hal), flow_ctrl, rx_thresh);
@ -515,9 +541,9 @@ esp_err_t uart_pattern_queue_reset(uart_port_t uart_num, int queue_length)
esp_err_t uart_enable_pattern_det_baud_intr(uart_port_t uart_num, char pattern_chr, uint8_t chr_num, int chr_tout, int post_idle, int pre_idle)
{
ESP_RETURN_ON_FALSE(uart_num < UART_NUM_MAX, ESP_FAIL, UART_TAG, "uart_num error");
ESP_RETURN_ON_FALSE(chr_tout >= 0 && chr_tout <= UART_RX_GAP_TOUT_V, ESP_FAIL, UART_TAG, "uart pattern set error\n");
ESP_RETURN_ON_FALSE(post_idle >= 0 && post_idle <= UART_POST_IDLE_NUM_V, ESP_FAIL, UART_TAG, "uart pattern set error\n");
ESP_RETURN_ON_FALSE(pre_idle >= 0 && pre_idle <= UART_PRE_IDLE_NUM_V, ESP_FAIL, UART_TAG, "uart pattern set error\n");
ESP_RETURN_ON_FALSE(chr_tout >= 0 && chr_tout <= UART_THRESHOLD_NUM(uart_num, UART_RX_GAP_TOUT_V), ESP_FAIL, UART_TAG, "uart pattern set error\n");
ESP_RETURN_ON_FALSE(post_idle >= 0 && post_idle <= UART_THRESHOLD_NUM(uart_num, UART_POST_IDLE_NUM_V), ESP_FAIL, UART_TAG, "uart pattern set error\n");
ESP_RETURN_ON_FALSE(pre_idle >= 0 && pre_idle <= UART_THRESHOLD_NUM(uart_num, UART_PRE_IDLE_NUM_V), ESP_FAIL, UART_TAG, "uart pattern set error\n");
uart_at_cmd_t at_cmd = {0};
at_cmd.cmd_char = pattern_chr;
at_cmd.char_num = chr_num;
@ -570,7 +596,7 @@ esp_err_t uart_disable_tx_intr(uart_port_t uart_num)
esp_err_t uart_enable_tx_intr(uart_port_t uart_num, int enable, int thresh)
{
ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_FAIL, UART_TAG, "uart_num error");
ESP_RETURN_ON_FALSE((thresh < SOC_UART_FIFO_LEN), ESP_FAIL, UART_TAG, "empty intr threshold error");
ESP_RETURN_ON_FALSE((thresh < UART_HW_FIFO_LEN(uart_num)), ESP_FAIL, UART_TAG, "empty intr threshold error");
uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_TXFIFO_EMPTY);
UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
uart_hal_set_txfifo_empty_thr(&(uart_context[uart_num].hal), thresh);
@ -592,13 +618,26 @@ static bool uart_try_set_iomux_pin(uart_port_t uart_num, int io_num, uint32_t id
/* Assign the correct funct to the GPIO. */
assert (upin->iomux_func != -1);
gpio_iomux_out(io_num, upin->iomux_func, false);
if (uart_num < SOC_UART_HP_NUM) {
gpio_iomux_out(io_num, upin->iomux_func, false);
/* If the pin is input, we also have to redirect the signal,
* in order to bypasse the GPIO matrix. */
if (upin->input) {
gpio_iomux_in(io_num, upin->signal);
/* If the pin is input, we also have to redirect the signal,
* in order to bypasse the GPIO matrix. */
if (upin->input) {
gpio_iomux_in(io_num, upin->signal);
}
}
#if (SOC_UART_LP_NUM >= 1)
else {
if (upin->input) {
rtc_gpio_set_direction(io_num, RTC_GPIO_MODE_INPUT_ONLY);
} else {
rtc_gpio_set_direction(io_num, RTC_GPIO_MODE_OUTPUT_ONLY);
}
rtc_gpio_init(io_num);
rtc_gpio_iomux_func_sel(io_num, upin->iomux_func);
}
#endif
return true;
}
@ -609,10 +648,21 @@ esp_err_t uart_set_pin(uart_port_t uart_num, int tx_io_num, int rx_io_num, int r
{
ESP_RETURN_ON_FALSE((uart_num >= 0), ESP_FAIL, UART_TAG, "uart_num error");
ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_FAIL, UART_TAG, "uart_num error");
ESP_RETURN_ON_FALSE((tx_io_num < 0 || (GPIO_IS_VALID_OUTPUT_GPIO(tx_io_num))), ESP_FAIL, UART_TAG, "tx_io_num error");
ESP_RETURN_ON_FALSE((rx_io_num < 0 || (GPIO_IS_VALID_GPIO(rx_io_num))), ESP_FAIL, UART_TAG, "rx_io_num error");
ESP_RETURN_ON_FALSE((rts_io_num < 0 || (GPIO_IS_VALID_OUTPUT_GPIO(rts_io_num))), ESP_FAIL, UART_TAG, "rts_io_num error");
ESP_RETURN_ON_FALSE((cts_io_num < 0 || (GPIO_IS_VALID_GPIO(cts_io_num))), ESP_FAIL, UART_TAG, "cts_io_num error");
if (uart_num < SOC_UART_HP_NUM) {
ESP_RETURN_ON_FALSE((tx_io_num < 0 || (GPIO_IS_VALID_OUTPUT_GPIO(tx_io_num))), ESP_FAIL, UART_TAG, "tx_io_num error");
ESP_RETURN_ON_FALSE((rx_io_num < 0 || (GPIO_IS_VALID_GPIO(rx_io_num))), ESP_FAIL, UART_TAG, "rx_io_num error");
ESP_RETURN_ON_FALSE((rts_io_num < 0 || (GPIO_IS_VALID_OUTPUT_GPIO(rts_io_num))), ESP_FAIL, UART_TAG, "rts_io_num error");
ESP_RETURN_ON_FALSE((cts_io_num < 0 || (GPIO_IS_VALID_GPIO(cts_io_num))), ESP_FAIL, UART_TAG, "cts_io_num error");
}
#if (SOC_UART_LP_NUM >= 1)
else { // LP_UART has its fixed IOs
const uart_periph_sig_t *pins = uart_periph_signal[uart_num].pins;
ESP_RETURN_ON_FALSE((tx_io_num < 0 || (tx_io_num == pins[SOC_UART_TX_PIN_IDX].default_gpio)), ESP_FAIL, UART_TAG, "tx_io_num error");
ESP_RETURN_ON_FALSE((rx_io_num < 0 || (rx_io_num == pins[SOC_UART_RX_PIN_IDX].default_gpio)), ESP_FAIL, UART_TAG, "rx_io_num error");
ESP_RETURN_ON_FALSE((rts_io_num < 0 || (rts_io_num == pins[SOC_UART_RTS_PIN_IDX].default_gpio)), ESP_FAIL, UART_TAG, "rts_io_num error");
ESP_RETURN_ON_FALSE((cts_io_num < 0 || (cts_io_num == pins[SOC_UART_CTS_PIN_IDX].default_gpio)), ESP_FAIL, UART_TAG, "cts_io_num error");
}
#endif
/* In the following statements, if the io_num is negative, no need to configure anything. */
if (tx_io_num >= 0 && !uart_try_set_iomux_pin(uart_num, tx_io_num, SOC_UART_TX_PIN_IDX)) {
@ -666,7 +716,7 @@ esp_err_t uart_set_dtr(uart_port_t uart_num, int level)
esp_err_t uart_set_tx_idle_num(uart_port_t uart_num, uint16_t idle_num)
{
ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_FAIL, UART_TAG, "uart_num error");
ESP_RETURN_ON_FALSE((idle_num <= UART_TX_IDLE_NUM_V), ESP_FAIL, UART_TAG, "uart idle num error");
ESP_RETURN_ON_FALSE((idle_num <= UART_THRESHOLD_NUM(uart_num, UART_TX_IDLE_NUM_V)), ESP_FAIL, UART_TAG, "uart idle num error");
UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
uart_hal_set_tx_idle_num(&(uart_context[uart_num].hal), idle_num);
UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
@ -677,22 +727,40 @@ esp_err_t uart_param_config(uart_port_t uart_num, const uart_config_t *uart_conf
{
ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_FAIL, UART_TAG, "uart_num error");
ESP_RETURN_ON_FALSE((uart_config), ESP_FAIL, UART_TAG, "param null");
ESP_RETURN_ON_FALSE((uart_config->rx_flow_ctrl_thresh < SOC_UART_FIFO_LEN), ESP_FAIL, UART_TAG, "rx flow thresh error");
ESP_RETURN_ON_FALSE((uart_config->rx_flow_ctrl_thresh < UART_HW_FIFO_LEN(uart_num)), ESP_FAIL, UART_TAG, "rx flow thresh error");
ESP_RETURN_ON_FALSE((uart_config->flow_ctrl < UART_HW_FLOWCTRL_MAX), ESP_FAIL, UART_TAG, "hw_flowctrl mode error");
ESP_RETURN_ON_FALSE((uart_config->data_bits < UART_DATA_BITS_MAX), ESP_FAIL, UART_TAG, "data bit error");
uart_module_enable(uart_num);
uart_sclk_t clk_src = (uart_config->source_clk) ? uart_config->source_clk : UART_SCLK_DEFAULT; // if no specifying the clock source (soc_module_clk_t starts from 1), then just use the default clock
soc_module_clk_t uart_sclk_sel = 0; // initialize to an invalid module clock ID
if (uart_num < SOC_UART_HP_NUM) {
uart_sclk_sel = (soc_module_clk_t)((uart_config->source_clk) ? uart_config->source_clk : UART_SCLK_DEFAULT); // if no specifying the clock source (soc_module_clk_t starts from 1), then just use the default clock
}
#if (SOC_UART_LP_NUM >= 1)
else {
uart_sclk_sel = (soc_module_clk_t)((uart_config->lp_source_clk) ? uart_config->lp_source_clk : LP_UART_SCLK_DEFAULT);
}
#endif
#if SOC_UART_SUPPORT_RTC_CLK
if (clk_src == UART_SCLK_RTC) {
if (uart_sclk_sel == (soc_module_clk_t)UART_SCLK_RTC) {
periph_rtc_dig_clk8m_enable();
}
#endif
uint32_t sclk_freq;
ESP_RETURN_ON_ERROR(uart_get_sclk_freq(clk_src, &sclk_freq), UART_TAG, "Invalid src_clk");
ESP_RETURN_ON_ERROR(esp_clk_tree_src_get_freq_hz(uart_sclk_sel, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &sclk_freq), UART_TAG, "Invalid src_clk");
UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
uart_hal_init(&(uart_context[uart_num].hal), uart_num);
uart_hal_set_sclk(&(uart_context[uart_num].hal), clk_src);
if (uart_num < SOC_UART_HP_NUM) {
uart_hal_set_sclk(&(uart_context[uart_num].hal), uart_sclk_sel);
}
#if (SOC_UART_LP_NUM >= 1)
else {
lp_periph_set_clk_src(uart_periph_signal[uart_num].lp_module, uart_sclk_sel);
}
#endif
uart_hal_set_baudrate(&(uart_context[uart_num].hal), uart_config->baud_rate, sclk_freq);
uart_hal_set_parity(&(uart_context[uart_num].hal), uart_config->parity);
uart_hal_set_data_bit_num(&(uart_context[uart_num].hal), uart_config->data_bits);
@ -1174,7 +1242,7 @@ static int uart_tx_all(uart_port_t uart_num, const char *src, size_t size, bool
xRingbufferSend(p_uart_obj[uart_num]->tx_ring_buf, (void *) (src + offset), send_size, portMAX_DELAY);
size -= send_size;
offset += send_size;
uart_enable_tx_intr(uart_num, 1, UART_EMPTY_THRESH_DEFAULT);
uart_enable_tx_intr(uart_num, 1, UART_THRESHOLD_NUM(uart_num, UART_EMPTY_THRESH_DEFAULT));
}
} else {
while (size) {
@ -1183,7 +1251,7 @@ static int uart_tx_all(uart_port_t uart_num, const char *src, size_t size, bool
uint32_t sent = uart_enable_tx_write_fifo(uart_num, (const uint8_t *) src, size);
if (sent < size) {
p_uart_obj[uart_num]->tx_waiting_fifo = true;
uart_enable_tx_intr(uart_num, 1, UART_EMPTY_THRESH_DEFAULT);
uart_enable_tx_intr(uart_num, 1, UART_THRESHOLD_NUM(uart_num, UART_EMPTY_THRESH_DEFAULT));
}
size -= sent;
src += sent;
@ -1425,15 +1493,20 @@ static void uart_free_driver_obj(uart_obj_t *uart_obj)
free(uart_obj->tx_done_sem_struct);
free(uart_obj->tx_fifo_sem_struct);
#endif
free(uart_obj->rx_data_buf);
free(uart_obj);
}
static uart_obj_t *uart_alloc_driver_obj(int event_queue_size, int tx_buffer_size, int rx_buffer_size)
static uart_obj_t *uart_alloc_driver_obj(uart_port_t uart_num, int event_queue_size, int tx_buffer_size, int rx_buffer_size)
{
uart_obj_t *uart_obj = heap_caps_calloc(1, sizeof(uart_obj_t), UART_MALLOC_CAPS);
if (!uart_obj) {
return NULL;
}
uart_obj->rx_data_buf = heap_caps_calloc(UART_HW_FIFO_LEN(uart_num), sizeof(uint32_t), UART_MALLOC_CAPS);
if (!uart_obj->rx_data_buf) {
goto err;
}
#if CONFIG_UART_ISR_IN_IRAM
if (event_queue_size > 0) {
uart_obj->event_queue_storage = heap_caps_calloc(event_queue_size, sizeof(uart_event_t), UART_MALLOC_CAPS);
@ -1524,8 +1597,8 @@ esp_err_t uart_driver_install(uart_port_t uart_num, int rx_buffer_size, int tx_b
ESP_RETURN_ON_FALSE((uart_num != CONFIG_ESP_CONSOLE_UART_NUM), ESP_FAIL, UART_TAG, "UART used by GDB-stubs! Please disable GDB in menuconfig.");
#endif // CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_FAIL, UART_TAG, "uart_num error");
ESP_RETURN_ON_FALSE((rx_buffer_size > SOC_UART_FIFO_LEN), ESP_FAIL, UART_TAG, "uart rx buffer length error");
ESP_RETURN_ON_FALSE((tx_buffer_size > SOC_UART_FIFO_LEN) || (tx_buffer_size == 0), ESP_FAIL, UART_TAG, "uart tx buffer length error");
ESP_RETURN_ON_FALSE((rx_buffer_size > UART_HW_FIFO_LEN(uart_num)), ESP_FAIL, UART_TAG, "uart rx buffer length error");
ESP_RETURN_ON_FALSE((tx_buffer_size > UART_HW_FIFO_LEN(uart_num)) || (tx_buffer_size == 0), ESP_FAIL, UART_TAG, "uart tx buffer length error");
#if CONFIG_UART_ISR_IN_IRAM
if ((intr_alloc_flags & ESP_INTR_FLAG_IRAM) == 0) {
ESP_LOGI(UART_TAG, "ESP_INTR_FLAG_IRAM flag not set while CONFIG_UART_ISR_IN_IRAM is enabled, flag updated");
@ -1539,7 +1612,7 @@ esp_err_t uart_driver_install(uart_port_t uart_num, int rx_buffer_size, int tx_b
#endif
if (p_uart_obj[uart_num] == NULL) {
p_uart_obj[uart_num] = uart_alloc_driver_obj(event_queue_size, tx_buffer_size, rx_buffer_size);
p_uart_obj[uart_num] = uart_alloc_driver_obj(uart_num, event_queue_size, tx_buffer_size, rx_buffer_size);
if (p_uart_obj[uart_num] == NULL) {
ESP_LOGE(UART_TAG, "UART driver malloc error");
return ESP_FAIL;
@ -1577,9 +1650,9 @@ esp_err_t uart_driver_install(uart_port_t uart_num, int rx_buffer_size, int tx_b
uart_intr_config_t uart_intr = {
.intr_enable_mask = UART_INTR_CONFIG_FLAG,
.rxfifo_full_thresh = UART_FULL_THRESH_DEFAULT,
.rxfifo_full_thresh = UART_THRESHOLD_NUM(uart_num, UART_FULL_THRESH_DEFAULT),
.rx_timeout_thresh = UART_TOUT_THRESH_DEFAULT,
.txfifo_empty_intr_thresh = UART_EMPTY_THRESH_DEFAULT,
.txfifo_empty_intr_thresh = UART_THRESHOLD_NUM(uart_num, UART_EMPTY_THRESH_DEFAULT),
};
uart_module_enable(uart_num);
uart_hal_disable_intr_mask(&(uart_context[uart_num].hal), UART_LL_INTR_MASK);
@ -1616,9 +1689,9 @@ esp_err_t uart_driver_delete(uart_port_t uart_num)
p_uart_obj[uart_num] = NULL;
#if SOC_UART_SUPPORT_RTC_CLK
uart_sclk_t sclk = 0;
soc_module_clk_t sclk = 0;
uart_hal_get_sclk(&(uart_context[uart_num].hal), &sclk);
if (sclk == UART_SCLK_RTC) {
if (sclk == (soc_module_clk_t)UART_SCLK_RTC) {
periph_rtc_dig_clk8m_disable();
}
#endif
@ -1653,6 +1726,9 @@ esp_err_t uart_set_mode(uart_port_t uart_num, uart_mode_t mode)
ESP_RETURN_ON_FALSE((!uart_hal_is_hw_rts_en(&(uart_context[uart_num].hal))), ESP_ERR_INVALID_ARG, UART_TAG,
"disable hw flowctrl before using RS485 mode");
}
if (uart_num >= SOC_UART_HP_NUM) {
ESP_RETURN_ON_FALSE((mode == UART_MODE_UART), ESP_ERR_INVALID_ARG, UART_TAG, "LP_UART can only be in normal UART mode");
}
UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
uart_hal_set_mode(&(uart_context[uart_num].hal), mode);
if (mode == UART_MODE_RS485_COLLISION_DETECT) {
@ -1673,7 +1749,7 @@ esp_err_t uart_set_mode(uart_port_t uart_num, uart_mode_t mode)
esp_err_t uart_set_rx_full_threshold(uart_port_t uart_num, int threshold)
{
ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_ERR_INVALID_ARG, UART_TAG, "uart_num error");
ESP_RETURN_ON_FALSE((threshold < UART_RXFIFO_FULL_THRHD_V) && (threshold > 0), ESP_ERR_INVALID_ARG, UART_TAG,
ESP_RETURN_ON_FALSE((threshold < UART_THRESHOLD_NUM(uart_num, UART_RXFIFO_FULL_THRHD_V)) && (threshold > 0), ESP_ERR_INVALID_ARG, UART_TAG,
"rx fifo full threshold value error");
if (p_uart_obj[uart_num] == NULL) {
ESP_LOGE(UART_TAG, "call uart_driver_install API first");
@ -1690,7 +1766,7 @@ esp_err_t uart_set_rx_full_threshold(uart_port_t uart_num, int threshold)
esp_err_t uart_set_tx_empty_threshold(uart_port_t uart_num, int threshold)
{
ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_ERR_INVALID_ARG, UART_TAG, "uart_num error");
ESP_RETURN_ON_FALSE((threshold < UART_TXFIFO_EMPTY_THRHD_V) && (threshold > 0), ESP_ERR_INVALID_ARG, UART_TAG,
ESP_RETURN_ON_FALSE((threshold < UART_THRESHOLD_NUM(uart_num, UART_TXFIFO_EMPTY_THRHD_V)) && (threshold > 0), ESP_ERR_INVALID_ARG, UART_TAG,
"tx fifo empty threshold value error");
if (p_uart_obj[uart_num] == NULL) {
ESP_LOGE(UART_TAG, "call uart_driver_install API first");
@ -1733,7 +1809,7 @@ esp_err_t uart_get_collision_flag(uart_port_t uart_num, bool *collision_flag)
esp_err_t uart_set_wakeup_threshold(uart_port_t uart_num, int wakeup_threshold)
{
ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_ERR_INVALID_ARG, UART_TAG, "uart_num error");
ESP_RETURN_ON_FALSE((wakeup_threshold <= UART_ACTIVE_THRESHOLD_V && wakeup_threshold > UART_MIN_WAKEUP_THRESH), ESP_ERR_INVALID_ARG, UART_TAG,
ESP_RETURN_ON_FALSE((wakeup_threshold <= UART_THRESHOLD_NUM(uart_num, UART_ACTIVE_THRESHOLD_V) && wakeup_threshold > UART_MIN_WAKEUP_THRESH), ESP_ERR_INVALID_ARG, UART_TAG,
"wakeup_threshold out of bounds");
UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
uart_hal_set_wakeup_thrd(&(uart_context[uart_num].hal), wakeup_threshold);

4
components/esp_gdbstub/src/gdbstub_transport.c
Wyświetl plik

@ -59,12 +59,12 @@ static inline void esp_gdbstub_uart_init(void)
case 0:
gdb_uart = &UART0;
break;
#if CONFIG_SOC_UART_NUM > 1
#if SOC_UART_HP_NUM > 1
case 1:
gdb_uart = &UART1;
break;
#endif
#if CONFIG_SOC_UART_NUM > 2
#if SOC_UART_HP_NUM > 2
case 2:
gdb_uart = &UART2;
break;

4
components/esp_hw_support/CMakeLists.txt
Wyświetl plik

@ -35,6 +35,10 @@ if(NOT BOOTLOADER_BUILD)
"port/${target}/esp_clk_tree.c"
"port/esp_clk_tree_common.c")
if(CONFIG_SOC_LP_PERIPHERALS_SUPPORTED)
list(APPEND srcs "lp_periph_ctrl.c")
endif()
if(CONFIG_SOC_ADC_SUPPORTED)
list(APPEND srcs "adc_share_hw_ctrl.c")
endif()

59
components/esp_hw_support/include/esp_private/lp_periph_ctrl.h 100644
Wyświetl plik

@ -0,0 +1,59 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/periph_defs.h"
#include "soc/clk_tree_defs.h"
#include "soc/soc_caps.h"
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_LP_PERIPHERALS_SUPPORTED
/**
* @brief Enable LP peripheral module by un-gating the clock and de-asserting the reset signal.
*
* @param[in] lp_periph LP peripheral module
*
* @note If @c lp_periph_module_enable() is called a number of times,
* @c lp_periph_module_disable() has to be called the same number of times,
* in order to put the peripheral into disabled state.
*/
void lp_periph_module_enable(lp_periph_module_t lp_periph);
/**
* @brief Disable LP peripheral module by gating the clock and asserting the reset signal.
*
* @param[in] lp_periph LP peripheral module
*
* @note If @c lp_periph_module_enable() is called a number of times,
* @c lp_periph_module_disable() has to be called the same number of times,
* in order to put the peripheral into disabled state.
*/
void lp_periph_module_disable(lp_periph_module_t lp_periph);
/**
* @brief Reset LP peripheral module by asserting and de-asserting the reset signal.
*
* @param[in] lp_periph LP peripheral module
*
* @note Calling this function does not enable or disable the clock for the module.
*/
void lp_periph_module_reset(lp_periph_module_t lp_periph);
/**
* @brief Set LP peripheral module clock source.
*
* @param[in] lp_periph LP peripheral module
* @param[in] clk_src Module clock source, check soc/clk_tree_defs.h for the available clock sources for each LP peripheral
*/
void lp_periph_set_clk_src(lp_periph_module_t lp_periph, soc_module_clk_t clk_src);
#endif
#ifdef __cplusplus
}
#endif

49
components/esp_hw_support/lp_periph_ctrl.c 100644
Wyświetl plik

@ -0,0 +1,49 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "freertos/FreeRTOS.h"
#include "esp_private/lp_periph_ctrl.h"
#include "hal/lp_periph_clk_ctrl_ll.h"
static portMUX_TYPE lp_periph_spinlock = portMUX_INITIALIZER_UNLOCKED;
static uint8_t ref_counts[LP_PERIPH_MODULE_MAX] = {0};
void lp_periph_module_enable(lp_periph_module_t lp_periph)
{
portENTER_CRITICAL(&lp_periph_spinlock);
if (ref_counts[lp_periph] == 0) {
// Enable clock and clear reset
lp_periph_ll_enable_clk_clear_rst(lp_periph);
}
ref_counts[lp_periph]++;
portEXIT_CRITICAL(&lp_periph_spinlock);
}
void lp_periph_module_disable(lp_periph_module_t lp_periph)
{
portENTER_CRITICAL(&lp_periph_spinlock);
ref_counts[lp_periph]--;
if (ref_counts[lp_periph] == 0) {
// Disable clock and set reset
lp_periph_ll_disable_clk_set_rst(lp_periph);
}
portEXIT_CRITICAL(&lp_periph_spinlock);
}
void lp_periph_module_reset(lp_periph_module_t lp_periph)
{
portENTER_CRITICAL(&lp_periph_spinlock);
lp_periph_ll_reset(lp_periph);
portEXIT_CRITICAL(&lp_periph_spinlock);
}
void lp_periph_set_clk_src(lp_periph_module_t lp_periph, soc_module_clk_t clk_src)
{
portENTER_CRITICAL(&lp_periph_spinlock);
lp_periph_ll_set_clk_src(lp_periph, clk_src);
portEXIT_CRITICAL(&lp_periph_spinlock);
}

6
components/esp_hw_support/sleep_modes.c
Wyświetl plik

@ -386,7 +386,7 @@ void esp_deep_sleep_deregister_hook(esp_deep_sleep_cb_t old_dslp_cb)
// [refactor-todo] provide target logic for body of uart functions below
static void IRAM_ATTR flush_uarts(void)
{
for (int i = 0; i < SOC_UART_NUM; ++i) {
for (int i = 0; i < SOC_UART_HP_NUM; ++i) {
#ifdef CONFIG_IDF_TARGET_ESP32
esp_rom_uart_tx_wait_idle(i);
#else
@ -405,7 +405,7 @@ static uint32_t s_suspended_uarts_bmap = 0;
static IRAM_ATTR void suspend_uarts(void)
{
s_suspended_uarts_bmap = 0;
for (int i = 0; i < SOC_UART_NUM; ++i) {
for (int i = 0; i < SOC_UART_HP_NUM; ++i) {
#ifndef CONFIG_IDF_TARGET_ESP32
if (!periph_ll_periph_enabled(PERIPH_UART0_MODULE + i)) {
continue;
@ -426,7 +426,7 @@ static IRAM_ATTR void suspend_uarts(void)
static void IRAM_ATTR resume_uarts(void)
{
for (int i = 0; i < SOC_UART_NUM; ++i) {
for (int i = 0; i < SOC_UART_HP_NUM; ++i) {
if (s_suspended_uarts_bmap & 0x1) {
uart_ll_force_xon(i);
}

2
components/esp_pm/pm_impl.c
Wyświetl plik

@ -714,7 +714,7 @@ void esp_pm_impl_init(void)
#endif // SOC_UART_SUPPORT_xxx
while(!uart_ll_is_tx_idle(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM)));
/* When DFS is enabled, override system setting and use REFTICK as UART clock source */
uart_ll_set_sclk(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM), clk_source);
uart_ll_set_sclk(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM), (soc_module_clk_t)clk_source);
uint32_t sclk_freq;
esp_err_t err = uart_get_sclk_freq(clk_source, &sclk_freq);

2
components/esp_system/test_apps/esp_system_unity_tests/main/test_sleep.c
Wyświetl plik

@ -228,7 +228,7 @@ TEST_CASE("light sleep and frequency switching", "[deepsleep]")
#elif SOC_UART_SUPPORT_XTAL_CLK
clk_source = UART_SCLK_XTAL;
#endif
uart_ll_set_sclk(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM), clk_source);
uart_ll_set_sclk(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM), (soc_module_clk_t)clk_source);
uint32_t sclk_freq;
TEST_ESP_OK(uart_get_sclk_freq(clk_source, &sclk_freq));

2
components/espcoredump/src/core_dump_uart.c
Wyświetl plik

@ -4,7 +4,7 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include <string.h>
#include "soc/uart_periph.h"
#include "soc/uart_reg.h"
#include "soc/gpio_periph.h"
#include "driver/gpio.h"
#include "hal/gpio_hal.h"

13
components/hal/esp32/include/hal/rtc_io_ll.h
Wyświetl plik

@ -38,6 +38,17 @@ typedef enum {
RTCIO_OUTPUT_OD = 0x1, /*!< RTCIO output mode is open-drain. */
} rtcio_ll_out_mode_t;
/**
* @brief Select a RTC IOMUX function for the RTC IO
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
* @param func Function to assign to the pin
*/
static inline void rtcio_ll_iomux_func_sel(int rtcio_num, int func)
{
SET_PERI_REG_BITS(rtc_io_desc[rtcio_num].reg, 0x3, func, rtc_io_desc[rtcio_num].func);
}
/**
* @brief Select the rtcio function.
*
@ -51,7 +62,7 @@ static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func)
// 0: GPIO connected to digital GPIO module. 1: GPIO connected to analog RTC module.
SET_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, (rtc_io_desc[rtcio_num].mux));
//0:RTC FUNCTION 1,2,3:Reserved
SET_PERI_REG_BITS(rtc_io_desc[rtcio_num].reg, RTC_IO_TOUCH_PAD1_FUN_SEL_V, RTCIO_LL_PIN_FUNC, rtc_io_desc[rtcio_num].func);
rtcio_ll_iomux_func_sel(rtcio_num, RTCIO_LL_PIN_FUNC);
} else if (func == RTCIO_FUNC_DIGITAL) {
CLEAR_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, (rtc_io_desc[rtcio_num].mux));
}

31
components/hal/esp32/include/hal/uart_ll.h
Wyświetl plik

@ -10,9 +10,10 @@
#pragma once
#include <stdlib.h>
#include "hal/misc.h"
#include "esp_attr.h"
#include "soc/uart_periph.h"
#include "soc/uart_reg.h"
#include "soc/uart_struct.h"
#include "hal/uart_types.h"
@ -23,7 +24,7 @@ extern "C" {
// The default fifo depth
#define UART_LL_FIFO_DEF_LEN (SOC_UART_FIFO_LEN)
// Get UART hardware instance with giving uart num
#define UART_LL_GET_HW(num) (((num) == 0) ? (&UART0) : (((num) == 1) ? (&UART1) : (&UART2)))
#define UART_LL_GET_HW(num) (((num) == UART_NUM_0) ? (&UART0) : (((num) == UART_NUM_1) ? (&UART1) : (&UART2)))
// The timeout calibration factor when using ref_tick
#define UART_LL_TOUT_REF_FACTOR_DEFAULT (8)
@ -63,9 +64,19 @@ typedef enum {
*
* @return None.
*/
FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, uart_sclk_t source_clk)
FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, soc_module_clk_t source_clk)
{
hw->conf0.tick_ref_always_on = (source_clk == UART_SCLK_APB) ? 1 : 0;
switch (source_clk) {
case UART_SCLK_REF_TICK:
hw->conf0.tick_ref_always_on = 0;
break;
case UART_SCLK_APB:
hw->conf0.tick_ref_always_on = 1;
break;
default:
// Invalid UART clock source
abort();
}
}
/**
@ -76,9 +87,17 @@ FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, uart_sclk_t source_clk)
*
* @return None.
*/
FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, uart_sclk_t* source_clk)
FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source_clk)
{
*source_clk = hw->conf0.tick_ref_always_on ? UART_SCLK_APB : UART_SCLK_REF_TICK;
switch (hw->conf0.tick_ref_always_on) {
default:
case 0:
*source_clk = UART_SCLK_REF_TICK;
break;
case 1:
*source_clk = UART_SCLK_APB;
break;
}
}
/**

13
components/hal/esp32c2/include/hal/uart_ll.h
Wyświetl plik

@ -10,7 +10,8 @@
#pragma once
#include "hal/uart_types.h"
#include "soc/uart_periph.h"
#include "soc/uart_reg.h"
#include "soc/uart_struct.h"
#include "hal/clk_tree_ll.h"
#include "esp_attr.h"
@ -21,7 +22,7 @@ extern "C" {
// The default fifo depth
#define UART_LL_FIFO_DEF_LEN (SOC_UART_FIFO_LEN)
// Get UART hardware instance with giving uart num
#define UART_LL_GET_HW(num) (((num) == 0) ? (&UART0) : (&UART1))
#define UART_LL_GET_HW(num) (((num) == UART_NUM_0) ? (&UART0) : (&UART1))
#define UART_LL_MIN_WAKEUP_THRESH (2)
#define UART_LL_INTR_MASK (0x7ffff) //All interrupt mask
@ -103,10 +104,9 @@ FORCE_INLINE_ATTR void uart_ll_sclk_disable(uart_dev_t *hw)
*
* @return None.
*/
FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, uart_sclk_t source_clk)
FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, soc_module_clk_t source_clk)
{
switch (source_clk) {
default:
case UART_SCLK_PLL_F40M:
hw->clk_conf.sclk_sel = 1;
break;
@ -116,6 +116,9 @@ FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, uart_sclk_t source_clk)
case UART_SCLK_XTAL:
hw->clk_conf.sclk_sel = 3;
break;
default:
// Invalid UART clock source
abort();
}
}
@ -127,7 +130,7 @@ FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, uart_sclk_t source_clk)
*
* @return None.
*/
FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, uart_sclk_t *source_clk)
FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source_clk)
{
switch (hw->clk_conf.sclk_sel) {
default:

13
components/hal/esp32c3/include/hal/uart_ll.h
Wyświetl plik

@ -10,9 +10,10 @@
#pragma once
#include <stdlib.h>
#include "hal/misc.h"
#include "hal/uart_types.h"
#include "soc/uart_periph.h"
#include "soc/uart_reg.h"
#include "soc/uart_struct.h"
#include "esp_attr.h"
@ -23,7 +24,7 @@ extern "C" {
// The default fifo depth
#define UART_LL_FIFO_DEF_LEN (SOC_UART_FIFO_LEN)
// Get UART hardware instance with giving uart num
#define UART_LL_GET_HW(num) (((num) == 0) ? (&UART0) : (&UART1))
#define UART_LL_GET_HW(num) (((num) == UART_NUM_0) ? (&UART0) : (&UART1))
#define UART_LL_MIN_WAKEUP_THRESH (2)
#define UART_LL_INTR_MASK (0x7ffff) //All interrupt mask
@ -105,10 +106,9 @@ FORCE_INLINE_ATTR void uart_ll_sclk_disable(uart_dev_t *hw)
*
* @return None.
*/
FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, uart_sclk_t source_clk)
FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, soc_module_clk_t source_clk)
{
switch (source_clk) {
default:
case UART_SCLK_APB:
hw->clk_conf.sclk_sel = 1;
break;
@ -118,6 +118,9 @@ FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, uart_sclk_t source_clk)
case UART_SCLK_XTAL:
hw->clk_conf.sclk_sel = 3;
break;
default:
// Invalid UART clock source
abort();
}
}
@ -129,7 +132,7 @@ FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, uart_sclk_t source_clk)
*
* @return None.
*/
FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, uart_sclk_t *source_clk)
FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source_clk)
{
switch (hw->clk_conf.sclk_sel) {
default:

13
components/hal/esp32c6/include/hal/clk_gate_ll.h
Wyświetl plik

@ -11,7 +11,6 @@
#include "soc/periph_defs.h"
#include "soc/pcr_reg.h"
#include "soc/soc.h"
#include "soc/lpperi_reg.h"
#include "esp_attr.h"
#ifdef __cplusplus
@ -79,9 +78,6 @@ static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph)
return PCR_SDIO_SLAVE_CLK_EN;
case PERIPH_REGDMA_MODULE:
return PCR_REGDMA_CLK_EN;
//TODO: LP_PERIPH modules are added temporarily and will be moved to a separate API (IDF-7374).
case PERIPH_LP_I2C0_MODULE:
return LPPERI_LP_EXT_I2C_CK_EN;
// case PERIPH_RNG_MODULE:
// return PCR_WIFI_CLK_RNG_EN;
// case PERIPH_WIFI_MODULE:
@ -175,9 +171,6 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en
return PCR_SDIO_SLAVE_RST_EN;
case PERIPH_REGDMA_MODULE:
return PCR_REGDMA_RST_EN;
//TODO: LP_PERIPH modules are added temporarily and will be moved to a separate API (IDF-7374).
case PERIPH_LP_I2C0_MODULE:
return LPPERI_LP_EXT_I2C_RESET_EN;
// case PERIPH_RNG_MODULE:
// return PCR_WIFI_CLK_RNG_EN;
// case PERIPH_WIFI_MODULE:
@ -264,9 +257,6 @@ static uint32_t periph_ll_get_clk_en_reg(periph_module_t periph)
return PCR_SDIO_SLAVE_CONF_REG;
case PERIPH_REGDMA_MODULE:
return PCR_REGDMA_CONF_REG;
//TODO: LP_PERIPH modules are added temporarily and will be moved to a separate API (IDF-7374).
case PERIPH_LP_I2C0_MODULE:
return LPPERI_CLK_EN_REG;
default:
return 0;
}
@ -333,9 +323,6 @@ static uint32_t periph_ll_get_rst_en_reg(periph_module_t periph)
return PCR_SDIO_SLAVE_CONF_REG;
case PERIPH_REGDMA_MODULE:
return PCR_REGDMA_CONF_REG;
//TODO: LP_PERIPH modules are added temporarily and will be moved to a separate API (IDF-7374).
case PERIPH_LP_I2C0_MODULE:
return LPPERI_RESET_EN_REG;
default:
return 0;
}

29
components/hal/esp32c6/include/hal/i2c_ll.h
Wyświetl plik

@ -17,7 +17,6 @@
#include "soc/pcr_struct.h"
#include "hal/i2c_types.h"
#include "soc/clk_tree_defs.h"
#include "soc/lp_clkrst_struct.h"
#ifdef __cplusplus
extern "C" {
@ -675,33 +674,6 @@ static inline void i2c_ll_set_source_clk(i2c_dev_t *hw, i2c_clock_source_t src_c
PCR.i2c_sclk_conf.i2c_sclk_sel = (src_clk == I2C_CLK_SRC_RC_FAST) ? 1 : 0;
}
#if SOC_LP_I2C_SUPPORTED
/**
* @brief Set LP I2C source clock
*
* @param hw Address offset of the LP I2C peripheral registers
* @param src_clk Source clock for the LP I2C peripheral
*
* @return None
*/
static inline void lp_i2c_ll_set_source_clk(i2c_dev_t *hw, soc_periph_lp_i2c_clk_src_t src_clk)
{
(void)hw;
// src_clk : (0) for LP_FAST_CLK (RTC Fast), (1) for XTAL_D2_CLK
switch (src_clk) {
case LP_I2C_SCLK_LP_FAST:
LP_CLKRST.lpperi.lp_i2c_clk_sel = 0;
break;
case LP_I2C_SCLK_XTAL_D2:
LP_CLKRST.lpperi.lp_i2c_clk_sel = 1;
break;
default:
// Invalid source clock selected
abort();
}
}
#endif /* SOC_LP_I2C_SUPPORTED */
/**
* @brief Enable I2C peripheral controller clock
*
@ -771,6 +743,7 @@ static inline volatile void *i2c_ll_get_interrupt_status_reg(i2c_dev_t *dev)
return &dev->int_status;
}
//////////////////////////////////////////Deprecated Functions//////////////////////////////////////////////////////////
/////////////////////////////The following functions are only used by the legacy driver/////////////////////////////////
/////////////////////////////They might be removed in the next major release (ESP-IDF 6.0)//////////////////////////////

105
components/hal/esp32c6/include/hal/lp_periph_clk_ctrl_ll.h 100644
Wyświetl plik

@ -0,0 +1,105 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdlib.h>
#include "soc/periph_defs.h"
#include "soc/clk_tree_defs.h"
#include "soc/soc.h"
#include "soc/lpperi_reg.h"
#include "soc/lp_clkrst_reg.h"
#ifdef __cplusplus
extern "C" {
#endif
static uint32_t lp_periph_ll_get_clk_en_mask(lp_periph_module_t lp_periph)
{
switch (lp_periph) {
case LP_PERIPH_I2C0_MODULE:
return LPPERI_LP_EXT_I2C_CK_EN;
case LP_PERIPH_UART0_MODULE:
return LPPERI_LP_UART_CK_EN;
default:
// Unsupported LP peripherals
abort();
}
}
static uint32_t lp_periph_ll_get_rst_en_mask(lp_periph_module_t lp_periph)
{
switch (lp_periph) {
case LP_PERIPH_I2C0_MODULE:
return LPPERI_LP_EXT_I2C_RESET_EN;
case LP_PERIPH_UART0_MODULE:
return LPPERI_LP_UART_RESET_EN;
default:
// Unsupported LP peripherals
abort();
}
}
static inline void lp_periph_ll_enable_clk_clear_rst(lp_periph_module_t lp_periph)
{
SET_PERI_REG_MASK(LPPERI_CLK_EN_REG, lp_periph_ll_get_clk_en_mask(lp_periph));
CLEAR_PERI_REG_MASK(LPPERI_RESET_EN_REG, lp_periph_ll_get_rst_en_mask(lp_periph));
}
static inline void lp_periph_ll_disable_clk_set_rst(lp_periph_module_t lp_periph)
{
CLEAR_PERI_REG_MASK(LPPERI_CLK_EN_REG, lp_periph_ll_get_clk_en_mask(lp_periph));
SET_PERI_REG_MASK(LPPERI_RESET_EN_REG, lp_periph_ll_get_rst_en_mask(lp_periph));
}
static inline void lp_periph_ll_reset(lp_periph_module_t lp_periph)
{
uint32_t bit_mask = lp_periph_ll_get_rst_en_mask(lp_periph);
SET_PERI_REG_MASK(LPPERI_RESET_EN_REG, bit_mask);
CLEAR_PERI_REG_MASK(LPPERI_RESET_EN_REG, bit_mask);
}
static inline void lp_periph_ll_set_clk_src(lp_periph_module_t lp_periph, soc_module_clk_t clk_src)
{
uint32_t val;
switch (lp_periph) {
case LP_PERIPH_I2C0_MODULE:
switch (clk_src) {
case LP_I2C_SCLK_LP_FAST:
val = 0;
break;
case LP_I2C_SCLK_XTAL_D2:
val = 1;
break;
default:
// Invalid LP_I2C clock source
abort();
}
REG_SET_FIELD(LP_CLKRST_LPPERI_REG, LP_CLKRST_LP_I2C_CLK_SEL, val);
break;
case LP_PERIPH_UART0_MODULE:
switch (clk_src) {
case LP_UART_SCLK_LP_FAST:
val = 0;
break;
case LP_UART_SCLK_XTAL_D2:
val = 1;
break;
default:
// Invalid LP_UART clock source
abort();
}
REG_SET_FIELD(LP_CLKRST_LPPERI_REG, LP_CLKRST_LP_UART_CLK_SEL, val);
break;
default:
// Unsupported LP peripherals
abort();
}
}
#ifdef __cplusplus
}
#endif

13
components/hal/esp32c6/include/hal/rtc_io_ll.h
Wyświetl plik

@ -46,6 +46,17 @@ typedef enum {
RTCIO_OUTPUT_OD = 0x1, /*!< RTCIO output mode is open-drain. */
} rtcio_ll_out_mode_t;
/**
* @brief Select a RTC IOMUX function for the RTC IO
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
* @param func Function to assign to the pin
*/
static inline void rtcio_ll_iomux_func_sel(int rtcio_num, int func)
{
LP_IO.gpio[rtcio_num].mcu_sel = func;
}
/**
* @brief Select the rtcio function.
*
@ -64,7 +75,7 @@ static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func)
sel_mask |= BIT(rtcio_num);
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.gpio_mux, gpio_mux_sel, sel_mask);
//0:RTC FUNCTION 1,2,3:Reserved
LP_IO.gpio[rtcio_num].mcu_sel = RTCIO_LL_PIN_FUNC;
rtcio_ll_iomux_func_sel(rtcio_num, RTCIO_LL_PIN_FUNC);
} else if (func == RTCIO_FUNC_DIGITAL) {
// Clear the bit to use digital GPIO module
uint32_t sel_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.gpio_mux, gpio_mux_sel);

190
components/hal/esp32c6/include/hal/uart_ll.h
Wyświetl plik

@ -12,9 +12,12 @@
#include "hal/misc.h"
#include "hal/uart_types.h"
#include "soc/uart_periph.h"
#include "soc/uart_reg.h"
#include "soc/uart_struct.h"
#include "soc/lp_uart_reg.h"
#include "soc/pcr_struct.h"
#include "soc/lp_clkrst_struct.h"
#include "hal/assert.h"
#ifdef __cplusplus
extern "C" {
@ -22,8 +25,11 @@ extern "C" {
// The default fifo depth
#define UART_LL_FIFO_DEF_LEN (SOC_UART_FIFO_LEN)
#define LP_UART_LL_FIFO_DEF_LEN (SOC_LP_UART_FIFO_LEN)
// Get UART hardware instance with giving uart num
#define UART_LL_GET_HW(num) (((num) == 0) ? (&UART0) : (&UART1))
#define UART_LL_GET_HW(num) (((num) == UART_NUM_0) ? (&UART0) : (((num) == UART_NUM_1) ? (&UART1) : (&LP_UART)))
#define UART_LL_REG_FIELD_BIT_SHIFT(hw) (((hw) == &LP_UART) ? 3 : 0)
#define UART_LL_MIN_WAKEUP_THRESH (2)
#define UART_LL_INTR_MASK (0x7ffff) //All interrupt mask
@ -77,6 +83,30 @@ typedef enum {
UART_INTR_WAKEUP = (0x1 << 19),
} uart_intr_t;
/****************************************** LP_UART Specific ********************************************/
/**
* @brief Get the LP_UART source clock.
*
* @param hw Beginning address of the peripheral registers.
* @param source_clk Current LP_UART clock source, one in soc_periph_lp_uart_clk_src_t.
*/
static inline void lp_uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source_clk)
{
(void)hw;
switch (LP_CLKRST.lpperi.lp_uart_clk_sel) {
default:
case 0:
*source_clk = LP_UART_SCLK_LP_FAST;
break;
case 1:
*source_clk = LP_UART_SCLK_XTAL_D2;
break;
}
}
// LP_UART clock control LL functions are located in lp_periph_clk_ctrl_ll.h
/*************************************** General LL functions ******************************************/
/**
* @brief Sync the update to UART core clock domain
*
@ -100,7 +130,13 @@ static inline void uart_ll_update(uart_dev_t *hw)
*/
static inline void uart_ll_set_reset_core(uart_dev_t *hw, bool core_rst_en)
{
UART_LL_PCR_REG_SET(hw, conf, rst_en, core_rst_en);
if ((hw) != &LP_UART) {
UART_LL_PCR_REG_SET(hw, conf, rst_en, core_rst_en);
} else {
// LP_UART reset shares the same register with other LP peripherals
// Needs to be protected with a lock, therefore, it has its unique LL function, and must be called from lp_periph_ctrl.c
abort();
}
}
/**
@ -112,7 +148,13 @@ static inline void uart_ll_set_reset_core(uart_dev_t *hw, bool core_rst_en)
*/
static inline void uart_ll_sclk_enable(uart_dev_t *hw)
{
UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_en, 1);
if ((hw) != &LP_UART) {
UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_en, 1);
} else {
// LP_UART clk_en shares the same register with other LP peripherals
// Needs to be protected with a lock, therefore, it has its unique LL function, and must be called from lp_periph_ctrl.c
abort();
}
}
/**
@ -124,7 +166,13 @@ static inline void uart_ll_sclk_enable(uart_dev_t *hw)
*/
static inline void uart_ll_sclk_disable(uart_dev_t *hw)
{
UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_en, 0);
if ((hw) != &LP_UART) {
UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_en, 0);
} else {
// LP_UART clk_en shares the same register with other LP peripherals
// Needs to be protected with a lock, therefore, it has its unique LL function, and must be called from lp_periph_ctrl.c
abort();
}
}
/**
@ -136,19 +184,29 @@ static inline void uart_ll_sclk_disable(uart_dev_t *hw)
*
* @return None.
*/
static inline void uart_ll_set_sclk(uart_dev_t *hw, uart_sclk_t source_clk)
static inline void uart_ll_set_sclk(uart_dev_t *hw, soc_module_clk_t source_clk)
{
switch (source_clk) {
default:
if ((hw) != &LP_UART) {
uint32_t sel_value = 0;
switch (source_clk) {
case UART_SCLK_PLL_F80M:
UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_sel, 1);
sel_value = 1;
break;
case UART_SCLK_RTC:
UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_sel, 2);
sel_value = 2;
break;
case UART_SCLK_XTAL:
UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_sel, 3);
sel_value = 3;
break;
default:
// Invalid HP_UART clock source
abort();
}
UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_sel, sel_value);
} else {
// LP_UART clk_sel shares the same register with other LP peripherals
// Needs to be protected with a lock, therefore, it has its unique LL function, and must be called from lp_periph_ctrl.c
abort();
}
}
@ -160,9 +218,10 @@ static inline void uart_ll_set_sclk(uart_dev_t *hw, uart_sclk_t source_clk)
*
* @return None.
*/
static inline void uart_ll_get_sclk(uart_dev_t *hw, uart_sclk_t *source_clk)
static inline void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source_clk)
{
switch (UART_LL_PCR_REG_GET(hw, sclk_conf, sclk_sel)) {
if ((hw) != &LP_UART) {
switch (UART_LL_PCR_REG_GET(hw, sclk_conf, sclk_sel)) {
default:
case 1:
*source_clk = UART_SCLK_PLL_F80M;
@ -173,6 +232,9 @@ static inline void uart_ll_get_sclk(uart_dev_t *hw, uart_sclk_t *source_clk)
case 3:
*source_clk = UART_SCLK_XTAL;
break;
}
} else {
lp_uart_ll_get_sclk(hw, source_clk);
}
}
@ -196,7 +258,11 @@ static inline void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t
// an integer part and a fractional part.
hw->clkdiv_sync.clkdiv_int = clk_div >> 4;
hw->clkdiv_sync.clkdiv_frag = clk_div & 0xf;
UART_LL_PCR_REG_U32_SET(hw, sclk_conf, sclk_div_num, sclk_div - 1);
if ((hw) == &LP_UART) {
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clk_conf, sclk_div_num, sclk_div - 1);
} else {
UART_LL_PCR_REG_U32_SET(hw, sclk_conf, sclk_div_num, sclk_div - 1);
}
#undef DIV_UP
uart_ll_update(hw);
}
@ -213,7 +279,13 @@ static inline uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_freq)
{
typeof(hw->clkdiv_sync) div_reg;
div_reg.val = hw->clkdiv_sync.val;
return ((sclk_freq << 4)) / (((div_reg.clkdiv_int << 4) | div_reg.clkdiv_frag) * (UART_LL_PCR_REG_U32_GET(hw, sclk_conf, sclk_div_num) + 1));
int sclk_div;
if ((hw) == &LP_UART) {
sclk_div = HAL_FORCE_READ_U32_REG_FIELD(hw->clk_conf, sclk_div_num) + 1;
} else {
sclk_div = UART_LL_PCR_REG_U32_GET(hw, sclk_conf, sclk_div_num) + 1;
}
return ((sclk_freq << 4)) / (((div_reg.clkdiv_int << 4) | div_reg.clkdiv_frag) * sclk_div);
}
/**
@ -362,7 +434,7 @@ static inline void uart_ll_txfifo_rst(uart_dev_t *hw)
*/
static inline uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw)
{
return hw->status.rxfifo_cnt;
return (hw->status.rxfifo_cnt) >> UART_LL_REG_FIELD_BIT_SHIFT(hw);
}
/**
@ -374,7 +446,9 @@ static inline uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw)
*/
static inline uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw)
{
return UART_LL_FIFO_DEF_LEN - hw->status.txfifo_cnt;
uint32_t total_fifo_len = ((hw) == &LP_UART) ? LP_UART_LL_FIFO_DEF_LEN : UART_LL_FIFO_DEF_LEN;
uint32_t txfifo_len = (hw->status.txfifo_cnt) >> UART_LL_REG_FIELD_BIT_SHIFT(hw);
return (total_fifo_len - txfifo_len);
}
/**
@ -443,13 +517,13 @@ static inline void uart_ll_get_parity(uart_dev_t *hw, uart_parity_t *parity_mode
* it will produce rxfifo_full_int_raw interrupt.
*
* @param hw Beginning address of the peripheral registers.
* @param full_thrhd The full threshold value of the rxfifo. `full_thrhd` should be less than `UART_LL_FIFO_DEF_LEN`.
* @param full_thrhd The full threshold value of the rxfifo. `full_thrhd` should be less than `(LP_)UART_LL_FIFO_DEF_LEN`.
*
* @return None.
*/
static inline void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full_thrhd)
{
hw->conf1.rxfifo_full_thrhd = full_thrhd;
hw->conf1.rxfifo_full_thrhd = full_thrhd << UART_LL_REG_FIELD_BIT_SHIFT(hw);
}
/**
@ -463,7 +537,7 @@ static inline void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full_thr
*/
static inline void uart_ll_set_txfifo_empty_thr(uart_dev_t *hw, uint16_t empty_thrhd)
{
hw->conf1.txfifo_empty_thrhd = empty_thrhd;
hw->conf1.txfifo_empty_thrhd = empty_thrhd << UART_LL_REG_FIELD_BIT_SHIFT(hw);
}
/**
@ -527,7 +601,7 @@ static inline void uart_ll_set_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_
{
//only when UART_HW_FLOWCTRL_RTS is set , will the rx_thresh value be set.
if (flow_ctrl & UART_HW_FLOWCTRL_RTS) {
hw->hwfc_conf_sync.rx_flow_thrhd = rx_thrs;
hw->hwfc_conf_sync.rx_flow_thrhd = rx_thrs << UART_LL_REG_FIELD_BIT_SHIFT(hw);
hw->hwfc_conf_sync.rx_flow_en = 1;
} else {
hw->hwfc_conf_sync.rx_flow_en = 0;
@ -573,8 +647,8 @@ static inline void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl_t *
if (sw_flow_ctrl_en) {
hw->swfc_conf0_sync.xonoff_del = 1;
hw->swfc_conf0_sync.sw_flow_con_en = 1;
hw->swfc_conf1.xon_threshold = flow_ctrl->xon_thrd;
hw->swfc_conf1.xoff_threshold = flow_ctrl->xoff_thrd;
hw->swfc_conf1.xon_threshold = (flow_ctrl->xon_thrd) << UART_LL_REG_FIELD_BIT_SHIFT(hw);
hw->swfc_conf1.xoff_threshold = (flow_ctrl->xoff_thrd) << UART_LL_REG_FIELD_BIT_SHIFT(hw);
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0_sync, xon_char, flow_ctrl->xon_char);
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0_sync, xoff_char, flow_ctrl->xoff_char);
} else {
@ -671,6 +745,10 @@ static inline void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_thrd)
*/
static inline void uart_ll_set_mode_normal(uart_dev_t *hw)
{
// This function is only for HP_UART use
// LP_UART can only work in normal mode
// lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct
hw->rs485_conf_sync.rs485_en = 0;
hw->rs485_conf_sync.rs485tx_rx_en = 0;
hw->rs485_conf_sync.rs485rxby_tx_en = 0;
@ -687,6 +765,10 @@ static inline void uart_ll_set_mode_normal(uart_dev_t *hw)
*/
static inline void uart_ll_set_mode_rs485_app_ctrl(uart_dev_t *hw)
{
// This function is only for HP_UART use
// LP_UART can only work in normal mode
// lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct
// Application software control, remove echo
hw->rs485_conf_sync.rs485rxby_tx_en = 1;
hw->conf0_sync.irda_en = 0;
@ -707,6 +789,10 @@ static inline void uart_ll_set_mode_rs485_app_ctrl(uart_dev_t *hw)
*/
static inline void uart_ll_set_mode_rs485_half_duplex(uart_dev_t *hw)
{
// This function is only for HP_UART use
// LP_UART can only work in normal mode
// lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct
// Enable receiver, sw_rts = 1 generates low level on RTS pin
hw->conf0_sync.sw_rts = 1;
// Half duplex mode
@ -730,6 +816,10 @@ static inline void uart_ll_set_mode_rs485_half_duplex(uart_dev_t *hw)
*/
static inline void uart_ll_set_mode_collision_detect(uart_dev_t *hw)
{
// This function is only for HP_UART use
// LP_UART can only work in normal mode
// lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct
hw->conf0_sync.irda_en = 0;
// Enable full-duplex mode
hw->rs485_conf_sync.rs485tx_rx_en = 1;
@ -751,6 +841,10 @@ static inline void uart_ll_set_mode_collision_detect(uart_dev_t *hw)
*/
static inline void uart_ll_set_mode_irda(uart_dev_t *hw)
{
// This function is only for HP_UART use
// LP_UART can only work in normal mode
// lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct
hw->rs485_conf_sync.rs485_en = 0;
hw->rs485_conf_sync.rs485tx_rx_en = 0;
hw->rs485_conf_sync.rs485rxby_tx_en = 0;
@ -775,15 +869,19 @@ static inline void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode)
uart_ll_set_mode_normal(hw);
break;
case UART_MODE_RS485_COLLISION_DETECT:
// Only HP_UART support this mode
uart_ll_set_mode_collision_detect(hw);
break;
case UART_MODE_RS485_APP_CTRL:
// Only HP_UART support this mode
uart_ll_set_mode_rs485_app_ctrl(hw);
break;
case UART_MODE_RS485_HALF_DUPLEX:
// Only HP_UART support this mode
uart_ll_set_mode_rs485_half_duplex(hw);
break;
case UART_MODE_IRDA:
// Only HP_UART support this mode
uart_ll_set_mode_irda(hw);
break;
}
@ -838,7 +936,7 @@ static inline void uart_ll_get_data_bit_num(uart_dev_t *hw, uart_word_length_t *
*/
static inline bool uart_ll_is_tx_idle(uart_dev_t *hw)
{
return ((hw->status.txfifo_cnt == 0) && (hw->fsm_status.st_utx_out == 0));
return ((((hw->status.txfifo_cnt) >> UART_LL_REG_FIELD_BIT_SHIFT(hw)) == 0) && (hw->fsm_status.st_utx_out == 0));
}
/**
@ -900,6 +998,9 @@ static inline void uart_ll_xon_force_on(uart_dev_t *hw, bool always_on)
*/
static inline void uart_ll_inverse_signal(uart_dev_t *hw, uint32_t inv_mask)
{
// LP_UART does not support UART_SIGNAL_IRDA_TX_INV and UART_SIGNAL_IRDA_RX_INV
// lp_uart_dev_t has no these fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct
typeof(hw->conf0_sync) conf0_reg;
conf0_reg.val = hw->conf0_sync.val;
conf0_reg.irda_tx_inv = (inv_mask & UART_SIGNAL_IRDA_TX_INV) ? 1 : 0;
@ -963,7 +1064,7 @@ static inline uint16_t uart_ll_get_rx_tout_thr(uart_dev_t *hw)
*/
static inline uint16_t uart_ll_max_tout_thrd(uart_dev_t *hw)
{
return UART_RX_TOUT_THRHD_V;
return ((hw) == &LP_UART) ? LP_UART_RX_TOUT_THRHD_V : UART_RX_TOUT_THRHD_V;
}
/**
@ -974,6 +1075,9 @@ static inline uint16_t uart_ll_max_tout_thrd(uart_dev_t *hw)
*/
static inline void uart_ll_set_autobaud_en(uart_dev_t *hw, bool enable)
{
// LP_UART does not support autobaud
// lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct
hw->conf0_sync.autobaud_en = enable ? 1 : 0;
uart_ll_update(hw);
}
@ -985,6 +1089,9 @@ static inline void uart_ll_set_autobaud_en(uart_dev_t *hw, bool enable)
*/
static inline uint32_t uart_ll_get_rxd_edge_cnt(uart_dev_t *hw)
{
// LP_UART does not support this feature
// lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct
return hw->rxd_cnt.rxd_edge_cnt;
}
@ -995,6 +1102,9 @@ static inline uint32_t uart_ll_get_rxd_edge_cnt(uart_dev_t *hw)
*/
static inline uint32_t uart_ll_get_pos_pulse_cnt(uart_dev_t *hw)
{
// LP_UART does not support this feature
// lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct
return hw->pospulse.posedge_min_cnt;
}
@ -1005,6 +1115,9 @@ static inline uint32_t uart_ll_get_pos_pulse_cnt(uart_dev_t *hw)
*/
static inline uint32_t uart_ll_get_neg_pulse_cnt(uart_dev_t *hw)
{
// LP_UART does not support this feature
// lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct
return hw->negpulse.negedge_min_cnt;
}
@ -1015,6 +1128,9 @@ static inline uint32_t uart_ll_get_neg_pulse_cnt(uart_dev_t *hw)
*/
static inline uint32_t uart_ll_get_high_pulse_cnt(uart_dev_t *hw)
{
// LP_UART does not support this feature
// lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct
return hw->highpulse.highpulse_min_cnt;
}
@ -1025,6 +1141,9 @@ static inline uint32_t uart_ll_get_high_pulse_cnt(uart_dev_t *hw)
*/
static inline uint32_t uart_ll_get_low_pulse_cnt(uart_dev_t *hw)
{
// LP_UART does not support this feature
// lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct
return hw->lowpulse.lowpulse_min_cnt;
}
@ -1037,9 +1156,11 @@ static inline uint32_t uart_ll_get_low_pulse_cnt(uart_dev_t *hw)
*/
static inline void uart_ll_force_xoff(uart_port_t uart_num)
{
REG_CLR_BIT(UART_SWFC_CONF0_SYNC_REG(uart_num), UART_FORCE_XON);
REG_SET_BIT(UART_SWFC_CONF0_SYNC_REG(uart_num), UART_SW_FLOW_CON_EN | UART_FORCE_XOFF);
uart_ll_update(UART_LL_GET_HW(uart_num));
uart_dev_t *hw = UART_LL_GET_HW(uart_num);
hw->swfc_conf0_sync.force_xon = 0;
hw->swfc_conf0_sync.sw_flow_con_en = 1;
hw->swfc_conf0_sync.force_xoff = 1;
uart_ll_update(hw);
}
/**
@ -1051,10 +1172,12 @@ static inline void uart_ll_force_xoff(uart_port_t uart_num)
*/
static inline void uart_ll_force_xon(uart_port_t uart_num)
{
REG_CLR_BIT(UART_SWFC_CONF0_SYNC_REG(uart_num), UART_FORCE_XOFF);
REG_SET_BIT(UART_SWFC_CONF0_SYNC_REG(uart_num), UART_FORCE_XON);
REG_CLR_BIT(UART_SWFC_CONF0_SYNC_REG(uart_num), UART_SW_FLOW_CON_EN | UART_FORCE_XON);
uart_ll_update(UART_LL_GET_HW(uart_num));
uart_dev_t *hw = UART_LL_GET_HW(uart_num);
hw->swfc_conf0_sync.force_xoff = 0;
hw->swfc_conf0_sync.force_xon = 1;
hw->swfc_conf0_sync.sw_flow_con_en = 0;
hw->swfc_conf0_sync.force_xon = 0;
uart_ll_update(hw);
}
/**
@ -1066,7 +1189,8 @@ static inline void uart_ll_force_xon(uart_port_t uart_num)
*/
static inline uint32_t uart_ll_get_fsm_status(uart_port_t uart_num)
{
return REG_GET_FIELD(UART_FSM_STATUS_REG(uart_num), UART_ST_UTX_OUT);
uart_dev_t *hw = UART_LL_GET_HW(uart_num);
return hw->fsm_status.st_utx_out;
}
/**

13
components/hal/esp32h2/include/hal/uart_ll.h
Wyświetl plik

@ -10,9 +10,10 @@
#pragma once
#include <stdlib.h>
#include "hal/misc.h"
#include "hal/uart_types.h"
#include "soc/uart_periph.h"
#include "soc/uart_reg.h"
#include "soc/uart_struct.h"
#include "soc/pcr_struct.h"
@ -23,7 +24,7 @@ extern "C" {
// The default fifo depth
#define UART_LL_FIFO_DEF_LEN (SOC_UART_FIFO_LEN)
// Get UART hardware instance with giving uart num
#define UART_LL_GET_HW(num) (((num) == 0) ? (&UART0) : (&UART1))
#define UART_LL_GET_HW(num) (((num) == UART_NUM_0) ? (&UART0) : (&UART1))
#define UART_LL_MIN_WAKEUP_THRESH (2)
#define UART_LL_INTR_MASK (0x7ffff) //All interrupt mask
@ -136,10 +137,9 @@ static inline void uart_ll_sclk_disable(uart_dev_t *hw)
*
* @return None.
*/
static inline void uart_ll_set_sclk(uart_dev_t *hw, uart_sclk_t source_clk)
static inline void uart_ll_set_sclk(uart_dev_t *hw, soc_module_clk_t source_clk)
{
switch (source_clk) {
default:
case UART_SCLK_PLL_F48M:
UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_sel, 1);
break;
@ -149,6 +149,9 @@ static inline void uart_ll_set_sclk(uart_dev_t *hw, uart_sclk_t source_clk)
case UART_SCLK_XTAL:
UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_sel, 3);
break;
default:
// Invalid UART clock source
abort();
}
}
@ -160,7 +163,7 @@ static inline void uart_ll_set_sclk(uart_dev_t *hw, uart_sclk_t source_clk)
*
* @return None.
*/
static inline void uart_ll_get_sclk(uart_dev_t *hw, uart_sclk_t *source_clk)
static inline void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source_clk)
{
switch (UART_LL_PCR_REG_GET(hw, sclk_conf, sclk_sel)) {
default:

13
components/hal/esp32s2/include/hal/rtc_io_ll.h
Wyświetl plik

@ -39,6 +39,17 @@ typedef enum {
RTCIO_OUTPUT_OD = 0x1, /*!< RTCIO output mode is open-drain. */
} rtcio_ll_out_mode_t;
/**
* @brief Select a RTC IOMUX function for the RTC IO
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
* @param func Function to assign to the pin
*/
static inline void rtcio_ll_iomux_func_sel(int rtcio_num, int func)
{
SET_PERI_REG_BITS(rtc_io_desc[rtcio_num].reg, 0x3, func, rtc_io_desc[rtcio_num].func);
}
/**
* @brief Select the rtcio function.
*
@ -53,7 +64,7 @@ static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func)
// 0: GPIO connected to digital GPIO module. 1: GPIO connected to analog RTC module.
SET_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, (rtc_io_desc[rtcio_num].mux));
//0:RTC FUNCTION 1,2,3:Reserved
SET_PERI_REG_BITS(rtc_io_desc[rtcio_num].reg, RTC_IO_TOUCH_PAD1_FUN_SEL_V, RTCIO_LL_PIN_FUNC, rtc_io_desc[rtcio_num].func);
rtcio_ll_iomux_func_sel(rtcio_num, RTCIO_LL_PIN_FUNC);
} else if (func == RTCIO_FUNC_DIGITAL) {
CLEAR_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, (rtc_io_desc[rtcio_num].mux));
SENS.sar_io_mux_conf.iomux_clk_gate_en = 0;

31
components/hal/esp32s2/include/hal/uart_ll.h
Wyświetl plik

@ -10,9 +10,10 @@
#pragma once
#include <stdlib.h>
#include "hal/misc.h"
#include "hal/uart_types.h"
#include "soc/uart_periph.h"
#include "soc/uart_reg.h"
#include "soc/uart_struct.h"
#include "esp_attr.h"
@ -23,7 +24,7 @@ extern "C" {
// The default fifo depth
#define UART_LL_FIFO_DEF_LEN (SOC_UART_FIFO_LEN)
// Get UART hardware instance with giving uart num
#define UART_LL_GET_HW(num) (((num) == 0) ? (&UART0) : (&UART1))
#define UART_LL_GET_HW(num) (((num) == UART_NUM_0) ? (&UART0) : (&UART1))
#define UART_LL_MIN_WAKEUP_THRESH (2)
#define UART_LL_INTR_MASK (0x7ffff) //All interrupt mask
@ -61,9 +62,19 @@ typedef enum {
*
* @return None.
*/
FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, uart_sclk_t source_clk)
FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, soc_module_clk_t source_clk)
{
hw->conf0.tick_ref_always_on = (source_clk == UART_SCLK_APB) ? 1 : 0;
switch (source_clk) {
case UART_SCLK_REF_TICK:
hw->conf0.tick_ref_always_on = 0;
break;
case UART_SCLK_APB:
hw->conf0.tick_ref_always_on = 1;
break;
default:
// Invalid UART clock source
abort();
}
}
/**
@ -74,9 +85,17 @@ FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, uart_sclk_t source_clk)
*
* @return None.
*/
FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, uart_sclk_t* source_clk)
FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source_clk)
{
*source_clk = hw->conf0.tick_ref_always_on ? UART_SCLK_APB : UART_SCLK_REF_TICK;
switch (hw->conf0.tick_ref_always_on) {
default:
case 0:
*source_clk = UART_SCLK_REF_TICK;
break;
case 1:
*source_clk = UART_SCLK_APB;
break;
}
}
/**

13
components/hal/esp32s3/include/hal/rtc_io_ll.h
Wyświetl plik

@ -41,6 +41,17 @@ typedef enum {
RTCIO_OUTPUT_OD = 0x1, /*!< RTCIO output mode is open-drain. */
} rtcio_ll_out_mode_t;
/**
* @brief Select a RTC IOMUX function for the RTC IO
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
* @param func Function to assign to the pin
*/
static inline void rtcio_ll_iomux_func_sel(int rtcio_num, int func)
{
SET_PERI_REG_BITS(rtc_io_desc[rtcio_num].reg, 0x3, func, rtc_io_desc[rtcio_num].func);
}
/**
* @brief Select the rtcio function.
*
@ -59,7 +70,7 @@ static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func)
// 0: GPIO connected to digital GPIO module. 1: GPIO connected to analog RTC module.
SET_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, (rtc_io_desc[rtcio_num].mux));
//0:RTC FUNCTION 1,2,3:Reserved
SET_PERI_REG_BITS(rtc_io_desc[rtcio_num].reg, RTC_IO_TOUCH_PAD1_FUN_SEL_V, RTCIO_LL_PIN_FUNC, rtc_io_desc[rtcio_num].func);
rtcio_ll_iomux_func_sel(rtcio_num, RTCIO_LL_PIN_FUNC);
} else if (func == RTCIO_FUNC_DIGITAL) {
CLEAR_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, (rtc_io_desc[rtcio_num].mux));
SENS.sar_peri_clk_gate_conf.iomux_clk_en = 0;

13
components/hal/esp32s3/include/hal/uart_ll.h
Wyświetl plik

@ -10,9 +10,10 @@
#pragma once
#include <stdlib.h>
#include "hal/misc.h"
#include "hal/uart_types.h"
#include "soc/uart_periph.h"
#include "soc/uart_reg.h"
#include "soc/uart_struct.h"
#include "esp_attr.h"
@ -23,7 +24,7 @@ extern "C" {
// The default fifo depth
#define UART_LL_FIFO_DEF_LEN (SOC_UART_FIFO_LEN)
// Get UART hardware instance with giving uart num
#define UART_LL_GET_HW(num) (((num) == 0) ? (&UART0) : (((num) == 1) ? (&UART1) : (&UART2)))
#define UART_LL_GET_HW(num) (((num) == UART_NUM_0) ? (&UART0) : (((num) == UART_NUM_1) ? (&UART1) : (&UART2)))
#define UART_LL_MIN_WAKEUP_THRESH (2)
#define UART_LL_INTR_MASK (0x7ffff) //All interrupt mask
@ -77,10 +78,9 @@ static inline void uart_ll_set_reset_core(uart_dev_t *hw, bool core_rst_en)
*
* @return None.
*/
FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, uart_sclk_t source_clk)
FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, soc_module_clk_t source_clk)
{
switch (source_clk) {
default:
case UART_SCLK_APB:
hw->clk_conf.sclk_sel = 1;
break;
@ -90,6 +90,9 @@ FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, uart_sclk_t source_clk)
case UART_SCLK_XTAL:
hw->clk_conf.sclk_sel = 3;
break;
default:
// Invalid UART clock source
abort();
}
}
@ -101,7 +104,7 @@ FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, uart_sclk_t source_clk)
*
* @return None.
*/
FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, uart_sclk_t *source_clk)
FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source_clk)
{
switch (hw->clk_conf.sclk_sel) {
default:

8
components/hal/include/hal/rtc_io_hal.h
Wyświetl plik

@ -163,6 +163,14 @@ void rtcio_hal_set_direction_in_sleep(int rtcio_num, rtc_gpio_mode_t mode);
*/
#define rtcio_hal_pulldown_disable(rtcio_num) rtcio_ll_pulldown_disable(rtcio_num)
/**
* Select a RTC IOMUX function for the RTC IO
*
* @param rtcio_num The index of rtcio. 0 ~ SOC_RTCIO_PIN_COUNT.
* @param func Function to assign to the pin
*/
#define rtcio_hal_iomux_func_sel(rtcio_num, func) rtcio_ll_iomux_func_sel(rtcio_num, func)
#endif // SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
#if SOC_RTCIO_HOLD_SUPPORTED

4
components/hal/include/hal/uart_hal.h
Wyświetl plik

@ -195,7 +195,7 @@ void uart_hal_init(uart_hal_context_t *hal, uart_port_t uart_num);
*
* @return None
*/
void uart_hal_set_sclk(uart_hal_context_t *hal, uart_sclk_t sclk);
void uart_hal_set_sclk(uart_hal_context_t *hal, soc_module_clk_t sclk);
/**
* @brief Get the UART source clock type
@ -205,7 +205,7 @@ void uart_hal_set_sclk(uart_hal_context_t *hal, uart_sclk_t sclk);
*
* @return None
*/
void uart_hal_get_sclk(uart_hal_context_t *hal, uart_sclk_t *sclk);
void uart_hal_get_sclk(uart_hal_context_t *hal, soc_module_clk_t *sclk);
/**
* @brief Configure the UART baud-rate and select the source clock

34
components/hal/include/hal/uart_types.h
Wyświetl plik

@ -18,7 +18,19 @@ extern "C" {
/**
* @brief UART port number, can be UART_NUM_0 ~ (UART_NUM_MAX -1).
*/
typedef int uart_port_t;
typedef enum {
UART_NUM_0, /*!< UART port 0 */
UART_NUM_1, /*!< UART port 1 */
#if SOC_UART_HP_NUM > 2
UART_NUM_2, /*!< UART port 2 */
#endif
#if (SOC_UART_LP_NUM >= 1)
LP_UART_NUM_0, /*!< LP UART port 0 */
#endif
UART_NUM_MAX, /*!< UART port max */
} uart_port_t;
_Static_assert(UART_NUM_MAX == SOC_UART_NUM, "UART_NUM_MAX does not match SOC_UART_NUM");
/**
* @brief UART mode selection
@ -92,6 +104,13 @@ typedef enum {
*/
typedef soc_periph_uart_clk_src_legacy_t uart_sclk_t;
#if (SOC_UART_LP_NUM >= 1)
/**
* @brief LP_UART source clock
*/
typedef soc_periph_lp_uart_clk_src_t lp_uart_sclk_t;
#endif
/**
* @brief UART AT cmd char configuration parameters
* Note that this function may different on different chip. Please refer to the TRM at confirguration.
@ -114,19 +133,6 @@ typedef struct {
uint8_t xoff_thrd; /*!< If the software flow control is enabled and the data amount in rxfifo is more than xoff_thrd, an xoff_char will be sent*/
} uart_sw_flowctrl_t;
/**
* @brief UART configuration parameters for uart_param_config function
*/
typedef struct {
int baud_rate; /*!< UART baud rate*/
uart_word_length_t data_bits; /*!< UART byte size*/
uart_parity_t parity; /*!< UART parity mode*/
uart_stop_bits_t stop_bits; /*!< UART stop bits*/
uart_hw_flowcontrol_t flow_ctrl; /*!< UART HW flow control mode (cts/rts)*/
uint8_t rx_flow_ctrl_thresh; /*!< UART HW RTS threshold*/
uart_sclk_t source_clk; /*!< UART source clock selection */
} uart_config_t;
#ifdef __cplusplus
}
#endif

9
components/hal/uart_hal.c
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@ -6,13 +6,14 @@
// The HAL layer for UART (common part)
#include "hal/uart_hal.h"
#include "soc/soc_caps.h"
void uart_hal_set_sclk(uart_hal_context_t *hal, uart_sclk_t sclk)
void uart_hal_set_sclk(uart_hal_context_t *hal, soc_module_clk_t sclk)
{
uart_ll_set_sclk(hal->dev, sclk);
}
void uart_hal_get_sclk(uart_hal_context_t *hal, uart_sclk_t *sclk)
void uart_hal_get_sclk(uart_hal_context_t *hal, soc_module_clk_t *sclk)
{
uart_ll_get_sclk(hal->dev, sclk);
}
@ -127,10 +128,8 @@ void uart_hal_set_loop_back(uart_hal_context_t *hal, bool loop_back_en)
uart_ll_set_loop_back(hal->dev, loop_back_en);
}
void uart_hal_init(uart_hal_context_t *hal, int uart_num)
void uart_hal_init(uart_hal_context_t *hal, uart_port_t uart_num)
{
// Set default clock source
uart_ll_set_sclk(hal->dev, UART_SCLK_DEFAULT);
// Set UART mode.
uart_ll_set_mode(hal->dev, UART_MODE_UART);
// Disable UART parity

4
components/mbedtls/test_apps/main/test_apb_dport_access.c
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Unlicense OR CC0-1.0
*/
@ -11,7 +11,7 @@
#include "sdkconfig.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "soc/uart_periph.h"
#include "soc/uart_reg.h"
#include "test_apb_dport_access.h"
#include "test_utils.h"

1
components/openthread/include/esp_openthread_types.h
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@ -16,6 +16,7 @@
#include "driver/spi_slave.h"
#include "hal/gpio_types.h"
#include "hal/uart_types.h"
#include "driver/uart.h"
#ifdef __cplusplus
extern "C" {

2
components/openthread/src/port/esp_uart_spinel_interface.cpp
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@ -108,7 +108,7 @@ void UartSpinelInterface::Update(esp_openthread_mainloop_context_t &mainloop)
int UartSpinelInterface::TryReadAndDecode(void)
{
uint8_t buffer[UART_FIFO_LEN];
uint8_t buffer[UART_HW_FIFO_LEN(m_uart_config.port)];
ssize_t rval;
do {

4
components/soc/esp32/include/soc/Kconfig.soc_caps.in
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@ -651,6 +651,10 @@ config SOC_UART_NUM
int
default 3
config SOC_UART_HP_NUM
int
default 3
config SOC_UART_SUPPORT_APB_CLK
bool
default y

1
components/soc/esp32/include/soc/soc_caps.h
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@ -319,6 +319,7 @@
/*-------------------------- UART CAPS ---------------------------------------*/
// ESP32 have 3 UART.
#define SOC_UART_NUM (3)
#define SOC_UART_HP_NUM (3)
#define SOC_UART_SUPPORT_APB_CLK (1) /*!< Support APB as the clock source */
#define SOC_UART_SUPPORT_REF_TICK (1) /*!< Support REF_TICK as the clock source */
#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */

4
components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
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@ -559,6 +559,10 @@ config SOC_UART_NUM
int
default 2
config SOC_UART_HP_NUM
int
default 2
config SOC_UART_FIFO_LEN
int
default 128

1
components/soc/esp32c2/include/soc/soc_caps.h
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@ -265,6 +265,7 @@
/*-------------------------- UART CAPS ---------------------------------------*/
// ESP32-C2 has 2 UARTs
#define SOC_UART_NUM (2)
#define SOC_UART_HP_NUM (2)
#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */
#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */
#define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */

4
components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
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@ -827,6 +827,10 @@ config SOC_UART_NUM
int
default 2
config SOC_UART_HP_NUM
int
default 2
config SOC_UART_FIFO_LEN
int
default 128

1
components/soc/esp32c3/include/soc/soc_caps.h
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@ -365,6 +365,7 @@
/*-------------------------- UART CAPS ---------------------------------------*/
// ESP32-C3 has 2 UARTs
#define SOC_UART_NUM (2)
#define SOC_UART_HP_NUM (2)
#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */
#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */

16
components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
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@ -183,6 +183,10 @@ config SOC_LP_AON_SUPPORTED
bool
default y
config SOC_LP_PERIPHERALS_SUPPORTED
bool
default y
config SOC_LP_I2C_SUPPORTED
bool
default y
@ -1060,13 +1064,25 @@ config SOC_CRYPTO_DPA_PROTECTION_SUPPORTED
default y
config SOC_UART_NUM
int
default 3
config SOC_UART_HP_NUM
int
default 2
config SOC_UART_LP_NUM
int
default 1
config SOC_UART_FIFO_LEN
int
default 128
config SOC_LP_UART_FIFO_LEN
int
default 16
config SOC_UART_BITRATE_MAX
int
default 5000000

13
components/soc/esp32c6/include/soc/clk_tree_defs.h
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@ -121,7 +121,9 @@ typedef enum {
SOC_MOD_CLK_XTAL32K, /*!< XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals */
SOC_MOD_CLK_RC_FAST, /*!< RC_FAST_CLK comes from the internal 20MHz rc oscillator, passing a clock gating to the peripherals */
SOC_MOD_CLK_XTAL, /*!< XTAL_CLK comes from the external 40MHz crystal */
// For LP peripherals
SOC_MOD_CLK_XTAL_D2, /*!< XTAL_D2_CLK comes from the external 40MHz crystal, passing a div of 2 to the LP peripherals */
SOC_MOD_CLK_INVALID, /*!< Indication of the end of the available module clock sources */
} soc_module_clk_t;
@ -219,12 +221,21 @@ typedef enum {
* @brief Type of UART clock source, reserved for the legacy UART driver
*/
typedef enum {
UART_SCLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< UART source clock is PLL_F80M */
UART_SCLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< UART source clock is PLL_F80M */
UART_SCLK_RTC = SOC_MOD_CLK_RC_FAST, /*!< UART source clock is RC_FAST */
UART_SCLK_XTAL = SOC_MOD_CLK_XTAL, /*!< UART source clock is XTAL */
UART_SCLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< UART source clock default choice is PLL_F80M */
} soc_periph_uart_clk_src_legacy_t;
/**
* @brief Type of LP_UART clock source
*/
typedef enum {
LP_UART_SCLK_LP_FAST = SOC_MOD_CLK_RTC_FAST, /*!< LP_UART source clock is LP(RTC)_FAST */
LP_UART_SCLK_XTAL_D2 = SOC_MOD_CLK_XTAL_D2, /*!< LP_UART source clock is XTAL_D2 */
LP_UART_SCLK_DEFAULT = SOC_MOD_CLK_RTC_FAST, /*!< LP_UART source clock default choice is LP(RTC)_FAST */
} soc_periph_lp_uart_clk_src_t;
//////////////////////////////////////////////////MCPWM/////////////////////////////////////////////////////////////////
/**

290
components/soc/esp32c6/include/soc/lp_uart_struct.h
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@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -16,11 +16,10 @@ extern "C" {
*/
typedef union {
struct {
/** rxfifo_rd_byte : RO; bitpos: [7:0]; default: 0;
/** rxfifo_rd_byte : RO; bitpos: [31:0]; default: 0;
* UART $n accesses FIFO via this register.
*/
uint32_t rxfifo_rd_byte:8;
uint32_t reserved_8:24;
uint32_t rxfifo_rd_byte:32;
};
uint32_t val;
} lp_uart_fifo_reg_t;
@ -75,92 +74,92 @@ typedef union {
*/
typedef union {
struct {
/** rxfifo_full_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
/** rxfifo_full : R/WTC/SS; bitpos: [0]; default: 0;
* This interrupt raw bit turns to high level when receiver receives more data than
* what rxfifo_full_thrhd specifies.
*/
uint32_t rxfifo_full_int_raw:1;
/** txfifo_empty_int_raw : R/WTC/SS; bitpos: [1]; default: 1;
uint32_t rxfifo_full:1;
/** txfifo_empty : R/WTC/SS; bitpos: [1]; default: 1;
* This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is
* less than what txfifo_empty_thrhd specifies .
*/
uint32_t txfifo_empty_int_raw:1;
/** parity_err_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
uint32_t txfifo_empty:1;
/** parity_err : R/WTC/SS; bitpos: [2]; default: 0;
* This interrupt raw bit turns to high level when receiver detects a parity error in
* the data.
*/
uint32_t parity_err_int_raw:1;
/** frm_err_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
uint32_t parity_err:1;
/** frm_err : R/WTC/SS; bitpos: [3]; default: 0;
* This interrupt raw bit turns to high level when receiver detects a data frame error
* .
*/
uint32_t frm_err_int_raw:1;
/** rxfifo_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
uint32_t frm_err:1;
/** rxfifo_ovf : R/WTC/SS; bitpos: [4]; default: 0;
* This interrupt raw bit turns to high level when receiver receives more data than
* the FIFO can store.
*/
uint32_t rxfifo_ovf_int_raw:1;
/** dsr_chg_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
uint32_t rxfifo_ovf:1;
/** dsr_chg : R/WTC/SS; bitpos: [5]; default: 0;
* This interrupt raw bit turns to high level when receiver detects the edge change of
* DSRn signal.
*/
uint32_t dsr_chg_int_raw:1;
/** cts_chg_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
uint32_t dsr_chg:1;
/** cts_chg : R/WTC/SS; bitpos: [6]; default: 0;
* This interrupt raw bit turns to high level when receiver detects the edge change of
* CTSn signal.
*/
uint32_t cts_chg_int_raw:1;
/** brk_det_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
uint32_t cts_chg:1;
/** brk_det : R/WTC/SS; bitpos: [7]; default: 0;
* This interrupt raw bit turns to high level when receiver detects a 0 after the stop
* bit.
*/
uint32_t brk_det_int_raw:1;
/** rxfifo_tout_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
uint32_t brk_det:1;
/** rxfifo_tout : R/WTC/SS; bitpos: [8]; default: 0;
* This interrupt raw bit turns to high level when receiver takes more time than
* rx_tout_thrhd to receive a byte.
*/
uint32_t rxfifo_tout_int_raw:1;
/** sw_xon_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
uint32_t rxfifo_tout:1;
/** sw_xon : R/WTC/SS; bitpos: [9]; default: 0;
* This interrupt raw bit turns to high level when receiver recevies Xon char when
* uart_sw_flow_con_en is set to 1.
*/
uint32_t sw_xon_int_raw:1;
/** sw_xoff_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
uint32_t sw_xon:1;
/** sw_xoff : R/WTC/SS; bitpos: [10]; default: 0;
* This interrupt raw bit turns to high level when receiver receives Xoff char when
* uart_sw_flow_con_en is set to 1.
*/
uint32_t sw_xoff_int_raw:1;
/** glitch_det_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
uint32_t sw_xoff:1;
/** glitch_det : R/WTC/SS; bitpos: [11]; default: 0;
* This interrupt raw bit turns to high level when receiver detects a glitch in the
* middle of a start bit.
*/
uint32_t glitch_det_int_raw:1;
/** tx_brk_done_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
uint32_t glitch_det:1;
/** tx_brk_done : R/WTC/SS; bitpos: [12]; default: 0;
* This interrupt raw bit turns to high level when transmitter completes sending
* NULL characters after all data in Tx-FIFO are sent.
*/
uint32_t tx_brk_done_int_raw:1;
/** tx_brk_idle_done_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
uint32_t tx_brk_done:1;
/** tx_brk_idle_done : R/WTC/SS; bitpos: [13]; default: 0;
* This interrupt raw bit turns to high level when transmitter has kept the shortest
* duration after sending the last data.
*/
uint32_t tx_brk_idle_done_int_raw:1;
/** tx_done_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
uint32_t tx_brk_idle_done:1;
/** tx_done : R/WTC/SS; bitpos: [14]; default: 0;
* This interrupt raw bit turns to high level when transmitter has send out all data
* in FIFO.
*/
uint32_t tx_done_int_raw:1;
uint32_t tx_done:1;
uint32_t reserved_15:3;
/** at_cmd_char_det_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
/** at_cmd_char_det : R/WTC/SS; bitpos: [18]; default: 0;
* This interrupt raw bit turns to high level when receiver detects the configured
* at_cmd char.
*/
uint32_t at_cmd_char_det_int_raw:1;
/** wakeup_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
uint32_t at_cmd_char_det:1;
/** wakeup : R/WTC/SS; bitpos: [19]; default: 0;
* This interrupt raw bit turns to high level when input rxd edge changes more times
* than what reg_active_threshold specifies in light sleeping mode.
*/
uint32_t wakeup_int_raw:1;
uint32_t wakeup:1;
uint32_t reserved_20:12;
};
uint32_t val;
@ -171,78 +170,78 @@ typedef union {
*/
typedef union {
struct {
/** rxfifo_full_int_st : RO; bitpos: [0]; default: 0;
/** rxfifo_full : RO; bitpos: [0]; default: 0;
* This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.
*/
uint32_t rxfifo_full_int_st:1;
/** txfifo_empty_int_st : RO; bitpos: [1]; default: 0;
uint32_t rxfifo_full:1;
/** txfifo_empty : RO; bitpos: [1]; default: 0;
* This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set
* to 1.
*/
uint32_t txfifo_empty_int_st:1;
/** parity_err_int_st : RO; bitpos: [2]; default: 0;
uint32_t txfifo_empty:1;
/** parity_err : RO; bitpos: [2]; default: 0;
* This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.
*/
uint32_t parity_err_int_st:1;
/** frm_err_int_st : RO; bitpos: [3]; default: 0;
uint32_t parity_err:1;
/** frm_err : RO; bitpos: [3]; default: 0;
* This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.
*/
uint32_t frm_err_int_st:1;
/** rxfifo_ovf_int_st : RO; bitpos: [4]; default: 0;
uint32_t frm_err:1;
/** rxfifo_ovf : RO; bitpos: [4]; default: 0;
* This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.
*/
uint32_t rxfifo_ovf_int_st:1;
/** dsr_chg_int_st : RO; bitpos: [5]; default: 0;
uint32_t rxfifo_ovf:1;
/** dsr_chg : RO; bitpos: [5]; default: 0;
* This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.
*/
uint32_t dsr_chg_int_st:1;
/** cts_chg_int_st : RO; bitpos: [6]; default: 0;
uint32_t dsr_chg:1;
/** cts_chg : RO; bitpos: [6]; default: 0;
* This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.
*/
uint32_t cts_chg_int_st:1;
/** brk_det_int_st : RO; bitpos: [7]; default: 0;
uint32_t cts_chg:1;
/** brk_det : RO; bitpos: [7]; default: 0;
* This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.
*/
uint32_t brk_det_int_st:1;
/** rxfifo_tout_int_st : RO; bitpos: [8]; default: 0;
uint32_t brk_det:1;
/** rxfifo_tout : RO; bitpos: [8]; default: 0;
* This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.
*/
uint32_t rxfifo_tout_int_st:1;
/** sw_xon_int_st : RO; bitpos: [9]; default: 0;
uint32_t rxfifo_tout:1;
/** sw_xon : RO; bitpos: [9]; default: 0;
* This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.
*/
uint32_t sw_xon_int_st:1;
/** sw_xoff_int_st : RO; bitpos: [10]; default: 0;
uint32_t sw_xon:1;
/** sw_xoff : RO; bitpos: [10]; default: 0;
* This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.
*/
uint32_t sw_xoff_int_st:1;
/** glitch_det_int_st : RO; bitpos: [11]; default: 0;
uint32_t sw_xoff:1;
/** glitch_det : RO; bitpos: [11]; default: 0;
* This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.
*/
uint32_t glitch_det_int_st:1;
/** tx_brk_done_int_st : RO; bitpos: [12]; default: 0;
uint32_t glitch_det:1;
/** tx_brk_done : RO; bitpos: [12]; default: 0;
* This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.
*/
uint32_t tx_brk_done_int_st:1;
/** tx_brk_idle_done_int_st : RO; bitpos: [13]; default: 0;
uint32_t tx_brk_done:1;
/** tx_brk_idle_done : RO; bitpos: [13]; default: 0;
* This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
* is set to 1.
*/
uint32_t tx_brk_idle_done_int_st:1;
/** tx_done_int_st : RO; bitpos: [14]; default: 0;
uint32_t tx_brk_idle_done:1;
/** tx_done : RO; bitpos: [14]; default: 0;
* This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.
*/
uint32_t tx_done_int_st:1;
uint32_t tx_done:1;
uint32_t reserved_15:3;
/** at_cmd_char_det_int_st : RO; bitpos: [18]; default: 0;
/** at_cmd_char_det : RO; bitpos: [18]; default: 0;
* This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set
* to 1.
*/
uint32_t at_cmd_char_det_int_st:1;
/** wakeup_int_st : RO; bitpos: [19]; default: 0;
uint32_t at_cmd_char_det:1;
/** wakeup : RO; bitpos: [19]; default: 0;
* This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.
*/
uint32_t wakeup_int_st:1;
uint32_t wakeup:1;
uint32_t reserved_20:12;
};
uint32_t val;
@ -253,75 +252,75 @@ typedef union {
*/
typedef union {
struct {
/** rxfifo_full_int_ena : R/W; bitpos: [0]; default: 0;
/** rxfifo_full : R/W; bitpos: [0]; default: 0;
* This is the enable bit for rxfifo_full_int_st register.
*/
uint32_t rxfifo_full_int_ena:1;
/** txfifo_empty_int_ena : R/W; bitpos: [1]; default: 0;
uint32_t rxfifo_full:1;
/** txfifo_empty : R/W; bitpos: [1]; default: 0;
* This is the enable bit for txfifo_empty_int_st register.
*/
uint32_t txfifo_empty_int_ena:1;
/** parity_err_int_ena : R/W; bitpos: [2]; default: 0;
uint32_t txfifo_empty:1;
/** parity_err : R/W; bitpos: [2]; default: 0;
* This is the enable bit for parity_err_int_st register.
*/
uint32_t parity_err_int_ena:1;
/** frm_err_int_ena : R/W; bitpos: [3]; default: 0;
uint32_t parity_err:1;
/** frm_err : R/W; bitpos: [3]; default: 0;
* This is the enable bit for frm_err_int_st register.
*/
uint32_t frm_err_int_ena:1;
/** rxfifo_ovf_int_ena : R/W; bitpos: [4]; default: 0;
uint32_t frm_err:1;
/** rxfifo_ovf : R/W; bitpos: [4]; default: 0;
* This is the enable bit for rxfifo_ovf_int_st register.
*/
uint32_t rxfifo_ovf_int_ena:1;
/** dsr_chg_int_ena : R/W; bitpos: [5]; default: 0;
uint32_t rxfifo_ovf:1;
/** dsr_chg : R/W; bitpos: [5]; default: 0;
* This is the enable bit for dsr_chg_int_st register.
*/
uint32_t dsr_chg_int_ena:1;
/** cts_chg_int_ena : R/W; bitpos: [6]; default: 0;
uint32_t dsr_chg:1;
/** cts_chg : R/W; bitpos: [6]; default: 0;
* This is the enable bit for cts_chg_int_st register.
*/
uint32_t cts_chg_int_ena:1;
/** brk_det_int_ena : R/W; bitpos: [7]; default: 0;
uint32_t cts_chg:1;
/** brk_det : R/W; bitpos: [7]; default: 0;
* This is the enable bit for brk_det_int_st register.
*/
uint32_t brk_det_int_ena:1;
/** rxfifo_tout_int_ena : R/W; bitpos: [8]; default: 0;
uint32_t brk_det:1;
/** rxfifo_tout : R/W; bitpos: [8]; default: 0;
* This is the enable bit for rxfifo_tout_int_st register.
*/
uint32_t rxfifo_tout_int_ena:1;
/** sw_xon_int_ena : R/W; bitpos: [9]; default: 0;
uint32_t rxfifo_tout:1;
/** sw_xon : R/W; bitpos: [9]; default: 0;
* This is the enable bit for sw_xon_int_st register.
*/
uint32_t sw_xon_int_ena:1;
/** sw_xoff_int_ena : R/W; bitpos: [10]; default: 0;
uint32_t sw_xon:1;
/** sw_xoff : R/W; bitpos: [10]; default: 0;
* This is the enable bit for sw_xoff_int_st register.
*/
uint32_t sw_xoff_int_ena:1;
/** glitch_det_int_ena : R/W; bitpos: [11]; default: 0;
uint32_t sw_xoff:1;
/** glitch_det : R/W; bitpos: [11]; default: 0;
* This is the enable bit for glitch_det_int_st register.
*/
uint32_t glitch_det_int_ena:1;
/** tx_brk_done_int_ena : R/W; bitpos: [12]; default: 0;
uint32_t glitch_det:1;
/** tx_brk_done : R/W; bitpos: [12]; default: 0;
* This is the enable bit for tx_brk_done_int_st register.
*/
uint32_t tx_brk_done_int_ena:1;
/** tx_brk_idle_done_int_ena : R/W; bitpos: [13]; default: 0;
uint32_t tx_brk_done:1;
/** tx_brk_idle_done : R/W; bitpos: [13]; default: 0;
* This is the enable bit for tx_brk_idle_done_int_st register.
*/
uint32_t tx_brk_idle_done_int_ena:1;
/** tx_done_int_ena : R/W; bitpos: [14]; default: 0;
uint32_t tx_brk_idle_done:1;
/** tx_done : R/W; bitpos: [14]; default: 0;
* This is the enable bit for tx_done_int_st register.
*/
uint32_t tx_done_int_ena:1;
uint32_t tx_done:1;
uint32_t reserved_15:3;
/** at_cmd_char_det_int_ena : R/W; bitpos: [18]; default: 0;
/** at_cmd_char_det : R/W; bitpos: [18]; default: 0;
* This is the enable bit for at_cmd_char_det_int_st register.
*/
uint32_t at_cmd_char_det_int_ena:1;
/** wakeup_int_ena : R/W; bitpos: [19]; default: 0;
uint32_t at_cmd_char_det:1;
/** wakeup : R/W; bitpos: [19]; default: 0;
* This is the enable bit for uart_wakeup_int_st register.
*/
uint32_t wakeup_int_ena:1;
uint32_t wakeup:1;
uint32_t reserved_20:12;
};
uint32_t val;
@ -332,75 +331,75 @@ typedef union {
*/
typedef union {
struct {
/** rxfifo_full_int_clr : WT; bitpos: [0]; default: 0;
/** rxfifo_full : WT; bitpos: [0]; default: 0;
* Set this bit to clear the rxfifo_full_int_raw interrupt.
*/
uint32_t rxfifo_full_int_clr:1;
/** txfifo_empty_int_clr : WT; bitpos: [1]; default: 0;
uint32_t rxfifo_full:1;
/** txfifo_empty : WT; bitpos: [1]; default: 0;
* Set this bit to clear txfifo_empty_int_raw interrupt.
*/
uint32_t txfifo_empty_int_clr:1;
/** parity_err_int_clr : WT; bitpos: [2]; default: 0;
uint32_t txfifo_empty:1;
/** parity_err : WT; bitpos: [2]; default: 0;
* Set this bit to clear parity_err_int_raw interrupt.
*/
uint32_t parity_err_int_clr:1;
/** frm_err_int_clr : WT; bitpos: [3]; default: 0;
uint32_t parity_err:1;
/** frm_err : WT; bitpos: [3]; default: 0;
* Set this bit to clear frm_err_int_raw interrupt.
*/
uint32_t frm_err_int_clr:1;
/** rxfifo_ovf_int_clr : WT; bitpos: [4]; default: 0;
uint32_t frm_err:1;
/** rxfifo_ovf : WT; bitpos: [4]; default: 0;
* Set this bit to clear rxfifo_ovf_int_raw interrupt.
*/
uint32_t rxfifo_ovf_int_clr:1;
/** dsr_chg_int_clr : WT; bitpos: [5]; default: 0;
uint32_t rxfifo_ovf:1;
/** dsr_chg : WT; bitpos: [5]; default: 0;
* Set this bit to clear the dsr_chg_int_raw interrupt.
*/
uint32_t dsr_chg_int_clr:1;
/** cts_chg_int_clr : WT; bitpos: [6]; default: 0;
uint32_t dsr_chg:1;
/** cts_chg : WT; bitpos: [6]; default: 0;
* Set this bit to clear the cts_chg_int_raw interrupt.
*/
uint32_t cts_chg_int_clr:1;
/** brk_det_int_clr : WT; bitpos: [7]; default: 0;
uint32_t cts_chg:1;
/** brk_det : WT; bitpos: [7]; default: 0;
* Set this bit to clear the brk_det_int_raw interrupt.
*/
uint32_t brk_det_int_clr:1;
/** rxfifo_tout_int_clr : WT; bitpos: [8]; default: 0;
uint32_t brk_det:1;
/** rxfifo_tout : WT; bitpos: [8]; default: 0;
* Set this bit to clear the rxfifo_tout_int_raw interrupt.
*/
uint32_t rxfifo_tout_int_clr:1;
/** sw_xon_int_clr : WT; bitpos: [9]; default: 0;
uint32_t rxfifo_tout:1;
/** sw_xon : WT; bitpos: [9]; default: 0;
* Set this bit to clear the sw_xon_int_raw interrupt.
*/
uint32_t sw_xon_int_clr:1;
/** sw_xoff_int_clr : WT; bitpos: [10]; default: 0;
uint32_t sw_xon:1;
/** sw_xoff : WT; bitpos: [10]; default: 0;
* Set this bit to clear the sw_xoff_int_raw interrupt.
*/
uint32_t sw_xoff_int_clr:1;
/** glitch_det_int_clr : WT; bitpos: [11]; default: 0;
uint32_t sw_xoff:1;
/** glitch_det : WT; bitpos: [11]; default: 0;
* Set this bit to clear the glitch_det_int_raw interrupt.
*/
uint32_t glitch_det_int_clr:1;
/** tx_brk_done_int_clr : WT; bitpos: [12]; default: 0;
uint32_t glitch_det:1;
/** tx_brk_done : WT; bitpos: [12]; default: 0;
* Set this bit to clear the tx_brk_done_int_raw interrupt..
*/
uint32_t tx_brk_done_int_clr:1;
/** tx_brk_idle_done_int_clr : WT; bitpos: [13]; default: 0;
uint32_t tx_brk_done:1;
/** tx_brk_idle_done : WT; bitpos: [13]; default: 0;
* Set this bit to clear the tx_brk_idle_done_int_raw interrupt.
*/
uint32_t tx_brk_idle_done_int_clr:1;
/** tx_done_int_clr : WT; bitpos: [14]; default: 0;
uint32_t tx_brk_idle_done:1;
/** tx_done : WT; bitpos: [14]; default: 0;
* Set this bit to clear the tx_done_int_raw interrupt.
*/
uint32_t tx_done_int_clr:1;
uint32_t tx_done:1;
uint32_t reserved_15:3;
/** at_cmd_char_det_int_clr : WT; bitpos: [18]; default: 0;
/** at_cmd_char_det : WT; bitpos: [18]; default: 0;
* Set this bit to clear the at_cmd_char_det_int_raw interrupt.
*/
uint32_t at_cmd_char_det_int_clr:1;
/** wakeup_int_clr : WT; bitpos: [19]; default: 0;
uint32_t at_cmd_char_det:1;
/** wakeup : WT; bitpos: [19]; default: 0;
* Set this bit to clear the uart_wakeup_int_raw interrupt.
*/
uint32_t wakeup_int_clr:1;
uint32_t wakeup:1;
uint32_t reserved_20:12;
};
uint32_t val;
@ -413,10 +412,10 @@ typedef union {
*/
typedef union {
struct {
/** clkdiv : R/W; bitpos: [11:0]; default: 694;
/** clkdiv_int : R/W; bitpos: [11:0]; default: 694;
* The integral part of the frequency divider factor.
*/
uint32_t clkdiv:12;
uint32_t clkdiv_int:12;
uint32_t reserved_12:8;
/** clkdiv_frag : R/W; bitpos: [23:20]; default: 0;
* The decimal part of the frequency divider factor.
@ -1019,10 +1018,10 @@ typedef union {
*/
typedef union {
struct {
/** at_cmd_char : R/W; bitpos: [7:0]; default: 43;
/** data : R/W; bitpos: [7:0]; default: 43;
* This register is used to configure the content of at_cmd char.
*/
uint32_t at_cmd_char:8;
uint32_t data:8;
/** char_num : R/W; bitpos: [15:8]; default: 3;
* This register is used to configure the num of continuous at_cmd chars received by
* receiver.
@ -1116,7 +1115,8 @@ typedef struct lp_uart_dev_t {
volatile lp_uart_id_reg_t id;
} lp_uart_dev_t;
extern lp_uart_dev_t LP_UART;
// We map the LP_UART instance to the uart_dev_t struct for convinience of using the same HAL/LL. See soc/uart_struct.h
// extern lp_uart_dev_t LP_UART;
#ifndef __cplusplus
_Static_assert(sizeof(lp_uart_dev_t) == 0xa0, "Invalid size of lp_uart_dev_t structure");

7
components/soc/esp32c6/include/soc/periph_defs.h
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@ -42,7 +42,6 @@ typedef enum {
PERIPH_SARADC_MODULE,
PERIPH_TEMPSENSOR_MODULE,
PERIPH_REGDMA_MODULE,
PERIPH_LP_I2C0_MODULE,
/* Peripherals clock managed by the modem_clock driver must be listed last in the enumeration */
PERIPH_WIFI_MODULE,
PERIPH_BT_MODULE,
@ -52,6 +51,12 @@ typedef enum {
PERIPH_MODULE_MAX
} periph_module_t;
typedef enum {
LP_PERIPH_I2C0_MODULE = 0,
LP_PERIPH_UART0_MODULE,
LP_PERIPH_MODULE_MAX,
} lp_periph_module_t;
#define PERIPH_MODEM_MODULE_MIN PERIPH_WIFI_MODULE
#define PERIPH_MODEM_MODULE_MAX PERIPH_PHY_MODULE
#define PERIPH_MODEM_MODULE_NUM (PERIPH_MODEM_MODULE_MAX - PERIPH_MODEM_MODULE_MIN + 1)

8
components/soc/esp32c6/include/soc/soc_caps.h
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@ -70,6 +70,7 @@
#define SOC_PAU_SUPPORTED 1
#define SOC_LP_TIMER_SUPPORTED 1
#define SOC_LP_AON_SUPPORTED 1
#define SOC_LP_PERIPHERALS_SUPPORTED 1
#define SOC_LP_I2C_SUPPORTED 1
/*-------------------------- XTAL CAPS ---------------------------------------*/
@ -437,9 +438,12 @@
#define SOC_CRYPTO_DPA_PROTECTION_SUPPORTED 1
/*-------------------------- UART CAPS ---------------------------------------*/
// ESP32-C6 has 2 UARTs
#define SOC_UART_NUM (2)
// ESP32-C6 has 3 UARTs (2 HP UART, and 1 LP UART)
#define SOC_UART_NUM (3)
#define SOC_UART_HP_NUM (2)
#define SOC_UART_LP_NUM (1U)
#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */
#define SOC_LP_UART_FIFO_LEN (16) /*!< The LP UART hardware FIFO length */
#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */
#define SOC_UART_SUPPORT_PLL_F80M_CLK (1) /*!< Support PLL_F80M as the clock source */
#define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */

12
components/soc/esp32c6/include/soc/uart_pins.h
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -22,6 +22,11 @@
#define U1RTS_GPIO_NUM (-1)
#define U1CTS_GPIO_NUM (-1)
#define LP_U0RXD_GPIO_NUM 4
#define LP_U0TXD_GPIO_NUM 5
#define LP_U0RTS_GPIO_NUM 2
#define LP_U0CTS_GPIO_NUM 3
/* The following defines are necessary for reconfiguring the UART
* to use IOMUX, at runtime. */
#define U0TXD_MUX_FUNC (FUNC_U0TXD_U0TXD)
@ -34,3 +39,8 @@
#define U1RXD_MUX_FUNC (-1)
#define U1RTS_MUX_FUNC (-1)
#define U1CTS_MUX_FUNC (-1)
#define LP_U0TXD_MUX_FUNC (1)
#define LP_U0RXD_MUX_FUNC (1)
#define LP_U0RTS_MUX_FUNC (1)
#define LP_U0CTS_MUX_FUNC (1)

63
components/soc/esp32c6/include/soc/uart_struct.h
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@ -875,6 +875,56 @@ typedef union {
uint32_t val;
} uart_rs485_conf_sync_reg_t;
/** Type of clk_conf register
* UART core clock configuration
*/
typedef union {
struct {
/** sclk_div_b : R/W; bitpos: [5:0]; default: 0;
* The denominator of the frequency divider factor.
*/
uint32_t sclk_div_b:6;
/** sclk_div_a : R/W; bitpos: [11:6]; default: 0;
* The numerator of the frequency divider factor.
*/
uint32_t sclk_div_a:6;
/** sclk_div_num : R/W; bitpos: [19:12]; default: 1;
* The integral part of the frequency divider factor.
*/
uint32_t sclk_div_num:8;
/** sclk_sel : R/W; bitpos: [21:20]; default: 3;
* UART clock source select. 1: 80Mhz. 2: 8Mhz. 3: XTAL.
*/
uint32_t sclk_sel:2;
/** sclk_en : R/W; bitpos: [22]; default: 1;
* Set this bit to enable UART Tx/Rx clock.
*/
uint32_t sclk_en:1;
/** rst_core : R/W; bitpos: [23]; default: 0;
* Write 1 then write 0 to this bit to reset UART Tx/Rx.
*/
uint32_t rst_core:1;
/** tx_sclk_en : R/W; bitpos: [24]; default: 1;
* Set this bit to enable UART Tx clock.
*/
uint32_t tx_sclk_en:1;
/** rx_sclk_en : R/W; bitpos: [25]; default: 1;
* Set this bit to enable UART Rx clock.
*/
uint32_t rx_sclk_en:1;
/** tx_rst_core : R/W; bitpos: [26]; default: 0;
* Write 1 then write 0 to this bit to reset UART Tx.
*/
uint32_t tx_rst_core:1;
/** rx_rst_core : R/W; bitpos: [27]; default: 0;
* Write 1 then write 0 to this bit to reset UART Rx.
*/
uint32_t rx_rst_core:1;
uint32_t reserved_28:4;
};
uint32_t val;
} uart_clk_conf_reg_t;
/** Group: Status Register */
/** Type of status register
@ -1218,12 +1268,12 @@ typedef struct uart_dev_s {
volatile uart_mem_tx_status_reg_t mem_tx_status;
volatile uart_mem_rx_status_reg_t mem_rx_status;
volatile uart_fsm_status_reg_t fsm_status;
volatile uart_pospulse_reg_t pospulse;
volatile uart_negpulse_reg_t negpulse;
volatile uart_lowpulse_reg_t lowpulse;
volatile uart_highpulse_reg_t highpulse;
volatile uart_rxd_cnt_reg_t rxd_cnt;
uint32_t reserved_088;
volatile uart_pospulse_reg_t pospulse; /* LP_UART instance has this register reserved */
volatile uart_negpulse_reg_t negpulse; /* LP_UART instance has this register reserved */
volatile uart_lowpulse_reg_t lowpulse; /* LP_UART instance has this register reserved */
volatile uart_highpulse_reg_t highpulse; /* LP_UART instance has this register reserved */
volatile uart_rxd_cnt_reg_t rxd_cnt; /* LP_UART instance has this register reserved */
volatile uart_clk_conf_reg_t clk_conf; /* UART0/1 instance have this register reserved, configure in corresponding PCR registers */
volatile uart_date_reg_t date;
volatile uart_afifo_status_reg_t afifo_status;
uint32_t reserved_094;
@ -1233,6 +1283,7 @@ typedef struct uart_dev_s {
extern uart_dev_t UART0;
extern uart_dev_t UART1;
extern uart_dev_t LP_UART;
#ifndef __cplusplus
_Static_assert(sizeof(uart_dev_t) == 0xa0, "Invalid size of uart_dev_t structure");

40
components/soc/esp32c6/uart_periph.c
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -10,7 +10,7 @@
Bunch of constants for every UART peripheral: GPIO signals, irqs, hw addr of registers etc
*/
const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
{
{ // HP UART0
.pins = {
[SOC_UART_TX_PIN_IDX] = {
.default_gpio = U0TXD_GPIO_NUM,
@ -44,7 +44,7 @@ const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
.module = PERIPH_UART0_MODULE,
},
{
{ // HP UART1
.pins = {
[SOC_UART_TX_PIN_IDX] = {
.default_gpio = U1TXD_GPIO_NUM,
@ -77,4 +77,38 @@ const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
.irq = ETS_UART1_INTR_SOURCE,
.module = PERIPH_UART1_MODULE,
},
{ // LP UART0
.pins = {
[SOC_UART_TX_PIN_IDX] = {
.default_gpio = LP_U0TXD_GPIO_NUM,
.iomux_func = LP_U0TXD_MUX_FUNC,
.input = 0,
.signal = UINT8_MAX, // Signal not available in signal map
},
[SOC_UART_RX_PIN_IDX] = {
.default_gpio = LP_U0RXD_GPIO_NUM,
.iomux_func = LP_U0RXD_MUX_FUNC,
.input = 1,
.signal = UINT8_MAX, // Signal not available in signal map
},
[SOC_UART_RTS_PIN_IDX] = {
.default_gpio = LP_U0RTS_GPIO_NUM,
.iomux_func = LP_U0RTS_MUX_FUNC,
.input = 0,
.signal = UINT8_MAX, // Signal not available in signal map
},
[SOC_UART_CTS_PIN_IDX] = {
.default_gpio = LP_U0CTS_GPIO_NUM,
.iomux_func = LP_U0CTS_MUX_FUNC,
.input = 1,
.signal = UINT8_MAX, // Signal not available in signal map
},
},
.irq = ETS_LP_UART_INTR_SOURCE,
.lp_module = LP_PERIPH_UART0_MODULE,
},
};

4
components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
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@ -1031,6 +1031,10 @@ config SOC_UART_NUM
int
default 2
config SOC_UART_HP_NUM
int
default 2
config SOC_UART_FIFO_LEN
int
default 128

1
components/soc/esp32h2/include/soc/soc_caps.h
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@ -435,6 +435,7 @@
/*-------------------------- UART CAPS ---------------------------------------*/
// ESP32-H2 has 2 UARTs
#define SOC_UART_NUM (2)
#define SOC_UART_HP_NUM (2)
#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */
#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */

4
components/soc/esp32s2/include/soc/Kconfig.soc_caps.in
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@ -755,6 +755,10 @@ config SOC_UART_NUM
int
default 2
config SOC_UART_HP_NUM
int
default 2
config SOC_UART_SUPPORT_WAKEUP_INT
bool
default y

1
components/soc/esp32s2/include/soc/soc_caps.h
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@ -323,6 +323,7 @@
/*-------------------------- UART CAPS ---------------------------------------*/
// ESP32-S2 has 2 UART.
#define SOC_UART_NUM (2)
#define SOC_UART_HP_NUM (2)
#define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */
#define SOC_UART_SUPPORT_APB_CLK (1) /*!< Support APB as the clock source */
#define SOC_UART_SUPPORT_REF_TICK (1) /*!< Support REF_TICK as the clock source */

4
components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
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@ -887,6 +887,10 @@ config SOC_UART_NUM
int
default 3
config SOC_UART_HP_NUM
int
default 3
config SOC_UART_FIFO_LEN
int
default 128

1
components/soc/esp32s3/include/soc/soc_caps.h
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@ -352,6 +352,7 @@
/*-------------------------- UART CAPS ---------------------------------------*/
// ESP32-S3 has 3 UARTs
#define SOC_UART_NUM (3)
#define SOC_UART_HP_NUM (3)
#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */
#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */
// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled

27
components/soc/include/soc/uart_periph.h
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@ -1,21 +1,11 @@
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/soc_caps.h"
#include "soc/uart_reg.h"
#include "soc/uart_struct.h"
#include "soc/periph_defs.h"
#include "soc/gpio_sig_map.h"
#include "soc/io_mux_reg.h"
@ -53,7 +43,12 @@ typedef struct {
typedef struct {
const uart_periph_sig_t pins[SOC_UART_PINS_COUNT];
const uint8_t irq;
const periph_module_t module;
union {
const periph_module_t module;
#if (SOC_UART_LP_NUM >= 1)
const lp_periph_module_t lp_module;
#endif
};
} uart_signal_conn_t;
extern const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM];

6
components/ulp/lp_core/lp_core_i2c.c
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@ -11,7 +11,7 @@
#include "driver/rtc_io.h"
#include "soc/rtc_io_channel.h"
#include "esp_private/esp_clk_tree_common.h"
#include "esp_private/periph_ctrl.h"
#include "esp_private/lp_periph_ctrl.h"
static const char *LPI2C_TAG = "lp_core_i2c";
@ -109,7 +109,7 @@ static esp_err_t lp_i2c_config_clk(const lp_core_i2c_cfg_t *cfg)
ESP_RETURN_ON_FALSE(cfg->i2c_timing_cfg.clk_speed_hz * 20 <= source_freq, ESP_ERR_INVALID_ARG, LPI2C_TAG, "I2C_SCLK frequency (%"PRId32") should operate at a frequency at least 20 times larger than the I2C SCL bus frequency (%"PRId32")", source_freq, cfg->i2c_timing_cfg.clk_speed_hz);
/* Set LP I2C source clock */
lp_i2c_ll_set_source_clk(i2c_hal.dev, source_clk);
lp_periph_set_clk_src(LP_PERIPH_I2C0_MODULE, (soc_module_clk_t)source_clk);
/* Configure LP I2C timing paramters. source_clk is ignored for LP_I2C in this call */
i2c_hal_set_bus_timing(&i2c_hal, (i2c_clock_source_t)source_clk, cfg->i2c_timing_cfg.clk_speed_hz, source_freq);
@ -132,7 +132,7 @@ esp_err_t lp_core_i2c_master_init(i2c_port_t lp_i2c_num, const lp_core_i2c_cfg_t
i2c_hal_init(&i2c_hal, lp_i2c_num);
/* Enable LP I2C controller clock */
periph_module_enable(PERIPH_LP_I2C0_MODULE);
lp_periph_module_enable(LP_PERIPH_I2C0_MODULE);
/* Initialize LP I2C Master mode */
i2c_hal_master_init(&i2c_hal);

6
components/vfs/test_apps/main/test_vfs_access.c
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@ -23,14 +23,14 @@ TEST_CASE("Can use access() for UART", "[vfs]")
const char *uarts[] = {
"/dev/uart/0",
"/dev/uart/1",
#if SOC_UART_NUM > 2
#if SOC_UART_HP_NUM > 2
"/dev/uart/2"
#endif
};
uart_driver_install(UART_NUM_0, 256, 0, 0, NULL, 0);
uart_driver_install(UART_NUM_1, 256, 0, 0, NULL, 0);
#if SOC_UART_NUM > 2
#if SOC_UART_HP_NUM > 2
uart_driver_install(UART_NUM_2, 256, 0, 0, NULL, 0);
#endif
@ -56,7 +56,7 @@ TEST_CASE("Can use access() for UART", "[vfs]")
uart_driver_delete(UART_NUM_0);
uart_driver_delete(UART_NUM_1);
#if SOC_UART_NUM > 2
#if SOC_UART_HP_NUM > 2
uart_driver_delete(UART_NUM_2);
#endif
}

4
components/vfs/test_apps/main/test_vfs_uart.c
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@ -38,8 +38,8 @@ static void fwrite_str_loopback(const char* str, size_t size)
static void flush_stdin_stdout(void)
{
vTaskDelay(10 / portTICK_PERIOD_MS);
char bitbucket[UART_FIFO_LEN];
while (fread(bitbucket, 1, UART_FIFO_LEN, stdin) > 0) {
char bitbucket[UART_HW_FIFO_LEN(CONFIG_ESP_CONSOLE_UART_NUM)];
while (fread(bitbucket, 1, UART_HW_FIFO_LEN(CONFIG_ESP_CONSOLE_UART_NUM), stdin) > 0) {
;
}
fflush(stdout);

3
components/vfs/vfs_uart.c
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@ -22,8 +22,7 @@
#include "soc/soc_caps.h"
#include "hal/uart_ll.h"
// TODO: make the number of UARTs chip dependent
#define UART_NUM SOC_UART_NUM
#define UART_NUM SOC_UART_HP_NUM
// Token signifying that no character is available
#define NONE -1

10
docs/en/api-reference/peripherals/uart.rst
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@ -8,9 +8,13 @@ Introduction
A Universal Asynchronous Receiver/Transmitter (UART) is a hardware feature that handles communication (i.e., timing requirements and data framing) using widely-adopted asynchronous serial communication interfaces, such as RS232, RS422, and RS485. A UART provides a widely adopted and cheap method to realize full-duplex or half-duplex data exchange among different devices.
The {IDF_TARGET_NAME} chip has {IDF_TARGET_SOC_UART_NUM} UART controllers (also referred to as port), each featuring an identical set of registers to simplify programming and for more flexibility.
The {IDF_TARGET_NAME} chip has {IDF_TARGET_SOC_UART_HP_NUM} UART controllers (also referred to as port), each featuring an identical set of registers to simplify programming and for more flexibility.
Each UART controller is independently configurable with parameters such as baud rate, data bit length, bit ordering, number of stop bits, parity bit, etc. All the controllers are compatible with UART-enabled devices from various manufacturers and can also support Infrared Data Association (IrDA) protocols.
Each UART controller is independently configurable with parameters such as baud rate, data bit length, bit ordering, number of stop bits, parity bit, etc. All the regular UART controllers are compatible with UART-enabled devices from various manufacturers and can also support Infrared Data Association (IrDA) protocols.
.. only:: SOC_UART_LP_NUM
Additionally, the {IDF_TARGET_NAME} chip has one low-power (LP) UART controller. It is the cut-down version of regular UART. Usually, the LP UART controller only support basic UART functionality with a much smaller RAM size, and does not support IrDA or RS485 protocols. For a full list of difference between UART and LP UART, please refer to the *{IDF_TARGET_NAME} Technical Reference Manual* > *UART Controller (UART)* > *Features* [`PDF <{IDF_TARGET_TRM_EN_URL}#uart>`__]).
Functional Overview
-------------------
@ -238,7 +242,7 @@ The API provides a convenient way to handle specific interrupts discussed in thi
Macros
^^^^^^
The API also defines several macros. For example, :c:macro:`UART_FIFO_LEN` defines the length of hardware FIFO buffers; :c:macro:`UART_BITRATE_MAX` gives the maximum baud rate supported by the UART controllers, etc.
The API also defines several macros. For example, :c:macro:`UART_HW_FIFO_LEN` defines the length of hardware FIFO buffers; :c:macro:`UART_BITRATE_MAX` gives the maximum baud rate supported by the UART controllers, etc.
.. _uart-api-deleting-driver:

1
docs/en/migration-guides/index.rst
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@ -11,3 +11,4 @@ ESP-IDF 5.x Migration Guide
release-5.x/5.0/index
release-5.x/5.1/index
release-5.x/5.2/index

9
docs/en/migration-guides/release-5.x/5.2/index.rst 100644
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@ -0,0 +1,9 @@
Migration from 5.1 to 5.2
-------------------------
:link_to_translation:`zh_CN:[中文]`
.. toctree::
:maxdepth: 1
peripherals

11
docs/en/migration-guides/release-5.x/5.2/peripherals.rst 100644
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@ -0,0 +1,11 @@
Peripherals
===========
:link_to_translation:`zh_CN:[中文]`
.. only:: SOC_UART_SUPPORTED
UART
----
- :c:macro:`UART_FIFO_LEN` is deprecated. Please use :c:macro:`UART_HW_FIFO_LEN` instead.

10
docs/zh_CN/api-reference/peripherals/uart.rst
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@ -8,9 +8,13 @@
通用异步接收器/发送器 (UART) 属于一种硬件功能，通过使用 RS232、RS422、RS485 等常见异步串行通信接口来处理通信时序要求和数据帧。UART 是实现不同设备之间全双工或半双工数据交换的一种常用且经济的方式。
{IDF_TARGET_NAME} 芯片有{IDF_TARGET_SOC_UART_NUM}个 UART 控制器（也称为端口），每个控制器都有一组相同的寄存器以简化编程并提高灵活性。
{IDF_TARGET_NAME} 芯片有{IDF_TARGET_SOC_UART_HP_NUM}个 UART 控制器（也称为端口），每个控制器都有一组相同的寄存器以简化编程并提高灵活性。
每个 UART 控制器可以独立配置波特率、数据位长度、位顺序、停止位位数、奇偶校验位等参数。所有控制器都与不同制造商的 UART 设备兼容，并且支持红外数据协会 (IrDA) 定义的标准协议。
每个 UART 控制器可以独立配置波特率、数据位长度、位顺序、停止位位数、奇偶校验位等参数。所有具备完整功能的 UART 控制器都能与不同制造商的 UART 设备兼容，并且支持红外数据协会 (IrDA) 定义的标准协议。
.. only:: SOC_UART_LP_NUM
此外，{IDF_TARGET_NAME} 芯片还有一个满足低功耗需求的 LP UART 控制器。LP UART 是原 UART 的功能剪裁版本。它只支持基础 UART 功能，不支持 IrDA 或 RS485 协议，并且只有一块较小的 RAM 存储空间。想要全面了解的 UART 及 LP UART 功能区别，请参考 *{IDF_TARGET_NAME} 技术参考手册* > UART 控制器 (UART) > 主要特性 [`PDF <{IDF_TARGET_TRM_EN_URL}#uart>`__]。
功能概述
-------------------
@ -238,7 +242,7 @@ API 提供了一种便利的方法来处理本文所讨论的特定中断，即
宏指令
^^^^^^^^^^^^
API 还定义了一些宏指令。例如，:c:macro:`UART_FIFO_LEN` 定义了硬件 FIFO 缓冲区的长度，:c:macro:`UART_BITRATE_MAX` 定义了 UART 控制器支持的最大波特率。
API 还定义了一些宏指令。例如，:c:macro:`UART_HW_FIFO_LEN` 定义了硬件 FIFO 缓冲区的长度，:c:macro:`UART_BITRATE_MAX` 定义了 UART 控制器支持的最大波特率。
.. _uart-api-deleting-driver:

1
docs/zh_CN/migration-guides/index.rst
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@ -11,3 +11,4 @@
release-5.x/5.0/index
release-5.x/5.1/index
release-5.x/5.2/index

9
docs/zh_CN/migration-guides/release-5.x/5.2/index.rst 100644
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@ -0,0 +1,9 @@
从 5.1 迁移到 5.2
-----------------
:link_to_translation:`en:[English]`
.. toctree::
:maxdepth: 1
peripherals

11
docs/zh_CN/migration-guides/release-5.x/5.2/peripherals.rst 100644
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@ -0,0 +1,11 @@
外设
============
:link_to_translation:`en:[English]`
.. only:: SOC_UART_SUPPORTED
UART
----
- :c:macro:`UART_FIFO_LEN` 已弃用，更新为 :c:macro:`UART_HW_FIFO_LEN`。

1
tools/ci/check_copyright_ignore.txt
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@ -970,7 +970,6 @@ components/soc/include/soc/ledc_periph.h
components/soc/include/soc/sdio_slave_periph.h
components/soc/include/soc/sdmmc_periph.h
components/soc/include/soc/sens_periph.h
components/soc/include/soc/uart_periph.h
components/soc/include/soc/uhci_periph.h
components/soc/lldesc.c
components/soc/soc_include_legacy_warn.c