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apm: added support for APM on esp32c6 

Closes: IDF-5819 IDF-5818
pull/10747/head
Sachin Billore 2023-01-24 20:24:33 +05:30 zatwierdzone przez BOT
rodzic e0e3700142
commit 8d0f6dab0f
8 zmienionych plików z 447 dodań i 10 usunięć
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2
components/esp_hw_support/dma/async_memcpy_impl_gdma.c
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@ -82,7 +82,7 @@ esp_err_t async_memcpy_impl_init(async_memcpy_impl_t *impl)
#if SOC_APM_SUPPORTED
// APM strategy: trusted mode
// TODO: IDF-5354 GDMA for M2M usage only need read and write permissions, we should disable the execute permission by the APM controller
apm_ll_set_master_secure_mode(APM_LL_MASTER_GDMA + m2m_trigger.instance_id, APM_LL_SECURE_MODE_TEE);
apm_tee_ll_set_master_secure_mode(APM_LL_MASTER_GDMA + m2m_trigger.instance_id, APM_LL_SECURE_MODE_TEE);
#endif // SOC_APM_SUPPORTED
gdma_rx_event_callbacks_t cbs = {

4
components/hal/CMakeLists.txt
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@ -155,6 +155,10 @@ if(NOT BOOTLOADER_BUILD)
list(APPEND srcs "${target}/pmu_hal.c")
endif()
if(CONFIG_SOC_APM_SUPPORTED)
list(APPEND srcs "apm_hal.c")
endif()
if(${target} STREQUAL "esp32")
list(APPEND srcs
"touch_sensor_hal.c"

80
components/hal/apm_hal.c 100644
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@ -0,0 +1,80 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "hal/assert.h"
#include "hal/apm_hal.h"
#include "hal/apm_ll.h"
void apm_tee_hal_set_master_secure_mode(apm_ll_master_id_t master_id, apm_ll_secure_mode_t sec_mode)
{
apm_tee_ll_set_master_secure_mode(master_id, sec_mode);
}
void apm_tee_hal_clk_gating_enable(bool enable)
{
apm_tee_ll_clk_gating_enable(enable);
}
void apm_hp_hal_region_filter_enable(uint32_t regn_num, bool enable)
{
apm_hp_ll_region_filter_enable(regn_num, enable);
}
void apm_hp_hal_m_filter_enable(apm_ll_hp_access_path_t hp_m_path, bool enable)
{
apm_hp_ll_m_filter_enable(hp_m_path, enable);
}
void apm_hp_hal_region_config(const apm_hp_hal_region_config_data_t *pms_data)
{
HAL_ASSERT((!pms_data) || (pms_data->regn_num > APM_LL_HP_MAX_REGION_NUM));
apm_hp_ll_set_region_start_address(pms_data->regn_num, pms_data->regn_start_addr);
apm_hp_ll_set_region_end_address(pms_data->regn_num, pms_data->regn_end_addr);
apm_hp_ll_sec_mode_region_attr_config(pms_data->regn_num, pms_data->sec_mode, pms_data->regn_pms);
}
uint8_t apm_hp_hal_m_exception_status(apm_ll_hp_access_path_t hp_m_path)
{
return apm_hp_ll_m_exception_status(hp_m_path);
}
void apm_hp_hal_m_exception_clear(apm_ll_hp_access_path_t hp_m_path)
{
apm_hp_ll_m_exception_clear(hp_m_path);
}
void apm_hp_hal_get_m_exception_info(apm_hp_m_exception_info_t *excp_info)
{
apm_hp_ll_get_m_exception_info(excp_info);
}
void apm_hp_hal_m_interrupt_enable(apm_ll_hp_access_path_t hp_m_path, bool enable)
{
apm_hp_ll_m_interrupt_enable(hp_m_path, enable);
}
void apm_hp_hal_clk_gating_enable(bool enable)
{
apm_hp_ll_clk_gating_enable(enable);
}
/* TBD: IDF-6759 */
void apm_hp_hal_master_sec_mode_config(apm_hp_secure_mode_config_t *sec_mode_data)
{
for (int i = 0; i < APM_LL_MASTER_MAX; i++) {
if (sec_mode_data->master_ids & (1 << i)) {
apm_tee_hal_set_master_secure_mode(i, sec_mode_data->sec_mode);
}
}
sec_mode_data->pms_data->sec_mode = sec_mode_data->sec_mode;
apm_hp_hal_region_config(sec_mode_data->pms_data);
}
void apm_hp_hal_reset_event_enable(bool enable)
{
apm_hp_ll_reset_event_enable(enable);
}

208
components/hal/esp32c6/include/hal/apm_ll.h
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@ -7,14 +7,30 @@
#include <stdint.h>
#include <stdbool.h>
#include "soc/pcr_reg.h"
#include "soc/tee_reg.h"
#define TEE_LL_MODE_CTRL_REG(master_id) (TEE_M0_MODE_CTRL_REG + 4 * (master_id))
#include "soc/hp_apm_reg.h"
#include "soc/hp_apm_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
#define TEE_LL_MODE_CTRL_REG(master_id) (TEE_M0_MODE_CTRL_REG + 4 * (master_id))
#define APM_LL_REGION_ADDR_START_REG(regn_num) (HP_APM_REGION0_ADDR_START_REG + 0xC * (regn_num))
#define APM_LL_REGION_ADDR_END_REG(regn_num) (HP_APM_REGION0_ADDR_END_REG + 0xC * (regn_num))
#define APM_LL_REGION_ADDR_ATTR_REG(regn_num) (HP_APM_REGION0_PMS_ATTR_REG + 0xC * (regn_num))
#define APM_LL_TEE_EXCP_STATUS_REG(sec_mode) (HP_APM_M0_STATUS_REG + 0x10 * (sec_mode))
#define APM_LL_TEE_EXCP_CLR_REG(sec_mode) (HP_APM_M0_STATUS_CLR_REG + 0x10 * (sec_mode))
#define APM_LL_TEE_EXCP_INFO0_REG(sec_mode) (HP_APM_M0_EXCEPTION_INFO0_REG + 0x10 * (sec_mode))
#define APM_LL_HP_SEC_MODE_REGION_ATTR(sec_mode, regn_pms) ((regn_pms) << (4 * (sec_mode - 1)))
#define APM_LL_HP_SEC_MODE_REGION_ATTR_V 0x00000003U
#define APM_LL_HP_SEC_MODE_REGION_ATTR_M(sec_mode) (APM_LL_HP_SEC_MODE_REGION_ATTR_V << (4 * (sec_mode - 1)))
#define APM_LL_HP_MAX_REGION_NUM 15
#define APM_LL_MASTER_MAX 32
/**
* @brief APM Master ID
*/
@ -46,17 +62,201 @@ typedef enum {
APM_LL_SECURE_MODE_REE2 = 3, /* Rich execution environment mode2 (need to configure APM strategy for this mode) */
} apm_ll_secure_mode_t;
/**
* @brief APM HP access path
*/
typedef enum {
APM_LL_HP_ACCESS_PATH_M0 = 0x0,
APM_LL_HP_ACCESS_PATH_M1 = 0x1,
APM_LL_HP_ACCESS_PATH_M2 = 0x2,
APM_LL_HP_ACCESS_PATH_M3 = 0x3,
} apm_ll_hp_access_path_t;
/**
* @brief APM exception information
*/
typedef struct {
uint8_t excp_id;
apm_ll_secure_mode_t sec_mode;
uint8_t excp_regn;
uint8_t excp_mode;
uint32_t excp_addr;
} apm_hp_m_exception_info_t;
/**
* @brief Set secure mode
*
* @param master_id APM master ID
* @param mode Secure mode
*/
static inline void apm_ll_set_master_secure_mode(apm_ll_master_id_t master_id, apm_ll_secure_mode_t mode)
static inline void apm_tee_ll_set_master_secure_mode(apm_ll_master_id_t master_id, apm_ll_secure_mode_t sec_mode)
{
REG_WRITE(TEE_LL_MODE_CTRL_REG(master_id), mode);
REG_WRITE(TEE_LL_MODE_CTRL_REG(master_id), sec_mode);
}
/**
* @brief TEE controller clock auto gating enable
*
* @param enable Flag for HP clock auto gating enable/disable
*/
static inline void apm_tee_ll_clk_gating_enable(bool enable)
{
if (enable) {
REG_SET_BIT(TEE_CLOCK_GATE_REG, TEE_CLK_EN);
} else {
REG_CLR_BIT(TEE_CLOCK_GATE_REG, TEE_CLK_EN);
}
}
/**
* @brief enable/disable HP Region access permission filter
*
* @param regn_num Memory Region number
* @param enable Flag for Region access filter enable/disable
*/
static inline void apm_hp_ll_region_filter_enable(uint32_t regn_num, bool enable)
{
if (enable) {
REG_SET_BIT(HP_APM_REGION_FILTER_EN_REG, BIT(regn_num));
} else {
REG_CLR_BIT(HP_APM_REGION_FILTER_EN_REG, BIT(regn_num));
}
}
/**
* @brief enable/disable HP access path(M[0:3])
*
* @param hp_m_path HP access path
* @param enable Flag for HP M path filter enable/disable
*/
static inline void apm_hp_ll_m_filter_enable(apm_ll_hp_access_path_t hp_m_path, bool enable)
{
if (enable) {
REG_SET_BIT(HP_APM_FUNC_CTRL_REG, BIT(hp_m_path));
} else {
REG_CLR_BIT(HP_APM_FUNC_CTRL_REG, BIT(hp_m_path));
}
}
/**
* @brief HP Region start address configuration
*
* @param regn_num HP Region number to be configured
* @param addr Region start address
*/
static inline void apm_hp_ll_set_region_start_address(uint32_t regn_num, uint32_t addr)
{
REG_WRITE(APM_LL_REGION_ADDR_START_REG(regn_num), addr);
}
/**
* @brief HP Region end address configuration
*
* @param regn_num HP Region number to be configured
* @param addr Region end address
*/
static inline void apm_hp_ll_set_region_end_address(uint32_t regn_num, uint32_t addr)
{
REG_WRITE(APM_LL_REGION_ADDR_END_REG(regn_num), addr);
}
/**
* @brief HP Region pms attributes configuration
*
* @param regn_num Region number to be configured
* @param sec_mode Secure mode of the Master
* @param regn_pms XWR permissions for the given secure mode and Region number
*/
static inline void apm_hp_ll_sec_mode_region_attr_config(uint32_t regn_num, apm_ll_secure_mode_t sec_mode, uint32_t regn_pms)
{
uint32_t val = 0;
val = REG_READ(APM_LL_REGION_ADDR_ATTR_REG(regn_num));
val &= ~APM_LL_HP_SEC_MODE_REGION_ATTR_M(sec_mode);
val |= APM_LL_HP_SEC_MODE_REGION_ATTR(sec_mode, regn_pms);
REG_WRITE(APM_LL_REGION_ADDR_ATTR_REG(regn_num), val);
}
/**
* @brief Get HP access path(M[0:3]) exception status
*
* @param hp_m_path HP access path
*/
static inline uint8_t apm_hp_ll_m_exception_status(apm_ll_hp_access_path_t hp_m_path)
{
return REG_READ(APM_LL_TEE_EXCP_STATUS_REG(hp_m_path));
}
/**
* @brief Clear HP access path(M[0:3]) exception
*
* @param hp_m_path HP access path
*/
static inline void apm_hp_ll_m_exception_clear(apm_ll_hp_access_path_t hp_m_path)
{
REG_SET_BIT(APM_LL_TEE_EXCP_CLR_REG(hp_m_path), HP_APM_M0_REGION_STATUS_CLR);
}
/**
* @brief Get HP access path(M[0:3]) exception information
*
* @param excp_info Exception related information like addr,
* region, sec_mode and master id
*/
static inline void apm_hp_ll_get_m_exception_info(apm_hp_m_exception_info_t *excp_info)
{
excp_info->excp_id = REG_GET_FIELD(APM_LL_TEE_EXCP_INFO0_REG(excp_info->sec_mode), HP_APM_M0_EXCEPTION_ID);
excp_info->excp_mode = REG_GET_FIELD(APM_LL_TEE_EXCP_INFO0_REG(excp_info->sec_mode), HP_APM_M0_EXCEPTION_MODE);
excp_info->excp_regn = REG_GET_FIELD(APM_LL_TEE_EXCP_INFO0_REG(excp_info->sec_mode), HP_APM_M0_EXCEPTION_REGION);
excp_info->excp_addr = REG_READ(HP_APM_M0_EXCEPTION_INFO1_REG);
}
/**
* @brief Interrupt enable for access path(M[0:3])
*
* @param hp_m_path HP access path
* @param enable Flag for access path interrupt enable/disable
*/
static inline void apm_hp_ll_m_interrupt_enable(apm_ll_hp_access_path_t hp_m_path, bool enable)
{
if (enable) {
REG_SET_BIT(HP_APM_INT_EN_REG, BIT(hp_m_path));
} else {
REG_CLR_BIT(HP_APM_INT_EN_REG, BIT(hp_m_path));
}
}
/**
* @brief HP clock auto gating enable
*
* @param enable Flag for HP clock auto gating enable/disable
*/
static inline void apm_hp_ll_clk_gating_enable(bool enable)
{
if (enable) {
REG_SET_BIT(HP_APM_CLOCK_GATE_REG, HP_APM_CLK_EN);
} else {
REG_CLR_BIT(HP_APM_CLOCK_GATE_REG, HP_APM_CLK_EN);
}
}
/**
* @brief APM/TEE/HP System Reg reset event bypass enable
*
* Disable: tee_reg/apm_reg/hp_system_reg will not only be reset by power-reset,
* but also some reset events.
* Enable: tee_reg/apm_reg/hp_system_reg will only be reset by power-reset.
* Some reset events will be bypassed.
*
* @param enable Flag for event bypass enable/disable
*/
static inline void apm_hp_ll_reset_event_enable(bool enable)
{
if (enable) {
REG_SET_BIT(PCR_RESET_EVENT_BYPASS_REG, PCR_RESET_EVENT_BYPASS_APM);
} else {
REG_CLR_BIT(PCR_RESET_EVENT_BYPASS_REG, PCR_RESET_EVENT_BYPASS_APM);
}
}
#ifdef __cplusplus
}
#endif

134
components/hal/include/hal/apm_hal.h 100644
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@ -0,0 +1,134 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "hal/apm_ll.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Region configuration data.
*/
typedef struct {
apm_ll_secure_mode_t sec_mode;
uint32_t regn_num;
uint32_t regn_start_addr;
uint32_t regn_end_addr;
uint32_t regn_pms;
} apm_hp_hal_region_config_data_t;
/**
* @brief Secure mode(TEE/REE[0:2] configuration data.
*/
typedef struct {
apm_ll_secure_mode_t sec_mode; /* Secure mode to be configured TEE/REE[0:2]. */
uint32_t master_ids; /* Bit mask for masters to be part of this secure mode. */
apm_hp_hal_region_config_data_t *pms_data; /* Region configuration data. */
} apm_hp_secure_mode_config_t;
/**
* @brief Set secure mode
*
* @param master_id APM master ID
* @param sec_mode Secure mode
*/
void apm_tee_hal_set_master_secure_mode(apm_ll_master_id_t master_id, apm_ll_secure_mode_t sec_mode);
/**
* @brief TEE controller clock auto gating enable
*
* @param enable Flag for HP clock auto gating enable/disable
*/
void apm_tee_hal_clk_gating_enable(bool enable);
/**
* @brief enable/disable HP Region access permission filter
*
* @param regn_num Memory Region number
* @param enable Flag for Region access filter enable/disable
*/
void apm_hp_hal_region_filter_enable(uint32_t regn_num, bool enable);
/**
* @brief enable/disable HP access path(M[0:3])
*
* @param hp_m_path HP access path
* @param enable Flag for HP M path filter enable/disable
*/
void apm_hp_hal_m_filter_enable(apm_ll_hp_access_path_t hp_m_path, bool enable);
/**
* @brief Region configuration
*
* @param pms_data Region configuration data
*/
void apm_hp_hal_region_config(const apm_hp_hal_region_config_data_t *pms_data);
/**
* @brief Get HP access path(M[0:3]) exception status
*
* @param hp_m_path HP access path
*/
uint8_t apm_hp_hal_m_exception_status(apm_ll_hp_access_path_t hp_m_path);
/**
* @brief Clear HP access path(M[0:3]) exception
*
* @param hp_m_path HP access path
*/
void apm_hp_hal_m_exception_clear(apm_ll_hp_access_path_t hp_m_path);
/**
* @brief Get HP access path(M[0:3]) exception information
*
* @param excp_info Exception related information like addr,
* region, sec_mode and master id
*/
void apm_hp_hal_get_m_exception_info(apm_hp_m_exception_info_t *excp_info);
/**
* @brief Interrupt enable for access path(M[0:3])
*
* @param hp_m_path HP access path
* @param enable Flag for access path interrupt enable/disable
*/
void apm_hp_hal_m_interrupt_enable(apm_ll_hp_access_path_t hp_m_path, bool enable);
/**
* @brief HP clock auto gating enable
*
* @param enable Flag for HP clock auto gating enable/disable
*/
void apm_hp_hal_clk_gating_enable(bool enable);
/**
* @brief TEE/REE execution environment configuration.
*
* This API will be called from TEE mode initialization code which is
* responsible to setup TEE/REE execution environment.
* It includes, allocation of all bus masters, memory ranges and other
* peripherals to the given secure mode.
* All this information should be passed by the TEE mode initialization code.
*/
void apm_hp_hal_master_sec_mode_config(apm_hp_secure_mode_config_t *sec_mode_data);
/**
* @brief APM/TEE/HP System Reg reset event bypass enable
*
* Disable: tee_reg/apm_reg/hp_system_reg will not only be reset by power-reset,
* but also some reset events.
* Enable: tee_reg/apm_reg/hp_system_reg will only be reset by power-reset.
* Some reset events will be bypassed.
*
* @param enable Flag for event bypass enable/disable
*/
void apm_hp_hal_reset_event_enable(bool enable);
#ifdef __cplusplus
}
#endif

23
components/hal/include/hal/apm_types.h 100644
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@ -0,0 +1,23 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief APM Region PMS authority
*/
typedef enum {
APM_REGION_PMS_X = 0x1, /*!< Region executive authority. */
APM_REGION_PMS_W = 0x2, /*!< Region write authority. */
APM_REGION_PMS_R = 0x4, /*!< Region read authority. */
} apm_region_pms_t;
#ifdef __cplusplus
}
#endif

4
components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
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@ -95,10 +95,6 @@ config SOC_BOD_SUPPORTED
bool
default y
config SOC_APM_SUPPORTED
bool
default y
config SOC_XTAL_SUPPORT_32M
bool
default y

2
components/soc/esp32h2/include/soc/soc_caps.h
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@ -62,7 +62,7 @@
// #define SOC_FLASH_ENC_SUPPORTED 1 // TODO: IDF-6282
// #define SOC_SECURE_BOOT_SUPPORTED 1 // TODO: IDF-6281
#define SOC_BOD_SUPPORTED 1
#define SOC_APM_SUPPORTED 1
// #define SOC_APM_SUPPORTED 1 // TODO: IDF-6277
/*-------------------------- XTAL CAPS ---------------------------------------*/
#define SOC_XTAL_SUPPORT_32M 1