From 6d40e191f8a78ffd4f441201de697674c4a2bf80 Mon Sep 17 00:00:00 2001 From: Darian Leung Date: Fri, 15 Mar 2024 02:37:26 +0800 Subject: [PATCH] refactor(hal/usb): Refactor usb_wrap_ll.h This commit rewrite the 'usb_wrap_ll.h' API as follows: - All APIs renamed from 'usb_fsls_phy_ll_...()' to 'usb_wrap_ll_...()' - APIs now match their equivalent counter parts in 'usb_serial_jtag_ll.h' --- .../src/bootloader_console.c | 9 +- .../hal/esp32s2/include/hal/usb_wrap_ll.h | 217 ++++++++++--- .../hal/esp32s3/include/hal/usb_wrap_ll.h | 298 +++++++++++------- components/hal/usb_wrap_hal.c | 45 +-- components/usb/usb_phy.c | 12 +- 5 files changed, 388 insertions(+), 193 deletions(-) diff --git a/components/bootloader_support/src/bootloader_console.c b/components/bootloader_support/src/bootloader_console.c index 066eac3114..3f5aa7f7b9 100644 --- a/components/bootloader_support/src/bootloader_console.c +++ b/components/bootloader_support/src/bootloader_console.c @@ -19,7 +19,7 @@ #include "esp32s2/rom/usb/cdc_acm.h" #include "esp32s2/rom/usb/usb_common.h" #endif -#if CONFIG_ESP_CONSOLE_USB_CDC && SOC_USB_SERIAL_JTAG_SUPPORTED +#if CONFIG_ESP_CONSOLE_USB_CDC #include "hal/usb_wrap_ll.h" #endif #include "esp_rom_gpio.h" @@ -106,10 +106,9 @@ void bootloader_console_init(void) esp_rom_output_usb_acm_init(s_usb_cdc_buf, sizeof(s_usb_cdc_buf)); esp_rom_output_set_as_console(ESP_ROM_USB_OTG_NUM); esp_rom_install_channel_putc(1, bootloader_console_write_char_usb); -#if SOC_USB_SERIAL_JTAG_SUPPORTED - usb_fsls_phy_ll_usb_wrap_pad_enable(&USB_WRAP, true); - usb_fsls_phy_ll_int_otg_enable(&USB_WRAP); -#endif + // Ensure that the USB FSLS PHY is mapped to the USB WRAP + usb_wrap_ll_phy_enable_pad(&USB_WRAP, true); + usb_wrap_ll_phy_enable_external(&USB_WRAP, false); } #endif //CONFIG_ESP_CONSOLE_USB_CDC diff --git a/components/hal/esp32s2/include/hal/usb_wrap_ll.h b/components/hal/esp32s2/include/hal/usb_wrap_ll.h index 91de90b145..879106067c 100644 --- a/components/hal/esp32s2/include/hal/usb_wrap_ll.h +++ b/components/hal/esp32s2/include/hal/usb_wrap_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -16,101 +16,224 @@ extern "C" { #endif +/* ---------------------------- USB PHY Control ---------------------------- */ + /** - * @brief Configures the internal PHY for USB_OTG + * @brief Enables and sets the override value for the session end signal * * @param hw Start address of the USB Wrap registers + * @param sessend Session end override value. True means VBus < 0.2V, false means VBus > 0.8V */ -static inline void usb_fsls_phy_ll_int_otg_enable(usb_wrap_dev_t *hw) +FORCE_INLINE_ATTR void usb_wrap_ll_phy_enable_srp_sessend_override(usb_wrap_dev_t *hw, bool sessend) { - hw->otg_conf.phy_sel = 0; + hw->otg_conf.srp_sessend_value = sessend; + hw->otg_conf.srp_sessend_override = 1; } /** - * @brief Configures the external PHY for USB_OTG + * @brief Disable session end override * * @param hw Start address of the USB Wrap registers */ -static inline void usb_fsls_phy_ll_ext_otg_enable(usb_wrap_dev_t *hw) +FORCE_INLINE_ATTR void usb_wrap_ll_phy_disable_srp_sessend_override(usb_wrap_dev_t *hw) { - //Enable external PHY - hw->otg_conf.phy_sel = 1; + hw->otg_conf.srp_sessend_override = 0; } /** - * @brief Configures port loads for the internal PHY + * @brief Sets whether the USB Wrap's FSLS PHY interface routes to an internal or external PHY * * @param hw Start address of the USB Wrap registers - * @param dp_pu D+ pullup load - * @param dp_pd D+ pulldown load - * @param dm_pu D- pullup load - * @param dm_pd D- pulldown load + * @param enable Enables external PHY, internal otherwise */ -static inline void usb_fsls_phy_ll_int_load_conf(usb_wrap_dev_t *hw, bool dp_pu, bool dp_pd, bool dm_pu, bool dm_pd) +FORCE_INLINE_ATTR void usb_wrap_ll_phy_enable_external(usb_wrap_dev_t *hw, bool enable) { - usb_wrap_otg_conf_reg_t conf; - conf.val = hw->otg_conf.val; - conf.pad_pull_override = 1; - conf.dp_pullup = dp_pu; - conf.dp_pulldown = dp_pd; - conf.dm_pullup = dm_pu; - conf.dm_pulldown = dm_pd; - hw->otg_conf.val = conf.val; + hw->otg_conf.phy_sel = enable; } /** - * @brief Enable the internal PHY control to D+/D- pad - * @param hw Start address of the USB Wrap registers - * @param pad_en Enable the PHY control to D+/D- pad - */ -static inline void usb_fsls_phy_ll_usb_wrap_pad_enable(usb_wrap_dev_t *hw, bool pad_en) -{ - hw->otg_conf.pad_enable = pad_en; -} - -/** - * @brief Enable the internal PHY's test mode + * @brief Enables/disables exchanging of the D+/D- pins USB PHY * * @param hw Start address of the USB Wrap registers - * @param en Whether to enable the internal PHY's test mode + * @param enable Enables pin exchange, disabled otherwise */ -static inline void usb_fsls_phy_ll_int_enable_test_mode(usb_wrap_dev_t *hw, bool en) +FORCE_INLINE_ATTR void usb_wrap_ll_phy_enable_pin_exchg(usb_wrap_dev_t *hw, bool enable) { - if (en) { - // Clear USB_WRAP_TEST_CONF_REG - hw->test_conf.val = 0; - // Set USB test pad oen - hw->test_conf.test_usb_wrap_oe = 1; - // Enable USB test mode - hw->test_conf.test_enable = 1; + if (enable) { + hw->otg_conf.exchg_pins = 1; + hw->otg_conf.exchg_pins_override = 1; } else { - hw->test_conf.test_enable = 0; + hw->otg_conf.exchg_pins_override = 0; + hw->otg_conf.exchg_pins = 0; } } +/** + * @brief Enables and sets voltage threshold overrides for USB FSLS PHY single-ended inputs + * + * @param hw Start address of the USB Wrap registers + * @param vrefh_step High voltage threshold. 0 to 3 indicating 80mV steps from 1.76V to 2V. + * @param vrefl_step Low voltage threshold. 0 to 3 indicating 80mV steps from 0.8V to 1.04V. + */ +FORCE_INLINE_ATTR void usb_wrap_ll_phy_enable_vref_override(usb_wrap_dev_t *hw, unsigned int vrefh_step, unsigned int vrefl_step) +{ + hw->otg_conf.vrefh = vrefh_step; + hw->otg_conf.vrefl = vrefl_step; + hw->otg_conf.vref_override = 1; +} + +/** + * @brief Disables voltage threshold overrides for USB FSLS PHY single-ended inputs + * + * @param hw Start address of the USB Wrap registers + */ +FORCE_INLINE_ATTR void usb_wrap_ll_phy_disable_vref_override(usb_wrap_dev_t *hw) +{ + hw->otg_conf.vref_override = 0; +} + +/** + * @brief Enable override of USB FSLS PHY's pull up/down resistors + * + * @param hw Start address of the USB Wrap registers + * @param dp_pu Enable D+ pullup + * @param dm_pu Enable D- pullup + * @param dp_pd Enable D+ pulldown + * @param dm_pd Enable D- pulldown + */ +FORCE_INLINE_ATTR void usb_wrap_ll_phy_enable_pull_override(usb_wrap_dev_t *hw, bool dp_pu, bool dm_pu, bool dp_pd, bool dm_pd) +{ + hw->otg_conf.dp_pullup = dp_pu; + hw->otg_conf.dp_pulldown = dp_pd; + hw->otg_conf.dm_pullup = dm_pu; + hw->otg_conf.dm_pulldown = dm_pd; + hw->otg_conf.pad_pull_override = 1; +} + +/** + * @brief Disable override of USB FSLS PHY pull up/down resistors + * + * @param hw Start address of the USB Wrap registers + */ +FORCE_INLINE_ATTR void usb_wrap_ll_phy_disable_pull_override(usb_wrap_dev_t *hw) +{ + hw->otg_conf.pad_pull_override = 0; +} + +/** + * @brief Sets the strength of the pullup resistor + * + * @param hw Start address of the USB Wrap registers + * @param strong True is a ~1.4K pullup, false is a ~2.4K pullup + */ +FORCE_INLINE_ATTR void usb_wrap_ll_phy_set_pullup_strength(usb_wrap_dev_t *hw, bool strong) +{ + hw->otg_conf.pullup_value = strong; +} + +/** + * @brief Check if USB FSLS PHY pads are enabled + * + * @param hw Start address of the USB Wrap registers + * @return True if enabled, false otherwise + */ +FORCE_INLINE_ATTR bool usb_wrap_ll_phy_is_pad_enabled(usb_wrap_dev_t *hw) +{ + return hw->otg_conf.pad_enable; +} + +/** + * @brief Enable the USB FSLS PHY pads + * + * @param hw Start address of the USB Wrap registers + * @param enable Whether to enable the USB FSLS PHY pads + */ +FORCE_INLINE_ATTR void usb_wrap_ll_phy_enable_pad(usb_wrap_dev_t *hw, bool enable) +{ + hw->otg_conf.pad_enable = enable; +} + +/** + * @brief Set USB FSLS PHY TX output clock edge + * + * @param hw Start address of the USB Wrap registers + * @param clk_neg_edge True if TX output at negedge, posedge otherwise + */ +FORCE_INLINE_ATTR void usb_wrap_ll_phy_set_tx_edge(usb_wrap_dev_t *hw, bool clk_neg_edge) +{ + hw->otg_conf.phy_tx_edge_sel = clk_neg_edge; +} + +/* ------------------------------ USB PHY Test ------------------------------ */ + +/** + * @brief Enable the USB FSLS PHY's test mode + * + * @param hw Start address of the USB Wrap registers + * @param enable Whether to enable the USB FSLS PHY's test mode + */ +FORCE_INLINE_ATTR void usb_wrap_ll_phy_enable_test_mode(usb_wrap_dev_t *hw, bool enable) +{ + hw->test_conf.test_enable = enable; +} + +/** + * @brief Set the USB FSLS PHY's signal test values + * + * @param hw Start address of the USB Wrap registers + * @param oen Output Enable (active low) signal + * @param tx_dp TX D+ + * @param tx_dm TX D- + * @param rx_dp RX D+ + * @param rx_dm RX D- + * @param rx_rcv RX RCV + */ +FORCE_INLINE_ATTR void usb_wrap_ll_phy_test_mode_set_signals(usb_wrap_dev_t *hw, + bool oen, + bool tx_dp, + bool tx_dm, + bool rx_dp, + bool rx_dm, + bool rx_rcv) +{ + usb_wrap_test_conf_reg_t test_conf; + test_conf.val = hw->test_conf.val; + + test_conf.test_usb_wrap_oe = oen; + test_conf.test_tx_dp = tx_dp; + test_conf.test_tx_dm = tx_dm; + test_conf.test_rx_rcv = rx_rcv; + test_conf.test_rx_dp = rx_dp; + test_conf.test_rx_dm = rx_dm; + + hw->test_conf.val = test_conf.val; +} + +/* ----------------------------- RCC Functions ----------------------------- */ + /** * Enable the bus clock for USB Wrap module * @param clk_en True if enable the clock of USB Wrap module */ -FORCE_INLINE_ATTR void usb_fsls_phy_ll_usb_wrap_enable_bus_clock(bool clk_en) +FORCE_INLINE_ATTR void usb_wrap_ll_enable_bus_clock(bool clk_en) { REG_SET_FIELD(DPORT_PERIP_CLK_EN0_REG, DPORT_USB_CLK_EN, clk_en); } // SYSTEM.perip_clk_enx are shared registers, so this function must be used in an atomic way -#define usb_fsls_phy_ll_usb_wrap_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; usb_fsls_phy_ll_usb_wrap_enable_bus_clock(__VA_ARGS__) +#define usb_wrap_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; usb_wrap_ll_enable_bus_clock(__VA_ARGS__) /** * @brief Reset the USB Wrap module */ -FORCE_INLINE_ATTR void usb_fsls_phy_ll_usb_wrap_reset_register(void) +FORCE_INLINE_ATTR void usb_wrap_ll_reset_register(void) { REG_SET_FIELD(DPORT_PERIP_RST_EN0_REG, DPORT_USB_RST, 1); REG_SET_FIELD(DPORT_PERIP_RST_EN0_REG, DPORT_USB_RST, 0); } // SYSTEM.perip_clk_enx are shared registers, so this function must be used in an atomic way -#define usb_fsls_phy_ll_usb_wrap_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; usb_fsls_phy_ll_usb_wrap_reset_register(__VA_ARGS__) +#define usb_wrap_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; usb_wrap_ll_reset_register(__VA_ARGS__) #ifdef __cplusplus } diff --git a/components/hal/esp32s3/include/hal/usb_wrap_ll.h b/components/hal/esp32s3/include/hal/usb_wrap_ll.h index f8195dd89e..e3dd68a2b9 100644 --- a/components/hal/esp32s3/include/hal/usb_wrap_ll.h +++ b/components/hal/esp32s3/include/hal/usb_wrap_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -12,167 +12,237 @@ #include "soc/system_struct.h" #include "soc/usb_wrap_struct.h" #include "soc/rtc_cntl_struct.h" -#include "soc/usb_serial_jtag_struct.h" #ifdef __cplusplus extern "C" { #endif +/* ---------------------------- USB PHY Control ---------------------------- */ + /** - * @brief Configures the internal PHY for USB_OTG + * @brief Enables and sets the override value for the session end signal + * + * @param hw Start address of the USB Wrap registers + * @param sessend Session end override value. True means VBus < 0.2V, false means VBus > 0.8V + */ +FORCE_INLINE_ATTR void usb_wrap_ll_phy_enable_srp_sessend_override(usb_wrap_dev_t *hw, bool sessend) +{ + hw->otg_conf.srp_sessend_value = sessend; + hw->otg_conf.srp_sessend_override = 1; +} + +/** + * @brief Disable session end override * * @param hw Start address of the USB Wrap registers */ -static inline void usb_fsls_phy_ll_int_otg_enable(usb_wrap_dev_t *hw) +FORCE_INLINE_ATTR void usb_wrap_ll_phy_disable_srp_sessend_override(usb_wrap_dev_t *hw) { - // USB_OTG use internal PHY - hw->otg_conf.phy_sel = 0; - // phy_sel is controlled by the following register value - RTCCNTL.usb_conf.sw_hw_usb_phy_sel = 1; - // phy_sel=sw_usb_phy_sel=1, USB_OTG is connected with internal PHY - RTCCNTL.usb_conf.sw_usb_phy_sel = 1; + hw->otg_conf.srp_sessend_override = 0; } /** - * @brief Configures the external PHY for USB_OTG + * @brief Sets whether the USB Wrap's FSLS PHY interface routes to an internal or external PHY * * @param hw Start address of the USB Wrap registers + * @param enable Enables external PHY, internal otherwise */ -static inline void usb_fsls_phy_ll_ext_otg_enable(usb_wrap_dev_t *hw) +FORCE_INLINE_ATTR void usb_wrap_ll_phy_enable_external(usb_wrap_dev_t *hw, bool enable) { - // USB_OTG use external PHY - hw->otg_conf.phy_sel = 1; - // phy_sel is controlled by the following register value + hw->otg_conf.phy_sel = enable; + // Enable SW control of muxing USB OTG vs USJ to the internal USB FSLS PHY RTCCNTL.usb_conf.sw_hw_usb_phy_sel = 1; - // phy_sel=sw_usb_phy_sel=0, USB_OTG is connected with external PHY through GPIO Matrix - RTCCNTL.usb_conf.sw_usb_phy_sel = 0; + /* + For 'sw_usb_phy_sel': + 0 - Internal USB FSLS PHY is mapped to the USJ. USB Wrap mapped to external PHY + 1 - Internal USB FSLS PHY is mapped to the USB Wrap. USJ mapped to external PHY + */ + RTCCNTL.usb_conf.sw_usb_phy_sel = !enable; } /** - * @brief Configures the internal PHY for USB_Serial_JTAG - * - * @param hw Start address of the USB Serial_JTAG registers - */ -static inline void usb_fsls_phy_ll_int_jtag_enable(usb_serial_jtag_dev_t *hw) -{ - // USB_Serial_JTAG use internal PHY - hw->conf0.phy_sel = 0; - // Disable software control USB D+ D- pullup pulldown (Device FS: dp_pullup = 1) - hw->conf0.pad_pull_override = 0; - // Enable USB D+ pullup - hw->conf0.dp_pullup = 1; - // Enable USB pad function - hw->conf0.usb_pad_enable = 1; - // phy_sel is controlled by the following register value - RTCCNTL.usb_conf.sw_hw_usb_phy_sel = 1; - // phy_sel=sw_usb_phy_sel=0, USB_Serial_JTAG is connected with internal PHY - RTCCNTL.usb_conf.sw_usb_phy_sel = 0; -} - -/** - * @brief Disable the internal PHY for USB_Serial_JTAG - * - * @param hw Start address of the USB Serial_JTAG registers - */ -static inline void usb_fsls_phy_ll_int_jtag_disable(usb_serial_jtag_dev_t *hw) -{ - // Disable USB D+ pullup - hw->conf0.dp_pullup = 0; - // Disable USB pad function - hw->conf0.usb_pad_enable = 0; -} - -/** - * @brief Configures the external PHY for USB_Serial_JTAG - * - * @param hw Start address of the USB Serial_JTAG registers - */ -static inline void usb_fsls_phy_ll_ext_jtag_enable(usb_serial_jtag_dev_t *hw) -{ - // USB_Serial_JTAG use external PHY - hw->conf0.phy_sel = 1; - // phy_sel is controlled by the following register value - RTCCNTL.usb_conf.sw_hw_usb_phy_sel = 1; - // phy_sel=sw_usb_phy_sel=1, USB_Serial_JTAG is connected with external PHY - RTCCNTL.usb_conf.sw_usb_phy_sel = 1; -} - -/** - * @brief Configures port loads for the internal PHY + * @brief Enables/disables exchanging of the D+/D- pins USB PHY * * @param hw Start address of the USB Wrap registers - * @param dp_pu D+ pullup load - * @param dp_pd D+ pulldown load - * @param dm_pu D- pullup load - * @param dm_pd D- pulldown load + * @param enable Enables pin exchange, disabled otherwise */ -static inline void usb_fsls_phy_ll_int_load_conf(usb_wrap_dev_t *hw, bool dp_pu, bool dp_pd, bool dm_pu, bool dm_pd) +FORCE_INLINE_ATTR void usb_wrap_ll_phy_enable_pin_exchg(usb_wrap_dev_t *hw, bool enable) { - usb_wrap_otg_conf_reg_t conf; - conf.val = hw->otg_conf.val; - - conf.pad_pull_override = 1; - conf.dp_pullup = dp_pu; - conf.dp_pulldown = dp_pd; - conf.dm_pullup = dm_pu; - conf.dm_pulldown = dm_pd; - - hw->otg_conf.val = conf.val; -} - -/** - * @brief Enable the internal PHY control to D+/D- pad - * @param hw Start address of the USB Wrap registers - * @param pad_en Enable the PHY control to D+/D- pad - */ -static inline void usb_fsls_phy_ll_usb_wrap_pad_enable(usb_wrap_dev_t *hw, bool pad_en) -{ - hw->otg_conf.pad_enable = pad_en; -} - -/** - * @brief Enable the internal PHY's test mode - * - * @param hw Start address of the USB Wrap registers - * @param en Whether to enable the internal PHY's test mode - */ -static inline void usb_fsls_phy_ll_int_enable_test_mode(usb_wrap_dev_t *hw, bool en) -{ - if (en) { - // Clear USB_WRAP_TEST_CONF_REG - hw->test_conf.val = 0; - // Set USB test pad oen - hw->test_conf.test_usb_wrap_oe = 1; - // Enable USB test mode - hw->test_conf.test_enable = 1; + if (enable) { + hw->otg_conf.exchg_pins = 1; + hw->otg_conf.exchg_pins_override = 1; } else { - hw->test_conf.test_enable = 0; + hw->otg_conf.exchg_pins_override = 0; + hw->otg_conf.exchg_pins = 0; } } +/** + * @brief Enables and sets voltage threshold overrides for USB FSLS PHY single-ended inputs + * + * @param hw Start address of the USB Wrap registers + * @param vrefh_step High voltage threshold. 0 to 3 indicating 80mV steps from 1.76V to 2V. + * @param vrefl_step Low voltage threshold. 0 to 3 indicating 80mV steps from 0.8V to 1.04V. + */ +FORCE_INLINE_ATTR void usb_wrap_ll_phy_enable_vref_override(usb_wrap_dev_t *hw, unsigned int vrefh_step, unsigned int vrefl_step) +{ + hw->otg_conf.vrefh = vrefh_step; + hw->otg_conf.vrefl = vrefl_step; + hw->otg_conf.vref_override = 1; +} + +/** + * @brief Disables voltage threshold overrides for USB FSLS PHY single-ended inputs + * + * @param hw Start address of the USB Wrap registers + */ +FORCE_INLINE_ATTR void usb_wrap_ll_phy_disable_vref_override(usb_wrap_dev_t *hw) +{ + hw->otg_conf.vref_override = 0; +} + +/** + * @brief Enable override of USB FSLS PHY's pull up/down resistors + * + * @param hw Start address of the USB Wrap registers + * @param dp_pu Enable D+ pullup + * @param dm_pu Enable D- pullup + * @param dp_pd Enable D+ pulldown + * @param dm_pd Enable D- pulldown + */ +FORCE_INLINE_ATTR void usb_wrap_ll_phy_enable_pull_override(usb_wrap_dev_t *hw, bool dp_pu, bool dm_pu, bool dp_pd, bool dm_pd) +{ + hw->otg_conf.dp_pullup = dp_pu; + hw->otg_conf.dp_pulldown = dp_pd; + hw->otg_conf.dm_pullup = dm_pu; + hw->otg_conf.dm_pulldown = dm_pd; + hw->otg_conf.pad_pull_override = 1; +} + +/** + * @brief Disable override of USB FSLS PHY pull up/down resistors + * + * @param hw Start address of the USB Wrap registers + */ +FORCE_INLINE_ATTR void usb_wrap_ll_phy_disable_pull_override(usb_wrap_dev_t *hw) +{ + hw->otg_conf.pad_pull_override = 0; +} + +/** + * @brief Sets the strength of the pullup resistor + * + * @param hw Start address of the USB Wrap registers + * @param strong True is a ~1.4K pullup, false is a ~2.4K pullup + */ +FORCE_INLINE_ATTR void usb_wrap_ll_phy_set_pullup_strength(usb_wrap_dev_t *hw, bool strong) +{ + hw->otg_conf.pullup_value = strong; +} + +/** + * @brief Check if USB FSLS PHY pads are enabled + * + * @param hw Start address of the USB Wrap registers + * @return True if enabled, false otherwise + */ +FORCE_INLINE_ATTR bool usb_wrap_ll_phy_is_pad_enabled(usb_wrap_dev_t *hw) +{ + return hw->otg_conf.pad_enable; +} + +/** + * @brief Enable the USB FSLS PHY pads + * + * @param hw Start address of the USB Wrap registers + * @param enable Whether to enable the USB FSLS PHY pads + */ +FORCE_INLINE_ATTR void usb_wrap_ll_phy_enable_pad(usb_wrap_dev_t *hw, bool enable) +{ + hw->otg_conf.pad_enable = enable; +} + +/** + * @brief Set USB FSLS PHY TX output clock edge + * + * @param hw Start address of the USB Wrap registers + * @param clk_neg_edge True if TX output at negedge, posedge otherwise + */ +FORCE_INLINE_ATTR void usb_wrap_ll_phy_set_tx_edge(usb_wrap_dev_t *hw, bool clk_neg_edge) +{ + hw->otg_conf.phy_tx_edge_sel = clk_neg_edge; +} + +/* ------------------------------ USB PHY Test ------------------------------ */ + +/** + * @brief Enable the USB FSLS PHY's test mode + * + * @param hw Start address of the USB Wrap registers + * @param enable Whether to enable the USB FSLS PHY's test mode + */ +FORCE_INLINE_ATTR void usb_wrap_ll_phy_enable_test_mode(usb_wrap_dev_t *hw, bool enable) +{ + hw->test_conf.test_enable = enable; +} + +/** + * @brief Set the USB FSLS PHY's signal test values + * + * @param hw Start address of the USB Wrap registers + * @param oen Output Enable (active low) signal + * @param tx_dp TX D+ + * @param tx_dm TX D- + * @param rx_dp RX D+ + * @param rx_dm RX D- + * @param rx_rcv RX RCV + */ +FORCE_INLINE_ATTR void usb_wrap_ll_phy_test_mode_set_signals(usb_wrap_dev_t *hw, + bool oen, + bool tx_dp, + bool tx_dm, + bool rx_dp, + bool rx_dm, + bool rx_rcv) +{ + usb_wrap_test_conf_reg_t test_conf; + test_conf.val = hw->test_conf.val; + + test_conf.test_usb_wrap_oe = oen; + test_conf.test_tx_dp = tx_dp; + test_conf.test_tx_dm = tx_dm; + test_conf.test_rx_rcv = rx_rcv; + test_conf.test_rx_dp = rx_dp; + test_conf.test_rx_dm = rx_dm; + + hw->test_conf.val = test_conf.val; +} + +/* ----------------------------- RCC Functions ----------------------------- */ + /** * Enable the bus clock for USB Wrap module * @param clk_en True if enable the clock of USB Wrap module */ -FORCE_INLINE_ATTR void usb_fsls_phy_ll_usb_wrap_enable_bus_clock(bool clk_en) +FORCE_INLINE_ATTR void usb_wrap_ll_enable_bus_clock(bool clk_en) { SYSTEM.perip_clk_en0.usb_clk_en = clk_en; } // SYSTEM.perip_clk_enx are shared registers, so this function must be used in an atomic way -#define usb_fsls_phy_ll_usb_wrap_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; usb_fsls_phy_ll_usb_wrap_enable_bus_clock(__VA_ARGS__) +#define usb_wrap_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; usb_wrap_ll_enable_bus_clock(__VA_ARGS__) /** * @brief Reset the USB Wrap module */ -FORCE_INLINE_ATTR void usb_fsls_phy_ll_usb_wrap_reset_register(void) +FORCE_INLINE_ATTR void usb_wrap_ll_reset_register(void) { SYSTEM.perip_rst_en0.usb_rst = 1; SYSTEM.perip_rst_en0.usb_rst = 0; } // SYSTEM.perip_clk_enx are shared registers, so this function must be used in an atomic way -#define usb_fsls_phy_ll_usb_wrap_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; usb_fsls_phy_ll_usb_wrap_reset_register(__VA_ARGS__) +#define usb_wrap_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; usb_wrap_ll_reset_register(__VA_ARGS__) #ifdef __cplusplus } diff --git a/components/hal/usb_wrap_hal.c b/components/hal/usb_wrap_hal.c index 58b77bba23..ffa4656634 100644 --- a/components/hal/usb_wrap_hal.c +++ b/components/hal/usb_wrap_hal.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -23,10 +23,10 @@ void usb_fsls_phy_hal_init(usb_fsls_phy_hal_context_t *hal) void usb_fsls_phy_hal_otg_conf(usb_fsls_phy_hal_context_t *hal, usb_phy_target_t phy_target) { if (phy_target == USB_PHY_TARGET_EXT) { - usb_fsls_phy_ll_ext_otg_enable(hal->wrap_dev); + usb_wrap_ll_phy_enable_external(hal->wrap_dev, true); } else if (phy_target == USB_PHY_TARGET_INT) { - usb_fsls_phy_ll_usb_wrap_pad_enable(hal->wrap_dev, true); - usb_fsls_phy_ll_int_otg_enable(hal->wrap_dev); + usb_wrap_ll_phy_enable_external(hal->wrap_dev, false); + usb_wrap_ll_phy_enable_pad(hal->wrap_dev, true); } } @@ -35,17 +35,9 @@ void usb_fsls_phy_hal_jtag_conf(usb_fsls_phy_hal_context_t *hal, usb_phy_target_ { if (phy_target == USB_PHY_TARGET_EXT) { usb_serial_jtag_ll_phy_enable_external(true); // USJ uses external PHY - // Enable SW control of muxing USB OTG vs USJ to the internal USB FSLS PHY - RTCCNTL.usb_conf.sw_hw_usb_phy_sel = 1; - // Internal USB FSLS PHY is mapped to the USJ - RTCCNTL.usb_conf.sw_usb_phy_sel = 1; } else if (phy_target == USB_PHY_TARGET_INT) { - usb_serial_jtag_ll_phy_enable_external(true); // USJ uses internal PHY + usb_serial_jtag_ll_phy_enable_external(false); // USJ uses internal PHY usb_serial_jtag_ll_phy_enable_pad(true); // Enable USB PHY pads - // Enable SW control of muxing USB OTG vs USJ to the internal USB FSLS PHY - RTCCNTL.usb_conf.sw_hw_usb_phy_sel = 1; - // Internal USB FSLS PHY is mapped to the USJ - RTCCNTL.usb_conf.sw_usb_phy_sel = 0; } } #endif @@ -53,7 +45,7 @@ void usb_fsls_phy_hal_jtag_conf(usb_fsls_phy_hal_context_t *hal, usb_phy_target_ void usb_fsls_phy_hal_int_load_conf_host(usb_fsls_phy_hal_context_t *hal) { // HOST - upstream: dp_pd = 1, dm_pd = 1 - usb_fsls_phy_ll_int_load_conf(hal->wrap_dev, false, true, false, true); + usb_wrap_ll_phy_enable_pull_override(hal->wrap_dev, false, false, true, true); } void usb_fsls_phy_hal_int_load_conf_dev(usb_fsls_phy_hal_context_t *hal, usb_phy_speed_t speed) @@ -61,18 +53,29 @@ void usb_fsls_phy_hal_int_load_conf_dev(usb_fsls_phy_hal_context_t *hal, usb_phy // DEVICE - downstream if (speed == USB_PHY_SPEED_LOW) { // LS: dm_pu = 1 - usb_fsls_phy_ll_int_load_conf(hal->wrap_dev, false, false, true, false); + usb_wrap_ll_phy_enable_pull_override(hal->wrap_dev, false, true, false, false); } else { // FS: dp_pu = 1 - usb_fsls_phy_ll_int_load_conf(hal->wrap_dev, true, false, false, false); + usb_wrap_ll_phy_enable_pull_override(hal->wrap_dev, true, false, false, false); } } void usb_fsls_phy_hal_int_mimick_disconn(usb_fsls_phy_hal_context_t *hal, bool disconn) { - /* - We mimick a disconnect by enabling the internal PHY's test mode, then forcing the output_enable to HIGH. This will: - A HIGH output_enable will cause the received VP and VM to be zero, thus mimicking a disconnection. - */ - usb_fsls_phy_ll_int_enable_test_mode(hal->wrap_dev, disconn); + if (disconn) { + /* + We mimick a disconnect by enabling the internal PHY's test mode, then forcing the output_enable to HIGH. This will: + A HIGH output_enable will cause the received VP and VM to be zero, thus mimicking a disconnection. + */ + usb_wrap_ll_phy_test_mode_set_signals(hal->wrap_dev, + true, // OEN + false, // TX D+ + false, // TX D- + false, // RX D+ + false, // RX D- + false); // RX RCv + usb_wrap_ll_phy_enable_test_mode(hal->wrap_dev, true); + } else { + usb_wrap_ll_phy_enable_test_mode(hal->wrap_dev, false); + } } diff --git a/components/usb/usb_phy.c b/components/usb/usb_phy.c index c687c21782..eef3a4ffe8 100644 --- a/components/usb/usb_phy.c +++ b/components/usb/usb_phy.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -223,8 +223,8 @@ static esp_err_t usb_phy_install(void) // Enable USB peripheral and reset the register portEXIT_CRITICAL(&phy_spinlock); USB_WRAP_RCC_ATOMIC() { - usb_fsls_phy_ll_usb_wrap_enable_bus_clock(true); - usb_fsls_phy_ll_usb_wrap_reset_register(); + usb_wrap_ll_enable_bus_clock(true); + usb_wrap_ll_reset_register(); } return ESP_OK; @@ -317,7 +317,7 @@ static void phy_uninstall(void) p_phy_ctrl_obj = NULL; USB_WRAP_RCC_ATOMIC() { // Disable USB peripheral without reset the module - usb_fsls_phy_ll_usb_wrap_enable_bus_clock(false); + usb_wrap_ll_enable_bus_clock(false); } } portEXIT_CRITICAL(&phy_spinlock); @@ -334,8 +334,8 @@ esp_err_t usb_del_phy(usb_phy_handle_t handle) p_phy_ctrl_obj->external_phy = NULL; } else { // Clear pullup and pulldown loads on D+ / D-, and disable the pads - usb_fsls_phy_ll_int_load_conf(handle->hal_context.wrap_dev, false, false, false, false); - usb_fsls_phy_ll_usb_wrap_pad_enable(handle->hal_context.wrap_dev, false); + usb_wrap_ll_phy_enable_pull_override(handle->hal_context.wrap_dev, false, false, false, false); + usb_wrap_ll_phy_enable_pad(handle->hal_context.wrap_dev, false); p_phy_ctrl_obj->internal_phy = NULL; } portEXIT_CRITICAL(&phy_spinlock);