kopia lustrzana https://github.com/espressif/esp-idf
feat(esp32c61): add & modify soc header files pass build (part 3/3)
wanlei
rodzic
ff976c3c31
commit
616c72b96c
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@ -4,3 +4,7 @@ components/bootloader_support/test_apps/rtc_custom_section:
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enable:
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- if: SOC_RTC_MEM_SUPPORTED == 1
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reason: this feature is supported on chips that have RTC memory
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disable:
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- if: IDF_TARGET == "esp32c61"
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temporary: true
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reason: IDF-9260
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Plik diff jest za duży
Load Diff
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@ -0,0 +1,93 @@
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/*
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _SOC_BOOT_MODE_H_
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#define _SOC_BOOT_MODE_H_
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#include "soc.h"
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/*SPI Boot*/
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#define IS_1XXX(v) (((v)&0x08)==0x08)
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/*Download Boot, SPI(or SDIO_V2)/UART0*/
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#define IS_00XX(v) (((v)&0x0c)==0x00)
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/*Download Boot, SDIO/UART0/UART1,FEI_FEO V2*/
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#define IS_0000(v) (((v)&0x0f)==0x00)
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/*Download Boot, SDIO/UART0/UART1,FEI_REO V2*/
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#define IS_0001(v) (((v)&0x0f)==0x01)
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/*Download Boot, SDIO/UART0/UART1,REI_FEO V2*/
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#define IS_0010(v) (((v)&0x0f)==0x02)
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/*Download Boot, SDIO/UART0/UART1,REI_REO V2*/
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#define IS_0011(v) (((v)&0x0f)==0x03)
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/*legacy SPI Boot*/
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#define IS_0100(v) (((v)&0x0f)==0x04)
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/*ATE/ANALOG Mode*/
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#define IS_0101(v) (((v)&0x0f)==0x05)
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/*SPI(or SDIO_V1) download Mode*/
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#define IS_0110(v) (((v)&0x0f)==0x06)
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/*Diagnostic Mode+UART0 download Mode*/
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#define IS_0111(v) (((v)&0x0f)==0x07)
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#define BOOT_MODE_GET() (GPIO_REG_READ(GPIO_STRAP_REG))
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/*do not include download mode*/
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#define ETS_IS_UART_BOOT() IS_0111(BOOT_MODE_GET())
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/*all spi boot including spi/legacy*/
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#define ETS_IS_FLASH_BOOT() (IS_1XXX(BOOT_MODE_GET()) || IS_0100(BOOT_MODE_GET()))
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/*all faster spi boot including spi*/
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#define ETS_IS_FAST_FLASH_BOOT() IS_1XXX(BOOT_MODE_GET())
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#if SUPPORT_SDIO_DOWNLOAD
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/*all sdio V2 of failing edge input, failing edge output*/
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#define ETS_IS_SDIO_FEI_FEO_V2_BOOT() IS_0000(BOOT_MODE_GET())
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/*all sdio V2 of failing edge input, raising edge output*/
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#define ETS_IS_SDIO_FEI_REO_V2_BOOT() IS_0001(BOOT_MODE_GET())
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/*all sdio V2 of raising edge input, failing edge output*/
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#define ETS_IS_SDIO_REI_FEO_V2_BOOT() IS_0010(BOOT_MODE_GET())
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/*all sdio V2 of raising edge input, raising edge output*/
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#define ETS_IS_SDIO_REI_REO_V2_BOOT() IS_0011(BOOT_MODE_GET())
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/*all sdio V1 of raising edge input, failing edge output*/
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#define ETS_IS_SDIO_REI_FEO_V1_BOOT() IS_0110(BOOT_MODE_GET())
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/*do not include joint download mode*/
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#define ETS_IS_SDIO_BOOT() IS_0110(BOOT_MODE_GET())
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#else
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/*do not include joint download mode*/
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#define ETS_IS_SPI_DOWNLOAD_BOOT() IS_0110(BOOT_MODE_GET())
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#endif
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/*joint download boot*/
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#define ETS_IS_JOINT_DOWNLOAD_BOOT() IS_00XX(BOOT_MODE_GET())
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/*ATE mode*/
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#define ETS_IS_ATE_BOOT() IS_0101(BOOT_MODE_GET())
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/*used by ETS_IS_SDIO_UART_BOOT*/
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#define SEL_NO_BOOT 0
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#define SEL_SDIO_BOOT BIT0
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#define SEL_UART_BOOT BIT1
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#define SEL_SPI_SLAVE_BOOT BIT2
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#endif /* _SOC_BOOT_MODE_H_ */
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@ -5750,7 +5750,7 @@ typedef struct {
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volatile cache_date_reg_t date;
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} cache_dev_t;
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extern cache_dev_t CACHE_CFG;
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extern cache_dev_t CACHE;
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#ifndef __cplusplus
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_Static_assert(sizeof(cache_dev_t) == 0x400, "Invalid size of cache_dev_t structure");
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@ -0,0 +1,155 @@
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/*
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define NLBITS 3
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#define CLIC_EXT_INTR_NUM_OFFSET 16
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#define DR_REG_CLIC_BASE (0x20800000)
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#define DR_REG_CLIC_CTRL_BASE (0x20801000)
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#define CLIC_INT_CONFIG_REG (DR_REG_CLIC_BASE + 0x0)
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/* CLIC_INT_CONFIG_NMBITS : R/W ;bitpos:[6:5] ;default: 2'd0 ; */
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/*description: .*/
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#define CLIC_INT_CONFIG_NMBITS 0x00000003
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#define CLIC_INT_CONFIG_NMBITS_M ((CLIC_INT_CONFIG_NMBITS_V) << (CLIC_INT_CONFIG_NMBITS_S))
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#define CLIC_INT_CONFIG_NMBITS_V 0x3
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#define CLIC_INT_CONFIG_NMBITS_S 5
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/* CLIC_INT_CONFIG_NLBITS : R/W ;bitpos:[4:1] ;default: 4'd0 ; */
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/*description: .*/
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#define CLIC_INT_CONFIG_NLBITS 0x0000000F
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#define CLIC_INT_CONFIG_NLBITS_M ((CLIC_INT_CONFIG_NLBITS_V) << (CCLIC_INT_CONFIG_NLBITS_S))
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#define CLIC_INT_CONFIG_NLBITS_V 0xF
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#define CLIC_INT_CONFIG_NLBITS_S 1
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/* CLIC_INT_CONFIG_NVBITS : R/W ;bitpos:[0] ;default: 1'd1 ; */
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/*description: .*/
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#define CLIC_INT_CONFIG_NVBITS (BIT(0))
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#define CLIC_INT_CONFIG_NVBITS_M (BIT(0))
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#define CLIC_INT_CONFIG_NVBITS_V 0x1
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#define CLIC_INT_CONFIG_NVBITS_S 0
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#define CLIC_INT_INFO_REG (DR_REG_CLIC_BASE + 0x4)
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/* CLIC_INT_INFO_NUM_INT : R/W ;bitpos:[24:21] ;default: 4'd0 ; */
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/*description: .*/
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#define CLIC_INT_INFO_CTLBITS 0x0000000F
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#define CLIC_INT_INFO_CTLBITS_M ((CLIC_INT_INFO_CTLBITS_V) << (CLIC_INT_INFO_CTLBITS_S))
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#define CLIC_INT_INFO_CTLBITS_V 0xF
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#define CLIC_INT_INFO_CTLBITS_S 21
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/* CLIC_INT_INFO_VERSION : R/W ;bitpos:[20:13] ;default: 8'd0 ; */
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/*description: .*/
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#define CLIC_INT_INFO_VERSION 0x000000FF
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#define CLIC_INT_INFO_VERSION_M ((CLIC_INT_INFO_VERSION_V) << (CLIC_INT_INFO_VERSION_S))
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#define CLIC_INT_INFO_VERSION_V 0xFF
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#define CLIC_INT_INFO_VERSION_S 13
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/* CLIC_INT_INFO_NUM_INT : R/W ;bitpos:[12:0] ;default: 13'd0 ; */
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/*description: .*/
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#define CLIC_INT_INFO_NUM_INT 0x00001FFF
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#define CLIC_INT_INFO_NUM_INT_M ((CLIC_INT_INFO_NUM_INT_V) << (CLIC_INT_INFO_NUM_INT_S))
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#define CLIC_INT_INFO_NUM_INT_V 0x1FFF
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#define CLIC_INT_INFO_NUM_INT_S 0
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#define CLIC_INT_THRESH_REG (DR_REG_CLIC_BASE + 0x8)
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/* CLIC_CPU_INT_THRESH : R/W ;bitpos:[31:24] ;default: 8'd0 ; */
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/*description: .*/
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#define CLIC_CPU_INT_THRESH 0x000000FF
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#define CLIC_CPU_INT_THRESH_M ((CLIC_CPU_INT_THRESH_V) << (CLIC_CPU_INT_THRESH_S))
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#define CLIC_CPU_INT_THRESH_V 0xFF
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#define CLIC_CPU_INT_THRESH_S 24
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#define CLIC_INT_CTRL_REG(i) (DR_REG_CLIC_CTRL_BASE + (i)*4)
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/* CLIC_INT_CTL : R/W ;bitpos:[31:24] ;default: 8'd0 ; */
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/*description: .*/
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#define CLIC_INT_CTL 0x000000FF
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#define CLIC_INT_CTL_M ((CLIC_INT_CTL_V) << (CLIC_INT_CTL_S))
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#define CLIC_INT_CTL_V 0xFF
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#define CLIC_INT_CTL_S 24
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/* CLIC_INT_ATTR_MODE : R/W ;bitpos:[23:22] ;default: 2'b11 ; */
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/*description: .*/
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#define CLIC_INT_ATTR_MODE 0x00000003
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#define CLIC_INT_ATTR_MODE_M ((CLIC_INT_ATTR_MODE_V) << (CLIC_INT_ATTR_MODE_S))
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#define CLIC_INT_ATTR_MODE_V 0x3
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#define CLIC_INT_ATTR_MODE_S 22
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/* CLIC_INT_ATTR_TRIG : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
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/*description: .*/
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#define CLIC_INT_ATTR_TRIG 0x00000003
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#define CLIC_INT_ATTR_TRIG_M ((CLIC_INT_ATTR_TRIG_V) << (CLIC_INT_ATTR_TRIG_S))
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#define CLIC_INT_ATTR_TRIG_V 0x3
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#define CLIC_INT_ATTR_TRIG_S 17
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/* CLIC_INT_ATTR_SHV : R/W ;bitpos:[16] ;default: 1'd0 ; */
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/*description: .*/
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#define CLIC_INT_ATTR_SHV (BIT(16))
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#define CLIC_INT_ATTR_SHV_M (BIT(16))
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#define CLIC_INT_ATTR_SHV_V 0x1
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#define CLIC_INT_ATTR_SHV_S 16
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/* CLIC_INT_IE : R/W ;bitpos:[8] ;default: 1'd0 ; */
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/*description: .*/
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#define CLIC_INT_IE (BIT(8))
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#define CLIC_INT_IE_M (BIT(8))
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#define CLIC_INT_IE_V 0x1
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#define CLIC_INT_IE_S 8
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/* CLIC_INT_IP : R/W ;bitpos:[0] ;default: 1'd0 ; */
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/*description: .*/
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#define CLIC_INT_IP (BIT(0))
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#define CLIC_INT_IP_M (BIT(0))
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#define CLIC_INT_IP_V 0x1
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#define CLIC_INT_IP_S 0
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// each of following registers are 8bits
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#define BYTE_CLIC_INT_IP_REG(i) (DR_REG_CLIC_CTRL_BASE + (i)*4)
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/* BYTE_CLIC_INT_IP : R/W ;bitpos:[0] ;default: 1'd0 ; */
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/*description: .*/
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#define BYTE_CLIC_INT_IP (BIT(0))
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#define BYTE_CLIC_INT_IP_M (BIT(0))
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#define BYTE_CLIC_INT_IP_V 0x1
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#define BYTE_CLIC_INT_IP_S 0
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#define BYTE_CLIC_INT_IE_REG(i) (DR_REG_CLIC_CTRL_BASE + 1 + (i)*4)
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/* BYTE_CLIC_INT_IE : R/W ;bitpos:[0] ;default: 1'd0 ; */
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/*description: .*/
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#define BYTE_CLIC_INT_IE (BIT(0))
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#define BYTE_CLIC_INT_IE_M (BIT(0))
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#define BYTE_CLIC_INT_IE_V 0x1
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#define BYTE_CLIC_INT_IE_S 0
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#define BYTE_CLIC_INT_ATTR_REG(i) (DR_REG_CLIC_CTRL_BASE + 2 + (i)*4)
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/* BYTE_CLIC_INT_ATTR_SHV : R/W ;bitpos:[0] ;default: 1'd0 ; */
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/*description: 1 means hardware vector interrupt.*/
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#define BYTE_CLIC_INT_ATTR_SHV (BIT(0))
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#define BYTE_CLIC_INT_ATTR_SHV_M (BIT(0))
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#define BYTE_CLIC_INT_ATTR_SHV_V 0x1
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#define BYTE_CLIC_INT_ATTR_SHV_S 0
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/* BYTE_CLIC_INT_ATTR_TRIG: R/W ; bitpos:[2:1] ;default: 2'd0 ; */
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/*description:
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[X0] -> level trigger
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[01] -> rising edge trigger
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[11] -> falling edge trigger */
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#define BYTE_CLIC_INT_ATTR_TRIG 0x00000003
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#define BYTE_CLIC_INT_ATTR_TRIG_M ((BYTE_CLIC_INT_ATTR_TRIG_V) << (BYTE_CLIC_INT_ATTR_TRIG_S))
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#define BYTE_CLIC_INT_ATTR_TRIG_V 0x3
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#define BYTE_CLIC_INT_ATTR_TRIG_S 1
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/* BYTE_CLIC_INT_ATTR_MODE: R/W ; bitpos:[7:6] ;default: 2'd0 ; */
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/*description: privilege level for interrupt, fixed to 2'b11 */
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#define BYTE_CLIC_INT_ATTR_MODE 0x00000003
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#define BYTE_CLIC_INT_ATTR_MODE_M ((BYTE_CLIC_INT_ATTR_MODE_V) << (BYTE_CLIC_INT_ATTR_MODE_S))
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#define BYTE_CLIC_INT_ATTR_MODE_V 0x3
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#define BYTE_CLIC_INT_ATTR_MODE_S 6
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#define BYTE_CLIC_INT_CTL_REG(i) (DR_REG_CLIC_CTRL_BASE + 3 + (i)*4)
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/* BYTE_CLIC_INT_ATTR_MODE: R/W ; bitpos:[7:5] ;default: 3'd0 ; */
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/*description: interrupt pririty */
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#define BYTE_CLIC_INT_CTL 0x00000007
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#define BYTE_CLIC_INT_CTL_M ((BYTE_CLIC_INT_CTL_V) << (BYTE_CLIC_INT_CTL_S))
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#define BYTE_CLIC_INT_CTL_V 0x7
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#define BYTE_CLIC_INT_CTL_S 5
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#ifdef __cplusplus
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}
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#endif
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@ -0,0 +1,76 @@
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/*
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include "soc/soc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*CLINT MINT*/
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#define CLINT_MINT_SIP_REG (DR_REG_CLINT_M_BASE + 0x0)
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/* CLINT_CPU_MINT_SIP : R/W ;bitpos:[0] ;default: 1'b0 ; */
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/*description: .*/
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#define CLINT_CPU_MINT_SIP BIT(0)
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#define CLINT_CPU_MINT_SIP_M BIT(0)
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#define CLINT_CPU_MINT_SIP_V 1
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#define CLINT_CPU_MINT_SIP_S 0
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#define CLINT_MINT_MTIMECMP_L_REG (DR_REG_CLINT_M_BASE + 0x4000)
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/* CLINT_CPU_MINT_MTIMECMP_L : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
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/*description: .*/
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#define CLINT_CPU_MINT_MTIMECMP_L 0xFFFFFFFF
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#define CLINT_CPU_MINT_MTIMECMP_L_M ((CLINT_CPU_MINT_MTIMECMP_L_V)<<(CLINT_CPU_MINT_MTIMECMP_L_S))
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#define CLINT_CPU_MINT_MTIMECMP_L_V 0xFFFFFFFF
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#define CLINT_CPU_MINT_MTIMECMP_L_S 0
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#define CLINT_MINT_MTIMECMP_H_REG (DR_REG_CLINT_M_BASE + 0x4004)
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/* CLINT_CPU_MINT_MTIMECMP_H : RO ;bitpos:[31:0] ;default: 32'h0 ; */
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/*description: .*/
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#define CLINT_CPU_MINT_MTIMECMP_H 0xFFFFFFFF
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#define CLINT_CPU_MINT_MTIMECMP_H_M ((CLINT_CPU_MINT_MTIMECMP_H_V)<<(CLINT_CPU_MINT_MTIMECMP_H_S))
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#define CLINT_CPU_MINT_MTIMECMP_H_V 0xFFFFFFFF
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#define CLINT_CPU_MINT_MTIMECMP_H_S 0
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#define CLINT_MINT_TIMECTL_REG (DR_REG_CLINT_M_BASE + 0x4010)
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/* CLINT_MINT_SAMPLING_MODE : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
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/*description: .*/
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#define CLINT_MINT_SAMPLING_MODE 0x00000003
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#define CLINT_MINT_SAMPLING_MODE_M ((CLINT_CPU_MINT_TIMECTL_V)<<(CLINT_CPU_MINT_TIMECTL_S))
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#define CLINT_MINT_SAMPLING_MODE_V 0x3
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#define CLINT_MINT_SAMPLING_MODE_S 4
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/* CLINT_MINT_COUNTER_OVERFLOW : R/W ;bitpos:[3] ;default: 1'b0 ; */
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/*description: */
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#define CLINT_MINT_COUNTER_OVERFLOW (BIT(3))
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#define CLINT_MINT_COUNTER_OVERFLOW_M (BIT(3))
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#define CLINT_MINT_COUNTER_OVERFLOW_V 0x1
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#define CLINT_MINT_COUNTER_OVERFLOW_S 3
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/* CLINT_MINT_COUNTER_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
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/*description: */
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#define CLINT_MINT_COUNTER_EN (BIT(0))
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#define CLINT_MINT_COUNTER_EN_M (BIT(0))
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#define CLINT_MINT_COUNTER_EN_V 0x1
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#define CLINT_MINT_COUNTER_EN_S 0
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#define CLINT_MINT_MTIME_L_REG (DR_REG_CLINT_M_BASE + 0xBFF8)
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/* CLINT_CPU_MINT_MTIME_L : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
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/*description: .*/
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#define CLINT_CPU_MINT_MTIME_L 0xFFFFFFFF
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#define CLINT_CPU_MINT_MTIME_L_M ((CLINT_CPU_MINT_MTIME_L_V)<<(CLINT_CPU_MINT_MTIME_L_S))
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#define CLINT_CPU_MINT_MTIME_L_V 0xFFFFFFFF
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#define CLINT_CPU_MINT_MTIME_L_S 0
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#define CLINT_MINT_MTIME_H_REG (DR_REG_CLINT_M_BASE + 0xBFFC)
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/* CLINT_CPU_MINT_MTIME_H : RO ;bitpos:[31:0] ;default: 32'h0 ; */
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/*description: .*/
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#define CLINT_CPU_MINT_MTIME_H 0xFFFFFFFF
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#define CLINT_CPU_MINT_MTIME_H_M ((CLINT_CPU_MINT_MTIME_H_V)<<(CLINT_CPU_MINT_MTIME_H_S))
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#define CLINT_CPU_MINT_MTIME_H_V 0xFFFFFFFF
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#define CLINT_CPU_MINT_MTIME_H_S 0
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#ifdef __cplusplus
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}
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#endif
|
||||
|
|
@ -0,0 +1,507 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
// TODO: [ESP32C61] IDF-9249, This file comes from verification code
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*
|
||||
************************* ESP32C61 Root Clock Source ****************************
|
||||
* 1) Internal 17.5MHz RC Oscillator: RC_FAST (may also referred as FOSC in TRM and reg. description)
|
||||
*
|
||||
* This RC oscillator generates a ~17.5MHz clock signal output as the RC_FAST_CLK.
|
||||
*
|
||||
* The exact frequency of RC_FAST_CLK can be computed in runtime through calibration.
|
||||
*
|
||||
* 2) External 40MHz Crystal Clock: XTAL
|
||||
*
|
||||
* 3) Internal 136kHz RC Oscillator: RC_SLOW (may also referrred as SOSC in TRM or reg. description)
|
||||
*
|
||||
* This RC oscillator generates a ~136kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock
|
||||
* can be computed in runtime through calibration.
|
||||
*
|
||||
* 4) Internal 32kHz RC Oscillator: RC32K
|
||||
*
|
||||
* The exact frequency of this clock can be computed in runtime through calibration.
|
||||
*
|
||||
* 5) External 32kHz Crystal Clock (optional): XTAL32K
|
||||
*
|
||||
* The clock source for this XTAL32K_CLK should be a 32kHz crystal connecting to the XTAL_32K_P and XTAL_32K_N
|
||||
* pins.
|
||||
*
|
||||
* XTAL32K_CLK can also be calibrated to get its exact frequency.
|
||||
*
|
||||
* 6) External Slow Clock (optional): OSC_SLOW
|
||||
*
|
||||
* A slow clock signal generated by an external circuit can be connected to GPIO0 to be the clock source for the
|
||||
* RTC_SLOW_CLK.
|
||||
*
|
||||
* OSC_SLOW_CLK can also be calibrated to get its exact frequency.
|
||||
*/
|
||||
|
||||
/* With the default value of FOSC_DFREQ = 100, RC_FAST clock frequency is 17.5 MHz +/- 7% */
|
||||
#define SOC_CLK_RC_FAST_FREQ_APPROX 17500000 /*!< Approximate RC_FAST_CLK frequency in Hz */
|
||||
#define SOC_CLK_RC_SLOW_FREQ_APPROX 136000 /*!< Approximate RC_SLOW_CLK frequency in Hz */
|
||||
#define SOC_CLK_RC32K_FREQ_APPROX 32768 /*!< Approximate RC32K_CLK frequency in Hz */
|
||||
#define SOC_CLK_XTAL32K_FREQ_APPROX 32768 /*!< Approximate XTAL32K_CLK frequency in Hz */
|
||||
#define SOC_CLK_OSC_SLOW_FREQ_APPROX 32768 /*!< Approximate OSC_SLOW_CLK (external slow clock) frequency in Hz */
|
||||
|
||||
// Naming convention: SOC_ROOT_CLK_{loc}_{type}_[attr]
|
||||
// {loc}: EXT, INT
|
||||
// {type}: XTAL, RC
|
||||
// [attr] - optional: [frequency], FAST, SLOW
|
||||
/**
|
||||
* @brief Root clock
|
||||
*/
|
||||
typedef enum {
|
||||
SOC_ROOT_CLK_INT_RC_FAST, /*!< Internal 17.5MHz RC oscillator */
|
||||
SOC_ROOT_CLK_INT_RC_SLOW, /*!< Internal 136kHz RC oscillator */
|
||||
SOC_ROOT_CLK_EXT_XTAL, /*!< External 40MHz crystal */
|
||||
SOC_ROOT_CLK_EXT_XTAL32K, /*!< External 32kHz crystal */
|
||||
SOC_ROOT_CLK_INT_RC32K, /*!< Internal 32kHz RC oscillator */
|
||||
SOC_ROOT_CLK_EXT_OSC_SLOW, /*!< External slow clock signal at pin0 */
|
||||
} soc_root_clk_t;
|
||||
|
||||
/**
|
||||
* @brief CPU_CLK mux inputs, which are the supported clock sources for the CPU_CLK
|
||||
* @note Enum values are matched with the register field values on purpose
|
||||
*/
|
||||
typedef enum {
|
||||
SOC_CPU_CLK_SRC_XTAL = 0, /*!< Select XTAL_CLK as CPU_CLK source */
|
||||
SOC_CPU_CLK_SRC_PLL = 1, /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 40MHz crystal oscillator frequency multiplier, 480MHz) */
|
||||
SOC_CPU_CLK_SRC_RC_FAST = 2, /*!< Select RC_FAST_CLK as CPU_CLK source */
|
||||
SOC_CPU_CLK_SRC_INVALID, /*!< Invalid CPU_CLK source */
|
||||
} soc_cpu_clk_src_t;
|
||||
|
||||
/**
|
||||
* @brief RTC_SLOW_CLK mux inputs, which are the supported clock sources for the RTC_SLOW_CLK
|
||||
* @note Enum values are matched with the register field values on purpose
|
||||
*/
|
||||
typedef enum {
|
||||
SOC_RTC_SLOW_CLK_SRC_RC_SLOW = 0, /*!< Select RC_SLOW_CLK as RTC_SLOW_CLK source */
|
||||
SOC_RTC_SLOW_CLK_SRC_XTAL32K = 1, /*!< Select XTAL32K_CLK as RTC_SLOW_CLK source */
|
||||
SOC_RTC_SLOW_CLK_SRC_RC32K = 2, /*!< Select RC32K_CLK as RTC_SLOW_CLK source */
|
||||
SOC_RTC_SLOW_CLK_SRC_OSC_SLOW = 3, /*!< Select OSC_SLOW_CLK (external slow clock) as RTC_SLOW_CLK source */
|
||||
SOC_RTC_SLOW_CLK_SRC_INVALID, /*!< Invalid RTC_SLOW_CLK source */
|
||||
} soc_rtc_slow_clk_src_t;
|
||||
|
||||
/**
|
||||
* @brief RTC_FAST_CLK mux inputs, which are the supported clock sources for the RTC_FAST_CLK
|
||||
* @note Enum values are matched with the register field values on purpose
|
||||
*/
|
||||
typedef enum {
|
||||
SOC_RTC_FAST_CLK_SRC_RC_FAST = 0, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */
|
||||
SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 1, /*!< Select XTAL_D2_CLK as RTC_FAST_CLK source */
|
||||
SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */
|
||||
SOC_RTC_FAST_CLK_SRC_INVALID, /*!< Invalid RTC_FAST_CLK source */
|
||||
} soc_rtc_fast_clk_src_t;
|
||||
|
||||
/**
|
||||
* @brief Possible main XTAL frequency options on the target
|
||||
* @note Enum values equal to the frequency value in MHz
|
||||
* @note Not all frequency values listed here are supported in IDF. Please check SOC_XTAL_SUPPORT_XXX in soc_caps.h for
|
||||
* the supported ones.
|
||||
*/
|
||||
typedef enum {
|
||||
SOC_XTAL_FREQ_40M = 40, /*!< 40MHz XTAL */
|
||||
} soc_xtal_freq_t;
|
||||
|
||||
// Naming convention: SOC_MOD_CLK_{[upstream]clock_name}_[attr]
|
||||
// {[upstream]clock_name}: XTAL, (BB)PLL, etc.
|
||||
// [attr] - optional: FAST, SLOW, D<divider>, F<freq>
|
||||
/**
|
||||
* @brief Supported clock sources for modules (CPU, peripherals, RTC, etc.)
|
||||
*
|
||||
* @note enum starts from 1, to save 0 for special purpose
|
||||
*/
|
||||
typedef enum {
|
||||
// For CPU domain
|
||||
SOC_MOD_CLK_CPU = 1, /*!< CPU_CLK can be sourced from XTAL, PLL, or RC_FAST by configuring soc_cpu_clk_src_t */
|
||||
// For RTC domain
|
||||
SOC_MOD_CLK_RTC_FAST, /*!< RTC_FAST_CLK can be sourced from XTAL_D2 or RC_FAST by configuring soc_rtc_fast_clk_src_t */
|
||||
SOC_MOD_CLK_RTC_SLOW, /*!< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, RC32K, or OSC_SLOW by configuring soc_rtc_slow_clk_src_t */
|
||||
// For digital domain: peripherals, WIFI, BLE
|
||||
SOC_MOD_CLK_PLL_F80M, /*!< PLL_F80M_CLK is derived from PLL (clock gating + fixed divider of 6), it has a fixed frequency of 80MHz */
|
||||
SOC_MOD_CLK_PLL_F160M, /*!< PLL_F160M_CLK is derived from PLL (clock gating + fixed divider of 3), it has a fixed frequency of 160MHz */
|
||||
SOC_MOD_CLK_PLL_F240M, /*!< PLL_F240M_CLK is derived from PLL (clock gating + fixed divider of 2), it has a fixed frequency of 240MHz */
|
||||
SOC_MOD_CLK_XTAL32K, /*!< XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals */
|
||||
SOC_MOD_CLK_RC_FAST, /*!< RC_FAST_CLK comes from the internal 20MHz rc oscillator, passing a clock gating to the peripherals */
|
||||
SOC_MOD_CLK_XTAL, /*!< XTAL_CLK comes from the external 40MHz crystal */
|
||||
// For LP peripherals
|
||||
SOC_MOD_CLK_XTAL_D2, /*!< XTAL_D2_CLK comes from the external 40MHz crystal, passing a div of 2 to the LP peripherals */
|
||||
|
||||
SOC_MOD_CLK_INVALID, /*!< Indication of the end of the available module clock sources */
|
||||
} soc_module_clk_t;
|
||||
|
||||
//////////////////////////////////////////////////SYSTIMER//////////////////////////////////////////////////////////////
|
||||
|
||||
/**
|
||||
* @brief Type of SYSTIMER clock source
|
||||
*/
|
||||
typedef enum {
|
||||
SYSTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< SYSTIMER source clock is XTAL */
|
||||
SYSTIMER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< SYSTIMER source clock is RC_FAST */
|
||||
SYSTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< SYSTIMER source clock default choice is XTAL */
|
||||
} soc_periph_systimer_clk_src_t;
|
||||
|
||||
//////////////////////////////////////////////////GPTimer///////////////////////////////////////////////////////////////
|
||||
|
||||
/**
|
||||
* @brief Array initializer for all supported clock sources of GPTimer
|
||||
*
|
||||
* The following code can be used to iterate all possible clocks:
|
||||
* @code{c}
|
||||
* soc_periph_gptimer_clk_src_t gptimer_clks[] = (soc_periph_gptimer_clk_src_t)SOC_GPTIMER_CLKS;
|
||||
* for (size_t i = 0; i< sizeof(gptimer_clks) / sizeof(gptimer_clks[0]); i++) {
|
||||
* soc_periph_gptimer_clk_src_t clk = gptimer_clks[i];
|
||||
* // Test GPTimer with the clock `clk`
|
||||
* }
|
||||
* @endcode
|
||||
*/
|
||||
#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL}
|
||||
|
||||
/**
|
||||
* @brief Type of GPTimer clock source
|
||||
*/
|
||||
typedef enum {
|
||||
GPTIMER_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */
|
||||
GPTIMER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
|
||||
GPTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
|
||||
GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default choice */
|
||||
} soc_periph_gptimer_clk_src_t;
|
||||
|
||||
/**
|
||||
* @brief Type of Timer Group clock source, reserved for the legacy timer group driver
|
||||
*/
|
||||
typedef enum {
|
||||
TIMER_SRC_CLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Timer group clock source is PLL_F80M */
|
||||
TIMER_SRC_CLK_XTAL = SOC_MOD_CLK_XTAL, /*!< Timer group clock source is XTAL */
|
||||
TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Timer group clock source default choice is PLL_F80M */
|
||||
} soc_periph_tg_clk_src_legacy_t;
|
||||
|
||||
//////////////////////////////////////////////////RMT///////////////////////////////////////////////////////////////////
|
||||
|
||||
/**
|
||||
* @brief Array initializer for all supported clock sources of RMT
|
||||
*/
|
||||
#define SOC_RMT_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL}
|
||||
|
||||
/**
|
||||
* @brief Type of RMT clock source
|
||||
*/
|
||||
typedef enum {
|
||||
RMT_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */
|
||||
RMT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
|
||||
RMT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
|
||||
RMT_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default choice */
|
||||
} soc_periph_rmt_clk_src_t;
|
||||
|
||||
/**
|
||||
* @brief Type of RMT clock source, reserved for the legacy RMT driver
|
||||
*/
|
||||
typedef enum {
|
||||
RMT_BASECLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< RMT source clock is PLL_F80M */
|
||||
RMT_BASECLK_XTAL = SOC_MOD_CLK_XTAL, /*!< RMT source clock is XTAL */
|
||||
RMT_BASECLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< RMT source clock default choice is PLL_F80M */
|
||||
} soc_periph_rmt_clk_src_legacy_t;
|
||||
|
||||
//////////////////////////////////////////////////Temp Sensor///////////////////////////////////////////////////////////
|
||||
|
||||
/**
|
||||
* @brief Array initializer for all supported clock sources of Temperature Sensor
|
||||
*/
|
||||
#define SOC_TEMP_SENSOR_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST}
|
||||
|
||||
/**
|
||||
* @brief Type of Temp Sensor clock source
|
||||
*/
|
||||
typedef enum {
|
||||
TEMPERATURE_SENSOR_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
|
||||
TEMPERATURE_SENSOR_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
|
||||
TEMPERATURE_SENSOR_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default choice */
|
||||
} soc_periph_temperature_sensor_clk_src_t;
|
||||
|
||||
///////////////////////////////////////////////////UART/////////////////////////////////////////////////////////////////
|
||||
|
||||
/**
|
||||
* @brief Array initializer for all supported clock sources of UART
|
||||
*/
|
||||
#define SOC_UART_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST}
|
||||
|
||||
/**
|
||||
* @brief Type of UART clock source, reserved for the legacy UART driver
|
||||
*/
|
||||
typedef enum {
|
||||
UART_SCLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< UART source clock is PLL_F80M */
|
||||
UART_SCLK_RTC = SOC_MOD_CLK_RC_FAST, /*!< UART source clock is RC_FAST */
|
||||
UART_SCLK_XTAL = SOC_MOD_CLK_XTAL, /*!< UART source clock is XTAL */
|
||||
UART_SCLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< UART source clock default choice is PLL_F80M */
|
||||
} soc_periph_uart_clk_src_legacy_t;
|
||||
|
||||
/**
|
||||
* @brief Array initializer for all supported clock sources of LP_UART
|
||||
*/
|
||||
#define SOC_LP_UART_CLKS {SOC_MOD_CLK_RTC_FAST, SOC_MOD_CLK_XTAL_D2}
|
||||
|
||||
/**
|
||||
* @brief Type of LP_UART clock source
|
||||
*/
|
||||
typedef enum {
|
||||
LP_UART_SCLK_LP_FAST = SOC_MOD_CLK_RTC_FAST, /*!< LP_UART source clock is LP(RTC)_FAST */
|
||||
LP_UART_SCLK_XTAL_D2 = SOC_MOD_CLK_XTAL_D2, /*!< LP_UART source clock is XTAL_D2 */
|
||||
LP_UART_SCLK_DEFAULT = SOC_MOD_CLK_RTC_FAST, /*!< LP_UART source clock default choice is LP(RTC)_FAST */
|
||||
} soc_periph_lp_uart_clk_src_t;
|
||||
|
||||
//////////////////////////////////////////////////MCPWM/////////////////////////////////////////////////////////////////
|
||||
|
||||
/**
|
||||
* @brief Array initializer for all supported clock sources of MCPWM Timer
|
||||
*/
|
||||
#define SOC_MCPWM_TIMER_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL}
|
||||
|
||||
/**
|
||||
* @brief Type of MCPWM timer clock source
|
||||
*/
|
||||
typedef enum {
|
||||
MCPWM_TIMER_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
|
||||
MCPWM_TIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
|
||||
MCPWM_TIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */
|
||||
} soc_periph_mcpwm_timer_clk_src_t;
|
||||
|
||||
/**
|
||||
* @brief Array initializer for all supported clock sources of MCPWM Capture Timer
|
||||
*/
|
||||
#define SOC_MCPWM_CAPTURE_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL}
|
||||
|
||||
/**
|
||||
* @brief Type of MCPWM capture clock source
|
||||
*/
|
||||
typedef enum {
|
||||
MCPWM_CAPTURE_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
|
||||
MCPWM_CAPTURE_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
|
||||
MCPWM_CAPTURE_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */
|
||||
} soc_periph_mcpwm_capture_clk_src_t;
|
||||
|
||||
/**
|
||||
* @brief Array initializer for all supported clock sources of MCPWM Carrier
|
||||
*/
|
||||
#define SOC_MCPWM_CARRIER_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL}
|
||||
|
||||
/**
|
||||
* @brief Type of MCPWM carrier clock source
|
||||
*/
|
||||
typedef enum {
|
||||
MCPWM_CARRIER_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
|
||||
MCPWM_CARRIER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
|
||||
MCPWM_CARRIER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */
|
||||
} soc_periph_mcpwm_carrier_clk_src_t;
|
||||
|
||||
///////////////////////////////////////////////////// I2S //////////////////////////////////////////////////////////////
|
||||
|
||||
/**
|
||||
* @brief Array initializer for all supported clock sources of I2S
|
||||
*/
|
||||
#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL, I2S_CLK_SRC_EXTERNAL}
|
||||
|
||||
/**
|
||||
* @brief I2S clock source enum
|
||||
*/
|
||||
typedef enum {
|
||||
I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default source clock */
|
||||
I2S_CLK_SRC_PLL_160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
|
||||
I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
|
||||
I2S_CLK_SRC_EXTERNAL = -1, /*!< Select external clock as source clock */
|
||||
} soc_periph_i2s_clk_src_t;
|
||||
|
||||
/////////////////////////////////////////////////I2C////////////////////////////////////////////////////////////////////
|
||||
|
||||
/**
|
||||
* @brief Array initializer for all supported clock sources of I2C
|
||||
*/
|
||||
#define SOC_I2C_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST}
|
||||
|
||||
/**
|
||||
* @brief Type of I2C clock source.
|
||||
*/
|
||||
typedef enum {
|
||||
I2C_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
|
||||
I2C_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
|
||||
I2C_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default source clock */
|
||||
} soc_periph_i2c_clk_src_t;
|
||||
|
||||
///////////////////////////////////////////////LP_I2C///////////////////////////////////////////////////////////////////
|
||||
|
||||
/**
|
||||
* @brief Array initializer for all supported clock sources of LP_I2C
|
||||
*/
|
||||
#define SOC_LP_I2C_CLKS {SOC_MOD_CLK_RTC_FAST, SOC_MOD_CLK_XTAL_D2}
|
||||
|
||||
/**
|
||||
* @brief Type of LP_I2C clock source.
|
||||
*/
|
||||
typedef enum {
|
||||
LP_I2C_SCLK_LP_FAST = SOC_MOD_CLK_RTC_FAST, /*!< LP_I2C source clock is RTC_FAST */
|
||||
LP_I2C_SCLK_XTAL_D2 = SOC_MOD_CLK_XTAL_D2, /*!< LP_I2C source clock is XTAL_D2 */
|
||||
LP_I2C_SCLK_DEFAULT = SOC_MOD_CLK_RTC_FAST, /*!< LP_I2C source clock default choice is RTC_FAST */
|
||||
} soc_periph_lp_i2c_clk_src_t;
|
||||
|
||||
/////////////////////////////////////////////////SPI////////////////////////////////////////////////////////////////////
|
||||
|
||||
/**
|
||||
* @brief Array initializer for all supported clock sources of SPI
|
||||
*/
|
||||
#define SOC_SPI_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST}
|
||||
|
||||
/**
|
||||
* @brief Type of SPI clock source.
|
||||
*/
|
||||
typedef enum {
|
||||
SPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_80M as SPI source clock */
|
||||
SPI_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_80M as SPI source clock */
|
||||
SPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as SPI source clock */
|
||||
SPI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as SPI source clock */
|
||||
} soc_periph_spi_clk_src_t;
|
||||
|
||||
//////////////////////////////////////////////////SDM//////////////////////////////////////////////////////////////
|
||||
|
||||
/**
|
||||
* @brief Array initializer for all supported clock sources of SDM
|
||||
*/
|
||||
#define SOC_SDM_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL}
|
||||
|
||||
/**
|
||||
* @brief Sigma Delta Modulator clock source
|
||||
*/
|
||||
typedef enum {
|
||||
SDM_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL clock as the source clock */
|
||||
SDM_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */
|
||||
SDM_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the default clock choice */
|
||||
} soc_periph_sdm_clk_src_t;
|
||||
|
||||
//////////////////////////////////////////////////GPIO Glitch Filter////////////////////////////////////////////////////
|
||||
|
||||
/**
|
||||
* @brief Array initializer for all supported clock sources of Glitch Filter
|
||||
*/
|
||||
#define SOC_GLITCH_FILTER_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL}
|
||||
|
||||
/**
|
||||
* @brief Glitch filter clock source
|
||||
*/
|
||||
|
||||
typedef enum {
|
||||
GLITCH_FILTER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL clock as the source clock */
|
||||
GLITCH_FILTER_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */
|
||||
GLITCH_FILTER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the default clock choice */
|
||||
} soc_periph_glitch_filter_clk_src_t;
|
||||
|
||||
//////////////////////////////////////////////////TWAI//////////////////////////////////////////////////////////////////
|
||||
|
||||
/**
|
||||
* @brief Array initializer for all supported clock sources of TWAI
|
||||
*/
|
||||
#define SOC_TWAI_CLKS {SOC_MOD_CLK_XTAL}
|
||||
|
||||
/**
|
||||
* @brief TWAI clock source
|
||||
*/
|
||||
typedef enum {
|
||||
TWAI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
|
||||
TWAI_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */
|
||||
} soc_periph_twai_clk_src_t;
|
||||
|
||||
//////////////////////////////////////////////////ADC///////////////////////////////////////////////////////////////////
|
||||
|
||||
/**
|
||||
* @brief Array initializer for all supported clock sources of ADC digital controller
|
||||
*/
|
||||
#define SOC_ADC_DIGI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST}
|
||||
|
||||
/**
|
||||
* @brief ADC digital controller clock source
|
||||
*/
|
||||
typedef enum {
|
||||
ADC_DIGI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
|
||||
ADC_DIGI_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */
|
||||
ADC_DIGI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
|
||||
ADC_DIGI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default clock choice */
|
||||
} soc_periph_adc_digi_clk_src_t;
|
||||
|
||||
//////////////////////////////////////////////////MWDT/////////////////////////////////////////////////////////////////
|
||||
|
||||
/**
|
||||
* @brief Array initializer for all supported clock sources of MWDT
|
||||
*/
|
||||
#define SOC_MWDT_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST}
|
||||
|
||||
/**
|
||||
* @brief MWDT clock source
|
||||
*/
|
||||
typedef enum {
|
||||
MWDT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
|
||||
MWDT_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL fixed 80 MHz as the source clock */
|
||||
MWDT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RTC fast as the source clock */
|
||||
MWDT_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select PLL fixed 80 MHz as the default clock choice */
|
||||
} soc_periph_mwdt_clk_src_t;
|
||||
|
||||
//////////////////////////////////////////////////LEDC/////////////////////////////////////////////////////////////////
|
||||
|
||||
/**
|
||||
* @brief Array initializer for all supported clock sources of LEDC
|
||||
*/
|
||||
#define SOC_LEDC_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST}
|
||||
|
||||
/**
|
||||
* @brief Type of LEDC clock source, reserved for the legacy LEDC driver
|
||||
*/
|
||||
typedef enum {
|
||||
LEDC_AUTO_CLK = 0, /*!< LEDC source clock will be automatically selected based on the giving resolution and duty parameter when init the timer*/
|
||||
LEDC_USE_PLL_DIV_CLK = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */
|
||||
LEDC_USE_RC_FAST_CLK = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
|
||||
LEDC_USE_XTAL_CLK = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
|
||||
|
||||
LEDC_USE_RTC8M_CLK __attribute__((deprecated("please use 'LEDC_USE_RC_FAST_CLK' instead"))) = LEDC_USE_RC_FAST_CLK, /*!< Alias of 'LEDC_USE_RC_FAST_CLK' */
|
||||
} soc_periph_ledc_clk_src_legacy_t;
|
||||
|
||||
//////////////////////////////////////////////////PARLIO////////////////////////////////////////////////////////////////
|
||||
|
||||
/**
|
||||
* @brief Array initializer for all supported clock sources of PARLIO
|
||||
*/
|
||||
#define SOC_PARLIO_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F240M}
|
||||
|
||||
/**
|
||||
* @brief PARLIO clock source
|
||||
*/
|
||||
typedef enum {
|
||||
PARLIO_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
|
||||
PARLIO_CLK_SRC_PLL_F240M = SOC_MOD_CLK_PLL_F240M, /*!< Select PLL_F240M as the source clock */
|
||||
PARLIO_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
|
||||
PARLIO_CLK_SRC_EXTERNAL = -1, /*!< Select EXTERNAL clock as the source clock */
|
||||
PARLIO_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F240M, /*!< Select PLL_F240M as the default clock choice */
|
||||
} soc_periph_parlio_clk_src_t;
|
||||
|
||||
//////////////////////////////////////////////CLOCK OUTPUT///////////////////////////////////////////////////////////
|
||||
typedef enum {
|
||||
CLKOUT_SIG_PLL = 1, /*!< PLL_CLK is the output of crystal oscillator frequency multiplier */
|
||||
CLKOUT_SIG_XTAL = 5, /*!< Main crystal oscillator clock */
|
||||
CLKOUT_SIG_PLL_F80M = 13, /*!< From PLL, usually be 80MHz */
|
||||
CLKOUT_SIG_CPU = 16, /*!< CPU clock */
|
||||
CLKOUT_SIG_AHB = 17, /*!< AHB clock */
|
||||
CLKOUT_SIG_APB = 18, /*!< APB clock */
|
||||
CLKOUT_SIG_XTAL32K = 21, /*!< External 32kHz crystal clock */
|
||||
CLKOUT_SIG_EXT32K = 22, /*!< External slow clock input through XTAL_32K_P */
|
||||
CLKOUT_SIG_RC_FAST = 23, /*!< RC fast clock, about 17.5MHz */
|
||||
CLKOUT_SIG_RC_32K = 24, /*!< Internal slow RC oscillator */
|
||||
CLKOUT_SIG_RC_SLOW = 25, /*!< RC slow clock, depends on the RTC_CLK_SRC configuration */
|
||||
CLKOUT_SIG_INVALID = 0xFF,
|
||||
} soc_clkout_sig_id_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,112 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _DPORT_ACCESS_H_
|
||||
#define _DPORT_ACCESS_H_
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc.h"
|
||||
#include "uart_reg.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
// Target does not have DPORT bus, so these macros are all same as the non-DPORT versions
|
||||
|
||||
#define DPORT_INTERRUPT_DISABLE()
|
||||
#define DPORT_INTERRUPT_RESTORE()
|
||||
|
||||
/**
|
||||
* @brief Read a sequence of DPORT registers to the buffer.
|
||||
*
|
||||
* @param[out] buff_out Contains the read data.
|
||||
* @param[in] address Initial address for reading registers.
|
||||
* @param[in] num_words The number of words.
|
||||
*/
|
||||
void esp_dport_access_read_buffer(uint32_t *buff_out, uint32_t address, uint32_t num_words);
|
||||
|
||||
// _DPORT_REG_WRITE & DPORT_REG_WRITE are equivalent.
|
||||
#define _DPORT_REG_READ(_r) (*(volatile uint32_t *)(_r))
|
||||
#define _DPORT_REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v)
|
||||
|
||||
// Write value to DPORT register (does not require protecting)
|
||||
#define DPORT_REG_WRITE(_r, _v) _DPORT_REG_WRITE((_r), (_v))
|
||||
|
||||
#define DPORT_REG_READ(_r) _DPORT_REG_READ(_r)
|
||||
#define DPORT_SEQUENCE_REG_READ(_r) _DPORT_REG_READ(_r)
|
||||
|
||||
//get bit or get bits from register
|
||||
#define DPORT_REG_GET_BIT(_r, _b) (DPORT_REG_READ(_r) & (_b))
|
||||
|
||||
//set bit or set bits to register
|
||||
#define DPORT_REG_SET_BIT(_r, _b) DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r)|(_b)))
|
||||
|
||||
//clear bit or clear bits of register
|
||||
#define DPORT_REG_CLR_BIT(_r, _b) DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r) & (~(_b))))
|
||||
|
||||
//set bits of register controlled by mask
|
||||
#define DPORT_REG_SET_BITS(_r, _b, _m) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~(_m))) | ((_b) & (_m))))
|
||||
|
||||
//get field from register, uses field _S & _V to determine mask
|
||||
#define DPORT_REG_GET_FIELD(_r, _f) ((DPORT_REG_READ(_r) >> (_f##_S)) & (_f##_V))
|
||||
|
||||
//set field to register, used when _f is not left shifted by _f##_S
|
||||
#define DPORT_REG_SET_FIELD(_r, _f, _v) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~((_f##_V) << (_f##_S))))|(((_v) & (_f##_V))<<(_f##_S))))
|
||||
|
||||
//get field value from a variable, used when _f is not left shifted by _f##_S
|
||||
#define DPORT_VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
|
||||
|
||||
//get field value from a variable, used when _f is left shifted by _f##_S
|
||||
#define DPORT_VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
|
||||
|
||||
//set field value to a variable, used when _f is not left shifted by _f##_S
|
||||
#define DPORT_VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
|
||||
|
||||
//set field value to a variable, used when _f is left shifted by _f##_S
|
||||
#define DPORT_VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
|
||||
|
||||
//generate a value from a field value, used when _f is not left shifted by _f##_S
|
||||
#define DPORT_FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
|
||||
|
||||
//generate a value from a field value, used when _f is left shifted by _f##_S
|
||||
#define DPORT_FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
|
||||
|
||||
//Register read macros with an underscore prefix access DPORT memory directly. In IDF apps, use the non-underscore versions to be SMP-safe.
|
||||
#define _DPORT_READ_PERI_REG(addr) (*((volatile uint32_t *)(addr)))
|
||||
#define _DPORT_WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)(addr))) = (uint32_t)(val)
|
||||
#define _DPORT_REG_SET_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r)|(_b)))
|
||||
#define _DPORT_REG_CLR_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r) & (~(_b))))
|
||||
|
||||
#define DPORT_READ_PERI_REG(addr) _DPORT_READ_PERI_REG(addr)
|
||||
|
||||
//write value to register
|
||||
#define DPORT_WRITE_PERI_REG(addr, val) _DPORT_WRITE_PERI_REG((addr), (val))
|
||||
|
||||
//clear bits of register controlled by mask
|
||||
#define DPORT_CLEAR_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)&(~(mask))))
|
||||
|
||||
//set bits of register controlled by mask
|
||||
#define DPORT_SET_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)|(mask)))
|
||||
|
||||
//get bits of register controlled by mask
|
||||
#define DPORT_GET_PERI_REG_MASK(reg, mask) (DPORT_READ_PERI_REG(reg) & (mask))
|
||||
|
||||
//get bits of register controlled by highest bit and lowest bit
|
||||
#define DPORT_GET_PERI_REG_BITS(reg, hipos,lowpos) ((DPORT_READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1))
|
||||
|
||||
//set bits of register controlled by mask and shift
|
||||
#define DPORT_SET_PERI_REG_BITS(reg,bit_map,value,shift) DPORT_WRITE_PERI_REG((reg), ((DPORT_READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift))))
|
||||
|
||||
//get field of register
|
||||
#define DPORT_GET_PERI_REG_BITS2(reg, mask,shift) ((DPORT_READ_PERI_REG(reg)>>(shift))&(mask))
|
||||
//}}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _DPORT_ACCESS_H_ */
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
/**
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define EFUSE_WRITE_OP_CODE 0x5a5a
|
||||
#define EFUSE_READ_OP_CODE 0x5aa5
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
Plik diff jest za duży
Load Diff
|
|
@ -3356,8 +3356,8 @@ typedef struct {
|
|||
volatile efuse_apb2otp_en_reg_t apb2otp_en;
|
||||
} efuse_dev_t;
|
||||
|
||||
extern efuse_dev_t EFUSE_AND_OTP_DEBUG0;
|
||||
extern efuse_dev_t EFUSE_AND_OTP_DEBUG1;
|
||||
extern efuse_dev_t EFUSE0;
|
||||
extern efuse_dev_t EFUSE1;
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(efuse_dev_t) == 0x70c, "Invalid size of efuse_dev_t structure");
|
||||
|
|
|
|||
|
|
@ -0,0 +1,153 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include "esp_bit_defs.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if !SOC_MMU_PAGE_SIZE
|
||||
/**
|
||||
* We define `SOC_MMU_PAGE_SIZE` in soc/CMakeLists.txt.
|
||||
* Here we give a default definition, if SOC_MMU_PAGE_SIZE doesn't exist. This is to pass the check_public_headers.py
|
||||
*/
|
||||
#define SOC_MMU_PAGE_SIZE 0x10000
|
||||
#endif
|
||||
|
||||
|
||||
#define SOC_IRAM0_CACHE_ADDRESS_LOW 0x42000000
|
||||
#define SOC_IRAM0_CACHE_ADDRESS_HIGH (SOC_IRAM0_CACHE_ADDRESS_LOW + ((SOC_MMU_PAGE_SIZE) * SOC_MMU_ENTRY_NUM))
|
||||
|
||||
#define SOC_DRAM0_CACHE_ADDRESS_LOW SOC_IRAM0_CACHE_ADDRESS_LOW //I/D share the same vaddr range
|
||||
#define SOC_DRAM0_CACHE_ADDRESS_HIGH SOC_IRAM0_CACHE_ADDRESS_HIGH //I/D share the same vaddr range
|
||||
|
||||
#define SOC_IRAM_FLASH_ADDRESS_LOW SOC_IRAM0_CACHE_ADDRESS_LOW
|
||||
#define SOC_IRAM_FLASH_ADDRESS_HIGH SOC_IRAM0_CACHE_ADDRESS_HIGH
|
||||
|
||||
#define SOC_DRAM_FLASH_ADDRESS_LOW SOC_DRAM0_CACHE_ADDRESS_LOW
|
||||
#define SOC_DRAM_FLASH_ADDRESS_HIGH SOC_DRAM0_CACHE_ADDRESS_HIGH
|
||||
|
||||
#define SOC_BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
|
||||
#define SOC_ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
|
||||
|
||||
#define SOC_ADDRESS_IN_IRAM0(vaddr) SOC_ADDRESS_IN_BUS(SOC_IRAM0, vaddr)
|
||||
#define SOC_ADDRESS_IN_IRAM0_CACHE(vaddr) SOC_ADDRESS_IN_BUS(SOC_IRAM0_CACHE, vaddr)
|
||||
#define SOC_ADDRESS_IN_DRAM0(vaddr) SOC_ADDRESS_IN_BUS(SOC_DRAM0, vaddr)
|
||||
#define SOC_ADDRESS_IN_DRAM0_CACHE(vaddr) SOC_ADDRESS_IN_BUS(SOC_DRAM0_CACHE, vaddr)
|
||||
|
||||
#define SOC_MMU_ACCESS_FLASH 0
|
||||
#define SOC_MMU_ACCESS_SPIRAM BIT(9)
|
||||
#define SOC_MMU_VALID BIT(10)
|
||||
#define SOC_MMU_SENSITIVE BIT(11)
|
||||
#define SOC_MMU_INVALID_MASK BIT(10)
|
||||
#define SOC_MMU_INVALID 0
|
||||
|
||||
/**
|
||||
* MMU entry valid bit mask for mapping value. For an entry:
|
||||
* valid bit + value bits
|
||||
* valid bit is BIT(9), so value bits are 0x1ff
|
||||
*/
|
||||
#define SOC_MMU_VALID_VAL_MASK 0x3ff
|
||||
/**
|
||||
* Max MMU available paddr page num.
|
||||
* `SOC_MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
|
||||
* 256 * 64KB, means MMU can support 16MB paddr at most
|
||||
*/
|
||||
#define SOC_MMU_MAX_PADDR_PAGE_NUM 512
|
||||
//MMU entry num
|
||||
#define SOC_MMU_ENTRY_NUM 512
|
||||
|
||||
/**
|
||||
* This is the mask used for mapping. e.g.:
|
||||
* 0x4200_0000 & SOC_MMU_VADDR_MASK
|
||||
*/
|
||||
#define SOC_MMU_VADDR_MASK ((SOC_MMU_PAGE_SIZE) * SOC_MMU_ENTRY_NUM - 1)
|
||||
|
||||
#define SOC_MMU_DBUS_VADDR_BASE 0x42000000
|
||||
#define SOC_MMU_IBUS_VADDR_BASE 0x42000000
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
* MMU Linear Address
|
||||
*----------------------------------------------------------------------------*/
|
||||
#if (SOC_MMU_PAGE_SIZE == 0x10000)
|
||||
/**
|
||||
* - 64KB MMU page size: the last 0xFFFF, which is the offset
|
||||
* - 128 MMU entries, needs 0x7F to hold it.
|
||||
*
|
||||
* Therefore, 0x7F,FFFF
|
||||
*/
|
||||
#define SOC_MMU_LINEAR_ADDR_MASK 0x1FFFFFF
|
||||
|
||||
#elif (SOC_MMU_PAGE_SIZE == 0x8000)
|
||||
/**
|
||||
* - 32KB MMU page size: the last 0x7FFF, which is the offset
|
||||
* - 128 MMU entries, needs 0x7F to hold it.
|
||||
*
|
||||
* Therefore, 0x3F,FFFF
|
||||
*/
|
||||
#define SOC_MMU_LINEAR_ADDR_MASK 0xFFFFFF
|
||||
|
||||
#elif (SOC_MMU_PAGE_SIZE == 0x4000)
|
||||
/**
|
||||
* - 16KB MMU page size: the last 0x3FFF, which is the offset
|
||||
* - 128 MMU entries, needs 0x7F to hold it.
|
||||
*
|
||||
* Therefore, 0x1F,FFFF
|
||||
*/
|
||||
#define SOC_MMU_LINEAR_ADDR_MASK 0x7FFFFF
|
||||
#endif //SOC_MMU_PAGE_SIZE
|
||||
|
||||
/**
|
||||
* - If high linear address isn't 0, this means MMU can recognize these addresses
|
||||
* - If high linear address is 0, this means MMU linear address range is equal or smaller than vaddr range.
|
||||
* Under this condition, we use the max linear space.
|
||||
*/
|
||||
#define SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW (SOC_IRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#if ((SOC_IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
|
||||
#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH (SOC_IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#else
|
||||
#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH (SOC_MMU_LINEAR_ADDR_MASK + 1)
|
||||
#endif
|
||||
|
||||
#define SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW (SOC_DRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#if ((SOC_DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
|
||||
#define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH (SOC_DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
|
||||
#else
|
||||
#define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH (SOC_MMU_LINEAR_ADDR_MASK + 1)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* I/D share the MMU linear address range
|
||||
*/
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW == SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW, "IRAM0 and DRAM0 linear address should be same");
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* ROM flash mmap driver needs below definitions
|
||||
*/
|
||||
#define CACHE_IROM_MMU_START 0
|
||||
#define CACHE_IROM_MMU_END Cache_Get_IROM_MMU_End()
|
||||
#define CACHE_IROM_MMU_SIZE (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
|
||||
|
||||
#define CACHE_DROM_MMU_START CACHE_IROM_MMU_END
|
||||
#define CACHE_DROM_MMU_END Cache_Get_DROM_MMU_End()
|
||||
#define CACHE_DROM_MMU_SIZE (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START)
|
||||
|
||||
#define CACHE_DROM_MMU_MAX_END 0x400
|
||||
|
||||
#define ICACHE_MMU_SIZE 0x200
|
||||
#define DCACHE_MMU_SIZE 0x200
|
||||
|
||||
#define MMU_BUS_START(i) 0
|
||||
#define MMU_BUS_SIZE(i) 0x200
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
//TODO: [ESP32C61] IDF-9316, check pins attribute
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief GPIO number
|
||||
*/
|
||||
typedef enum {
|
||||
GPIO_NUM_NC = -1, /*!< Use to signal not connected to S/W */
|
||||
GPIO_NUM_0 = 0, /*!< GPIO0, input and output */
|
||||
GPIO_NUM_1 = 1, /*!< GPIO1, input and output */
|
||||
GPIO_NUM_2 = 2, /*!< GPIO2, input and output */
|
||||
GPIO_NUM_3 = 3, /*!< GPIO3, input and output */
|
||||
GPIO_NUM_4 = 4, /*!< GPIO4, input and output */
|
||||
GPIO_NUM_5 = 5, /*!< GPIO5, input and output */
|
||||
GPIO_NUM_6 = 6, /*!< GPIO6, input and output */
|
||||
GPIO_NUM_7 = 7, /*!< GPIO7, input and output */
|
||||
GPIO_NUM_8 = 8, /*!< GPIO8, input and output */
|
||||
GPIO_NUM_9 = 9, /*!< GPIO9, input and output */
|
||||
GPIO_NUM_10 = 10, /*!< GPIO10, input and output */
|
||||
GPIO_NUM_11 = 11, /*!< GPIO11, input and output */
|
||||
GPIO_NUM_12 = 12, /*!< GPIO12, input and output */
|
||||
GPIO_NUM_13 = 13, /*!< GPIO13, input and output */
|
||||
GPIO_NUM_14 = 14, /*!< GPIO14, input and output */
|
||||
GPIO_NUM_15 = 15, /*!< GPIO15, input and output */
|
||||
GPIO_NUM_16 = 16, /*!< GPIO16, input and output */
|
||||
GPIO_NUM_17 = 17, /*!< GPIO17, input and output */
|
||||
GPIO_NUM_18 = 18, /*!< GPIO18, input and output */
|
||||
GPIO_NUM_19 = 19, /*!< GPIO19, input and output */
|
||||
GPIO_NUM_20 = 20, /*!< GPIO20, input and output */
|
||||
GPIO_NUM_21 = 21, /*!< GPIO21, input and output */
|
||||
GPIO_NUM_22 = 22, /*!< GPIO22, input and output */
|
||||
GPIO_NUM_23 = 23, /*!< GPIO23, input and output */
|
||||
GPIO_NUM_24 = 24, /*!< GPIO24, input and output */
|
||||
GPIO_NUM_25 = 25, /*!< GPIO25, input and output */
|
||||
GPIO_NUM_26 = 26, /*!< GPIO26, input and output */
|
||||
GPIO_NUM_27 = 27, /*!< GPIO27, input and output */
|
||||
GPIO_NUM_28 = 28, /*!< GPIO28, input and output */
|
||||
GPIO_NUM_MAX,
|
||||
} gpio_num_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define GPIO_MATRIX_CONST_ONE_INPUT (0x38)
|
||||
#define GPIO_MATRIX_CONST_ZERO_INPUT (0x3C)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -6,6 +6,7 @@
|
|||
|
||||
#pragma once
|
||||
|
||||
// version date 2310090
|
||||
#define EXT_ADC_START_IDX 0
|
||||
#define LEDC_LS_SIG_OUT0_IDX 0
|
||||
#define LEDC_LS_SIG_OUT1_IDX 1
|
||||
|
|
@ -175,4 +176,5 @@
|
|||
#define MODEM_DIAG29_IDX 158
|
||||
#define MODEM_DIAG30_IDX 159
|
||||
#define MODEM_DIAG31_IDX 160
|
||||
// version date 2310090
|
||||
|
||||
#define SIG_GPIO_OUT_IDX 256
|
||||
|
|
|
|||
|
|
@ -0,0 +1,222 @@
|
|||
/**
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
|
||||
//TODO: [ESP32C61] IDF-9276, inherit from c6
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define I2C_ANA_MST_I2C0_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x0)
|
||||
/* I2C_MST_I2C0_BUSY : RO ;bitpos:[25] ;default: 1'h0 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_I2C0_BUSY (BIT(25))
|
||||
#define I2C_ANA_MST_I2C0_BUSY_M (BIT(25))
|
||||
#define I2C_ANA_MST_I2C0_BUSY_V 0x1
|
||||
#define I2C_ANA_MST_I2C0_BUSY_S 25
|
||||
/* I2C_MST_I2C0_CTRL : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_I2C0_CTRL 0x01FFFFFF
|
||||
#define I2C_ANA_MST_I2C0_CTRL_M ((I2C_MST_I2C0_CTRL_V)<<(I2C_MST_I2C0_CTRL_S))
|
||||
#define I2C_ANA_MST_I2C0_CTRL_V 0x1FFFFFF
|
||||
#define I2C_ANA_MST_I2C0_CTRL_S 0
|
||||
|
||||
#define I2C_ANA_MST_I2C1_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x4)
|
||||
/* I2C_MST_I2C1_BUSY : RO ;bitpos:[25] ;default: 1'h0 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_I2C1_BUSY (BIT(25))
|
||||
#define I2C_ANA_MST_I2C1_BUSY_M (BIT(25))
|
||||
#define I2C_ANA_MST_I2C1_BUSY_V 0x1
|
||||
#define I2C_ANA_MST_I2C1_BUSY_S 25
|
||||
/* I2C_MST_I2C1_CTRL : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_I2C1_CTRL 0x01FFFFFF
|
||||
#define I2C_ANA_MST_I2C1_CTRL_M ((I2C_MST_I2C1_CTRL_V)<<(I2C_MST_I2C1_CTRL_S))
|
||||
#define I2C_ANA_MST_I2C1_CTRL_V 0x1FFFFFF
|
||||
#define I2C_ANA_MST_I2C1_CTRL_S 0
|
||||
|
||||
#define I2C_ANA_MST_I2C0_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x8)
|
||||
/* I2C_MST_I2C0_STATUS : RO ;bitpos:[31:24] ;default: 8'h0 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_I2C0_STATUS 0x000000FF
|
||||
#define I2C_ANA_MST_I2C0_STATUS_M ((I2C_MST_I2C0_STATUS_V)<<(I2C_MST_I2C0_STATUS_S))
|
||||
#define I2C_ANA_MST_I2C0_STATUS_V 0xFF
|
||||
#define I2C_ANA_MST_I2C0_STATUS_S 24
|
||||
/* I2C_MST_I2C0_CONF : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_I2C0_CONF 0x00FFFFFF
|
||||
#define I2C_ANA_MST_I2C0_CONF_M ((I2C_MST_I2C0_CONF_V)<<(I2C_MST_I2C0_CONF_S))
|
||||
#define I2C_ANA_MST_I2C0_CONF_V 0xFFFFFF
|
||||
#define I2C_ANA_MST_I2C0_CONF_S 0
|
||||
|
||||
#define I2C_ANA_MST_I2C1_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0xC)
|
||||
/* I2C_MST_I2C1_STATUS : RO ;bitpos:[31:24] ;default: 8'h0 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_I2C1_STATUS 0x000000FF
|
||||
#define I2C_ANA_MST_I2C1_STATUS_M ((I2C_MST_I2C1_STATUS_V)<<(I2C_MST_I2C1_STATUS_S))
|
||||
#define I2C_ANA_MST_I2C1_STATUS_V 0xFF
|
||||
#define I2C_ANA_MST_I2C1_STATUS_S 24
|
||||
/* I2C_MST_I2C1_CONF : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_I2C1_CONF 0x00FFFFFF
|
||||
#define I2C_ANA_MST_I2C1_CONF_M ((I2C_MST_I2C1_CONF_V)<<(I2C_MST_I2C1_CONF_S))
|
||||
#define I2C_ANA_MST_I2C1_CONF_V 0xFFFFFF
|
||||
#define I2C_ANA_MST_I2C1_CONF_S 0
|
||||
|
||||
#define I2C_ANA_MST_I2C_BURST_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x10)
|
||||
/* I2C_MST_BURST_CTRL : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_BURST_CTRL 0xFFFFFFFF
|
||||
#define I2C_ANA_MST_BURST_CTRL_M ((I2C_MST_BURST_CTRL_V)<<(I2C_MST_BURST_CTRL_S))
|
||||
#define I2C_ANA_MST_BURST_CTRL_V 0xFFFFFFFF
|
||||
#define I2C_ANA_MST_BURST_CTRL_S 0
|
||||
|
||||
#define I2C_ANA_MST_I2C_BURST_STATUS_REG (DR_REG_I2C_ANA_MST_BASE + 0x14)
|
||||
/* I2C_MST_BURST_TIMEOUT_CNT : R/W ;bitpos:[31:20] ;default: 12'h400 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_BURST_TIMEOUT_CNT 0x00000FFF
|
||||
#define I2C_ANA_MST_BURST_TIMEOUT_CNT_M ((I2C_MST_BURST_TIMEOUT_CNT_V)<<(I2C_MST_BURST_TIMEOUT_CNT_S))
|
||||
#define I2C_ANA_MST_BURST_TIMEOUT_CNT_V 0xFFF
|
||||
#define I2C_ANA_MST_BURST_TIMEOUT_CNT_S 20
|
||||
/* I2C_MST1_BURST_ERR_FLAG : RO ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST1_BURST_ERR_FLAG (BIT(2))
|
||||
#define I2C_ANA_MST1_BURST_ERR_FLAG_M (BIT(2))
|
||||
#define I2C_ANA_MST1_BURST_ERR_FLAG_V 0x1
|
||||
#define I2C_ANA_MST1_BURST_ERR_FLAG_S 2
|
||||
/* I2C_MST0_BURST_ERR_FLAG : RO ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST0_BURST_ERR_FLAG (BIT(1))
|
||||
#define I2C_ANA_MST0_BURST_ERR_FLAG_M (BIT(1))
|
||||
#define I2C_ANA_MST0_BURST_ERR_FLAG_V 0x1
|
||||
#define I2C_ANA_MST0_BURST_ERR_FLAG_S 1
|
||||
/* I2C_MST_BURST_DONE : RO ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_BURST_DONE (BIT(0))
|
||||
#define I2C_ANA_MST_BURST_DONE_M (BIT(0))
|
||||
#define I2C_ANA_MST_BURST_DONE_V 0x1
|
||||
#define I2C_ANA_MST_BURST_DONE_S 0
|
||||
|
||||
#define I2C_ANA_MST_ANA_CONF0_REG (DR_REG_I2C_ANA_MST_BASE + 0x18)
|
||||
/* I2C_ANA_MST_STATUS0 : RO ;bitpos:[31:24] ;default: 8'h0 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_ANA_STATUS0 0x000000FF
|
||||
#define I2C_ANA_MST_ANA_STATUS0_M ((I2C_ANA_MST_STATUS0_V)<<(I2C_ANA_MST_STATUS0_S))
|
||||
#define I2C_ANA_MST_ANA_STATUS0_V 0xFF
|
||||
#define I2C_ANA_MST_ANA_STATUS0_S 24
|
||||
/* I2C_ANA_MST_ANA_CONF0 : R/W ;bitpos:[23:0] ;default: 24'h00_e408 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_ANA_CONF0 0x00FFFFFF
|
||||
#define I2C_ANA_MST_ANA_CONF0_M ((I2C_ANA_MST_ANA_CONF0_V)<<(I2C_ANA_MST_ANA_CONF0_S))
|
||||
#define I2C_ANA_MST_ANA_CONF0_V 0xFFFFFF
|
||||
#define I2C_ANA_MST_ANA_CONF0_S 0
|
||||
|
||||
#define I2C_ANA_MST_ANA_CONF1_REG (DR_REG_I2C_ANA_MST_BASE + 0x1C)
|
||||
/* I2C_ANA_MST_STATUS1 : RO ;bitpos:[31:24] ;default: 8'h0 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_ANA_STATUS1 0x000000FF
|
||||
#define I2C_ANA_MST_ANA_STATUS1_M ((I2C_ANA_MST_STATUS1_V)<<(I2C_ANA_MST_STATUS1_S))
|
||||
#define I2C_ANA_MST_ANA_STATUS1_V 0xFF
|
||||
#define I2C_ANA_MST_ANA_STATUS1_S 24
|
||||
/* I2C_MST_AANA_NA_CONF1 : R/W ;bitpos:[23:0] ;default: 24'h00_002d ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_ANA_CONF1 0x00FFFFFF
|
||||
#define I2C_ANA_MST_ANA_CONF1_M ((I2C_ANA_MST_ANA_CONF1_V)<<(I2C_ANA_MST_ANA_CONF1_S))
|
||||
#define I2C_ANA_MST_ANA_CONF1_V 0xFFFFFF
|
||||
#define I2C_ANA_MST_ANA_CONF1_S 0
|
||||
|
||||
#define I2C_ANA_MST_ANA_CONF2_REG (DR_REG_I2C_ANA_MST_BASE + 0x20)
|
||||
/* I2C_ANA_MST_STATUS2 : RO ;bitpos:[31:24] ;default: 8'h0 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_ANA_STATUS2 0x000000FF
|
||||
#define I2C_ANA_MST_ANA_STATUS2_M ((I2C_ANA_MST_STATUS2_V)<<(I2C_ANA_MST_STATUS2_S))
|
||||
#define I2C_ANA_MST_ANA_STATUS2_V 0xFF
|
||||
#define I2C_ANA_MST_ANA_STATUS2_S 24
|
||||
/* I2C_ANA_MST_ANA_CONF2 : R/W ;bitpos:[23:0] ;default: 24'h00_0004 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_ANA_CONF2 0x00FFFFFF
|
||||
#define I2C_ANA_MST_ANA_CONF2_M ((I2C_ANA_MST_ANA_CONF2_V)<<(I2C_ANA_MST_ANA_CONF2_S))
|
||||
#define I2C_ANA_MST_ANA_CONF2_V 0xFFFFFF
|
||||
#define I2C_ANA_MST_ANA_CONF2_S 0
|
||||
|
||||
#define I2C_ANA_MST_I2C0_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x24)
|
||||
/* I2C_MST_I2C0_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD 0x0000001F
|
||||
#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_M ((I2C_MST_I2C0_SDA_SIDE_GUARD_V)<<(I2C_MST_I2C0_SDA_SIDE_GUARD_S))
|
||||
#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_V 0x1F
|
||||
#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_S 6
|
||||
/* I2C_MST_I2C0_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR 0x0000003F
|
||||
#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_M ((I2C_MST_I2C0_SCL_PULSE_DUR_V)<<(I2C_MST_I2C0_SCL_PULSE_DUR_S))
|
||||
#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_V 0x3F
|
||||
#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_S 0
|
||||
|
||||
#define I2C_ANA_MST_I2C1_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x28)
|
||||
/* I2C_MST_I2C1_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD 0x0000001F
|
||||
#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_M ((I2C_MST_I2C1_SDA_SIDE_GUARD_V)<<(I2C_MST_I2C1_SDA_SIDE_GUARD_S))
|
||||
#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_V 0x1F
|
||||
#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_S 6
|
||||
/* I2C_MST_I2C1_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR 0x0000003F
|
||||
#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_M ((I2C_MST_I2C1_SCL_PULSE_DUR_V)<<(I2C_MST_I2C1_SCL_PULSE_DUR_S))
|
||||
#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_V 0x3F
|
||||
#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_S 0
|
||||
|
||||
#define I2C_ANA_MST_HW_I2C_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x2C)
|
||||
/* I2C_MST_ARBITER_DIS : R/W ;bitpos:[11] ;default: 1'h0 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_ARBITER_DIS (BIT(11))
|
||||
#define I2C_ANA_MST_ARBITER_DIS_M (BIT(11))
|
||||
#define I2C_ANA_MST_ARBITER_DIS_V 0x1
|
||||
#define I2C_ANA_MST_ARBITER_DIS_S 11
|
||||
/* I2C_MST_HW_I2C_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD 0x0000001F
|
||||
#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_M ((I2C_MST_HW_I2C_SDA_SIDE_GUARD_V)<<(I2C_MST_HW_I2C_SDA_SIDE_GUARD_S))
|
||||
#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_V 0x1F
|
||||
#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_S 6
|
||||
/* I2C_MST_HW_I2C_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR 0x0000003F
|
||||
#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_M ((I2C_MST_HW_I2C_SCL_PULSE_DUR_V)<<(I2C_MST_HW_I2C_SCL_PULSE_DUR_S))
|
||||
#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_V 0x3F
|
||||
#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_S 0
|
||||
|
||||
#define I2C_ANA_MST_NOUSE_REG (DR_REG_I2C_ANA_MST_BASE + 0x30)
|
||||
/* I2C_MST_NOUSE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_NOUSE 0xFFFFFFFF
|
||||
#define I2C_ANA_MST_NOUSE_M ((I2C_MST_NOUSE_V)<<(I2C_MST_NOUSE_S))
|
||||
#define I2C_ANA_MST_NOUSE_V 0xFFFFFFFF
|
||||
#define I2C_ANA_MST_NOUSE_S 0
|
||||
|
||||
#define I2C_ANA_MST_DATE_REG (DR_REG_I2C_ANA_MST_BASE + 0x34)
|
||||
/* I2C_MST_CLK_EN : R/W ;bitpos:[28] ;default: 1'h0 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_CLK_EN (BIT(28))
|
||||
#define I2C_ANA_MST_CLK_EN_M (BIT(28))
|
||||
#define I2C_ANA_MST_CLK_EN_V 0x1
|
||||
#define I2C_ANA_MST_CLK_EN_S 28
|
||||
/* I2C_MST_DATE : R/W ;bitpos:[27:0] ;default: 28'h2201300 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_DATE 0x0FFFFFFF
|
||||
#define I2C_ANA_MST_DATE_M ((I2C_MST_DATE_V)<<(I2C_MST_DATE_S))
|
||||
#define I2C_ANA_MST_DATE_V 0xFFFFFFF
|
||||
#define I2C_ANA_MST_DATE_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include "soc/soc_caps.h"
|
||||
#include "soc/clic_reg.h"
|
||||
|
||||
/**
|
||||
* ESP32C61 uses the CLIC controller as the interrupt controller (SOC_INT_CLIC_SUPPORTED = y)
|
||||
*/
|
||||
|
||||
#define INTERRUPT_CURRENT_CORE_INT_THRESH_REG (CLIC_INT_THRESH_REG)
|
||||
|
||||
#define INTERRUPT_CORE0_CPU_INT_THRESH_REG INTERRUPT_CURRENT_CORE_INT_THRESH_REG
|
||||
|
||||
#define DR_REG_INTERRUPT_CORE0_BASE DR_REG_INTERRUPT_MATRIX_BASE
|
||||
|
|
@ -35,15 +35,15 @@ typedef enum {
|
|||
ETS_LP_WDT_INTR_SOURCE,
|
||||
ETS_LP_PERI_TIMEOUT_INTR_SOURCE,
|
||||
ETS_LP_APM_M0_INTR_SOURCE,
|
||||
ETS_CPU_INTR_FROM_CPU_0_SOURCE,
|
||||
ETS_CPU_INTR_FROM_CPU_1_SOURCE,
|
||||
ETS_CPU_INTR_FROM_CPU_2_SOURCE,
|
||||
ETS_CPU_INTR_FROM_CPU_3_SOURCE,
|
||||
ETS_FROM_CPU_INTR0_SOURCE,
|
||||
ETS_FROM_CPU_INTR1_SOURCE,
|
||||
ETS_FROM_CPU_INTR2_SOURCE,
|
||||
ETS_FROM_CPU_INTR3_SOURCE,
|
||||
ETS_ASSIST_DEBUG_INTR_SOURCE,
|
||||
ETS_TRACE_INTR_SOURCE,
|
||||
ETS_CACHE_INTR_SOURCE,
|
||||
ETS_CPU_PERI_TIMEOUT_INTR_SOURCE,
|
||||
ETS_GPIO_INTERRUPT_PRO_SOURCE,
|
||||
ETS_GPIO_INTR_SOURCE,
|
||||
ETS_GPIO_INTERRUPT_EXT_SOURCE,
|
||||
ETS_PAU_INTR_SOURCE,
|
||||
ETS_HP_PERI_TIMEOUT_INTR_SOURCE,
|
||||
|
|
@ -62,10 +62,10 @@ typedef enum {
|
|||
ETS_I2C_EXT0_INTR_SOURCE,
|
||||
ETS_TG0_T0_INTR_SOURCE,
|
||||
ETS_TG0_T1_INTR_SOURCE,
|
||||
ETS_TG0_WDT_INTR_SOURCE,
|
||||
ETS_TG0_WDT_LEVEL_INTR_SOURCE,
|
||||
ETS_TG1_T0_INTR_SOURCE,
|
||||
ETS_TG1_T1_INTR_SOURCE,
|
||||
ETS_TG1_WDT_INTR_SOURCE,
|
||||
ETS_TG1_WDT_LEVEL_INTR_SOURCE,
|
||||
ETS_SYSTIMER_TARGET0_INTR_SOURCE,
|
||||
ETS_SYSTIMER_TARGET1_INTR_SOURCE,
|
||||
ETS_SYSTIMER_TARGET2_INTR_SOURCE,
|
||||
|
|
|
|||
|
|
@ -67,6 +67,22 @@ extern "C" {
|
|||
#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S)
|
||||
#define MCU_SEL_V 0x7
|
||||
#define MCU_SEL_S 12
|
||||
/* Pin filter (Pulse width shorter than 2 clock cycles will be filtered out) */
|
||||
#define FILTER_EN (BIT(15))
|
||||
#define FILTER_EN_M (FILTER_EN_V << FILTER_EN_S)
|
||||
#define FILTER_EN_V 1
|
||||
#define FILTER_EN_S 15
|
||||
|
||||
#define PIN_SLP_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_IE)
|
||||
#define PIN_SLP_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE)
|
||||
#define PIN_SLP_OUTPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_OE)
|
||||
#define PIN_SLP_OUTPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_OE)
|
||||
#define PIN_SLP_PULLUP_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PU)
|
||||
#define PIN_SLP_PULLUP_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PU)
|
||||
#define PIN_SLP_PULLDOWN_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PD)
|
||||
#define PIN_SLP_PULLDOWN_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PD)
|
||||
#define PIN_SLP_SEL_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_SEL)
|
||||
#define PIN_SLP_SEL_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL)
|
||||
|
||||
#define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
|
||||
#define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
|
||||
|
|
@ -76,6 +92,8 @@ extern "C" {
|
|||
#define PIN_PULLDWN_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PD)
|
||||
#define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD)
|
||||
#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
|
||||
#define PIN_FILTER_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FILTER_EN)
|
||||
#define PIN_FILTER_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FILTER_EN)
|
||||
|
||||
#define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_U_PAD_XTAL_32K_P
|
||||
#define IO_MUX_GPIO1_REG PERIPHS_IO_MUX_U_PAD_XTAL_32K_N
|
||||
|
|
@ -124,7 +142,6 @@ extern "C" {
|
|||
#define MAX_GPIO_NUM 34
|
||||
#define HIGH_IO_HOLD_BIT_SHIFT 32
|
||||
|
||||
|
||||
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
|
||||
#define PIN_CTRL (REG_IO_MUX_BASE +0x00)
|
||||
#define PAD_POWER_SEL BIT(15)
|
||||
|
|
@ -137,6 +154,20 @@ extern "C" {
|
|||
#define PAD_POWER_SWITCH_DELAY_M (PAD_POWER_SWITCH_DELAY_V << PAD_POWER_SWITCH_DELAY_S)
|
||||
#define PAD_POWER_SWITCH_DELAY_S 12
|
||||
|
||||
//TODO: [ESP32C61] IDF-9316, copy from verify
|
||||
#define IO_MUX_CLK_OUT3 0x0000000F
|
||||
#define IO_MUX_CLK_OUT3_M ((IO_MUX_CLK_OUT3_V)<<(IO_MUX_CLK_OUT3_S))
|
||||
#define IO_MUX_CLK_OUT3_V 0xF
|
||||
#define IO_MUX_CLK_OUT3_S 8
|
||||
#define IO_MUX_CLK_OUT2 0x0000000F
|
||||
#define IO_MUX_CLK_OUT2_M ((IO_MUX_CLK_OUT2_V)<<(IO_MUX_CLK_OUT2_S))
|
||||
#define IO_MUX_CLK_OUT2_V 0xF
|
||||
#define IO_MUX_CLK_OUT2_S 4
|
||||
#define IO_MUX_CLK_OUT1 0x0000000F
|
||||
#define IO_MUX_CLK_OUT1_M ((IO_MUX_CLK_OUT1_V)<<(IO_MUX_CLK_OUT1_S))
|
||||
#define IO_MUX_CLK_OUT1_V 0xF
|
||||
#define IO_MUX_CLK_OUT1_S 0
|
||||
|
||||
#define CLK_OUT3 IO_MUX_CLK_OUT3
|
||||
#define CLK_OUT3_V IO_MUX_CLK_OUT3_V
|
||||
#define CLK_OUT3_S IO_MUX_CLK_OUT3_S
|
||||
|
|
|
|||
|
|
@ -1628,7 +1628,7 @@ typedef union {
|
|||
* 3: RC_SLOW_CLK\\
|
||||
* 4: RC_FAST_CLK\\
|
||||
*/
|
||||
uint32_t 32k_sel:3;
|
||||
uint32_t clk_32k_sel:3;
|
||||
uint32_t reserved_3:5;
|
||||
/** fosc_tick_num : R/W; bitpos: [15:8]; default: 7;
|
||||
* When PCR_32K_SEL set as 4, This field PCR_FOSC_TICK_NUM is used to set the divider
|
||||
|
|
|
|||
|
|
@ -0,0 +1,58 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "soc/interrupts.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
/* HP peripherals */
|
||||
PERIPH_LEDC_MODULE = 0,
|
||||
PERIPH_UART0_MODULE,
|
||||
PERIPH_UART1_MODULE,
|
||||
PERIPH_USB_DEVICE_MODULE,
|
||||
PERIPH_I2C0_MODULE,
|
||||
PERIPH_I2S1_MODULE,
|
||||
PERIPH_TIMG0_MODULE,
|
||||
PERIPH_TIMG1_MODULE,
|
||||
PERIPH_SPI_MODULE, //SPI1
|
||||
PERIPH_SPI2_MODULE, //SPI2
|
||||
PERIPH_RNG_MODULE,
|
||||
PERIPH_SHA_MODULE,
|
||||
PERIPH_ECC_MODULE,
|
||||
PERIPH_GDMA_MODULE,
|
||||
PERIPH_ETM_MODULE,
|
||||
PERIPH_SYSTIMER_MODULE,
|
||||
PERIPH_SARADC_MODULE,
|
||||
PERIPH_TEMPSENSOR_MODULE,
|
||||
PERIPH_REGDMA_MODULE,
|
||||
PERIPH_ASSIST_DEBUG_MODULE,
|
||||
/* Peripherals clock managed by the modem_clock driver must be listed last in the enumeration */
|
||||
PERIPH_WIFI_MODULE,
|
||||
PERIPH_BT_MODULE,
|
||||
PERIPH_IEEE802154_MODULE,
|
||||
PERIPH_COEX_MODULE,
|
||||
PERIPH_PHY_MODULE,
|
||||
PERIPH_ANA_I2C_MASTER_MODULE,
|
||||
PERIPH_MODEM_ETM_MODULE,
|
||||
PERIPH_MODEM_ADC_COMMON_FE_MODULE,
|
||||
PERIPH_MODULE_MAX
|
||||
/* !!! Don't append soc modules here !!! */
|
||||
} periph_module_t;
|
||||
|
||||
#define PERIPH_MODEM_MODULE_MIN PERIPH_WIFI_MODULE
|
||||
#define PERIPH_MODEM_MODULE_MAX PERIPH_MODEM_ADC_COMMON_FE_MODULE
|
||||
#define PERIPH_MODEM_MODULE_NUM (PERIPH_MODEM_MODULE_MAX - PERIPH_MODEM_MODULE_MIN + 1)
|
||||
#define IS_MODEM_MODULE(periph) ((periph>=PERIPH_MODEM_MODULE_MIN) && (periph<=PERIPH_MODEM_MODULE_MAX))
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
Plik diff jest za duży
Load Diff
|
|
@ -6,55 +6,56 @@
|
|||
|
||||
#pragma once
|
||||
|
||||
#define DR_REG_UART0_BASE 0x60000000
|
||||
#define DR_REG_UART1_BASE 0x60001000
|
||||
#define DR_REG_MSPI0_BASE 0x60002000
|
||||
#define DR_REG_MSPI1_BASE 0x60003000
|
||||
#define DR_REG_I2C_BASE 0x60004000
|
||||
#define DR_REG_UART2_BASE 0x60006000
|
||||
#define DR_REG_LEDC_BASE 0x60007000
|
||||
#define DR_REG_TIMG0_BASE 0x60008000
|
||||
#define DR_REG_TIMG1_BASE 0x60009000
|
||||
#define DR_REG_SYSTIMER_BASE 0x6000A000
|
||||
#define DR_REG_I2S_BASE 0x6000C000
|
||||
#define DR_REG_SARADC_BASE 0x6000E000
|
||||
#define DR_REG_USB_SERIAL_JTAG_BASE 0x6000F000
|
||||
#define DR_REG_INTERRUPT_MATRIX_BASE 0x60010000
|
||||
#define DR_REG_SOC_ETM_BASE 0x60013000
|
||||
#define DR_REG_PVT_MONITOR_BASE 0x60019000
|
||||
#define DR_REG_PSRAM_MEM_MONITOR_BASE 0x6001A000
|
||||
#define DR_REG_AHB_GDMA_BASE 0x60080000
|
||||
#define DR_REG_GPSPI_BASE 0x60081000
|
||||
#define DR_REG_SHA_BASE 0x60089000
|
||||
#define DR_REG_ECC_BASE 0x6008B000
|
||||
#define DR_REG_ECDSA_BASE 0x6008E000
|
||||
#define DR_REG_IO_MUX_BASE 0x60090000
|
||||
#define DR_REG_GPIO_BASE 0x60091000
|
||||
#define DR_REG_TCM_MEM_MONITOR_BASE 0x60092000
|
||||
#define DR_REG_PAU_BASE 0x60093000
|
||||
#define DR_REG_HP_SYSTEM_REG_BASE 0x60095000
|
||||
#define DR_REG_PCR_REG_BASE 0x60096000
|
||||
#define DR_REG_TEE_REG_BASE 0x60098000
|
||||
#define DR_REG_HP_APM_REG_BASE 0x60099000
|
||||
#define DR_REG_MISC_BASE 0x6009F000
|
||||
#define DR_REG_MODEM0_BASE 0x600A0000
|
||||
#define DR_REG_MODEM1_BASE 0x600AC000
|
||||
#define DR_REG_MODEM_PWR0_BASE 0x600AD000
|
||||
#define DR_REG_MODEM_PWR1_BASE 0x600AF000
|
||||
#define DR_REG_PMU_BASE 0x600B0000
|
||||
#define DR_REG_LP_CLKRST_BASE 0x600B0400
|
||||
#define DR_REG_LP_TIMER_BASE 0x600B0C00
|
||||
#define DR_REG_LP_AON_BASE 0x600B1000
|
||||
#define DR_REG_LP_WDT_BASE 0x600B1C00
|
||||
#define DR_REG_LPPERI_BASE 0x600B2800
|
||||
#define DR_REG_LP_ANA_REG_BASE 0x600B2C00
|
||||
#define DR_REG_LP_TEE_BASE 0x600B3400
|
||||
#define DR_REG_LP_APM_BASE 0x600B3800
|
||||
#define DR_REG_LP_IO_MUX_BASE 0x600B4000
|
||||
#define DR_REG_LP_GPIO_BASE 0x600B4400
|
||||
#define DR_REG_EFUSE_AND_OTP_DEBUG0_BASE 0x600B4800
|
||||
#define DR_REG_EFUSE_AND_OTP_DEBUG1_BASE 0x600B4C00
|
||||
#define DR_REG_TRACE_BASE 0x600C0000
|
||||
#define DR_REG_ASSIST_DEBUG_BASE 0x600C2000
|
||||
#define DR_REG_INTPRI_REG_BASE 0x600C5000
|
||||
#define DR_REG_CACHE_CFG_BASE 0x600C8000
|
||||
#define DR_REG_UART0_BASE 0x60000000
|
||||
#define DR_REG_UART1_BASE 0x60001000
|
||||
#define DR_REG_MSPI0_BASE 0x60002000
|
||||
#define DR_REG_MSPI1_BASE 0x60003000
|
||||
#define DR_REG_I2C_BASE 0x60004000
|
||||
#define DR_REG_UART2_BASE 0x60006000
|
||||
#define DR_REG_LEDC_BASE 0x60007000
|
||||
#define DR_REG_TIMG0_BASE 0x60008000
|
||||
#define DR_REG_TIMG1_BASE 0x60009000
|
||||
#define DR_REG_SYSTIMER_BASE 0x6000A000
|
||||
#define DR_REG_I2S_BASE 0x6000C000
|
||||
#define DR_REG_SARADC_BASE 0x6000E000
|
||||
#define DR_REG_USB_SERIAL_JTAG_BASE 0x6000F000
|
||||
#define DR_REG_INTERRUPT_MATRIX_BASE 0x60010000
|
||||
#define DR_REG_SOC_ETM_BASE 0x60013000
|
||||
#define DR_REG_PVT_MONITOR_BASE 0x60019000
|
||||
#define DR_REG_PSRAM_MEM_MONITOR_BASE 0x6001A000
|
||||
#define DR_REG_AHB_GDMA_BASE 0x60080000
|
||||
#define DR_REG_GPSPI_BASE 0x60081000
|
||||
#define DR_REG_SHA_BASE 0x60089000
|
||||
#define DR_REG_ECC_BASE 0x6008B000
|
||||
#define DR_REG_ECDSA_BASE 0x6008E000
|
||||
#define DR_REG_IO_MUX_BASE 0x60090000
|
||||
#define DR_REG_GPIO_BASE 0x60091000
|
||||
#define DR_REG_TCM_MEM_MONITOR_BASE 0x60092000
|
||||
#define DR_REG_PAU_BASE 0x60093000
|
||||
#define DR_REG_HP_SYSTEM_BASE 0x60095000
|
||||
#define DR_REG_PCR_BASE 0x60096000
|
||||
#define DR_REG_TEE_REG_BASE 0x60098000
|
||||
#define DR_REG_HP_APM_REG_BASE 0x60099000
|
||||
#define DR_REG_MISC_BASE 0x6009F000
|
||||
#define DR_REG_MODEM0_BASE 0x600A0000
|
||||
#define DR_REG_MODEM1_BASE 0x600AC000
|
||||
#define DR_REG_MODEM_PWR0_BASE 0x600AD000
|
||||
#define DR_REG_MODEM_PWR1_BASE 0x600AF000
|
||||
#define DR_REG_I2C_ANA_MST_BASE 0x600AF800 //TODO: [ESP32C61] IDF-9276, from verify
|
||||
#define DR_REG_PMU_BASE 0x600B0000
|
||||
#define DR_REG_LP_CLKRST_BASE 0x600B0400
|
||||
#define DR_REG_LP_TIMER_BASE 0x600B0C00
|
||||
#define DR_REG_LP_AON_BASE 0x600B1000
|
||||
#define DR_REG_LP_WDT_BASE 0x600B1C00
|
||||
#define DR_REG_LPPERI_BASE 0x600B2800
|
||||
#define DR_REG_LP_ANA_BASE 0x600B2C00
|
||||
#define DR_REG_LP_TEE_BASE 0x600B3400
|
||||
#define DR_REG_LP_APM_BASE 0x600B3800
|
||||
#define DR_REG_LP_IO_MUX_BASE 0x600B4000
|
||||
#define DR_REG_LP_GPIO_BASE 0x600B4400
|
||||
#define DR_REG_EFUSE0_BASE 0x600B4800
|
||||
#define DR_REG_EFUSE1_BASE 0x600B4C00
|
||||
#define DR_REG_TRACE_BASE 0x600C0000
|
||||
#define DR_REG_ASSIST_DEBUG_BASE 0x600C2000
|
||||
#define DR_REG_INTPRI_BASE 0x600C5000
|
||||
#define DR_REG_CACHE_BASE 0x600C8000
|
||||
|
|
|
|||
|
|
@ -0,0 +1,175 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
/**
|
||||
* @file regi2c_bbpll.h
|
||||
* @brief Register definitions for digital PLL (BBPLL)
|
||||
*
|
||||
* This file lists register fields of BBPLL, located on an internal configuration
|
||||
* bus. These definitions are used via macros defined in regi2c_ctrl.h, by
|
||||
* rtc_clk_cpu_freq_set function in rtc_clk.c.
|
||||
*/
|
||||
|
||||
#define I2C_BBPLL 0x66
|
||||
#define I2C_BBPLL_HOSTID 0
|
||||
|
||||
#define I2C_BBPLL_IR_CAL_DELAY 0
|
||||
#define I2C_BBPLL_IR_CAL_DELAY_MSB 3
|
||||
#define I2C_BBPLL_IR_CAL_DELAY_LSB 0
|
||||
|
||||
#define I2C_BBPLL_IR_CAL_CK_DIV 0
|
||||
#define I2C_BBPLL_IR_CAL_CK_DIV_MSB 7
|
||||
#define I2C_BBPLL_IR_CAL_CK_DIV_LSB 4
|
||||
|
||||
#define I2C_BBPLL_IR_CAL_EXT_CAP 1
|
||||
#define I2C_BBPLL_IR_CAL_EXT_CAP_MSB 3
|
||||
#define I2C_BBPLL_IR_CAL_EXT_CAP_LSB 0
|
||||
|
||||
#define I2C_BBPLL_IR_CAL_ENX_CAP 1
|
||||
#define I2C_BBPLL_IR_CAL_ENX_CAP_MSB 4
|
||||
#define I2C_BBPLL_IR_CAL_ENX_CAP_LSB 4
|
||||
|
||||
#define I2C_BBPLL_IR_CAL_RSTB 1
|
||||
#define I2C_BBPLL_IR_CAL_RSTB_MSB 5
|
||||
#define I2C_BBPLL_IR_CAL_RSTB_LSB 5
|
||||
|
||||
#define I2C_BBPLL_IR_CAL_START 1
|
||||
#define I2C_BBPLL_IR_CAL_START_MSB 6
|
||||
#define I2C_BBPLL_IR_CAL_START_LSB 6
|
||||
|
||||
#define I2C_BBPLL_IR_CAL_UNSTOP 1
|
||||
#define I2C_BBPLL_IR_CAL_UNSTOP_MSB 7
|
||||
#define I2C_BBPLL_IR_CAL_UNSTOP_LSB 7
|
||||
|
||||
#define I2C_BBPLL_OC_REF_DIV 2
|
||||
#define I2C_BBPLL_OC_REF_DIV_MSB 3
|
||||
#define I2C_BBPLL_OC_REF_DIV_LSB 0
|
||||
|
||||
#define I2C_BBPLL_OC_DCHGP 2
|
||||
#define I2C_BBPLL_OC_DCHGP_MSB 6
|
||||
#define I2C_BBPLL_OC_DCHGP_LSB 4
|
||||
|
||||
#define I2C_BBPLL_OC_ENB_FCAL 2
|
||||
#define I2C_BBPLL_OC_ENB_FCAL_MSB 7
|
||||
#define I2C_BBPLL_OC_ENB_FCAL_LSB 7
|
||||
|
||||
#define I2C_BBPLL_OC_DIV_7_0 3
|
||||
#define I2C_BBPLL_OC_DIV_7_0_MSB 7
|
||||
#define I2C_BBPLL_OC_DIV_7_0_LSB 0
|
||||
|
||||
#define I2C_BBPLL_RSTB_DIV_ADC 4
|
||||
#define I2C_BBPLL_RSTB_DIV_ADC_MSB 0
|
||||
#define I2C_BBPLL_RSTB_DIV_ADC_LSB 0
|
||||
|
||||
#define I2C_BBPLL_MODE_HF 4
|
||||
#define I2C_BBPLL_MODE_HF_MSB 1
|
||||
#define I2C_BBPLL_MODE_HF_LSB 1
|
||||
|
||||
#define I2C_BBPLL_DIV_ADC 4
|
||||
#define I2C_BBPLL_DIV_ADC_MSB 3
|
||||
#define I2C_BBPLL_DIV_ADC_LSB 2
|
||||
|
||||
#define I2C_BBPLL_DIV_DAC 4
|
||||
#define I2C_BBPLL_DIV_DAC_MSB 4
|
||||
#define I2C_BBPLL_DIV_DAC_LSB 4
|
||||
|
||||
#define I2C_BBPLL_DIV_CPU 4
|
||||
#define I2C_BBPLL_DIV_CPU_MSB 5
|
||||
#define I2C_BBPLL_DIV_CPU_LSB 5
|
||||
|
||||
#define I2C_BBPLL_OC_ENB_VCON 4
|
||||
#define I2C_BBPLL_OC_ENB_VCON_MSB 6
|
||||
#define I2C_BBPLL_OC_ENB_VCON_LSB 6
|
||||
|
||||
#define I2C_BBPLL_OC_TSCHGP 4
|
||||
#define I2C_BBPLL_OC_TSCHGP_MSB 7
|
||||
#define I2C_BBPLL_OC_TSCHGP_LSB 7
|
||||
|
||||
#define I2C_BBPLL_OC_DR1 5
|
||||
#define I2C_BBPLL_OC_DR1_MSB 2
|
||||
#define I2C_BBPLL_OC_DR1_LSB 0
|
||||
|
||||
#define I2C_BBPLL_OC_DR3 5
|
||||
#define I2C_BBPLL_OC_DR3_MSB 6
|
||||
#define I2C_BBPLL_OC_DR3_LSB 4
|
||||
|
||||
#define I2C_BBPLL_EN_USB 5
|
||||
#define I2C_BBPLL_EN_USB_MSB 7
|
||||
#define I2C_BBPLL_EN_USB_LSB 7
|
||||
|
||||
#define I2C_BBPLL_OC_DCUR 6
|
||||
#define I2C_BBPLL_OC_DCUR_MSB 2
|
||||
#define I2C_BBPLL_OC_DCUR_LSB 0
|
||||
|
||||
#define I2C_BBPLL_INC_CUR 6
|
||||
#define I2C_BBPLL_INC_CUR_MSB 3
|
||||
#define I2C_BBPLL_INC_CUR_LSB 3
|
||||
|
||||
#define I2C_BBPLL_OC_DHREF_SEL 6
|
||||
#define I2C_BBPLL_OC_DHREF_SEL_MSB 5
|
||||
#define I2C_BBPLL_OC_DHREF_SEL_LSB 4
|
||||
|
||||
#define I2C_BBPLL_OC_DLREF_SEL 6
|
||||
#define I2C_BBPLL_OC_DLREF_SEL_MSB 7
|
||||
#define I2C_BBPLL_OC_DLREF_SEL_LSB 6
|
||||
|
||||
#define I2C_BBPLL_OR_CAL_CAP 8
|
||||
#define I2C_BBPLL_OR_CAL_CAP_MSB 3
|
||||
#define I2C_BBPLL_OR_CAL_CAP_LSB 0
|
||||
|
||||
#define I2C_BBPLL_OR_CAL_UDF 8
|
||||
#define I2C_BBPLL_OR_CAL_UDF_MSB 4
|
||||
#define I2C_BBPLL_OR_CAL_UDF_LSB 4
|
||||
|
||||
#define I2C_BBPLL_OR_CAL_OVF 8
|
||||
#define I2C_BBPLL_OR_CAL_OVF_MSB 5
|
||||
#define I2C_BBPLL_OR_CAL_OVF_LSB 5
|
||||
|
||||
#define I2C_BBPLL_OR_CAL_END 8
|
||||
#define I2C_BBPLL_OR_CAL_END_MSB 6
|
||||
#define I2C_BBPLL_OR_CAL_END_LSB 6
|
||||
|
||||
#define I2C_BBPLL_OR_LOCK 8
|
||||
#define I2C_BBPLL_OR_LOCK_MSB 7
|
||||
#define I2C_BBPLL_OR_LOCK_LSB 7
|
||||
|
||||
#define I2C_BBPLL_OC_VCO_DBIAS 9
|
||||
#define I2C_BBPLL_OC_VCO_DBIAS_MSB 1
|
||||
#define I2C_BBPLL_OC_VCO_DBIAS_LSB 0
|
||||
|
||||
#define I2C_BBPLL_BBADC_DELAY2 9
|
||||
#define I2C_BBPLL_BBADC_DELAY2_MSB 3
|
||||
#define I2C_BBPLL_BBADC_DELAY2_LSB 2
|
||||
|
||||
#define I2C_BBPLL_BBADC_DVDD 9
|
||||
#define I2C_BBPLL_BBADC_DVDD_MSB 5
|
||||
#define I2C_BBPLL_BBADC_DVDD_LSB 4
|
||||
|
||||
#define I2C_BBPLL_BBADC_DREF 9
|
||||
#define I2C_BBPLL_BBADC_DREF_MSB 7
|
||||
#define I2C_BBPLL_BBADC_DREF_LSB 6
|
||||
|
||||
#define I2C_BBPLL_BBADC_DCUR 10
|
||||
#define I2C_BBPLL_BBADC_DCUR_MSB 1
|
||||
#define I2C_BBPLL_BBADC_DCUR_LSB 0
|
||||
|
||||
#define I2C_BBPLL_BBADC_INPUT_SHORT 10
|
||||
#define I2C_BBPLL_BBADC_INPUT_SHORT_MSB 2
|
||||
#define I2C_BBPLL_BBADC_INPUT_SHORT_LSB 2
|
||||
|
||||
#define I2C_BBPLL_ENT_PLL 10
|
||||
#define I2C_BBPLL_ENT_PLL_MSB 3
|
||||
#define I2C_BBPLL_ENT_PLL_LSB 3
|
||||
|
||||
#define I2C_BBPLL_DTEST 10
|
||||
#define I2C_BBPLL_DTEST_MSB 5
|
||||
#define I2C_BBPLL_DTEST_LSB 4
|
||||
|
||||
#define I2C_BBPLL_ENT_ADC 10
|
||||
#define I2C_BBPLL_ENT_ADC_MSB 7
|
||||
#define I2C_BBPLL_ENT_ADC_LSB 6
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
/**
|
||||
* @file regi2c_bias.h
|
||||
* @brief Register definitions for bias
|
||||
*
|
||||
* This file lists register fields of BIAS. These definitions are used via macros defined in regi2c_ctrl.h, by
|
||||
* bootloader_hardware_init function in bootloader_esp32c6.c.
|
||||
*/
|
||||
|
||||
#define I2C_BIAS 0X6A
|
||||
#define I2C_BIAS_HOSTID 0
|
||||
|
||||
#define I2C_BIAS_DREG_1P1_PVT 1
|
||||
#define I2C_BIAS_DREG_1P1_PVT_MSB 3
|
||||
#define I2C_BIAS_DREG_1P1_PVT_LSB 0
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "esp_bit_defs.h"
|
||||
|
||||
/* Analog function control register */
|
||||
#define I2C_MST_ANA_CONF0_REG 0x600AF818
|
||||
#define I2C_MST_BBPLL_STOP_FORCE_HIGH (BIT(2))
|
||||
#define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3))
|
||||
#define I2C_MST_BBPLL_CAL_DONE (BIT(24))
|
||||
|
||||
|
||||
#define ANA_CONFIG_REG 0x600AF81C
|
||||
#define ANA_CONFIG_S (8)
|
||||
#define ANA_CONFIG_M (0x3FF)
|
||||
|
||||
#define ANA_I2C_SAR_FORCE_PD BIT(18)
|
||||
#define ANA_I2C_BBPLL_M BIT(17) /* Clear to enable BBPLL */
|
||||
|
||||
|
||||
#define ANA_CONFIG2_REG 0x600AF820
|
||||
#define ANA_CONFIG2_M BIT(18)
|
||||
|
||||
#define ANA_I2C_SAR_FORCE_PU BIT(16)
|
||||
|
|
@ -0,0 +1,64 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
/**
|
||||
* @file regi2c_dig_reg.h
|
||||
* @brief Register definitions for digital to get rtc voltage & digital voltage
|
||||
* by setting rtc_dbias_Wak & dig_dbias_wak or by analog self-calibration.
|
||||
*/
|
||||
|
||||
#define I2C_DIG_REG 0x6D
|
||||
#define I2C_DIG_REG_HOSTID 0
|
||||
|
||||
#define I2C_DIG_REG_EXT_RTC_DREG 4
|
||||
#define I2C_DIG_REG_EXT_RTC_DREG_MSB 4
|
||||
#define I2C_DIG_REG_EXT_RTC_DREG_LSB 0
|
||||
|
||||
#define I2C_DIG_REG_ENX_RTC_DREG 4
|
||||
#define I2C_DIG_REG_ENX_RTC_DREG_MSB 7
|
||||
#define I2C_DIG_REG_ENX_RTC_DREG_LSB 7
|
||||
|
||||
#define I2C_DIG_REG_EXT_RTC_DREG_SLEEP 5
|
||||
#define I2C_DIG_REG_EXT_RTC_DREG_SLEEP_MSB 4
|
||||
#define I2C_DIG_REG_EXT_RTC_DREG_SLEEP_LSB 0
|
||||
|
||||
#define I2C_DIG_REG_ENIF_RTC_DREG 5
|
||||
#define I2C_DIG_REG_ENIF_RTC_DREG_MSB 7
|
||||
#define I2C_DIG_REG_ENIF_RTC_DREG_LSB 7
|
||||
|
||||
#define I2C_DIG_REG_EXT_DIG_DREG 6
|
||||
#define I2C_DIG_REG_EXT_DIG_DREG_MSB 4
|
||||
#define I2C_DIG_REG_EXT_DIG_DREG_LSB 0
|
||||
|
||||
#define I2C_DIG_REG_ENX_DIG_DREG 6
|
||||
#define I2C_DIG_REG_ENX_DIG_DREG_MSB 7
|
||||
#define I2C_DIG_REG_ENX_DIG_DREG_LSB 7
|
||||
|
||||
#define I2C_DIG_REG_EXT_DIG_DREG_SLEEP 7
|
||||
#define I2C_DIG_REG_EXT_DIG_DREG_SLEEP_MSB 4
|
||||
#define I2C_DIG_REG_EXT_DIG_DREG_SLEEP_LSB 0
|
||||
|
||||
#define I2C_DIG_REG_ENIF_DIG_DREG 7
|
||||
#define I2C_DIG_REG_ENIF_DIG_DREG_MSB 7
|
||||
#define I2C_DIG_REG_ENIF_DIG_DREG_LSB 7
|
||||
|
||||
#define I2C_DIG_REG_OR_EN_CONT_CAL 9
|
||||
#define I2C_DIG_REG_OR_EN_CONT_CAL_MSB 7
|
||||
#define I2C_DIG_REG_OR_EN_CONT_CAL_LSB 7
|
||||
|
||||
#define I2C_DIG_REG_XPD_RTC_REG 13
|
||||
#define I2C_DIG_REG_XPD_RTC_REG_MSB 2
|
||||
#define I2C_DIG_REG_XPD_RTC_REG_LSB 2
|
||||
|
||||
#define I2C_DIG_REG_XPD_DIG_REG 13
|
||||
#define I2C_DIG_REG_XPD_DIG_REG_MSB 3
|
||||
#define I2C_DIG_REG_XPD_DIG_REG_LSB 3
|
||||
|
||||
#define I2C_DIG_REG_SCK_DCAP 14
|
||||
#define I2C_DIG_REG_SCK_DCAP_MSB 7
|
||||
#define I2C_DIG_REG_SCK_DCAP_LSB 0
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
/**
|
||||
* @file regi2c_lp_bias.h
|
||||
* @brief Register definitions for analog to calibrate o_code for getting a more precise voltage.
|
||||
*
|
||||
* This file lists register fields of low power dbais, located on an internal configuration
|
||||
* bus. These definitions are used via macros defined in regi2c_ctrl.h, by
|
||||
* rtc_init function in rtc_init.c.
|
||||
*/
|
||||
|
||||
#define I2C_ULP 0x61
|
||||
#define I2C_ULP_HOSTID 0
|
||||
|
||||
#define I2C_ULP_IR_RESETB 0
|
||||
#define I2C_ULP_IR_RESETB_MSB 0
|
||||
#define I2C_ULP_IR_RESETB_LSB 0
|
||||
|
||||
#define I2C_ULP_IR_FORCE_XPD_CK 0
|
||||
#define I2C_ULP_IR_FORCE_XPD_CK_MSB 2
|
||||
#define I2C_ULP_IR_FORCE_XPD_CK_LSB 2
|
||||
|
||||
#define I2C_ULP_IR_FORCE_XPD_IPH 0
|
||||
#define I2C_ULP_IR_FORCE_XPD_IPH_MSB 4
|
||||
#define I2C_ULP_IR_FORCE_XPD_IPH_LSB 4
|
||||
|
||||
#define I2C_ULP_IR_DISABLE_WATCHDOG_CK 0
|
||||
#define I2C_ULP_IR_DISABLE_WATCHDOG_CK_MSB 6
|
||||
#define I2C_ULP_IR_DISABLE_WATCHDOG_CK_LSB 6
|
||||
|
||||
#define I2C_ULP_O_DONE_FLAG 3
|
||||
#define I2C_ULP_O_DONE_FLAG_MSB 0
|
||||
#define I2C_ULP_O_DONE_FLAG_LSB 0
|
||||
|
||||
#define I2C_ULP_BG_O_DONE_FLAG 3
|
||||
#define I2C_ULP_BG_O_DONE_FLAG_MSB 3
|
||||
#define I2C_ULP_BG_O_DONE_FLAG_LSB 3
|
||||
|
||||
#define I2C_ULP_OCODE 4
|
||||
#define I2C_ULP_OCODE_MSB 7
|
||||
#define I2C_ULP_OCODE_LSB 0
|
||||
|
||||
#define I2C_ULP_IR_FORCE_CODE 5
|
||||
#define I2C_ULP_IR_FORCE_CODE_MSB 6
|
||||
#define I2C_ULP_IR_FORCE_CODE_LSB 6
|
||||
|
||||
#define I2C_ULP_EXT_CODE 6
|
||||
#define I2C_ULP_EXT_CODE_MSB 7
|
||||
#define I2C_ULP_EXT_CODE_LSB 0
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
//+-----------------------------------------------Terminology---------------------------------------------+
|
||||
//| |
|
||||
//| CPU Reset: Reset CPU core only, once reset done, CPU will execute from reset vector |
|
||||
//| |
|
||||
//| Core Reset: Reset the whole digital system except RTC sub-system |
|
||||
//| |
|
||||
//| System Reset: Reset the whole digital system, including RTC sub-system |
|
||||
//| |
|
||||
//| Chip Reset: Reset the whole chip, including the analog part |
|
||||
//| |
|
||||
//+-------------------------------------------------------------------------------------------------------+
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* @brief Naming conventions: RESET_REASON_{reset level}_{reset reason}
|
||||
* @note refer to TRM: <Reset and Clock> chapter
|
||||
*/
|
||||
typedef enum {
|
||||
RESET_REASON_CHIP_POWER_ON = 0x01, // Power on reset
|
||||
RESET_REASON_CHIP_BROWN_OUT = 0x01, // VDD voltage is not stable and resets the chip
|
||||
RESET_REASON_CORE_SW = 0x03, // Software resets the digital core (hp system) by LP_AON_HPSYS_SW_RESET
|
||||
RESET_REASON_CORE_DEEP_SLEEP = 0x05, // Deep sleep reset the digital core (hp system)
|
||||
RESET_REASON_CORE_SDIO = 0x06, // SDIO module resets the digital core (hp system)
|
||||
RESET_REASON_CORE_MWDT0 = 0x07, // Main watch dog 0 resets digital core (hp system)
|
||||
RESET_REASON_CORE_MWDT1 = 0x08, // Main watch dog 1 resets digital core (hp system)
|
||||
RESET_REASON_CORE_RTC_WDT = 0x09, // RTC watch dog resets digital core (hp system)
|
||||
RESET_REASON_CPU0_MWDT0 = 0x0B, // Main watch dog 0 resets CPU 0
|
||||
RESET_REASON_CPU0_SW = 0x0C, // Software resets CPU 0 by LP_AON_CPU_CORE0_SW_RESET
|
||||
RESET_REASON_CPU0_RTC_WDT = 0x0D, // RTC watch dog resets CPU 0
|
||||
RESET_REASON_SYS_BROWN_OUT = 0x0F, // VDD voltage is not stable and resets the digital core
|
||||
RESET_REASON_SYS_RTC_WDT = 0x10, // RTC watch dog resets digital core and rtc module
|
||||
RESET_REASON_CPU0_MWDT1 = 0x11, // Main watch dog 1 resets CPU 0
|
||||
RESET_REASON_SYS_SUPER_WDT = 0x12, // Super watch dog resets the digital core and rtc module
|
||||
RESET_REASON_CORE_EFUSE_CRC = 0x14, // eFuse CRC error resets the digital core (hp system)
|
||||
RESET_REASON_CORE_USB_UART = 0x15, // USB UART resets the digital core (hp system)
|
||||
RESET_REASON_CORE_USB_JTAG = 0x16, // USB JTAG resets the digital core (hp system)
|
||||
RESET_REASON_CPU0_JTAG = 0x18, // JTAG resets the CPU 0
|
||||
} soc_reset_reason_t;
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "esp_bit_defs.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum periph_retention_module_bitmap {
|
||||
/* clock module, which includes system and modem */
|
||||
SLEEP_RETENTION_MODULE_CLOCK_SYSTEM = BIT(1),
|
||||
SLEEP_RETENTION_MODULE_CLOCK_MODEM = BIT(2),
|
||||
|
||||
/* modem module, which includes WiFi, BLE and 802.15.4 */
|
||||
SLEEP_RETENTION_MODULE_WIFI_MAC = BIT(10),
|
||||
SLEEP_RETENTION_MODULE_WIFI_BB = BIT(11),
|
||||
SLEEP_RETENTION_MODULE_BLE_MAC = BIT(12),
|
||||
SLEEP_RETENTION_MODULE_BT_BB = BIT(13),
|
||||
SLEEP_RETENTION_MODULE_802154_MAC = BIT(14),
|
||||
|
||||
/* digital peripheral module, which includes Interrupt Matrix, HP_SYSTEM,
|
||||
* TEE, APM, UART, Timer Group, IOMUX, SPIMEM, SysTimer, etc.. */
|
||||
SLEEP_RETENTION_MODULE_INTR_MATRIX = BIT(16),
|
||||
SLEEP_RETENTION_MODULE_HP_SYSTEM = BIT(17),
|
||||
SLEEP_RETENTION_MODULE_TEE_APM = BIT(18),
|
||||
SLEEP_RETENTION_MODULE_UART0 = BIT(19),
|
||||
SLEEP_RETENTION_MODULE_TG0 = BIT(20),
|
||||
SLEEP_RETENTION_MODULE_IOMUX = BIT(21),
|
||||
SLEEP_RETENTION_MODULE_SPIMEM = BIT(22),
|
||||
SLEEP_RETENTION_MODULE_SYSTIMER = BIT(23),
|
||||
SLEEP_RETENTION_MODULE_GDMA_CH0 = BIT(24),
|
||||
SLEEP_RETENTION_MODULE_GDMA_CH1 = BIT(25),
|
||||
SLEEP_RETENTION_MODULE_GDMA_CH2 = BIT(26),
|
||||
SLEEP_RETENTION_MODULE_I2C0 = BIT(27),
|
||||
SLEEP_RETENTION_MODULE_ALL = (uint32_t)-1
|
||||
} periph_retention_module_bitmap_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,240 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
#include <stdint.h>
|
||||
#include "esp_assert.h"
|
||||
#endif
|
||||
|
||||
#include "esp_bit_defs.h"
|
||||
#include "reg_base.h"
|
||||
|
||||
#define PRO_CPU_NUM (0)
|
||||
|
||||
#define REG_UART_BASE(i) (DR_REG_UART0_BASE + (i) * 0x1000) // UART0 and UART1
|
||||
#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000)
|
||||
#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0)
|
||||
#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on C61
|
||||
#define REG_TIMG_BASE(i) (DR_REG_TIMG0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1
|
||||
#define REG_SPI_MEM_BASE(i) (DR_REG_MSPI0_BASE + (i) * 0x1000) // SPIMEM0 and SPIMEM1
|
||||
#define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (0)) // only one GPSPI on C61
|
||||
#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE) // only one I2C on C61
|
||||
|
||||
//Registers Operation {{
|
||||
#define ETS_UNCACHED_ADDR(addr) (addr)
|
||||
#define ETS_CACHED_ADDR(addr) (addr)
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
|
||||
//write value to register
|
||||
#define REG_WRITE(_r, _v) do { \
|
||||
(*(volatile uint32_t *)(_r)) = (_v); \
|
||||
} while(0)
|
||||
|
||||
//read value from register
|
||||
#define REG_READ(_r) ({ \
|
||||
(*(volatile uint32_t *)(_r)); \
|
||||
})
|
||||
|
||||
//get bit or get bits from register
|
||||
#define REG_GET_BIT(_r, _b) ({ \
|
||||
(*(volatile uint32_t*)(_r) & (_b)); \
|
||||
})
|
||||
|
||||
//set bit or set bits to register
|
||||
#define REG_SET_BIT(_r, _b) do { \
|
||||
*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r)) | (_b); \
|
||||
} while(0)
|
||||
|
||||
//clear bit or clear bits of register
|
||||
#define REG_CLR_BIT(_r, _b) do { \
|
||||
*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r)) & (~(_b)); \
|
||||
} while(0)
|
||||
|
||||
//set bits of register controlled by mask
|
||||
#define REG_SET_BITS(_r, _b, _m) do { \
|
||||
*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m)); \
|
||||
} while(0)
|
||||
|
||||
//get field from register, uses field _S & _V to determine mask
|
||||
#define REG_GET_FIELD(_r, _f) ({ \
|
||||
((REG_READ(_r) >> (_f##_S)) & (_f##_V)); \
|
||||
})
|
||||
|
||||
//set field of a register from variable, uses field _S & _V to determine mask
|
||||
#define REG_SET_FIELD(_r, _f, _v) do { \
|
||||
REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S)))); \
|
||||
} while(0)
|
||||
|
||||
//get field value from a variable, used when _f is not left shifted by _f##_S
|
||||
#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
|
||||
|
||||
//get field value from a variable, used when _f is left shifted by _f##_S
|
||||
#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
|
||||
|
||||
//set field value to a variable, used when _f is not left shifted by _f##_S
|
||||
#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
|
||||
|
||||
//set field value to a variable, used when _f is left shifted by _f##_S
|
||||
#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
|
||||
|
||||
//generate a value from a field value, used when _f is not left shifted by _f##_S
|
||||
#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
|
||||
|
||||
//generate a value from a field value, used when _f is left shifted by _f##_S
|
||||
#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
|
||||
|
||||
//read value from register
|
||||
#define READ_PERI_REG(addr) ({ \
|
||||
(*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))); \
|
||||
})
|
||||
|
||||
//write value to register
|
||||
#define WRITE_PERI_REG(addr, val) do { \
|
||||
(*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val); \
|
||||
} while(0)
|
||||
|
||||
//clear bits of register controlled by mask
|
||||
#define CLEAR_PERI_REG_MASK(reg, mask) do { \
|
||||
WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); \
|
||||
} while(0)
|
||||
|
||||
//set bits of register controlled by mask
|
||||
#define SET_PERI_REG_MASK(reg, mask) do { \
|
||||
WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); \
|
||||
} while(0)
|
||||
|
||||
//get bits of register controlled by mask
|
||||
#define GET_PERI_REG_MASK(reg, mask) ({ \
|
||||
(READ_PERI_REG(reg) & (mask)); \
|
||||
})
|
||||
|
||||
//get bits of register controlled by highest bit and lowest bit
|
||||
#define GET_PERI_REG_BITS(reg, hipos,lowpos) ({ \
|
||||
((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)); \
|
||||
})
|
||||
|
||||
//set bits of register controlled by mask and shift
|
||||
#define SET_PERI_REG_BITS(reg,bit_map,value,shift) do { \
|
||||
WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & (bit_map))<<(shift)) ); \
|
||||
} while(0)
|
||||
|
||||
//get field of register
|
||||
#define GET_PERI_REG_BITS2(reg, mask,shift) ({ \
|
||||
((READ_PERI_REG(reg)>>(shift))&(mask)); \
|
||||
})
|
||||
|
||||
#endif /* !__ASSEMBLER__ */
|
||||
//}}
|
||||
|
||||
//Periheral Clock {{
|
||||
#define APB_CLK_FREQ_ROM ( 40*1000000 )
|
||||
#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM
|
||||
#define CPU_CLK_FREQ_MHZ_BTLD (80) // The cpu clock frequency (in MHz) to set at 2nd stage bootloader system clock configuration
|
||||
#define APB_CLK_FREQ ( 40*1000000 )
|
||||
#define MODEM_REQUIRED_MIN_APB_CLK_FREQ ( 80*1000000 )
|
||||
#define REF_CLK_FREQ ( 1000000 )
|
||||
#define XTAL_CLK_FREQ (40*1000000)
|
||||
#define GPIO_MATRIX_DELAY_NS 0
|
||||
//}}
|
||||
|
||||
/* Overall memory map */
|
||||
/* Note: We should not use MACROs similar in cache_memory.h
|
||||
* those are defined during run-time. But the MACROs here
|
||||
* should be defined statically!
|
||||
*/
|
||||
|
||||
#define SOC_IROM_LOW 0x42000000
|
||||
#define SOC_IROM_HIGH 0x44000000
|
||||
#define SOC_EXTRAM_DATA_LOW 0x42000000
|
||||
#define SOC_EXTRAM_DATA_HIGH 0x44000000
|
||||
#define SOC_DROM_LOW SOC_IROM_LOW
|
||||
#define SOC_DROM_HIGH SOC_IROM_HIGH
|
||||
#define SOC_IROM_MASK_LOW 0x40000000
|
||||
#define SOC_IROM_MASK_HIGH 0x4004AC00
|
||||
#define SOC_DROM_MASK_LOW 0x4004AC00
|
||||
#define SOC_DROM_MASK_HIGH 0x40070000
|
||||
#define SOC_IRAM_LOW 0x40800000
|
||||
#define SOC_IRAM_HIGH 0x40850000
|
||||
#define SOC_DRAM_LOW 0x40800000
|
||||
#define SOC_DRAM_HIGH 0x40850000
|
||||
#define SOC_RTC_IRAM_LOW 0x50000000 // ESP32-C61 only has 16k LP memory
|
||||
#define SOC_RTC_IRAM_HIGH 0x50004000
|
||||
#define SOC_RTC_DRAM_LOW 0x50000000
|
||||
#define SOC_RTC_DRAM_HIGH 0x50004000
|
||||
#define SOC_RTC_DATA_LOW 0x50000000
|
||||
#define SOC_RTC_DATA_HIGH 0x50004000
|
||||
|
||||
//First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias.
|
||||
#define SOC_DIRAM_IRAM_LOW 0x40800000
|
||||
#define SOC_DIRAM_IRAM_HIGH 0x40850000
|
||||
#define SOC_DIRAM_DRAM_LOW 0x40800000
|
||||
#define SOC_DIRAM_DRAM_HIGH 0x40850000
|
||||
|
||||
#define MAP_DRAM_TO_IRAM(addr) (addr)
|
||||
#define MAP_IRAM_TO_DRAM(addr) (addr)
|
||||
|
||||
// Region of memory accessible via DMA. See esp_ptr_dma_capable().
|
||||
#define SOC_DMA_LOW 0x40800000
|
||||
#define SOC_DMA_HIGH 0x40850000
|
||||
|
||||
// Region of RAM that is byte-accessible. See esp_ptr_byte_accessible().
|
||||
#define SOC_BYTE_ACCESSIBLE_LOW 0x40800000
|
||||
#define SOC_BYTE_ACCESSIBLE_HIGH 0x40850000
|
||||
|
||||
//Region of memory that is internal, as in on the same silicon die as the ESP32 CPUs
|
||||
//(excluding RTC data region, that's checked separately.) See esp_ptr_internal().
|
||||
#define SOC_MEM_INTERNAL_LOW 0x40800000
|
||||
#define SOC_MEM_INTERNAL_HIGH 0x40850000
|
||||
#define SOC_MEM_INTERNAL_LOW1 0x40800000
|
||||
#define SOC_MEM_INTERNAL_HIGH1 0x40850000
|
||||
|
||||
#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_IRAM_HIGH - SOC_IRAM_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space
|
||||
|
||||
// Region of address space that holds peripherals
|
||||
#define SOC_PERIPHERAL_LOW 0x60000000
|
||||
#define SOC_PERIPHERAL_HIGH 0x60100000
|
||||
|
||||
// CPU sub-system region, contains interrupt config registers
|
||||
#define SOC_CPU_SUBSYSTEM_LOW 0x20000000
|
||||
#define SOC_CPU_SUBSYSTEM_HIGH 0x30000000
|
||||
|
||||
// Start (highest address) of ROM boot stack, only relevant during early boot
|
||||
#define SOC_ROM_STACK_START 0x4084c9f0
|
||||
#define SOC_ROM_STACK_SIZE 0x2000
|
||||
|
||||
//On RISC-V CPUs, the interrupt sources are all external interrupts, whose type, source and priority are configured by SW.
|
||||
//There is no HW NMI conception. SW should controlled the masked levels through INT_THRESH_REG.
|
||||
|
||||
//CPU0 Interrupt numbers used in components/riscv/vectors.S. Change it's logic if modifying
|
||||
#define ETS_T1_WDT_INUM 24
|
||||
#define ETS_CACHEERR_INUM 25
|
||||
#define ETS_MEMPROT_ERR_INUM 26
|
||||
#define ETS_ASSIST_DEBUG_INUM 27 // Note: this interrupt can be combined with others (e.g., CACHEERR), as we can identify its trigger is activated
|
||||
|
||||
//CPU0 Max valid interrupt number
|
||||
#define ETS_MAX_INUM 31
|
||||
|
||||
//CPU0 Interrupt number used in ROM, should be cancelled in SDK
|
||||
#define ETS_SLC_INUM 1
|
||||
#define ETS_UART0_INUM 5
|
||||
#define ETS_UART1_INUM 5
|
||||
#define ETS_SPI2_INUM 1
|
||||
//CPU0 Interrupt number used in ROM code only when module init function called, should pay attention here.
|
||||
#define ETS_GPIO_INUM 4
|
||||
|
||||
//Other interrupt number should be managed by the user
|
||||
|
||||
//Invalid interrupt for number interrupt matrix
|
||||
#define ETS_INVALID_INUM 0
|
||||
|
||||
//Interrupt medium level, used for INT WDT for example
|
||||
#define SOC_INTERRUPT_LEVEL_MEDIUM 4
|
||||
|
||||
// Interrupt number for the Interrupt watchdog
|
||||
#define ETS_INT_WDT_INUM (ETS_T1_WDT_INUM)
|
||||
|
|
@ -0,0 +1,572 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/*
|
||||
* These defines are parsed and imported as kconfig variables via the script
|
||||
* `tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py`
|
||||
*
|
||||
* If this file is changed the script will automatically run the script
|
||||
* and generate the kconfig variables as part of the pre-commit hooks.
|
||||
*
|
||||
* It can also be run manually. For more information, see `${IDF_PATH}/tools/gen_soc_caps_kconfig/README.md`
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
/*-------------------------- COMMON CAPS ---------------------------------------*/
|
||||
// #define SOC_ADC_SUPPORTED 1 //TODO: [ESP32C61] IDF-9302, IDF-9303, IDF-9304
|
||||
// #define SOC_DEDICATED_GPIO_SUPPORTED 1 //TODO: [ESP32C61] IDF-9321
|
||||
#define SOC_UART_SUPPORTED 1 //TODO: [ESP32C61] IDF-9320
|
||||
// #define SOC_GDMA_SUPPORTED 1 //TODO: [ESP32C61] IDF-9310, IDF-9311
|
||||
// #define SOC_AHB_GDMA_SUPPORTED 1 //TODO: [ESP32C61] IDF-9310, IDF-9311
|
||||
// #define SOC_GPTIMER_SUPPORTED 1 //TODO: [ESP32C61] IDF-9306
|
||||
// #define SOC_BT_SUPPORTED 1
|
||||
// #define SOC_IEEE802154_SUPPORTED 1
|
||||
// #define SOC_ASYNC_MEMCPY_SUPPORTED 1 //TODO: [ESP32C61] IDF-9315
|
||||
// #define SOC_USB_SERIAL_JTAG_SUPPORTED 1 //TODO: [ESP32C61] IDF-9319
|
||||
// #define SOC_TEMP_SENSOR_SUPPORTED 1 //TODO: [ESP32C61] IDF-9322
|
||||
// #define SOC_WIFI_SUPPORTED 1
|
||||
// #define SOC_SUPPORTS_SECURE_DL_MODE 1
|
||||
// #define SOC_ULP_SUPPORTED 1
|
||||
#define SOC_EFUSE_KEY_PURPOSE_FIELD 1
|
||||
#define SOC_EFUSE_SUPPORTED 1 //TODO: [ESP32C61] IDF-9282
|
||||
#define SOC_RTC_FAST_MEM_SUPPORTED 1
|
||||
#define SOC_RTC_MEM_SUPPORTED 1 //TODO: [ESP32C61] IDF-9274
|
||||
// #define SOC_I2S_SUPPORTED 1 //TODO: [ESP32C61] IDF-9312, IDF-9313
|
||||
// #define SOC_SDM_SUPPORTED 1 //TODO: [ESP32C61] IDF-9335
|
||||
// #define SOC_GPSPI_SUPPORTED 1 //TODO: [ESP32C61] IDF-9299, IDF-9300, IDF-9301
|
||||
// #define SOC_LEDC_SUPPORTED 1 //TODO: [ESP32C61] IDF-9291
|
||||
// #define SOC_I2C_SUPPORTED 1 //TODO: [ESP32C61] IDF-9296, IDF-9297
|
||||
#define SOC_SYSTIMER_SUPPORTED 1 //TODO: [ESP32C61] IDF-9307, IDF-9308
|
||||
// #define SOC_SUPPORT_COEXISTENCE 1
|
||||
// #define SOC_MPI_SUPPORTED 1
|
||||
// #define SOC_SHA_SUPPORTED 1 //TODO: [ESP32C61] IDF-9234
|
||||
// #define SOC_HMAC_SUPPORTED 1 //TODO: [ESP32C61] IDF-9323
|
||||
// #define SOC_DIG_SIGN_SUPPORTED 1 //TODO: [ESP32C61] IDF-9325
|
||||
// #define SOC_ECC_SUPPORTED 1 //TODO: [ESP32C61] IDF-9235
|
||||
#define SOC_FLASH_ENC_SUPPORTED 1 //TODO: [ESP32C61] IDF-9232
|
||||
// #define SOC_SECURE_BOOT_SUPPORTED 1 //TODO: [ESP32C61] IDF-9233
|
||||
// #define SOC_BOD_SUPPORTED 1 //TODO: [ESP32C61] IDF-9254
|
||||
// #define SOC_APM_SUPPORTED 1 //TODO: [ESP32C61] IDF-9230
|
||||
// #define SOC_PMU_SUPPORTED 1
|
||||
// #define SOC_LP_TIMER_SUPPORTED 1 //TODO: [ESP32C61] IDF-9244
|
||||
// #define SOC_LP_AON_SUPPORTED 1
|
||||
// #define SOC_LP_PERIPHERALS_SUPPORTED 1
|
||||
// #define SOC_CLK_TREE_SUPPORTED 1 //TODO: [ESP32C61] IDF-9249
|
||||
// #define SOC_ASSIST_DEBUG_SUPPORTED 1 //TODO: [ESP32C61] IDF-9270
|
||||
// #define SOC_WDT_SUPPORTED 1 //TODO: [ESP32C61] IDF-9257
|
||||
#define SOC_SPI_FLASH_SUPPORTED 1 //TODO: [ESP32C61] IDF-9314
|
||||
// #define SOC_RNG_SUPPORTED 1 //TODO: [ESP32C61] IDF-9236
|
||||
// #define SOC_MODEM_CLOCK_SUPPORTED 1
|
||||
// #define SOC_REG_I2C_SUPPORTED 1 //TODO: [ESP32C61] IDF-9276
|
||||
|
||||
// #define SOC_PCNT_SUPPORTED 0 //TODO: [ESP32C61] IDF-9332
|
||||
// #define SOC_MCPWM_SUPPORTED 0 //TODO: [ESP32C61] IDF-9338
|
||||
// #define SOC_TWAI_SUPPORTED 0 //TODO: [ESP32C61] IDF-9336
|
||||
// #define SOC_ETM_SUPPORTED 0
|
||||
// #define SOC_PARLIO_SUPPORTED 0 //TODO: [ESP32C61] IDF-9333, 9334
|
||||
// #define SOC_LP_CORE_SUPPORTED 0 //TODO: [ESP32C61] IDF-9331
|
||||
// #define SOC_RMT_SUPPORTED 0 //TODO: [ESP32C61] IDF-9343
|
||||
// #define SOC_AES_SUPPORTED 0 //TODO: [ESP32C61] IDF-9328
|
||||
// #define SOC_SDIO_SLAVE_SUPPORTED 0
|
||||
// #define SOC_PAU_SUPPORTED 0
|
||||
// #define SOC_LP_I2C_SUPPORTED 0 //TODO: [ESP32C61] IDF-9330, IDF-9337
|
||||
// #define SOC_ULP_LP_UART_SUPPORTED 0 //TODO: [ESP32C61] IDF-9329, IDF-9341
|
||||
|
||||
/*-------------------------- XTAL CAPS ---------------------------------------*/
|
||||
#define SOC_XTAL_SUPPORT_40M 1
|
||||
|
||||
/*-------------------------- AES CAPS -----------------------------------------*/
|
||||
#define SOC_AES_SUPPORT_DMA (1)
|
||||
|
||||
/* Has a centralized DMA, which is shared with all peripherals */
|
||||
#define SOC_AES_GDMA (1)
|
||||
|
||||
#define SOC_AES_SUPPORT_AES_128 (1)
|
||||
#define SOC_AES_SUPPORT_AES_256 (1)
|
||||
|
||||
/*-------------------------- ADC CAPS -------------------------------*/
|
||||
/*!< SAR ADC Module*/
|
||||
#define SOC_ADC_DIG_CTRL_SUPPORTED 1
|
||||
#define SOC_ADC_DIG_IIR_FILTER_SUPPORTED 1
|
||||
#define SOC_ADC_MONITOR_SUPPORTED 1
|
||||
#define SOC_ADC_DIG_SUPPORTED_UNIT(UNIT) 1 //Digital controller supported ADC unit
|
||||
#define SOC_ADC_DMA_SUPPORTED 1
|
||||
#define SOC_ADC_PERIPH_NUM (1U)
|
||||
#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (7)
|
||||
#define SOC_ADC_MAX_CHANNEL_NUM (7)
|
||||
#define SOC_ADC_ATTEN_NUM (4)
|
||||
|
||||
/*!< Digital */
|
||||
#define SOC_ADC_DIGI_CONTROLLER_NUM (1U)
|
||||
#define SOC_ADC_PATT_LEN_MAX (8) /*!< Two pattern tables, each contains 4 items. Each item takes 1 byte */
|
||||
#define SOC_ADC_DIGI_MAX_BITWIDTH (12)
|
||||
#define SOC_ADC_DIGI_MIN_BITWIDTH (12)
|
||||
#define SOC_ADC_DIGI_IIR_FILTER_NUM (2)
|
||||
#define SOC_ADC_DIGI_MONITOR_NUM (2)
|
||||
#define SOC_ADC_DIGI_RESULT_BYTES (4)
|
||||
#define SOC_ADC_DIGI_DATA_BYTES_PER_CONV (4)
|
||||
/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval <= 4095 */
|
||||
#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333
|
||||
#define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611
|
||||
|
||||
/*!< RTC */
|
||||
#define SOC_ADC_RTC_MIN_BITWIDTH (12)
|
||||
#define SOC_ADC_RTC_MAX_BITWIDTH (12)
|
||||
|
||||
/*!< Calibration */
|
||||
#define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/
|
||||
#define SOC_ADC_SELF_HW_CALI_SUPPORTED (1) /*!< support HW offset self calibration */
|
||||
#define SOC_ADC_CALIB_CHAN_COMPENS_SUPPORTED (1) /*!< support channel compensation to the HW offset calibration */
|
||||
|
||||
/*!< Interrupt */
|
||||
#define SOC_ADC_TEMPERATURE_SHARE_INTR (1)
|
||||
|
||||
/*!< ADC power control is shared by PWDET */
|
||||
#define SOC_ADC_SHARED_POWER 1
|
||||
|
||||
/*-------------------------- APB BACKUP DMA CAPS -------------------------------*/
|
||||
#define SOC_APB_BACKUP_DMA (0)
|
||||
|
||||
/*-------------------------- BROWNOUT CAPS -----------------------------------*/
|
||||
#define SOC_BROWNOUT_RESET_SUPPORTED 1
|
||||
|
||||
/*-------------------------- CACHE CAPS --------------------------------------*/
|
||||
#define SOC_SHARED_IDCACHE_SUPPORTED 1 //Shared Cache for both instructions and data
|
||||
#define SOC_CACHE_FREEZE_SUPPORTED 1
|
||||
|
||||
/*-------------------------- CPU CAPS ----------------------------------------*/
|
||||
#define SOC_CPU_CORES_NUM (1U)
|
||||
#define SOC_CPU_INTR_NUM 32
|
||||
#define SOC_CPU_HAS_FLEXIBLE_INTC 1
|
||||
#define SOC_INT_PLIC_SUPPORTED 0 //riscv platform-level interrupt controller
|
||||
#define SOC_INT_CLIC_SUPPORTED 1
|
||||
#define SOC_INT_HW_NESTED_SUPPORTED 1 // Support for hardware interrupts nesting
|
||||
#define SOC_BRANCH_PREDICTOR_SUPPORTED 1
|
||||
|
||||
#define SOC_CPU_BREAKPOINTS_NUM 4
|
||||
#define SOC_CPU_WATCHPOINTS_NUM 4
|
||||
#define SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 0x80000000 // bytes
|
||||
|
||||
#define SOC_CPU_HAS_PMA 1
|
||||
#define SOC_CPU_IDRAM_SPLIT_USING_PMP 1
|
||||
|
||||
/*-------------------------- DIGITAL SIGNATURE CAPS ----------------------------------------*/
|
||||
//TODO: [ESP32C61] IDF-9325 (Copy from esp32c6, need check)
|
||||
/** The maximum length of a Digital Signature in bits. */
|
||||
#define SOC_DS_SIGNATURE_MAX_BIT_LEN (3072)
|
||||
|
||||
/** Initialization vector (IV) length for the RSA key parameter message digest (MD) in bytes. */
|
||||
#define SOC_DS_KEY_PARAM_MD_IV_LENGTH (16)
|
||||
|
||||
/** Maximum wait time for DS parameter decryption key. If overdue, then key error.
|
||||
See TRM DS chapter for more details */
|
||||
#define SOC_DS_KEY_CHECK_MAX_WAIT_US (1100)
|
||||
|
||||
/*-------------------------- GDMA CAPS -------------------------------------*/
|
||||
#define SOC_AHB_GDMA_VERSION 1U
|
||||
#define SOC_GDMA_NUM_GROUPS_MAX 1U
|
||||
#define SOC_GDMA_PAIRS_PER_GROUP_MAX 3
|
||||
#define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule
|
||||
|
||||
/*-------------------------- ETM CAPS --------------------------------------*/
|
||||
#define SOC_ETM_GROUPS 1U // Number of ETM groups
|
||||
#define SOC_ETM_CHANNELS_PER_GROUP 50 // Number of ETM channels in the group
|
||||
|
||||
/*-------------------------- GPIO CAPS ---------------------------------------*/
|
||||
// ESP32-C61 has 1 GPIO peripheral
|
||||
#define SOC_GPIO_PORT 1U
|
||||
#define SOC_GPIO_PIN_COUNT 31
|
||||
// #define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1 //TODO: [ESP32C61] IDF-9340
|
||||
// #define SOC_GPIO_FLEX_GLITCH_FILTER_NUM 8 //TODO: [ESP32C61] IDF-9340
|
||||
|
||||
// GPIO peripheral has the ETM extension
|
||||
// #define SOC_GPIO_SUPPORT_ETM 1 //TODO: [ESP32C61] IDF-9340
|
||||
#define SOC_GPIO_ETM_EVENTS_PER_GROUP 8
|
||||
#define SOC_GPIO_ETM_TASKS_PER_GROUP 8
|
||||
|
||||
// Target has the full LP IO subsystem
|
||||
// On ESP32-C61, Digital IOs have their own registers to control pullup/down capability, independent of LP registers.
|
||||
#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1)
|
||||
// GPIO0~7 on ESP32C61 can support chip deep sleep wakeup
|
||||
// #define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1) //TODO:reopen
|
||||
|
||||
#define SOC_GPIO_VALID_GPIO_MASK ((1U<<SOC_GPIO_PIN_COUNT) - 1)
|
||||
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
|
||||
|
||||
#define SOC_GPIO_IN_RANGE_MAX 30
|
||||
#define SOC_GPIO_OUT_RANGE_MAX 30
|
||||
|
||||
#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7)
|
||||
|
||||
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_8~GPIO_NUM_30)
|
||||
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x000000007FFFFF00ULL
|
||||
|
||||
// Support to force hold all IOs
|
||||
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
|
||||
// Support to hold a single digital I/O when the digital domain is powered off
|
||||
#define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1)
|
||||
|
||||
// The Clock Out singnal is route to the pin by GPIO matrix
|
||||
#define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX (1)
|
||||
|
||||
/*-------------------------- RTCIO CAPS --------------------------------------*/
|
||||
//TODO: [ESP32C61] IDF-9317
|
||||
// #define SOC_RTCIO_PIN_COUNT 8
|
||||
// #define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1 /* This macro indicates that the target has separate RTC IOMUX hardware feature,
|
||||
// * so it supports unique IOMUX configuration (including IE, OE, PU, PD, DRV etc.)
|
||||
// * when the pins are switched to RTC function.
|
||||
// */
|
||||
// #define SOC_RTCIO_HOLD_SUPPORTED 1
|
||||
// #define SOC_RTCIO_WAKE_SUPPORTED 1
|
||||
|
||||
/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
|
||||
#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
|
||||
#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */
|
||||
#define SOC_DEDIC_PERIPH_ALWAYS_ENABLE (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */
|
||||
|
||||
/*-------------------------- I2C CAPS ----------------------------------------*/
|
||||
// ESP32-C61 has 1 I2C
|
||||
#define SOC_I2C_NUM (1U)
|
||||
|
||||
#define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */
|
||||
#define SOC_I2C_CMD_REG_NUM (8) /*!< Number of I2C command registers */
|
||||
#define SOC_I2C_SUPPORT_SLAVE (1)
|
||||
|
||||
#define SOC_I2C_SUPPORT_HW_FSM_RST (1)
|
||||
#define SOC_I2C_SUPPORT_HW_CLR_BUS (1)
|
||||
|
||||
#define SOC_I2C_SUPPORT_XTAL (1)
|
||||
#define SOC_I2C_SUPPORT_RTC (1)
|
||||
#define SOC_I2C_SUPPORT_10BIT_ADDR (1)
|
||||
#define SOC_I2C_SLAVE_SUPPORT_BROADCAST (1)
|
||||
#define SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE (1)
|
||||
#define SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS (1)
|
||||
#define SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH (1)
|
||||
|
||||
/*-------------------------- LP_I2C CAPS -------------------------------------*/
|
||||
// ESP32-C61 has 1 LP_I2C
|
||||
#define SOC_LP_I2C_NUM (1U)
|
||||
|
||||
#define SOC_LP_I2C_FIFO_LEN (16) /*!< LP_I2C hardware FIFO depth */
|
||||
|
||||
/*-------------------------- I2S CAPS ----------------------------------------*/
|
||||
#define SOC_I2S_NUM (1U)
|
||||
#define SOC_I2S_HW_VERSION_2 (1)
|
||||
#define SOC_I2S_SUPPORTS_XTAL (1)
|
||||
#define SOC_I2S_SUPPORTS_PLL_F160M (1)
|
||||
#define SOC_I2S_SUPPORTS_PCM (1)
|
||||
#define SOC_I2S_SUPPORTS_PDM (1)
|
||||
#define SOC_I2S_SUPPORTS_PDM_TX (1)
|
||||
#define SOC_I2S_PDM_MAX_TX_LINES (2)
|
||||
#define SOC_I2S_SUPPORTS_TDM (1)
|
||||
|
||||
/*-------------------------- LEDC CAPS ---------------------------------------*/
|
||||
#define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK (1)
|
||||
#define SOC_LEDC_SUPPORT_XTAL_CLOCK (1)
|
||||
#define SOC_LEDC_CHANNEL_NUM (6)
|
||||
#define SOC_LEDC_TIMER_BIT_WIDTH (20)
|
||||
#define SOC_LEDC_SUPPORT_FADE_STOP (1)
|
||||
#define SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED (1)
|
||||
#define SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX (16)
|
||||
#define SOC_LEDC_FADE_PARAMS_BIT_WIDTH (10)
|
||||
|
||||
/*-------------------------- MMU CAPS ----------------------------------------*/
|
||||
#define SOC_MMU_PAGE_SIZE_CONFIGURABLE (1)
|
||||
#define SOC_MMU_PERIPH_NUM (1U)
|
||||
#define SOC_MMU_LINEAR_ADDRESS_REGION_NUM (1U)
|
||||
#define SOC_MMU_DI_VADDR_SHARED (1) /*!< D/I vaddr are shared */
|
||||
|
||||
/*-------------------------- MPU CAPS ----------------------------------------*/
|
||||
#define SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED 0
|
||||
#define SOC_MPU_MIN_REGION_SIZE 0x20000000U
|
||||
#define SOC_MPU_REGIONS_MAX_NUM 8
|
||||
#define SOC_MPU_REGION_RO_SUPPORTED 0
|
||||
#define SOC_MPU_REGION_WO_SUPPORTED 0
|
||||
|
||||
/*-------------------------- PCNT CAPS ---------------------------------------*/
|
||||
#define SOC_PCNT_GROUPS 1U
|
||||
#define SOC_PCNT_UNITS_PER_GROUP 4
|
||||
#define SOC_PCNT_CHANNELS_PER_UNIT 2
|
||||
#define SOC_PCNT_THRES_POINT_PER_UNIT 2
|
||||
#define SOC_PCNT_SUPPORT_RUNTIME_THRES_UPDATE 1
|
||||
|
||||
/*--------------------------- RMT CAPS ---------------------------------------*/
|
||||
#define SOC_RMT_GROUPS 1U /*!< One RMT group */
|
||||
#define SOC_RMT_TX_CANDIDATES_PER_GROUP 2 /*!< Number of channels that capable of Transmit */
|
||||
#define SOC_RMT_RX_CANDIDATES_PER_GROUP 2 /*!< Number of channels that capable of Receive */
|
||||
#define SOC_RMT_CHANNELS_PER_GROUP 4 /*!< Total 4 channels */
|
||||
#define SOC_RMT_MEM_WORDS_PER_CHANNEL 48 /*!< Each channel owns 48 words memory (1 word = 4 Bytes) */
|
||||
#define SOC_RMT_SUPPORT_RX_PINGPONG 1 /*!< Support Ping-Pong mode on RX path */
|
||||
#define SOC_RMT_SUPPORT_RX_DEMODULATION 1 /*!< Support signal demodulation on RX path (i.e. remove carrier) */
|
||||
#define SOC_RMT_SUPPORT_TX_ASYNC_STOP 1 /*!< Support stop transmission asynchronously */
|
||||
#define SOC_RMT_SUPPORT_TX_LOOP_COUNT 1 /*!< Support transmit specified number of cycles in loop mode */
|
||||
#define SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP 1 /*!< Hardware support of auto-stop in loop mode */
|
||||
#define SOC_RMT_SUPPORT_TX_SYNCHRO 1 /*!< Support coordinate a group of TX channels to start simultaneously */
|
||||
#define SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY 1 /*!< TX carrier can be modulated to data phase only */
|
||||
#define SOC_RMT_SUPPORT_XTAL 1 /*!< Support set XTAL clock as the RMT clock source */
|
||||
#define SOC_RMT_SUPPORT_RC_FAST 1 /*!< Support set RC_FAST as the RMT clock source */
|
||||
|
||||
/*-------------------------- MCPWM CAPS --------------------------------------*/
|
||||
#define SOC_MCPWM_GROUPS (1U) ///< 1 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals)
|
||||
#define SOC_MCPWM_TIMERS_PER_GROUP (3) ///< The number of timers that each group has
|
||||
#define SOC_MCPWM_OPERATORS_PER_GROUP (3) ///< The number of operators that each group has
|
||||
#define SOC_MCPWM_COMPARATORS_PER_OPERATOR (2) ///< The number of comparators that each operator has
|
||||
#define SOC_MCPWM_GENERATORS_PER_OPERATOR (2) ///< The number of generators that each operator has
|
||||
#define SOC_MCPWM_TRIGGERS_PER_OPERATOR (2) ///< The number of triggers that each operator has
|
||||
#define SOC_MCPWM_GPIO_FAULTS_PER_GROUP (3) ///< The number of fault signal detectors that each group has
|
||||
#define SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP (1) ///< The number of capture timers that each group has
|
||||
#define SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER (3) ///< The number of capture channels that each capture timer has
|
||||
#define SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP (3) ///< The number of GPIO synchros that each group has
|
||||
#define SOC_MCPWM_SWSYNC_CAN_PROPAGATE (1) ///< Software sync event can be routed to its output
|
||||
#define SOC_MCPWM_SUPPORT_ETM (1) ///< Support ETM (Event Task Matrix)
|
||||
#define SOC_MCPWM_CAPTURE_CLK_FROM_GROUP (1) ///< Capture timer shares clock with other PWM timers
|
||||
|
||||
/*------------------------ USB SERIAL JTAG CAPS ------------------------------*/
|
||||
// #define SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP (1) /*!< Support to maintain minimum usb communication during light sleep */ // TODO: IDF-6395
|
||||
|
||||
/*-------------------------- PARLIO CAPS --------------------------------------*/
|
||||
#define SOC_PARLIO_GROUPS 1U /*!< Number of parallel IO peripherals */
|
||||
#define SOC_PARLIO_TX_UNITS_PER_GROUP 1U /*!< number of TX units in each group */
|
||||
#define SOC_PARLIO_RX_UNITS_PER_GROUP 1U /*!< number of RX units in each group */
|
||||
#define SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH 16 /*!< Number of data lines of the TX unit */
|
||||
#define SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH 16 /*!< Number of data lines of the RX unit */
|
||||
#define SOC_PARLIO_TX_RX_SHARE_INTERRUPT 1 /*!< TX and RX unit share the same interrupt source number */
|
||||
|
||||
/*--------------------------- MPI CAPS ---------------------------------------*/
|
||||
#define SOC_MPI_MEM_BLOCKS_NUM (4)
|
||||
#define SOC_MPI_OPERATIONS_NUM (3)
|
||||
|
||||
/*--------------------------- RSA CAPS ---------------------------------------*/
|
||||
//TODO: [ESP32C61] IDF-9326
|
||||
#define SOC_RSA_MAX_BIT_LEN (3072)
|
||||
|
||||
// TODO: IDF-5353 (Copy from esp32c3, need check)
|
||||
/*--------------------------- SHA CAPS ---------------------------------------*/
|
||||
|
||||
/* Max amount of bytes in a single DMA operation is 4095,
|
||||
for SHA this means that the biggest safe amount of bytes is
|
||||
31 blocks of 128 bytes = 3968
|
||||
*/
|
||||
#define SOC_SHA_DMA_MAX_BUFFER_SIZE (3968)
|
||||
#define SOC_SHA_SUPPORT_DMA (1)
|
||||
|
||||
/* The SHA engine is able to resume hashing from a user */
|
||||
#define SOC_SHA_SUPPORT_RESUME (1)
|
||||
|
||||
/* Has a centralized DMA, which is shared with all peripherals */
|
||||
#define SOC_SHA_GDMA (1)
|
||||
|
||||
/* Supported HW algorithms */
|
||||
#define SOC_SHA_SUPPORT_SHA1 (1)
|
||||
#define SOC_SHA_SUPPORT_SHA224 (1)
|
||||
#define SOC_SHA_SUPPORT_SHA256 (1)
|
||||
|
||||
/*-------------------------- Sigma Delta Modulator CAPS -----------------*/
|
||||
#define SOC_SDM_GROUPS 1U
|
||||
#define SOC_SDM_CHANNELS_PER_GROUP 4
|
||||
#define SOC_SDM_CLK_SUPPORT_PLL_F80M 1
|
||||
#define SOC_SDM_CLK_SUPPORT_XTAL 1
|
||||
|
||||
/*-------------------------- SPI CAPS ----------------------------------------*/
|
||||
#define SOC_SPI_PERIPH_NUM 2
|
||||
#define SOC_SPI_PERIPH_CS_NUM(i) 6
|
||||
#define SOC_SPI_MAX_CS_NUM 6
|
||||
|
||||
#define SOC_SPI_MAXIMUM_BUFFER_SIZE 64
|
||||
|
||||
#define SOC_SPI_SUPPORT_DDRCLK 1
|
||||
#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1
|
||||
#define SOC_SPI_SUPPORT_CD_SIG 1
|
||||
#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1
|
||||
#define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1
|
||||
#define SOC_SPI_SUPPORT_CLK_XTAL 1
|
||||
#define SOC_SPI_SUPPORT_CLK_PLL_F80M 1
|
||||
#define SOC_SPI_SUPPORT_CLK_RC_FAST 1
|
||||
|
||||
// Peripheral supports DIO, DOUT, QIO, or QOUT
|
||||
// host_id = 0 -> SPI0/SPI1, host_id = 1 -> SPI2,
|
||||
#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;})
|
||||
|
||||
#define SOC_MEMSPI_IS_INDEPENDENT 1
|
||||
#define SOC_SPI_MAX_PRE_DIVIDER 16
|
||||
|
||||
/*-------------------------- SPI MEM CAPS ---------------------------------------*/
|
||||
#define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1)
|
||||
#define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND (1) //TODO: [ESP32C61] IDF-9255
|
||||
#define SOC_SPI_MEM_SUPPORT_AUTO_RESUME (1)
|
||||
#define SOC_SPI_MEM_SUPPORT_IDLE_INTR (1)
|
||||
#define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1)
|
||||
#define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1)
|
||||
#define SOC_SPI_MEM_SUPPORT_WRAP (1)
|
||||
|
||||
#define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1
|
||||
#define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1
|
||||
#define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1
|
||||
|
||||
/*-------------------------- SYSTIMER CAPS ----------------------------------*/
|
||||
#define SOC_SYSTIMER_COUNTER_NUM 2 // Number of counter units
|
||||
#define SOC_SYSTIMER_ALARM_NUM 3 // Number of alarm units
|
||||
#define SOC_SYSTIMER_BIT_WIDTH_LO 32 // Bit width of systimer low part
|
||||
#define SOC_SYSTIMER_BIT_WIDTH_HI 20 // Bit width of systimer high part
|
||||
#define SOC_SYSTIMER_FIXED_DIVIDER 1 // Clock source divider is fixed: 2.5
|
||||
#define SOC_SYSTIMER_SUPPORT_RC_FAST 1 // Systimer can use RC_FAST clock source
|
||||
#define SOC_SYSTIMER_INT_LEVEL 1 // Systimer peripheral uses level interrupt
|
||||
#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE 1 // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
|
||||
#define SOC_SYSTIMER_SUPPORT_ETM 1 // Systimer comparator can generate ETM event
|
||||
|
||||
/*-------------------------- LP_TIMER CAPS ----------------------------------*/
|
||||
#define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part
|
||||
#define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part
|
||||
|
||||
/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
|
||||
#define SOC_TIMER_GROUPS (2)
|
||||
#define SOC_TIMER_GROUP_TIMERS_PER_GROUP (1U)
|
||||
#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54)
|
||||
#define SOC_TIMER_GROUP_SUPPORT_XTAL (1)
|
||||
#define SOC_TIMER_GROUP_SUPPORT_RC_FAST (1)
|
||||
#define SOC_TIMER_GROUP_TOTAL_TIMERS (2)
|
||||
#define SOC_TIMER_SUPPORT_ETM (1)
|
||||
|
||||
/*--------------------------- WATCHDOG CAPS ---------------------------------------*/
|
||||
#define SOC_MWDT_SUPPORT_XTAL (1)
|
||||
|
||||
/*-------------------------- TWAI CAPS ---------------------------------------*/
|
||||
#define SOC_TWAI_CONTROLLER_NUM 2
|
||||
#define SOC_TWAI_CLK_SUPPORT_XTAL 1
|
||||
#define SOC_TWAI_BRP_MIN 2
|
||||
#define SOC_TWAI_BRP_MAX 32768
|
||||
#define SOC_TWAI_SUPPORTS_RX_STATUS 1
|
||||
|
||||
|
||||
/*-------------------------- eFuse CAPS----------------------------*/
|
||||
#define SOC_EFUSE_DIS_DOWNLOAD_ICACHE 1
|
||||
#define SOC_EFUSE_DIS_PAD_JTAG 1
|
||||
#define SOC_EFUSE_DIS_USB_JTAG 1
|
||||
#define SOC_EFUSE_DIS_DIRECT_BOOT 1
|
||||
#define SOC_EFUSE_SOFT_DIS_JTAG 1
|
||||
#define SOC_EFUSE_DIS_ICACHE 1
|
||||
#define SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK 1 // XTS-AES key purpose not supported for this block
|
||||
|
||||
/*-------------------------- Secure Boot CAPS----------------------------*/
|
||||
#define SOC_SECURE_BOOT_V2_RSA 0
|
||||
#define SOC_SECURE_BOOT_V2_ECC 1
|
||||
#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3
|
||||
#define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1
|
||||
#define SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY 1
|
||||
|
||||
/*-------------------------- Flash Encryption CAPS----------------------------*/
|
||||
#define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX (64)
|
||||
#define SOC_FLASH_ENCRYPTION_XTS_AES 1
|
||||
#define SOC_FLASH_ENCRYPTION_XTS_AES_128 1
|
||||
|
||||
/*------------------------ Anti DPA (Security) CAPS --------------------------*/
|
||||
#define SOC_CRYPTO_DPA_PROTECTION_SUPPORTED 1
|
||||
|
||||
/*-------------------------- UART CAPS ---------------------------------------*/
|
||||
// ESP32-C61 has 3 UARTs (2 HP UART, and 1 LP UART)
|
||||
#define SOC_UART_NUM (3)
|
||||
#define SOC_UART_HP_NUM (2)
|
||||
#define SOC_UART_LP_NUM (1U)
|
||||
#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */
|
||||
#define SOC_LP_UART_FIFO_LEN (16) /*!< The LP UART hardware FIFO length */
|
||||
#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */
|
||||
#define SOC_UART_SUPPORT_PLL_F80M_CLK (1) /*!< Support PLL_F80M as the clock source */
|
||||
#define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */
|
||||
#define SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */
|
||||
#define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */
|
||||
|
||||
// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
|
||||
#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1)
|
||||
|
||||
// TODO: IDF-5679 (Copy from esp32c3, need check)
|
||||
/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/
|
||||
#define SOC_COEX_HW_PTI (1)
|
||||
|
||||
/*-------------------------- EXTERNAL COEXISTENCE CAPS -------------------------------------*/
|
||||
#define SOC_EXTERNAL_COEX_ADVANCE (1) /*!< HARDWARE ADVANCED EXTERNAL COEXISTENCE CAPS */
|
||||
#define SOC_EXTERNAL_COEX_LEADER_TX_LINE (0) /*!< EXTERNAL COEXISTENCE TX LINE CAPS */
|
||||
|
||||
/*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/
|
||||
#define SOC_PHY_DIG_REGS_MEM_SIZE (21*4)
|
||||
|
||||
// TODO: IDF-5679 (Copy from esp32c3, need check)
|
||||
/*--------------- WIFI LIGHT SLEEP CLOCK WIDTH CAPS --------------------------*/
|
||||
#define SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH (12)
|
||||
|
||||
// TODO: IDF-5351 (Copy from esp32c3, need check)
|
||||
/*-------------------------- Power Management CAPS ----------------------------*/
|
||||
#define SOC_PM_SUPPORT_WIFI_WAKEUP (1)
|
||||
#define SOC_PM_SUPPORT_BEACON_WAKEUP (1)
|
||||
#define SOC_PM_SUPPORT_BT_WAKEUP (1)
|
||||
#define SOC_PM_SUPPORT_EXT1_WAKEUP (1)
|
||||
#define SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN (1) /*!<Supports one bit per pin to configue the EXT1 trigger level */
|
||||
// #define SOC_PM_SUPPORT_CPU_PD (1)
|
||||
#define SOC_PM_SUPPORT_MODEM_PD (1)
|
||||
#define SOC_PM_SUPPORT_XTAL32K_PD (1)
|
||||
#define SOC_PM_SUPPORT_RC32K_PD (1)
|
||||
#define SOC_PM_SUPPORT_RC_FAST_PD (1)
|
||||
#define SOC_PM_SUPPORT_VDDSDIO_PD (1)
|
||||
// #define SOC_PM_SUPPORT_TOP_PD (1)
|
||||
#define SOC_PM_SUPPORT_HP_AON_PD (1)
|
||||
#define SOC_PM_SUPPORT_MAC_BB_PD (1)
|
||||
#define SOC_PM_SUPPORT_RTC_PERIPH_PD (1)
|
||||
|
||||
#define SOC_PM_SUPPORT_PMU_MODEM_STATE (0)
|
||||
/* macro redefine for pass esp_wifi headers md5sum check */
|
||||
#define MAC_SUPPORT_PMU_MODEM_STATE SOC_PM_SUPPORT_PMU_MODEM_STATE
|
||||
|
||||
|
||||
#define SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY (1) /*!<Supports CRC only the stub code in RTC memory */
|
||||
|
||||
// #define SOC_PM_CPU_RETENTION_BY_SW (1)
|
||||
#define SOC_PM_MODEM_RETENTION_BY_REGDMA (0)
|
||||
#define SOC_PM_RETENTION_HAS_CLOCK_BUG (1)
|
||||
|
||||
#define SOC_PM_PAU_LINK_NUM (4)
|
||||
|
||||
/*-------------------------- CLOCK SUBSYSTEM CAPS ----------------------------------------*/
|
||||
#define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION (1)
|
||||
#define SOC_MODEM_CLOCK_IS_INDEPENDENT (1)
|
||||
|
||||
#define SOC_CLK_XTAL32K_SUPPORTED (1) /*!< Support to connect an external low frequency crystal */
|
||||
#define SOC_CLK_OSC_SLOW_SUPPORTED (1) /*!< Support to connect an external oscillator, not a crystal */
|
||||
#define SOC_CLK_RC32K_SUPPORTED (1) /*!< Support an internal 32kHz RC oscillator */
|
||||
|
||||
#define SOC_RCC_IS_INDEPENDENT 1 /*!< Reset and Clock Control is independent, thanks to the PCR registers */
|
||||
|
||||
/*-------------------------- Temperature Sensor CAPS -------------------------------------*/
|
||||
#define SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC (1)
|
||||
#define SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL (1)
|
||||
#define SOC_TEMPERATURE_SENSOR_INTR_SUPPORT (1)
|
||||
|
||||
/*------------------------------------ WI-FI CAPS ------------------------------------*/
|
||||
#define SOC_WIFI_HW_TSF (1) /*!< Support hardware TSF */
|
||||
#define SOC_WIFI_FTM_SUPPORT (0) /*!< Support FTM */
|
||||
#define SOC_WIFI_GCMP_SUPPORT (1) /*!< Support GCMP(GCMP128 and GCMP256) */
|
||||
#define SOC_WIFI_WAPI_SUPPORT (1) /*!< Support WAPI */
|
||||
#define SOC_WIFI_CSI_SUPPORT (1) /*!< Support CSI */
|
||||
#define SOC_WIFI_MESH_SUPPORT (1) /*!< Support WIFI MESH */
|
||||
#define SOC_WIFI_HE_SUPPORT (1) /*!< Support Wi-Fi 6 */
|
||||
|
||||
/*---------------------------------- Bluetooth CAPS ----------------------------------*/
|
||||
// #define SOC_BLE_SUPPORTED (1) /*!< Support Bluetooth Low Energy hardware */
|
||||
// #define SOC_BLE_MESH_SUPPORTED (1) /*!< Support BLE MESH */
|
||||
// #define SOC_ESP_NIMBLE_CONTROLLER (1) /*!< Support BLE EMBEDDED controller V1 */
|
||||
// #define SOC_BLE_50_SUPPORTED (1) /*!< Support Bluetooth 5.0 */
|
||||
// #define SOC_BLE_DEVICE_PRIVACY_SUPPORTED (1) /*!< Support BLE device privacy mode */
|
||||
// #define SOC_BLE_POWER_CONTROL_SUPPORTED (1) /*!< Support Bluetooth Power Control */
|
||||
// #define SOC_BLE_PERIODIC_ADV_ENH_SUPPORTED (1) /*!< Support For BLE Periodic Adv Enhancements */
|
||||
// #define SOC_BLUFI_SUPPORTED (1) /*!< Support BLUFI */
|
||||
// #define SOC_BLE_MULTI_CONN_OPTIMIZATION (1) /*!< Support multiple connections optimization */
|
||||
|
||||
// #define SOC_BLE_USE_WIFI_PWR_CLK_WORKAROUND (1)
|
||||
|
||||
/*------------------------------------- PHY CAPS -------------------------------------*/
|
||||
#define SOC_PHY_COMBO_MODULE (1) /*!< Support Wi-Fi, BLE and 15.4*/
|
||||
|
||||
/*------------------------------------- No Reset CAPS -------------------------------------*/
|
||||
#define SOC_CAPS_NO_RESET_BY_ANA_BOD (1)
|
||||
Plik diff jest za duży
Load Diff
Plik diff jest za duży
Load Diff
|
|
@ -0,0 +1,26 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _SOC_SPI_PINS_H_
|
||||
#define _SOC_SPI_PINS_H_
|
||||
|
||||
#define SPI_FUNC_NUM 0
|
||||
#define SPI_IOMUX_PIN_NUM_CS 24
|
||||
#define SPI_IOMUX_PIN_NUM_CLK 29
|
||||
#define SPI_IOMUX_PIN_NUM_MOSI 30
|
||||
#define SPI_IOMUX_PIN_NUM_MISO 25
|
||||
#define SPI_IOMUX_PIN_NUM_WP 26
|
||||
#define SPI_IOMUX_PIN_NUM_HD 28
|
||||
|
||||
#define SPI2_FUNC_NUM 2
|
||||
#define SPI2_IOMUX_PIN_NUM_MISO 2
|
||||
#define SPI2_IOMUX_PIN_NUM_HD 4
|
||||
#define SPI2_IOMUX_PIN_NUM_WP 5
|
||||
#define SPI2_IOMUX_PIN_NUM_CLK 6
|
||||
#define SPI2_IOMUX_PIN_NUM_MOSI 7
|
||||
#define SPI2_IOMUX_PIN_NUM_CS 16
|
||||
|
||||
#endif
|
||||
|
|
@ -1084,90 +1084,90 @@ typedef union {
|
|||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** dma_infifo_full_err_int_ena : R/W; bitpos: [0]; default: 0;
|
||||
/** dma_infifo_full_err : R/W; bitpos: [0]; default: 0;
|
||||
* Write 1 to enable SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
|
||||
*/
|
||||
uint32_t dma_infifo_full_err_int_ena:1;
|
||||
/** dma_outfifo_empty_err_int_ena : R/W; bitpos: [1]; default: 0;
|
||||
uint32_t dma_infifo_full_err:1;
|
||||
/** dma_outfifo_empty_err : R/W; bitpos: [1]; default: 0;
|
||||
* Write 1 to enable SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
|
||||
*/
|
||||
uint32_t dma_outfifo_empty_err_int_ena:1;
|
||||
/** slv_ex_qpi_int_ena : R/W; bitpos: [2]; default: 0;
|
||||
uint32_t dma_outfifo_empty_err:1;
|
||||
/** slv_ex_qpi : R/W; bitpos: [2]; default: 0;
|
||||
* Write 1 to enable SPI_SLV_EX_QPI_INT interrupt.
|
||||
*/
|
||||
uint32_t slv_ex_qpi_int_ena:1;
|
||||
/** slv_en_qpi_int_ena : R/W; bitpos: [3]; default: 0;
|
||||
uint32_t slv_ex_qpi:1;
|
||||
/** slv_en_qpi : R/W; bitpos: [3]; default: 0;
|
||||
* Write 1 to enable SPI_SLV_EN_QPI_INT interrupt.
|
||||
*/
|
||||
uint32_t slv_en_qpi_int_ena:1;
|
||||
/** slv_cmd7_int_ena : R/W; bitpos: [4]; default: 0;
|
||||
uint32_t slv_en_qpi:1;
|
||||
/** slv_cmd7 : R/W; bitpos: [4]; default: 0;
|
||||
* Write 1 to enable SPI_SLV_CMD7_INT interrupt.
|
||||
*/
|
||||
uint32_t slv_cmd7_int_ena:1;
|
||||
/** slv_cmd8_int_ena : R/W; bitpos: [5]; default: 0;
|
||||
uint32_t slv_cmd7:1;
|
||||
/** slv_cmd8 : R/W; bitpos: [5]; default: 0;
|
||||
* Write 1 to enable SPI_SLV_CMD8_INT interrupt.
|
||||
*/
|
||||
uint32_t slv_cmd8_int_ena:1;
|
||||
/** slv_cmd9_int_ena : R/W; bitpos: [6]; default: 0;
|
||||
uint32_t slv_cmd8:1;
|
||||
/** slv_cmd9 : R/W; bitpos: [6]; default: 0;
|
||||
* Write 1 to enable SPI_SLV_CMD9_INT interrupt.
|
||||
*/
|
||||
uint32_t slv_cmd9_int_ena:1;
|
||||
/** slv_cmda_int_ena : R/W; bitpos: [7]; default: 0;
|
||||
uint32_t slv_cmd9:1;
|
||||
/** slv_cmda : R/W; bitpos: [7]; default: 0;
|
||||
* Write 1 to enable SPI_SLV_CMDA_INT interrupt.
|
||||
*/
|
||||
uint32_t slv_cmda_int_ena:1;
|
||||
/** slv_rd_dma_done_int_ena : R/W; bitpos: [8]; default: 0;
|
||||
uint32_t slv_cmda:1;
|
||||
/** slv_rd_dma_done : R/W; bitpos: [8]; default: 0;
|
||||
* Write 1 to enable SPI_SLV_RD_DMA_DONE_INT interrupt.
|
||||
*/
|
||||
uint32_t slv_rd_dma_done_int_ena:1;
|
||||
/** slv_wr_dma_done_int_ena : R/W; bitpos: [9]; default: 0;
|
||||
uint32_t slv_rd_dma_done:1;
|
||||
/** slv_wr_dma_done : R/W; bitpos: [9]; default: 0;
|
||||
* Write 1 to enable SPI_SLV_WR_DMA_DONE_INT interrupt.
|
||||
*/
|
||||
uint32_t slv_wr_dma_done_int_ena:1;
|
||||
/** slv_rd_buf_done_int_ena : R/W; bitpos: [10]; default: 0;
|
||||
uint32_t slv_wr_dma_done:1;
|
||||
/** slv_rd_buf_done : R/W; bitpos: [10]; default: 0;
|
||||
* Write 1 to enable SPI_SLV_RD_BUF_DONE_INT interrupt.
|
||||
*/
|
||||
uint32_t slv_rd_buf_done_int_ena:1;
|
||||
/** slv_wr_buf_done_int_ena : R/W; bitpos: [11]; default: 0;
|
||||
uint32_t slv_rd_buf_done:1;
|
||||
/** slv_wr_buf_done : R/W; bitpos: [11]; default: 0;
|
||||
* Write 1 to enable SPI_SLV_WR_BUF_DONE_INT interrupt.
|
||||
*/
|
||||
uint32_t slv_wr_buf_done_int_ena:1;
|
||||
/** trans_done_int_ena : R/W; bitpos: [12]; default: 0;
|
||||
uint32_t slv_wr_buf_done:1;
|
||||
/** trans_done : R/W; bitpos: [12]; default: 0;
|
||||
* Write 1 to enable SPI_TRANS_DONE_INT interrupt.
|
||||
*/
|
||||
uint32_t trans_done_int_ena:1;
|
||||
/** dma_seg_trans_done_int_ena : R/W; bitpos: [13]; default: 0;
|
||||
uint32_t trans_done:1;
|
||||
/** dma_seg_trans_done : R/W; bitpos: [13]; default: 0;
|
||||
* Write 1 to enable SPI_DMA_SEG_TRANS_DONE_INT interrupt.
|
||||
*/
|
||||
uint32_t dma_seg_trans_done_int_ena:1;
|
||||
/** seg_magic_err_int_ena : R/W; bitpos: [14]; default: 0;
|
||||
uint32_t dma_seg_trans_done:1;
|
||||
/** seg_magic_err : R/W; bitpos: [14]; default: 0;
|
||||
* Write 1 to enable SPI_SEG_MAGIC_ERR_INT interrupt.
|
||||
*/
|
||||
uint32_t seg_magic_err_int_ena:1;
|
||||
/** slv_buf_addr_err_int_ena : R/W; bitpos: [15]; default: 0;
|
||||
uint32_t seg_magic_err:1;
|
||||
/** slv_buf_addr_err : R/W; bitpos: [15]; default: 0;
|
||||
* The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
|
||||
*/
|
||||
uint32_t slv_buf_addr_err_int_ena:1;
|
||||
/** slv_cmd_err_int_ena : R/W; bitpos: [16]; default: 0;
|
||||
uint32_t slv_buf_addr_err:1;
|
||||
/** slv_cmd_err : R/W; bitpos: [16]; default: 0;
|
||||
* Write 1 to enable SPI_SLV_CMD_ERR_INT interrupt.
|
||||
*/
|
||||
uint32_t slv_cmd_err_int_ena:1;
|
||||
/** mst_rx_afifo_wfull_err_int_ena : R/W; bitpos: [17]; default: 0;
|
||||
uint32_t slv_cmd_err:1;
|
||||
/** mst_rx_afifo_wfull_err : R/W; bitpos: [17]; default: 0;
|
||||
* Write 1 to enable SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
|
||||
*/
|
||||
uint32_t mst_rx_afifo_wfull_err_int_ena:1;
|
||||
/** mst_tx_afifo_rempty_err_int_ena : R/W; bitpos: [18]; default: 0;
|
||||
uint32_t mst_rx_afifo_wfull_err:1;
|
||||
/** mst_tx_afifo_rempty_err : R/W; bitpos: [18]; default: 0;
|
||||
* Write 1 to enable SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
|
||||
*/
|
||||
uint32_t mst_tx_afifo_rempty_err_int_ena:1;
|
||||
/** app2_int_ena : R/W; bitpos: [19]; default: 0;
|
||||
uint32_t mst_tx_afifo_rempty_err:1;
|
||||
/** app2 : R/W; bitpos: [19]; default: 0;
|
||||
* Write 1 to enable SPI_APP2_INT interrupt.
|
||||
*/
|
||||
uint32_t app2_int_ena:1;
|
||||
/** app1_int_ena : R/W; bitpos: [20]; default: 0;
|
||||
uint32_t app2:1;
|
||||
/** app1 : R/W; bitpos: [20]; default: 0;
|
||||
* Write 1 to enable SPI_APP1_INT interrupt.
|
||||
*/
|
||||
uint32_t app1_int_ena:1;
|
||||
uint32_t app1:1;
|
||||
uint32_t reserved_21:11;
|
||||
};
|
||||
uint32_t val;
|
||||
|
|
@ -1178,90 +1178,90 @@ typedef union {
|
|||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** dma_infifo_full_err_int_clr : WT; bitpos: [0]; default: 0;
|
||||
/** dma_infifo_full_err : WT; bitpos: [0]; default: 0;
|
||||
* Write 1 to clear SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
|
||||
*/
|
||||
uint32_t dma_infifo_full_err_int_clr:1;
|
||||
/** dma_outfifo_empty_err_int_clr : WT; bitpos: [1]; default: 0;
|
||||
uint32_t dma_infifo_full_err:1;
|
||||
/** dma_outfifo_empty_err : WT; bitpos: [1]; default: 0;
|
||||
* Write 1 to clear SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
|
||||
*/
|
||||
uint32_t dma_outfifo_empty_err_int_clr:1;
|
||||
/** slv_ex_qpi_int_clr : WT; bitpos: [2]; default: 0;
|
||||
uint32_t dma_outfifo_empty_err:1;
|
||||
/** slv_ex_qpi : WT; bitpos: [2]; default: 0;
|
||||
* Write 1 to clear SPI_SLV_EX_QPI_INT interrupt.
|
||||
*/
|
||||
uint32_t slv_ex_qpi_int_clr:1;
|
||||
/** slv_en_qpi_int_clr : WT; bitpos: [3]; default: 0;
|
||||
uint32_t slv_ex_qpi:1;
|
||||
/** slv_en_qpi : WT; bitpos: [3]; default: 0;
|
||||
* Write 1 to clear SPI_SLV_EN_QPI_INT interrupt.
|
||||
*/
|
||||
uint32_t slv_en_qpi_int_clr:1;
|
||||
/** slv_cmd7_int_clr : WT; bitpos: [4]; default: 0;
|
||||
uint32_t slv_en_qpi:1;
|
||||
/** slv_cmd7 : WT; bitpos: [4]; default: 0;
|
||||
* Write 1 to clear SPI_SLV_CMD7_INT interrupt.
|
||||
*/
|
||||
uint32_t slv_cmd7_int_clr:1;
|
||||
/** slv_cmd8_int_clr : WT; bitpos: [5]; default: 0;
|
||||
uint32_t slv_cmd7:1;
|
||||
/** slv_cmd8 : WT; bitpos: [5]; default: 0;
|
||||
* Write 1 to clear SPI_SLV_CMD8_INT interrupt.
|
||||
*/
|
||||
uint32_t slv_cmd8_int_clr:1;
|
||||
/** slv_cmd9_int_clr : WT; bitpos: [6]; default: 0;
|
||||
uint32_t slv_cmd8:1;
|
||||
/** slv_cmd9 : WT; bitpos: [6]; default: 0;
|
||||
* Write 1 to clear SPI_SLV_CMD9_INT interrupt.
|
||||
*/
|
||||
uint32_t slv_cmd9_int_clr:1;
|
||||
/** slv_cmda_int_clr : WT; bitpos: [7]; default: 0;
|
||||
uint32_t slv_cmd9:1;
|
||||
/** slv_cmda : WT; bitpos: [7]; default: 0;
|
||||
* Write 1 to clear SPI_SLV_CMDA_INT interrupt.
|
||||
*/
|
||||
uint32_t slv_cmda_int_clr:1;
|
||||
/** slv_rd_dma_done_int_clr : WT; bitpos: [8]; default: 0;
|
||||
uint32_t slv_cmda:1;
|
||||
/** slv_rd_dma_done : WT; bitpos: [8]; default: 0;
|
||||
* Write 1 to clear SPI_SLV_RD_DMA_DONE_INT interrupt.
|
||||
*/
|
||||
uint32_t slv_rd_dma_done_int_clr:1;
|
||||
/** slv_wr_dma_done_int_clr : WT; bitpos: [9]; default: 0;
|
||||
uint32_t slv_rd_dma_done:1;
|
||||
/** slv_wr_dma_done : WT; bitpos: [9]; default: 0;
|
||||
* Write 1 to clear SPI_SLV_WR_DMA_DONE_INT interrupt.
|
||||
*/
|
||||
uint32_t slv_wr_dma_done_int_clr:1;
|
||||
/** slv_rd_buf_done_int_clr : WT; bitpos: [10]; default: 0;
|
||||
uint32_t slv_wr_dma_done:1;
|
||||
/** slv_rd_buf_done : WT; bitpos: [10]; default: 0;
|
||||
* Write 1 to clear SPI_SLV_RD_BUF_DONE_INT interrupt.
|
||||
*/
|
||||
uint32_t slv_rd_buf_done_int_clr:1;
|
||||
/** slv_wr_buf_done_int_clr : WT; bitpos: [11]; default: 0;
|
||||
uint32_t slv_rd_buf_done:1;
|
||||
/** slv_wr_buf_done : WT; bitpos: [11]; default: 0;
|
||||
* Write 1 to clear SPI_SLV_WR_BUF_DONE_INT interrupt.
|
||||
*/
|
||||
uint32_t slv_wr_buf_done_int_clr:1;
|
||||
/** trans_done_int_clr : WT; bitpos: [12]; default: 0;
|
||||
uint32_t slv_wr_buf_done:1;
|
||||
/** trans_done : WT; bitpos: [12]; default: 0;
|
||||
* Write 1 to clear SPI_TRANS_DONE_INT interrupt.
|
||||
*/
|
||||
uint32_t trans_done_int_clr:1;
|
||||
/** dma_seg_trans_done_int_clr : WT; bitpos: [13]; default: 0;
|
||||
uint32_t trans_done:1;
|
||||
/** dma_seg_trans_done : WT; bitpos: [13]; default: 0;
|
||||
* Write 1 to clear SPI_DMA_SEG_TRANS_DONE_INT interrupt.
|
||||
*/
|
||||
uint32_t dma_seg_trans_done_int_clr:1;
|
||||
/** seg_magic_err_int_clr : WT; bitpos: [14]; default: 0;
|
||||
uint32_t dma_seg_trans_done:1;
|
||||
/** seg_magic_err : WT; bitpos: [14]; default: 0;
|
||||
* Write 1 to clear SPI_SEG_MAGIC_ERR_INT interrupt.
|
||||
*/
|
||||
uint32_t seg_magic_err_int_clr:1;
|
||||
/** slv_buf_addr_err_int_clr : WT; bitpos: [15]; default: 0;
|
||||
uint32_t seg_magic_err:1;
|
||||
/** slv_buf_addr_err : WT; bitpos: [15]; default: 0;
|
||||
* The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
|
||||
*/
|
||||
uint32_t slv_buf_addr_err_int_clr:1;
|
||||
/** slv_cmd_err_int_clr : WT; bitpos: [16]; default: 0;
|
||||
uint32_t slv_buf_addr_err:1;
|
||||
/** slv_cmd_err : WT; bitpos: [16]; default: 0;
|
||||
* Write 1 to clear SPI_SLV_CMD_ERR_INT interrupt.
|
||||
*/
|
||||
uint32_t slv_cmd_err_int_clr:1;
|
||||
/** mst_rx_afifo_wfull_err_int_clr : WT; bitpos: [17]; default: 0;
|
||||
uint32_t slv_cmd_err:1;
|
||||
/** mst_rx_afifo_wfull_err : WT; bitpos: [17]; default: 0;
|
||||
* Write 1 to clear SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
|
||||
*/
|
||||
uint32_t mst_rx_afifo_wfull_err_int_clr:1;
|
||||
/** mst_tx_afifo_rempty_err_int_clr : WT; bitpos: [18]; default: 0;
|
||||
uint32_t mst_rx_afifo_wfull_err:1;
|
||||
/** mst_tx_afifo_rempty_err : WT; bitpos: [18]; default: 0;
|
||||
* Write 1 to clear SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
|
||||
*/
|
||||
uint32_t mst_tx_afifo_rempty_err_int_clr:1;
|
||||
/** app2_int_clr : WT; bitpos: [19]; default: 0;
|
||||
uint32_t mst_tx_afifo_rempty_err:1;
|
||||
/** app2 : WT; bitpos: [19]; default: 0;
|
||||
* Write 1 to clear SPI_APP2_INT interrupt.
|
||||
*/
|
||||
uint32_t app2_int_clr:1;
|
||||
/** app1_int_clr : WT; bitpos: [20]; default: 0;
|
||||
uint32_t app2:1;
|
||||
/** app1 : WT; bitpos: [20]; default: 0;
|
||||
* Write 1 to clear SPI_APP1_INT interrupt.
|
||||
*/
|
||||
uint32_t app1_int_clr:1;
|
||||
uint32_t app1:1;
|
||||
uint32_t reserved_21:11;
|
||||
};
|
||||
uint32_t val;
|
||||
|
|
@ -1272,94 +1272,94 @@ typedef union {
|
|||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** dma_infifo_full_err_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
|
||||
/** dma_infifo_full_err : R/WTC/SS; bitpos: [0]; default: 0;
|
||||
* The raw interrupt status of SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
|
||||
*/
|
||||
uint32_t dma_infifo_full_err_int_raw:1;
|
||||
/** dma_outfifo_empty_err_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
|
||||
uint32_t dma_infifo_full_err:1;
|
||||
/** dma_outfifo_empty_err : R/WTC/SS; bitpos: [1]; default: 0;
|
||||
* The raw interrupt status of SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
|
||||
*/
|
||||
uint32_t dma_outfifo_empty_err_int_raw:1;
|
||||
/** slv_ex_qpi_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
|
||||
uint32_t dma_outfifo_empty_err:1;
|
||||
/** slv_ex_qpi : R/WTC/SS; bitpos: [2]; default: 0;
|
||||
* The raw interrupt status of SPI_SLV_EX_QPI_INT interrupt.
|
||||
*/
|
||||
uint32_t slv_ex_qpi_int_raw:1;
|
||||
/** slv_en_qpi_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
|
||||
uint32_t slv_ex_qpi:1;
|
||||
/** slv_en_qpi : R/WTC/SS; bitpos: [3]; default: 0;
|
||||
* The raw interrupt status of SPI_SLV_EN_QPI_INT interrupt.
|
||||
*/
|
||||
uint32_t slv_en_qpi_int_raw:1;
|
||||
/** slv_cmd7_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
|
||||
uint32_t slv_en_qpi:1;
|
||||
/** slv_cmd7 : R/WTC/SS; bitpos: [4]; default: 0;
|
||||
* The raw interrupt status of SPI_SLV_CMD7_INT interrupt.
|
||||
*/
|
||||
uint32_t slv_cmd7_int_raw:1;
|
||||
/** slv_cmd8_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
|
||||
uint32_t slv_cmd7:1;
|
||||
/** slv_cmd8 : R/WTC/SS; bitpos: [5]; default: 0;
|
||||
* The raw interrupt status of SPI_SLV_CMD8_INT interrupt.
|
||||
*/
|
||||
uint32_t slv_cmd8_int_raw:1;
|
||||
/** slv_cmd9_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
|
||||
uint32_t slv_cmd8:1;
|
||||
/** slv_cmd9 : R/WTC/SS; bitpos: [6]; default: 0;
|
||||
* The raw interrupt status of SPI_SLV_CMD9_INT interrupt.
|
||||
*/
|
||||
uint32_t slv_cmd9_int_raw:1;
|
||||
/** slv_cmda_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
|
||||
uint32_t slv_cmd9:1;
|
||||
/** slv_cmda : R/WTC/SS; bitpos: [7]; default: 0;
|
||||
* The raw interrupt status of SPI_SLV_CMDA_INT interrupt.
|
||||
*/
|
||||
uint32_t slv_cmda_int_raw:1;
|
||||
/** slv_rd_dma_done_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
|
||||
uint32_t slv_cmda:1;
|
||||
/** slv_rd_dma_done : R/WTC/SS; bitpos: [8]; default: 0;
|
||||
* The raw interrupt status of SPI_SLV_RD_DMA_DONE_INT interrupt.
|
||||
*/
|
||||
uint32_t slv_rd_dma_done_int_raw:1;
|
||||
/** slv_wr_dma_done_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
|
||||
uint32_t slv_rd_dma_done:1;
|
||||
/** slv_wr_dma_done : R/WTC/SS; bitpos: [9]; default: 0;
|
||||
* The raw interrupt status of SPI_SLV_WR_DMA_DONE_INT interrupt.
|
||||
*/
|
||||
uint32_t slv_wr_dma_done_int_raw:1;
|
||||
/** slv_rd_buf_done_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
|
||||
uint32_t slv_wr_dma_done:1;
|
||||
/** slv_rd_buf_done : R/WTC/SS; bitpos: [10]; default: 0;
|
||||
* The raw interrupt status of SPI_SLV_RD_BUF_DONE_INT interrupt.
|
||||
*/
|
||||
uint32_t slv_rd_buf_done_int_raw:1;
|
||||
/** slv_wr_buf_done_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
|
||||
uint32_t slv_rd_buf_done:1;
|
||||
/** slv_wr_buf_done : R/WTC/SS; bitpos: [11]; default: 0;
|
||||
* The raw interrupt status of SPI_SLV_WR_BUF_DONE_INT interrupt.
|
||||
*/
|
||||
uint32_t slv_wr_buf_done_int_raw:1;
|
||||
/** trans_done_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
|
||||
uint32_t slv_wr_buf_done:1;
|
||||
/** trans_done : R/WTC/SS; bitpos: [12]; default: 0;
|
||||
* The raw interrupt status of SPI_TRANS_DONE_INT interrupt.
|
||||
*/
|
||||
uint32_t trans_done_int_raw:1;
|
||||
/** dma_seg_trans_done_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
|
||||
uint32_t trans_done:1;
|
||||
/** dma_seg_trans_done : R/WTC/SS; bitpos: [13]; default: 0;
|
||||
* The raw interrupt status of SPI_DMA_SEG_TRANS_DONE_INT interrupt.
|
||||
*/
|
||||
uint32_t dma_seg_trans_done_int_raw:1;
|
||||
/** seg_magic_err_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
|
||||
uint32_t dma_seg_trans_done:1;
|
||||
/** seg_magic_err : R/WTC/SS; bitpos: [14]; default: 0;
|
||||
* The raw interrupt status of SPI_SEG_MAGIC_ERR_INT interrupt.
|
||||
*/
|
||||
uint32_t seg_magic_err_int_raw:1;
|
||||
/** slv_buf_addr_err_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
|
||||
uint32_t seg_magic_err:1;
|
||||
/** slv_buf_addr_err : R/WTC/SS; bitpos: [15]; default: 0;
|
||||
* The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address
|
||||
* of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is
|
||||
* bigger than 63. 0: Others.
|
||||
*/
|
||||
uint32_t slv_buf_addr_err_int_raw:1;
|
||||
/** slv_cmd_err_int_raw : R/WTC/SS; bitpos: [16]; default: 0;
|
||||
uint32_t slv_buf_addr_err:1;
|
||||
/** slv_cmd_err : R/WTC/SS; bitpos: [16]; default: 0;
|
||||
* The raw interrupt status of SPI_SLV_CMD_ERR_INT interrupt.
|
||||
*/
|
||||
uint32_t slv_cmd_err_int_raw:1;
|
||||
/** mst_rx_afifo_wfull_err_int_raw : R/WTC/SS; bitpos: [17]; default: 0;
|
||||
uint32_t slv_cmd_err:1;
|
||||
/** mst_rx_afifo_wfull_err : R/WTC/SS; bitpos: [17]; default: 0;
|
||||
* The raw interrupt status of SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
|
||||
*/
|
||||
uint32_t mst_rx_afifo_wfull_err_int_raw:1;
|
||||
/** mst_tx_afifo_rempty_err_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
|
||||
uint32_t mst_rx_afifo_wfull_err:1;
|
||||
/** mst_tx_afifo_rempty_err : R/WTC/SS; bitpos: [18]; default: 0;
|
||||
* The raw interrupt status of SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
|
||||
*/
|
||||
uint32_t mst_tx_afifo_rempty_err_int_raw:1;
|
||||
/** app2_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
|
||||
uint32_t mst_tx_afifo_rempty_err:1;
|
||||
/** app2 : R/WTC/SS; bitpos: [19]; default: 0;
|
||||
* The raw interrupt status of SPI_APP2_INT interrupt. The value is only controlled by
|
||||
* the application.
|
||||
*/
|
||||
uint32_t app2_int_raw:1;
|
||||
/** app1_int_raw : R/WTC/SS; bitpos: [20]; default: 0;
|
||||
uint32_t app2:1;
|
||||
/** app1 : R/WTC/SS; bitpos: [20]; default: 0;
|
||||
* The raw interrupt status of SPI_APP1_INT interrupt. The value is only controlled by
|
||||
* the application.
|
||||
*/
|
||||
uint32_t app1_int_raw:1;
|
||||
uint32_t app1:1;
|
||||
uint32_t reserved_21:11;
|
||||
};
|
||||
uint32_t val;
|
||||
|
|
@ -1370,90 +1370,90 @@ typedef union {
|
|||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** dma_infifo_full_err_int_st : RO; bitpos: [0]; default: 0;
|
||||
/** dma_infifo_full_err : RO; bitpos: [0]; default: 0;
|
||||
* The interrupt status of SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
|
||||
*/
|
||||
uint32_t dma_infifo_full_err_int_st:1;
|
||||
/** dma_outfifo_empty_err_int_st : RO; bitpos: [1]; default: 0;
|
||||
uint32_t dma_infifo_full_err:1;
|
||||
/** dma_outfifo_empty_err : RO; bitpos: [1]; default: 0;
|
||||
* The interrupt status of SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
|
||||
*/
|
||||
uint32_t dma_outfifo_empty_err_int_st:1;
|
||||
/** slv_ex_qpi_int_st : RO; bitpos: [2]; default: 0;
|
||||
uint32_t dma_outfifo_empty_err:1;
|
||||
/** slv_ex_qpi : RO; bitpos: [2]; default: 0;
|
||||
* The interrupt status of SPI_SLV_EX_QPI_INT interrupt.
|
||||
*/
|
||||
uint32_t slv_ex_qpi_int_st:1;
|
||||
/** slv_en_qpi_int_st : RO; bitpos: [3]; default: 0;
|
||||
uint32_t slv_ex_qpi:1;
|
||||
/** slv_en_qpi : RO; bitpos: [3]; default: 0;
|
||||
* The interrupt status of SPI_SLV_EN_QPI_INT interrupt.
|
||||
*/
|
||||
uint32_t slv_en_qpi_int_st:1;
|
||||
/** slv_cmd7_int_st : RO; bitpos: [4]; default: 0;
|
||||
uint32_t slv_en_qpi:1;
|
||||
/** slv_cmd7 : RO; bitpos: [4]; default: 0;
|
||||
* The interrupt status of SPI_SLV_CMD7_INT interrupt.
|
||||
*/
|
||||
uint32_t slv_cmd7_int_st:1;
|
||||
/** slv_cmd8_int_st : RO; bitpos: [5]; default: 0;
|
||||
uint32_t slv_cmd7:1;
|
||||
/** slv_cmd8 : RO; bitpos: [5]; default: 0;
|
||||
* The interrupt status of SPI_SLV_CMD8_INT interrupt.
|
||||
*/
|
||||
uint32_t slv_cmd8_int_st:1;
|
||||
/** slv_cmd9_int_st : RO; bitpos: [6]; default: 0;
|
||||
uint32_t slv_cmd8:1;
|
||||
/** slv_cmd9 : RO; bitpos: [6]; default: 0;
|
||||
* The interrupt status of SPI_SLV_CMD9_INT interrupt.
|
||||
*/
|
||||
uint32_t slv_cmd9_int_st:1;
|
||||
/** slv_cmda_int_st : RO; bitpos: [7]; default: 0;
|
||||
uint32_t slv_cmd9:1;
|
||||
/** slv_cmda : RO; bitpos: [7]; default: 0;
|
||||
* The interrupt status of SPI_SLV_CMDA_INT interrupt.
|
||||
*/
|
||||
uint32_t slv_cmda_int_st:1;
|
||||
/** slv_rd_dma_done_int_st : RO; bitpos: [8]; default: 0;
|
||||
uint32_t slv_cmda:1;
|
||||
/** slv_rd_dma_done : RO; bitpos: [8]; default: 0;
|
||||
* The interrupt status of SPI_SLV_RD_DMA_DONE_INT interrupt.
|
||||
*/
|
||||
uint32_t slv_rd_dma_done_int_st:1;
|
||||
/** slv_wr_dma_done_int_st : RO; bitpos: [9]; default: 0;
|
||||
uint32_t slv_rd_dma_done:1;
|
||||
/** slv_wr_dma_done : RO; bitpos: [9]; default: 0;
|
||||
* The interrupt status of SPI_SLV_WR_DMA_DONE_INT interrupt.
|
||||
*/
|
||||
uint32_t slv_wr_dma_done_int_st:1;
|
||||
/** slv_rd_buf_done_int_st : RO; bitpos: [10]; default: 0;
|
||||
uint32_t slv_wr_dma_done:1;
|
||||
/** slv_rd_buf_done : RO; bitpos: [10]; default: 0;
|
||||
* The interrupt status of SPI_SLV_RD_BUF_DONE_INT interrupt.
|
||||
*/
|
||||
uint32_t slv_rd_buf_done_int_st:1;
|
||||
/** slv_wr_buf_done_int_st : RO; bitpos: [11]; default: 0;
|
||||
uint32_t slv_rd_buf_done:1;
|
||||
/** slv_wr_buf_done : RO; bitpos: [11]; default: 0;
|
||||
* The interrupt status of SPI_SLV_WR_BUF_DONE_INT interrupt.
|
||||
*/
|
||||
uint32_t slv_wr_buf_done_int_st:1;
|
||||
/** trans_done_int_st : RO; bitpos: [12]; default: 0;
|
||||
uint32_t slv_wr_buf_done:1;
|
||||
/** trans_done : RO; bitpos: [12]; default: 0;
|
||||
* The interrupt status of SPI_TRANS_DONE_INT interrupt.
|
||||
*/
|
||||
uint32_t trans_done_int_st:1;
|
||||
/** dma_seg_trans_done_int_st : RO; bitpos: [13]; default: 0;
|
||||
uint32_t trans_done:1;
|
||||
/** dma_seg_trans_done : RO; bitpos: [13]; default: 0;
|
||||
* The interrupt status of SPI_DMA_SEG_TRANS_DONE_INT interrupt.
|
||||
*/
|
||||
uint32_t dma_seg_trans_done_int_st:1;
|
||||
/** seg_magic_err_int_st : RO; bitpos: [14]; default: 0;
|
||||
uint32_t dma_seg_trans_done:1;
|
||||
/** seg_magic_err : RO; bitpos: [14]; default: 0;
|
||||
* The interrupt status of SPI_SEG_MAGIC_ERR_INT interrupt.
|
||||
*/
|
||||
uint32_t seg_magic_err_int_st:1;
|
||||
/** slv_buf_addr_err_int_st : RO; bitpos: [15]; default: 0;
|
||||
uint32_t seg_magic_err:1;
|
||||
/** slv_buf_addr_err : RO; bitpos: [15]; default: 0;
|
||||
* The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
|
||||
*/
|
||||
uint32_t slv_buf_addr_err_int_st:1;
|
||||
/** slv_cmd_err_int_st : RO; bitpos: [16]; default: 0;
|
||||
uint32_t slv_buf_addr_err:1;
|
||||
/** slv_cmd_err : RO; bitpos: [16]; default: 0;
|
||||
* The interrupt status of SPI_SLV_CMD_ERR_INT interrupt.
|
||||
*/
|
||||
uint32_t slv_cmd_err_int_st:1;
|
||||
/** mst_rx_afifo_wfull_err_int_st : RO; bitpos: [17]; default: 0;
|
||||
uint32_t slv_cmd_err:1;
|
||||
/** mst_rx_afifo_wfull_err : RO; bitpos: [17]; default: 0;
|
||||
* The interrupt status of SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
|
||||
*/
|
||||
uint32_t mst_rx_afifo_wfull_err_int_st:1;
|
||||
/** mst_tx_afifo_rempty_err_int_st : RO; bitpos: [18]; default: 0;
|
||||
uint32_t mst_rx_afifo_wfull_err:1;
|
||||
/** mst_tx_afifo_rempty_err : RO; bitpos: [18]; default: 0;
|
||||
* The interrupt status of SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
|
||||
*/
|
||||
uint32_t mst_tx_afifo_rempty_err_int_st:1;
|
||||
/** app2_int_st : RO; bitpos: [19]; default: 0;
|
||||
uint32_t mst_tx_afifo_rempty_err:1;
|
||||
/** app2 : RO; bitpos: [19]; default: 0;
|
||||
* The interrupt status of SPI_APP2_INT interrupt.
|
||||
*/
|
||||
uint32_t app2_int_st:1;
|
||||
/** app1_int_st : RO; bitpos: [20]; default: 0;
|
||||
uint32_t app2:1;
|
||||
/** app1 : RO; bitpos: [20]; default: 0;
|
||||
* The interrupt status of SPI_APP1_INT interrupt.
|
||||
*/
|
||||
uint32_t app1_int_st:1;
|
||||
uint32_t app1:1;
|
||||
uint32_t reserved_21:11;
|
||||
};
|
||||
uint32_t val;
|
||||
|
|
@ -1464,90 +1464,90 @@ typedef union {
|
|||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** dma_infifo_full_err_int_set : WT; bitpos: [0]; default: 0;
|
||||
/** dma_infifo_full_err : WT; bitpos: [0]; default: 0;
|
||||
* Write 1 to set SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
|
||||
*/
|
||||
uint32_t dma_infifo_full_err_int_set:1;
|
||||
/** dma_outfifo_empty_err_int_set : WT; bitpos: [1]; default: 0;
|
||||
uint32_t dma_infifo_full_err:1;
|
||||
/** dma_outfifo_empty_err : WT; bitpos: [1]; default: 0;
|
||||
* Write 1 to set SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
|
||||
*/
|
||||
uint32_t dma_outfifo_empty_err_int_set:1;
|
||||
/** slv_ex_qpi_int_set : WT; bitpos: [2]; default: 0;
|
||||
uint32_t dma_outfifo_empty_err:1;
|
||||
/** slv_ex_qpi : WT; bitpos: [2]; default: 0;
|
||||
* Write 1 to set SPI_SLV_EX_QPI_INT interrupt.
|
||||
*/
|
||||
uint32_t slv_ex_qpi_int_set:1;
|
||||
/** slv_en_qpi_int_set : WT; bitpos: [3]; default: 0;
|
||||
uint32_t slv_ex_qpi:1;
|
||||
/** slv_en_qpi : WT; bitpos: [3]; default: 0;
|
||||
* Write 1 to set SPI_SLV_EN_QPI_INT interrupt.
|
||||
*/
|
||||
uint32_t slv_en_qpi_int_set:1;
|
||||
/** slv_cmd7_int_set : WT; bitpos: [4]; default: 0;
|
||||
uint32_t slv_en_qpi:1;
|
||||
/** slv_cmd7 : WT; bitpos: [4]; default: 0;
|
||||
* Write 1 to set SPI_SLV_CMD7_INT interrupt.
|
||||
*/
|
||||
uint32_t slv_cmd7_int_set:1;
|
||||
/** slv_cmd8_int_set : WT; bitpos: [5]; default: 0;
|
||||
uint32_t slv_cmd7:1;
|
||||
/** slv_cmd8 : WT; bitpos: [5]; default: 0;
|
||||
* Write 1 to set SPI_SLV_CMD8_INT interrupt.
|
||||
*/
|
||||
uint32_t slv_cmd8_int_set:1;
|
||||
/** slv_cmd9_int_set : WT; bitpos: [6]; default: 0;
|
||||
uint32_t slv_cmd8:1;
|
||||
/** slv_cmd9 : WT; bitpos: [6]; default: 0;
|
||||
* Write 1 to set SPI_SLV_CMD9_INT interrupt.
|
||||
*/
|
||||
uint32_t slv_cmd9_int_set:1;
|
||||
/** slv_cmda_int_set : WT; bitpos: [7]; default: 0;
|
||||
uint32_t slv_cmd9:1;
|
||||
/** slv_cmda : WT; bitpos: [7]; default: 0;
|
||||
* Write 1 to set SPI_SLV_CMDA_INT interrupt.
|
||||
*/
|
||||
uint32_t slv_cmda_int_set:1;
|
||||
/** slv_rd_dma_done_int_set : WT; bitpos: [8]; default: 0;
|
||||
uint32_t slv_cmda:1;
|
||||
/** slv_rd_dma_done : WT; bitpos: [8]; default: 0;
|
||||
* Write 1 to set SPI_SLV_RD_DMA_DONE_INT interrupt.
|
||||
*/
|
||||
uint32_t slv_rd_dma_done_int_set:1;
|
||||
/** slv_wr_dma_done_int_set : WT; bitpos: [9]; default: 0;
|
||||
uint32_t slv_rd_dma_done:1;
|
||||
/** slv_wr_dma_done : WT; bitpos: [9]; default: 0;
|
||||
* Write 1 to set SPI_SLV_WR_DMA_DONE_INT interrupt.
|
||||
*/
|
||||
uint32_t slv_wr_dma_done_int_set:1;
|
||||
/** slv_rd_buf_done_int_set : WT; bitpos: [10]; default: 0;
|
||||
uint32_t slv_wr_dma_done:1;
|
||||
/** slv_rd_buf_done : WT; bitpos: [10]; default: 0;
|
||||
* Write 1 to set SPI_SLV_RD_BUF_DONE_INT interrupt.
|
||||
*/
|
||||
uint32_t slv_rd_buf_done_int_set:1;
|
||||
/** slv_wr_buf_done_int_set : WT; bitpos: [11]; default: 0;
|
||||
uint32_t slv_rd_buf_done:1;
|
||||
/** slv_wr_buf_done : WT; bitpos: [11]; default: 0;
|
||||
* Write 1 to set SPI_SLV_WR_BUF_DONE_INT interrupt.
|
||||
*/
|
||||
uint32_t slv_wr_buf_done_int_set:1;
|
||||
/** trans_done_int_set : WT; bitpos: [12]; default: 0;
|
||||
uint32_t slv_wr_buf_done:1;
|
||||
/** trans_done : WT; bitpos: [12]; default: 0;
|
||||
* Write 1 to set SPI_TRANS_DONE_INT interrupt.
|
||||
*/
|
||||
uint32_t trans_done_int_set:1;
|
||||
/** dma_seg_trans_done_int_set : WT; bitpos: [13]; default: 0;
|
||||
uint32_t trans_done:1;
|
||||
/** dma_seg_trans_done : WT; bitpos: [13]; default: 0;
|
||||
* Write 1 to set SPI_DMA_SEG_TRANS_DONE_INT interrupt.
|
||||
*/
|
||||
uint32_t dma_seg_trans_done_int_set:1;
|
||||
/** seg_magic_err_int_set : WT; bitpos: [14]; default: 0;
|
||||
uint32_t dma_seg_trans_done:1;
|
||||
/** seg_magic_err : WT; bitpos: [14]; default: 0;
|
||||
* Write 1 to set SPI_SEG_MAGIC_ERR_INT interrupt.
|
||||
*/
|
||||
uint32_t seg_magic_err_int_set:1;
|
||||
/** slv_buf_addr_err_int_set : WT; bitpos: [15]; default: 0;
|
||||
uint32_t seg_magic_err:1;
|
||||
/** slv_buf_addr_err : WT; bitpos: [15]; default: 0;
|
||||
* The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
|
||||
*/
|
||||
uint32_t slv_buf_addr_err_int_set:1;
|
||||
/** slv_cmd_err_int_set : WT; bitpos: [16]; default: 0;
|
||||
uint32_t slv_buf_addr_err:1;
|
||||
/** slv_cmd_err : WT; bitpos: [16]; default: 0;
|
||||
* Write 1 to set SPI_SLV_CMD_ERR_INT interrupt.
|
||||
*/
|
||||
uint32_t slv_cmd_err_int_set:1;
|
||||
/** mst_rx_afifo_wfull_err_int_set : WT; bitpos: [17]; default: 0;
|
||||
uint32_t slv_cmd_err:1;
|
||||
/** mst_rx_afifo_wfull_err : WT; bitpos: [17]; default: 0;
|
||||
* Write 1 to set SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
|
||||
*/
|
||||
uint32_t mst_rx_afifo_wfull_err_int_set:1;
|
||||
/** mst_tx_afifo_rempty_err_int_set : WT; bitpos: [18]; default: 0;
|
||||
uint32_t mst_rx_afifo_wfull_err:1;
|
||||
/** mst_tx_afifo_rempty_err : WT; bitpos: [18]; default: 0;
|
||||
* Write 1 to set SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
|
||||
*/
|
||||
uint32_t mst_tx_afifo_rempty_err_int_set:1;
|
||||
/** app2_int_set : WT; bitpos: [19]; default: 0;
|
||||
uint32_t mst_tx_afifo_rempty_err:1;
|
||||
/** app2 : WT; bitpos: [19]; default: 0;
|
||||
* Write 1 to set SPI_APP2_INT interrupt.
|
||||
*/
|
||||
uint32_t app2_int_set:1;
|
||||
/** app1_int_set : WT; bitpos: [20]; default: 0;
|
||||
uint32_t app2:1;
|
||||
/** app1 : WT; bitpos: [20]; default: 0;
|
||||
* Write 1 to set SPI_APP1_INT interrupt.
|
||||
*/
|
||||
uint32_t app1_int_set:1;
|
||||
uint32_t app1:1;
|
||||
uint32_t reserved_21:11;
|
||||
};
|
||||
uint32_t val;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,102 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/soc_caps.h"
|
||||
#include "soc/regdma.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Provide access to interrupt matrix configuration registers retention
|
||||
* context defination.
|
||||
*
|
||||
* This is an internal function of the sleep retention driver, and is not
|
||||
* useful for external use.
|
||||
*/
|
||||
#define INT_MTX_RETENTION_LINK_LEN 1
|
||||
extern const regdma_entries_config_t intr_matrix_regs_retention[INT_MTX_RETENTION_LINK_LEN];
|
||||
|
||||
/**
|
||||
* @brief Provide access to hp_system configuration registers retention
|
||||
* context defination.
|
||||
*
|
||||
* This is an internal function of the sleep retention driver, and is not
|
||||
* useful for external use.
|
||||
*/
|
||||
#define HP_SYSTEM_RETENTION_LINK_LEN 1
|
||||
extern const regdma_entries_config_t hp_system_regs_retention[HP_SYSTEM_RETENTION_LINK_LEN];
|
||||
|
||||
/**
|
||||
* @brief Provide access to TEE_APM configuration registers retention
|
||||
* context defination.
|
||||
*
|
||||
* This is an internal function of the sleep retention driver, and is not
|
||||
* useful for external use.
|
||||
*/
|
||||
#define TEE_APM_RETENTION_LINK_LEN 2
|
||||
extern const regdma_entries_config_t tee_apm_regs_retention[TEE_APM_RETENTION_LINK_LEN];
|
||||
#define TEE_APM_HIGH_PRI_RETENTION_LINK_LEN 1
|
||||
extern const regdma_entries_config_t tee_apm_highpri_regs_retention[TEE_APM_HIGH_PRI_RETENTION_LINK_LEN];
|
||||
|
||||
/**
|
||||
* @brief Provide access to uart configuration registers retention
|
||||
* context defination.
|
||||
*
|
||||
* This is an internal function of the sleep retention driver, and is not
|
||||
* useful for external use.
|
||||
*/
|
||||
#define UART_RETENTION_LINK_LEN 3
|
||||
extern const regdma_entries_config_t uart_regs_retention[UART_RETENTION_LINK_LEN];
|
||||
|
||||
/**
|
||||
* @brief Provide access to timer group configuration registers retention
|
||||
* context defination.
|
||||
*
|
||||
* This is an internal function of the sleep retention driver, and is not
|
||||
* useful for external use.
|
||||
*/
|
||||
#define TIMG_RETENTION_LINK_LEN 8
|
||||
extern const regdma_entries_config_t tg_regs_retention[TIMG_RETENTION_LINK_LEN];
|
||||
|
||||
/**
|
||||
* @brief Provide access to IOMUX configuration registers retention
|
||||
* context defination.
|
||||
*
|
||||
* This is an internal function of the sleep retention driver, and is not
|
||||
* useful for external use.
|
||||
*/
|
||||
#define IOMUX_RETENTION_LINK_LEN 4
|
||||
extern const regdma_entries_config_t iomux_regs_retention[IOMUX_RETENTION_LINK_LEN];
|
||||
|
||||
/**
|
||||
* @brief Provide access to spimem configuration registers retention
|
||||
* context defination.
|
||||
*
|
||||
* This is an internal function of the sleep retention driver, and is not
|
||||
* useful for external use.
|
||||
*/
|
||||
#define SPIMEM_RETENTION_LINK_LEN 8
|
||||
extern const regdma_entries_config_t spimem_regs_retention[SPIMEM_RETENTION_LINK_LEN];
|
||||
|
||||
/**
|
||||
* @brief Provide access to systimer configuration registers retention
|
||||
* context defination.
|
||||
*
|
||||
* This is an internal function of the sleep retention driver, and is not
|
||||
* useful for external use.
|
||||
*/
|
||||
#define SYSTIMER_RETENTION_LINK_LEN 19
|
||||
extern const regdma_entries_config_t systimer_regs_retention[SYSTIMER_RETENTION_LINK_LEN];
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include "soc/hp_system_reg.h"
|
||||
|
||||
#include "intpri_reg.h"
|
||||
#define SYSTEM_CPU_INTR_FROM_CPU_0_REG INTPRI_CPU_INTR_FROM_CPU_0_REG
|
||||
#define SYSTEM_CPU_INTR_FROM_CPU_0 INTPRI_CPU_INTR_FROM_CPU_0
|
||||
|
|
@ -95,18 +95,18 @@ typedef union {
|
|||
/** timer_unit0_value_valid : R/SS/WTC; bitpos: [29]; default: 0;
|
||||
* Represents UNIT0 value is synchronized and valid.
|
||||
*/
|
||||
uint32_t timer_unit0_value_valid:1;
|
||||
uint32_t timer_unit_value_valid:1;
|
||||
/** timer_unit0_update : WT; bitpos: [30]; default: 0;
|
||||
* Configures whether or not to update timer UNIT0, i.e., reads the UNIT0 count value
|
||||
* to SYSTIMER_TIMER_UNIT0_VALUE_HI and SYSTIMER_TIMER_UNIT0_VALUE_LO. \\
|
||||
* 0: No effect\\
|
||||
* 1: Update timer UNIT0 \\
|
||||
*/
|
||||
uint32_t timer_unit0_update:1;
|
||||
uint32_t timer_unit_update:1;
|
||||
uint32_t reserved_31:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_unit0_op_reg_t;
|
||||
} systimer_unit_op_reg_t;
|
||||
|
||||
/** Type of unit0_load_hi register
|
||||
* High 20 bits to be loaded to UNIT0
|
||||
|
|
@ -116,7 +116,7 @@ typedef union {
|
|||
/** timer_unit0_load_hi : R/W; bitpos: [19:0]; default: 0;
|
||||
* Configures the value to be loaded to UNIT0, high 20 bits.
|
||||
*/
|
||||
uint32_t timer_unit0_load_hi:20;
|
||||
uint32_t timer_unit_load_hi:20;
|
||||
uint32_t reserved_20:12;
|
||||
};
|
||||
uint32_t val;
|
||||
|
|
@ -130,7 +130,7 @@ typedef union {
|
|||
/** timer_unit0_load_lo : R/W; bitpos: [31:0]; default: 0;
|
||||
* Configures the value to be loaded to UNIT0, low 32 bits.
|
||||
*/
|
||||
uint32_t timer_unit0_load_lo:32;
|
||||
uint32_t timer_unit_load_lo:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_unit0_load_lo_reg_t;
|
||||
|
|
@ -143,7 +143,7 @@ typedef union {
|
|||
/** timer_unit0_value_hi : RO; bitpos: [19:0]; default: 0;
|
||||
* Represents UNIT0 read value, high 20 bits.
|
||||
*/
|
||||
uint32_t timer_unit0_value_hi:20;
|
||||
uint32_t timer_unit_value_hi:20;
|
||||
uint32_t reserved_20:12;
|
||||
};
|
||||
uint32_t val;
|
||||
|
|
@ -157,7 +157,7 @@ typedef union {
|
|||
/** timer_unit0_value_lo : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents UNIT0 read value, low 32 bits.
|
||||
*/
|
||||
uint32_t timer_unit0_value_lo:32;
|
||||
uint32_t timer_unit_value_lo:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_unit0_value_lo_reg_t;
|
||||
|
|
@ -177,7 +177,7 @@ typedef union {
|
|||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_unit0_load_reg_t;
|
||||
} systimer_unit_load_reg_t;
|
||||
|
||||
|
||||
/** Group: SYSTEM TIMER UNIT1 CONTROL AND CONFIGURATION REGISTER */
|
||||
|
|
@ -204,7 +204,7 @@ typedef union {
|
|||
} systimer_unit1_op_reg_t;
|
||||
|
||||
/** Type of unit1_load_hi register
|
||||
* High 20 bits to be loaded to UNIT1
|
||||
* High 20 bits to be loaded to UNIT1systimer_unit1_load_reg_t
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
|
|
@ -284,7 +284,7 @@ typedef union {
|
|||
/** timer_target0_hi : R/W; bitpos: [19:0]; default: 0;
|
||||
* Configures the alarm value to be loaded to COMP0, high 20 bits.
|
||||
*/
|
||||
uint32_t timer_target0_hi:20;
|
||||
uint32_t timer_target_hi:20;
|
||||
uint32_t reserved_20:12;
|
||||
};
|
||||
uint32_t val;
|
||||
|
|
@ -298,7 +298,7 @@ typedef union {
|
|||
/** timer_target0_lo : R/W; bitpos: [31:0]; default: 0;
|
||||
* Configures the alarm value to be loaded to COMP0, low 32 bits.
|
||||
*/
|
||||
uint32_t timer_target0_lo:32;
|
||||
uint32_t timer_target_lo:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_target0_lo_reg_t;
|
||||
|
|
@ -308,26 +308,26 @@ typedef union {
|
|||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** target0_period : R/W; bitpos: [25:0]; default: 0;
|
||||
/** target_period : R/W; bitpos: [25:0]; default: 0;
|
||||
* Configures COMP0 alarm period.
|
||||
*/
|
||||
uint32_t target0_period:26;
|
||||
uint32_t target_period:26;
|
||||
uint32_t reserved_26:4;
|
||||
/** target0_period_mode : R/W; bitpos: [30]; default: 0;
|
||||
/** target_period_mode : R/W; bitpos: [30]; default: 0;
|
||||
* Selects the two alarm modes for COMP0. \\
|
||||
* 0: Target mode\\
|
||||
* 1: Period mode\\
|
||||
*/
|
||||
uint32_t target0_period_mode:1;
|
||||
/** target0_timer_unit_sel : R/W; bitpos: [31]; default: 0;
|
||||
uint32_t target_period_mode:1;
|
||||
/** target_timer_unit_sel : R/W; bitpos: [31]; default: 0;
|
||||
* Chooses the counter value for comparison with COMP0.\\
|
||||
* 0: Use the count value from UNIT$0\\
|
||||
* 1: Use the count value from UNIT$1\\
|
||||
*/
|
||||
uint32_t target0_timer_unit_sel:1;
|
||||
uint32_t target_timer_unit_sel:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_target0_conf_reg_t;
|
||||
} systimer_target_conf_reg_t;
|
||||
|
||||
/** Type of comp0_load register
|
||||
* COMP0 synchronization register
|
||||
|
|
@ -344,7 +344,7 @@ typedef union {
|
|||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_comp0_load_reg_t;
|
||||
} systimer_comp_load_reg_t;
|
||||
|
||||
|
||||
/** Group: SYSTEM TIMER COMP1 CONTROL AND CONFIGURATION REGISTER */
|
||||
|
|
@ -585,7 +585,7 @@ typedef union {
|
|||
/** target0_lo_ro : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the actual target value of COMP0, low 32 bits.
|
||||
*/
|
||||
uint32_t target0_lo_ro:32;
|
||||
uint32_t target_lo_ro:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_real_target0_lo_reg_t;
|
||||
|
|
@ -598,7 +598,7 @@ typedef union {
|
|||
/** target0_hi_ro : RO; bitpos: [19:0]; default: 0;
|
||||
* Represents the actual target value of COMP0, high 20 bits.
|
||||
*/
|
||||
uint32_t target0_hi_ro:20;
|
||||
uint32_t target_hi_ro:20;
|
||||
uint32_t reserved_20:12;
|
||||
};
|
||||
uint32_t val;
|
||||
|
|
@ -677,43 +677,45 @@ typedef union {
|
|||
uint32_t val;
|
||||
} systimer_date_reg_t;
|
||||
|
||||
typedef struct systimer_unit_load_val_reg
|
||||
{
|
||||
systimer_unit0_load_hi_reg_t hi;
|
||||
systimer_unit0_load_lo_reg_t lo;
|
||||
} systimer_unit_load_val_reg_t;
|
||||
|
||||
typedef struct {
|
||||
typedef struct systimer_target_val_reg
|
||||
{
|
||||
systimer_target0_hi_reg_t hi;
|
||||
systimer_target0_lo_reg_t lo;
|
||||
} systimer_target_val_reg_t;
|
||||
|
||||
typedef struct systimer_unit_value_reg
|
||||
{
|
||||
systimer_unit0_value_hi_reg_t hi;
|
||||
systimer_unit0_value_lo_reg_t lo;
|
||||
} systimer_unit_value_reg_t;
|
||||
|
||||
typedef struct systimer_real_target_reg
|
||||
{
|
||||
systimer_real_target0_lo_reg_t lo;
|
||||
systimer_real_target0_hi_reg_t hi;
|
||||
} systimer_real_target_reg_t;
|
||||
|
||||
|
||||
typedef struct systimer_dev_t{
|
||||
volatile systimer_conf_reg_t conf;
|
||||
volatile systimer_unit0_op_reg_t unit0_op;
|
||||
volatile systimer_unit1_op_reg_t unit1_op;
|
||||
volatile systimer_unit0_load_hi_reg_t unit0_load_hi;
|
||||
volatile systimer_unit0_load_lo_reg_t unit0_load_lo;
|
||||
volatile systimer_unit1_load_hi_reg_t unit1_load_hi;
|
||||
volatile systimer_unit1_load_lo_reg_t unit1_load_lo;
|
||||
volatile systimer_target0_hi_reg_t target0_hi;
|
||||
volatile systimer_target0_lo_reg_t target0_lo;
|
||||
volatile systimer_target1_hi_reg_t target1_hi;
|
||||
volatile systimer_target1_lo_reg_t target1_lo;
|
||||
volatile systimer_target2_hi_reg_t target2_hi;
|
||||
volatile systimer_target2_lo_reg_t target2_lo;
|
||||
volatile systimer_target0_conf_reg_t target0_conf;
|
||||
volatile systimer_target1_conf_reg_t target1_conf;
|
||||
volatile systimer_target2_conf_reg_t target2_conf;
|
||||
volatile systimer_unit0_value_hi_reg_t unit0_value_hi;
|
||||
volatile systimer_unit0_value_lo_reg_t unit0_value_lo;
|
||||
volatile systimer_unit1_value_hi_reg_t unit1_value_hi;
|
||||
volatile systimer_unit1_value_lo_reg_t unit1_value_lo;
|
||||
volatile systimer_comp0_load_reg_t comp0_load;
|
||||
volatile systimer_comp1_load_reg_t comp1_load;
|
||||
volatile systimer_comp2_load_reg_t comp2_load;
|
||||
volatile systimer_unit0_load_reg_t unit0_load;
|
||||
volatile systimer_unit1_load_reg_t unit1_load;
|
||||
volatile systimer_unit_op_reg_t unit_op[2];
|
||||
volatile systimer_unit_load_val_reg_t unit_load_val[2];
|
||||
volatile systimer_target_val_reg_t target_val[3];
|
||||
volatile systimer_target_conf_reg_t target_conf[3];
|
||||
volatile systimer_unit_value_reg_t unit_val[2];
|
||||
volatile systimer_comp_load_reg_t comp_load[3];
|
||||
volatile systimer_unit_load_reg_t unit_load[2];
|
||||
volatile systimer_int_ena_reg_t int_ena;
|
||||
volatile systimer_int_raw_reg_t int_raw;
|
||||
volatile systimer_int_clr_reg_t int_clr;
|
||||
volatile systimer_int_st_reg_t int_st;
|
||||
volatile systimer_real_target0_lo_reg_t real_target0_lo;
|
||||
volatile systimer_real_target0_hi_reg_t real_target0_hi;
|
||||
volatile systimer_real_target1_lo_reg_t real_target1_lo;
|
||||
volatile systimer_real_target1_hi_reg_t real_target1_hi;
|
||||
volatile systimer_real_target2_lo_reg_t real_target2_lo;
|
||||
volatile systimer_real_target2_hi_reg_t real_target2_hi;
|
||||
volatile systimer_real_target_reg_t real_target[3];
|
||||
uint32_t reserved_08c[28];
|
||||
volatile systimer_date_reg_t date;
|
||||
} systimer_dev_t;
|
||||
|
|
@ -14,7 +14,7 @@ extern "C" {
|
|||
/** TIMG_T0CONFIG_REG register
|
||||
* Timer 0 configuration register
|
||||
*/
|
||||
#define TIMG_T0CONFIG_REG (DR_REG_TIMG_BASE + 0x0)
|
||||
#define TIMG_T0CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0)
|
||||
/** TIMG_T0_USE_XTAL : R/W; bitpos: [9]; default: 0;
|
||||
* 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source
|
||||
* clock of timer group.
|
||||
|
|
@ -71,7 +71,7 @@ extern "C" {
|
|||
/** TIMG_T0LO_REG register
|
||||
* Timer 0 current value, low 32 bits
|
||||
*/
|
||||
#define TIMG_T0LO_REG (DR_REG_TIMG_BASE + 0x4)
|
||||
#define TIMG_T0LO_REG(i) (REG_TIMG_BASE(i) + 0x4)
|
||||
/** TIMG_T0_LO : RO; bitpos: [31:0]; default: 0;
|
||||
* After writing to TIMG_T0UPDATE_REG, the low 32 bits of the time-base counter
|
||||
* of timer 0 can be read here.
|
||||
|
|
@ -84,7 +84,7 @@ extern "C" {
|
|||
/** TIMG_T0HI_REG register
|
||||
* Timer 0 current value, high 22 bits
|
||||
*/
|
||||
#define TIMG_T0HI_REG (DR_REG_TIMG_BASE + 0x8)
|
||||
#define TIMG_T0HI_REG(i) (REG_TIMG_BASE(i) + 0x8)
|
||||
/** TIMG_T0_HI : RO; bitpos: [21:0]; default: 0;
|
||||
* After writing to TIMG_T0UPDATE_REG, the high 22 bits of the time-base counter
|
||||
* of timer 0 can be read here.
|
||||
|
|
@ -97,7 +97,7 @@ extern "C" {
|
|||
/** TIMG_T0UPDATE_REG register
|
||||
* Write to copy current timer value to TIMGn_T0_(LO/HI)_REG
|
||||
*/
|
||||
#define TIMG_T0UPDATE_REG (DR_REG_TIMG_BASE + 0xc)
|
||||
#define TIMG_T0UPDATE_REG(i) (REG_TIMG_BASE(i) + 0xc)
|
||||
/** TIMG_T0_UPDATE : R/W/SC; bitpos: [31]; default: 0;
|
||||
* After writing 0 or 1 to TIMG_T0UPDATE_REG, the counter value is latched.
|
||||
*/
|
||||
|
|
@ -109,7 +109,7 @@ extern "C" {
|
|||
/** TIMG_T0ALARMLO_REG register
|
||||
* Timer 0 alarm value, low 32 bits
|
||||
*/
|
||||
#define TIMG_T0ALARMLO_REG (DR_REG_TIMG_BASE + 0x10)
|
||||
#define TIMG_T0ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x10)
|
||||
/** TIMG_T0_ALARM_LO : R/W; bitpos: [31:0]; default: 0;
|
||||
* Timer 0 alarm trigger time-base counter value, low 32 bits.
|
||||
*/
|
||||
|
|
@ -121,7 +121,7 @@ extern "C" {
|
|||
/** TIMG_T0ALARMHI_REG register
|
||||
* Timer 0 alarm value, high bits
|
||||
*/
|
||||
#define TIMG_T0ALARMHI_REG (DR_REG_TIMG_BASE + 0x14)
|
||||
#define TIMG_T0ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x14)
|
||||
/** TIMG_T0_ALARM_HI : R/W; bitpos: [21:0]; default: 0;
|
||||
* Timer 0 alarm trigger time-base counter value, high 22 bits.
|
||||
*/
|
||||
|
|
@ -133,7 +133,7 @@ extern "C" {
|
|||
/** TIMG_T0LOADLO_REG register
|
||||
* Timer 0 reload value, low 32 bits
|
||||
*/
|
||||
#define TIMG_T0LOADLO_REG (DR_REG_TIMG_BASE + 0x18)
|
||||
#define TIMG_T0LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x18)
|
||||
/** TIMG_T0_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
|
||||
* Low 32 bits of the value that a reload will load onto timer 0 time-base
|
||||
* Counter.
|
||||
|
|
@ -146,7 +146,7 @@ extern "C" {
|
|||
/** TIMG_T0LOADHI_REG register
|
||||
* Timer 0 reload value, high 22 bits
|
||||
*/
|
||||
#define TIMG_T0LOADHI_REG (DR_REG_TIMG_BASE + 0x1c)
|
||||
#define TIMG_T0LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x1c)
|
||||
/** TIMG_T0_LOAD_HI : R/W; bitpos: [21:0]; default: 0;
|
||||
* High 22 bits of the value that a reload will load onto timer 0 time-base
|
||||
* counter.
|
||||
|
|
@ -159,7 +159,7 @@ extern "C" {
|
|||
/** TIMG_T0LOAD_REG register
|
||||
* Write to reload timer from TIMG_T0_(LOADLOLOADHI)_REG
|
||||
*/
|
||||
#define TIMG_T0LOAD_REG (DR_REG_TIMG_BASE + 0x20)
|
||||
#define TIMG_T0LOAD_REG(i) (REG_TIMG_BASE(i) + 0x20)
|
||||
/** TIMG_T0_LOAD : WT; bitpos: [31:0]; default: 0;
|
||||
*
|
||||
* Write any value to trigger a timer 0 time-base counter reload.
|
||||
|
|
@ -330,7 +330,7 @@ extern "C" {
|
|||
/** TIMG_WDTCONFIG0_REG register
|
||||
* Watchdog timer configuration register
|
||||
*/
|
||||
#define TIMG_WDTCONFIG0_REG (DR_REG_TIMG_BASE + 0x48)
|
||||
#define TIMG_WDTCONFIG0_REG(i) (REG_TIMG_BASE(i) + 0x48)
|
||||
/** TIMG_WDT_APPCPU_RESET_EN : R/W; bitpos: [12]; default: 0;
|
||||
* WDT reset CPU enable.
|
||||
*/
|
||||
|
|
@ -421,7 +421,7 @@ extern "C" {
|
|||
/** TIMG_WDTCONFIG1_REG register
|
||||
* Watchdog timer prescaler register
|
||||
*/
|
||||
#define TIMG_WDTCONFIG1_REG (DR_REG_TIMG_BASE + 0x4c)
|
||||
#define TIMG_WDTCONFIG1_REG(i) (REG_TIMG_BASE(i) + 0x4c)
|
||||
/** TIMG_WDT_DIVCNT_RST : WT; bitpos: [0]; default: 0;
|
||||
* When set, WDT 's clock divider counter will be reset.
|
||||
*/
|
||||
|
|
@ -441,7 +441,7 @@ extern "C" {
|
|||
/** TIMG_WDTCONFIG2_REG register
|
||||
* Watchdog timer stage 0 timeout value
|
||||
*/
|
||||
#define TIMG_WDTCONFIG2_REG (DR_REG_TIMG_BASE + 0x50)
|
||||
#define TIMG_WDTCONFIG2_REG(i) (REG_TIMG_BASE(i) + 0x50)
|
||||
/** TIMG_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 26000000;
|
||||
* Stage 0 timeout value, in MWDT clock cycles.
|
||||
*/
|
||||
|
|
@ -453,7 +453,7 @@ extern "C" {
|
|||
/** TIMG_WDTCONFIG3_REG register
|
||||
* Watchdog timer stage 1 timeout value
|
||||
*/
|
||||
#define TIMG_WDTCONFIG3_REG (DR_REG_TIMG_BASE + 0x54)
|
||||
#define TIMG_WDTCONFIG3_REG(i) (REG_TIMG_BASE(i) + 0x54)
|
||||
/** TIMG_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 134217727;
|
||||
* Stage 1 timeout value, in MWDT clock cycles.
|
||||
*/
|
||||
|
|
@ -465,7 +465,7 @@ extern "C" {
|
|||
/** TIMG_WDTCONFIG4_REG register
|
||||
* Watchdog timer stage 2 timeout value
|
||||
*/
|
||||
#define TIMG_WDTCONFIG4_REG (DR_REG_TIMG_BASE + 0x58)
|
||||
#define TIMG_WDTCONFIG4_REG(i) (REG_TIMG_BASE(i) + 0x58)
|
||||
/** TIMG_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 1048575;
|
||||
* Stage 2 timeout value, in MWDT clock cycles.
|
||||
*/
|
||||
|
|
@ -477,7 +477,7 @@ extern "C" {
|
|||
/** TIMG_WDTCONFIG5_REG register
|
||||
* Watchdog timer stage 3 timeout value
|
||||
*/
|
||||
#define TIMG_WDTCONFIG5_REG (DR_REG_TIMG_BASE + 0x5c)
|
||||
#define TIMG_WDTCONFIG5_REG(i) (REG_TIMG_BASE(i) + 0x5c)
|
||||
/** TIMG_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 1048575;
|
||||
* Stage 3 timeout value, in MWDT clock cycles.
|
||||
*/
|
||||
|
|
@ -489,7 +489,7 @@ extern "C" {
|
|||
/** TIMG_WDTFEED_REG register
|
||||
* Write to feed the watchdog timer
|
||||
*/
|
||||
#define TIMG_WDTFEED_REG (DR_REG_TIMG_BASE + 0x60)
|
||||
#define TIMG_WDTFEED_REG(i) (REG_TIMG_BASE(i) + 0x60)
|
||||
/** TIMG_WDT_FEED : WT; bitpos: [31:0]; default: 0;
|
||||
* Write any value to feed the MWDT. (WO)
|
||||
*/
|
||||
|
|
@ -501,7 +501,7 @@ extern "C" {
|
|||
/** TIMG_WDTWPROTECT_REG register
|
||||
* Watchdog write protect register
|
||||
*/
|
||||
#define TIMG_WDTWPROTECT_REG (DR_REG_TIMG_BASE + 0x64)
|
||||
#define TIMG_WDTWPROTECT_REG(i) (REG_TIMG_BASE(i) + 0x64)
|
||||
/** TIMG_WDT_WKEY : R/W; bitpos: [31:0]; default: 1356348065;
|
||||
* If the register contains a different value than its reset value, write
|
||||
* protection is enabled.
|
||||
|
|
@ -514,7 +514,7 @@ extern "C" {
|
|||
/** TIMG_RTCCALICFG_REG register
|
||||
* RTC calibration configure register
|
||||
*/
|
||||
#define TIMG_RTCCALICFG_REG (DR_REG_TIMG_BASE + 0x68)
|
||||
#define TIMG_RTCCALICFG_REG(i) (REG_TIMG_BASE(i) + 0x68)
|
||||
/** TIMG_RTC_CALI_START_CYCLING : R/W; bitpos: [12]; default: 1;
|
||||
* 0: one-shot frequency calculation,1: periodic frequency calculation,
|
||||
*/
|
||||
|
|
@ -554,7 +554,7 @@ extern "C" {
|
|||
/** TIMG_RTCCALICFG1_REG register
|
||||
* RTC calibration configure1 register
|
||||
*/
|
||||
#define TIMG_RTCCALICFG1_REG (DR_REG_TIMG_BASE + 0x6c)
|
||||
#define TIMG_RTCCALICFG1_REG(i) (REG_TIMG_BASE(i) + 0x6c)
|
||||
/** TIMG_RTC_CALI_CYCLING_DATA_VLD : RO; bitpos: [0]; default: 0;
|
||||
* indicate periodic frequency calculation is done.
|
||||
*/
|
||||
|
|
@ -574,7 +574,7 @@ extern "C" {
|
|||
/** TIMG_INT_ENA_TIMERS_REG register
|
||||
* Interrupt enable bits
|
||||
*/
|
||||
#define TIMG_INT_ENA_TIMERS_REG (DR_REG_TIMG_BASE + 0x70)
|
||||
#define TIMG_INT_ENA_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x70)
|
||||
/** TIMG_T0_INT_ENA : R/W; bitpos: [0]; default: 0;
|
||||
* The interrupt enable bit for the TIMG_T$x_INT interrupt.
|
||||
*/
|
||||
|
|
@ -600,7 +600,7 @@ extern "C" {
|
|||
/** TIMG_INT_RAW_TIMERS_REG register
|
||||
* Raw interrupt status
|
||||
*/
|
||||
#define TIMG_INT_RAW_TIMERS_REG (DR_REG_TIMG_BASE + 0x74)
|
||||
#define TIMG_INT_RAW_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x74)
|
||||
/** TIMG_T0_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
|
||||
* The raw interrupt status bit for the TIMG_T$x_INT interrupt.
|
||||
*/
|
||||
|
|
@ -626,7 +626,7 @@ extern "C" {
|
|||
/** TIMG_INT_ST_TIMERS_REG register
|
||||
* Masked interrupt status
|
||||
*/
|
||||
#define TIMG_INT_ST_TIMERS_REG (DR_REG_TIMG_BASE + 0x78)
|
||||
#define TIMG_INT_ST_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x78)
|
||||
/** TIMG_T0_INT_ST : RO; bitpos: [0]; default: 0;
|
||||
* The masked interrupt status bit for the TIMG_T$x_INT interrupt.
|
||||
*/
|
||||
|
|
@ -652,7 +652,7 @@ extern "C" {
|
|||
/** TIMG_INT_CLR_TIMERS_REG register
|
||||
* Interrupt clear bits
|
||||
*/
|
||||
#define TIMG_INT_CLR_TIMERS_REG (DR_REG_TIMG_BASE + 0x7c)
|
||||
#define TIMG_INT_CLR_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x7c)
|
||||
/** TIMG_T0_INT_CLR : WT; bitpos: [0]; default: 0;
|
||||
* Set this bit to clear the TIMG_T$x_INT interrupt.
|
||||
*/
|
||||
|
|
@ -678,7 +678,7 @@ extern "C" {
|
|||
/** TIMG_RTCCALICFG2_REG register
|
||||
* Timer group calibration register
|
||||
*/
|
||||
#define TIMG_RTCCALICFG2_REG (DR_REG_TIMG_BASE + 0x80)
|
||||
#define TIMG_RTCCALICFG2_REG(i) (REG_TIMG_BASE(i) + 0x80)
|
||||
/** TIMG_RTC_CALI_TIMEOUT : RO; bitpos: [0]; default: 0;
|
||||
* RTC calibration timeout indicator
|
||||
*/
|
||||
|
|
@ -705,7 +705,7 @@ extern "C" {
|
|||
/** TIMG_NTIMERS_DATE_REG register
|
||||
* Timer version control register
|
||||
*/
|
||||
#define TIMG_NTIMERS_DATE_REG (DR_REG_TIMG_BASE + 0xf8)
|
||||
#define TIMG_NTIMERS_DATE_REG(i) (REG_TIMG_BASE(i) + 0xf8)
|
||||
/** TIMG_NTIMGS_DATE : R/W; bitpos: [27:0]; default: 35688770;
|
||||
* Timer version control register
|
||||
*/
|
||||
|
|
@ -717,7 +717,7 @@ extern "C" {
|
|||
/** TIMG_REGCLK_REG register
|
||||
* Timer group clock gate register
|
||||
*/
|
||||
#define TIMG_REGCLK_REG (DR_REG_TIMG_BASE + 0xfc)
|
||||
#define TIMG_REGCLK_REG(i) (REG_TIMG_BASE(i) + 0xfc)
|
||||
/** TIMG_ETM_EN : R/W; bitpos: [28]; default: 1;
|
||||
* enable timer's etm task and event
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -167,163 +167,6 @@ typedef union {
|
|||
} timg_txload_reg_t;
|
||||
|
||||
|
||||
/** Group: T1 Control and configuration registers */
|
||||
/** Type of txconfig register
|
||||
* Timer x configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:9;
|
||||
/** tx_use_xtal : R/W; bitpos: [9]; default: 0;
|
||||
* 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source
|
||||
* clock of timer group.
|
||||
*/
|
||||
uint32_t tx_use_xtal:1;
|
||||
/** tx_alarm_en : R/W/SC; bitpos: [10]; default: 0;
|
||||
* When set, the alarm is enabled. This bit is automatically cleared once an
|
||||
* alarm occurs.
|
||||
*/
|
||||
uint32_t tx_alarm_en:1;
|
||||
uint32_t reserved_11:1;
|
||||
/** tx_divcnt_rst : WT; bitpos: [12]; default: 0;
|
||||
* When set, Timer x 's clock divider counter will be reset.
|
||||
*/
|
||||
uint32_t tx_divcnt_rst:1;
|
||||
/** tx_divider : R/W; bitpos: [28:13]; default: 1;
|
||||
* Timer x clock (Tx_clk) prescaler value.
|
||||
*/
|
||||
uint32_t tx_divider:16;
|
||||
/** tx_autoreload : R/W; bitpos: [29]; default: 1;
|
||||
* When set, timer x auto-reload at alarm is enabled.
|
||||
*/
|
||||
uint32_t tx_autoreload:1;
|
||||
/** tx_increase : R/W; bitpos: [30]; default: 1;
|
||||
* When set, the timer x time-base counter will increment every clock tick. When
|
||||
* cleared, the timer x time-base counter will decrement.
|
||||
*/
|
||||
uint32_t tx_increase:1;
|
||||
/** tx_en : R/W/SS/SC; bitpos: [31]; default: 0;
|
||||
* When set, the timer x time-base counter is enabled.
|
||||
*/
|
||||
uint32_t tx_en:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_txconfig_reg_t;
|
||||
|
||||
/** Type of txlo register
|
||||
* Timer x current value, low 32 bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tx_lo : RO; bitpos: [31:0]; default: 0;
|
||||
* After writing to TIMG_TxUPDATE_REG, the low 32 bits of the time-base counter
|
||||
* of timer x can be read here.
|
||||
*/
|
||||
uint32_t tx_lo:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_txlo_reg_t;
|
||||
|
||||
/** Type of txhi register
|
||||
* Timer x current value, high 22 bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tx_hi : RO; bitpos: [21:0]; default: 0;
|
||||
* After writing to TIMG_TxUPDATE_REG, the high 22 bits of the time-base counter
|
||||
* of timer x can be read here.
|
||||
*/
|
||||
uint32_t tx_hi:22;
|
||||
uint32_t reserved_22:10;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_txhi_reg_t;
|
||||
|
||||
/** Type of txupdate register
|
||||
* Write to copy current timer value to TIMGn_Tx_(LO/HI)_REG
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:31;
|
||||
/** tx_update : R/W/SC; bitpos: [31]; default: 0;
|
||||
* After writing 0 or 1 to TIMG_TxUPDATE_REG, the counter value is latched.
|
||||
*/
|
||||
uint32_t tx_update:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_txupdate_reg_t;
|
||||
|
||||
/** Type of txalarmlo register
|
||||
* Timer x alarm value, low 32 bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tx_alarm_lo : R/W; bitpos: [31:0]; default: 0;
|
||||
* Timer x alarm trigger time-base counter value, low 32 bits.
|
||||
*/
|
||||
uint32_t tx_alarm_lo:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_txalarmlo_reg_t;
|
||||
|
||||
/** Type of txalarmhi register
|
||||
* Timer x alarm value, high bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tx_alarm_hi : R/W; bitpos: [21:0]; default: 0;
|
||||
* Timer x alarm trigger time-base counter value, high 22 bits.
|
||||
*/
|
||||
uint32_t tx_alarm_hi:22;
|
||||
uint32_t reserved_22:10;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_txalarmhi_reg_t;
|
||||
|
||||
/** Type of txloadlo register
|
||||
* Timer x reload value, low 32 bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tx_load_lo : R/W; bitpos: [31:0]; default: 0;
|
||||
* Low 32 bits of the value that a reload will load onto timer x time-base
|
||||
* Counter.
|
||||
*/
|
||||
uint32_t tx_load_lo:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_txloadlo_reg_t;
|
||||
|
||||
/** Type of txloadhi register
|
||||
* Timer x reload value, high 22 bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tx_load_hi : R/W; bitpos: [21:0]; default: 0;
|
||||
* High 22 bits of the value that a reload will load onto timer x time-base
|
||||
* counter.
|
||||
*/
|
||||
uint32_t tx_load_hi:22;
|
||||
uint32_t reserved_22:10;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_txloadhi_reg_t;
|
||||
|
||||
/** Type of txload register
|
||||
* Write to reload timer from TIMG_Tx_(LOADLOLOADHI)_REG
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tx_load : WT; bitpos: [31:0]; default: 0;
|
||||
*
|
||||
* Write any value to trigger a timer x time-base counter reload.
|
||||
*/
|
||||
uint32_t tx_load:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_txload_reg_t;
|
||||
|
||||
|
||||
/** Group: WDT Control and configuration registers */
|
||||
/** Type of wdtconfig0 register
|
||||
* Watchdog timer configuration register
|
||||
|
|
@ -706,7 +549,7 @@ typedef struct {
|
|||
} timg_hwtimer_reg_t;
|
||||
|
||||
|
||||
typedef struct {
|
||||
typedef struct timg_dev_t {
|
||||
volatile timg_hwtimer_reg_t hw_timer[2];
|
||||
volatile timg_wdtconfig0_reg_t wdtconfig0;
|
||||
volatile timg_wdtconfig1_reg_t wdtconfig1;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,18 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// This file defines GPIO lookup macros for available UART IO_MUX pins on ESP32C61.
|
||||
|
||||
#pragma once
|
||||
|
||||
//UART channels
|
||||
#define UART_GPIO16_DIRECT_CHANNEL UART_NUM_0
|
||||
#define UART_NUM_0_TXD_DIRECT_GPIO_NUM 16
|
||||
#define UART_GPIO17_DIRECT_CHANNEL UART_NUM_0
|
||||
#define UART_NUM_0_RXD_DIRECT_GPIO_NUM 17
|
||||
|
||||
#define UART_TXD_GPIO16_DIRECT_CHANNEL UART_GPIO16_DIRECT_CHANNEL
|
||||
#define UART_RXD_GPIO17_DIRECT_CHANNEL UART_GPIO17_DIRECT_CHANNEL
|
||||
|
|
@ -0,0 +1,46 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "soc/io_mux_reg.h"
|
||||
|
||||
/* Specify the number of pins for UART */
|
||||
#define SOC_UART_PINS_COUNT (4)
|
||||
|
||||
/* Specify the GPIO pin number for each UART signal in the IOMUX */
|
||||
#define U0RXD_GPIO_NUM 10
|
||||
#define U0TXD_GPIO_NUM 11
|
||||
#define U0RTS_GPIO_NUM (-1)
|
||||
#define U0CTS_GPIO_NUM (-1)
|
||||
|
||||
#define U1RXD_GPIO_NUM (-1)
|
||||
#define U1TXD_GPIO_NUM (-1)
|
||||
#define U1RTS_GPIO_NUM (-1)
|
||||
#define U1CTS_GPIO_NUM (-1)
|
||||
|
||||
#define LP_U0RXD_GPIO_NUM 4
|
||||
#define LP_U0TXD_GPIO_NUM 5
|
||||
#define LP_U0RTS_GPIO_NUM 2
|
||||
#define LP_U0CTS_GPIO_NUM 3
|
||||
|
||||
/* The following defines are necessary for reconfiguring the UART
|
||||
* to use IOMUX, at runtime. */
|
||||
#define U0TXD_MUX_FUNC (FUNC_U0TXD_U0TXD)
|
||||
#define U0RXD_MUX_FUNC (FUNC_U0RXD_U0RXD)
|
||||
/* No func for the following pins, they shall not be used */
|
||||
#define U0RTS_MUX_FUNC (-1)
|
||||
#define U0CTS_MUX_FUNC (-1)
|
||||
/* Same goes for UART1 */
|
||||
#define U1TXD_MUX_FUNC (-1)
|
||||
#define U1RXD_MUX_FUNC (-1)
|
||||
#define U1RTS_MUX_FUNC (-1)
|
||||
#define U1CTS_MUX_FUNC (-1)
|
||||
|
||||
#define LP_U0TXD_MUX_FUNC (1)
|
||||
#define LP_U0RXD_MUX_FUNC (1)
|
||||
#define LP_U0RTS_MUX_FUNC (1)
|
||||
#define LP_U0CTS_MUX_FUNC (1)
|
||||
|
|
@ -14,7 +14,7 @@ extern "C" {
|
|||
/** UART_FIFO_REG register
|
||||
* FIFO data register
|
||||
*/
|
||||
#define UART_FIFO_REG (DR_REG_UART_BASE + 0x0)
|
||||
#define UART_FIFO_REG(i) (REG_UART_BASE(i) + 0x0)
|
||||
/** UART_RXFIFO_RD_BYTE : RO; bitpos: [7:0]; default: 0;
|
||||
* Represents the data UART $n read from FIFO.\\
|
||||
* Measurement unit: byte.
|
||||
|
|
@ -27,7 +27,7 @@ extern "C" {
|
|||
/** UART_INT_RAW_REG register
|
||||
* Raw interrupt status
|
||||
*/
|
||||
#define UART_INT_RAW_REG (DR_REG_UART_BASE + 0x4)
|
||||
#define UART_INT_RAW_REG(i) (REG_UART_BASE(i) + 0x4)
|
||||
/** UART_RXFIFO_FULL_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
|
||||
* The raw interrupt status of UART_RXFIFO_FULL_INT.
|
||||
*/
|
||||
|
|
@ -172,7 +172,7 @@ extern "C" {
|
|||
/** UART_INT_ST_REG register
|
||||
* Masked interrupt status
|
||||
*/
|
||||
#define UART_INT_ST_REG (DR_REG_UART_BASE + 0x8)
|
||||
#define UART_INT_ST_REG(i) (REG_UART_BASE(i) + 0x8)
|
||||
/** UART_RXFIFO_FULL_INT_ST : RO; bitpos: [0]; default: 0;
|
||||
* The masked interrupt status of UART_RXFIFO_FULL_INT.
|
||||
*/
|
||||
|
|
@ -317,7 +317,7 @@ extern "C" {
|
|||
/** UART_INT_ENA_REG register
|
||||
* Interrupt enable bits
|
||||
*/
|
||||
#define UART_INT_ENA_REG (DR_REG_UART_BASE + 0xc)
|
||||
#define UART_INT_ENA_REG(i) (REG_UART_BASE(i) + 0xc)
|
||||
/** UART_RXFIFO_FULL_INT_ENA : R/W; bitpos: [0]; default: 0;
|
||||
* Write 1 to enable UART_RXFIFO_FULL_INT.
|
||||
*/
|
||||
|
|
@ -462,7 +462,7 @@ extern "C" {
|
|||
/** UART_INT_CLR_REG register
|
||||
* Interrupt clear bits
|
||||
*/
|
||||
#define UART_INT_CLR_REG (DR_REG_UART_BASE + 0x10)
|
||||
#define UART_INT_CLR_REG(i) (REG_UART_BASE(i) + 0x10)
|
||||
/** UART_RXFIFO_FULL_INT_CLR : WT; bitpos: [0]; default: 0;
|
||||
* Write 1 to clear UART_RXFIFO_FULL_INT.
|
||||
*/
|
||||
|
|
@ -607,7 +607,7 @@ extern "C" {
|
|||
/** UART_CLKDIV_SYNC_REG register
|
||||
* Clock divider configuration
|
||||
*/
|
||||
#define UART_CLKDIV_SYNC_REG (DR_REG_UART_BASE + 0x14)
|
||||
#define UART_CLKDIV_SYNC_REG(i) (REG_UART_BASE(i) + 0x14)
|
||||
/** UART_CLKDIV : R/W; bitpos: [11:0]; default: 694;
|
||||
* Configures the integral part of the divisor for baud rate generation.
|
||||
*/
|
||||
|
|
@ -626,7 +626,7 @@ extern "C" {
|
|||
/** UART_RX_FILT_REG register
|
||||
* RX filter configuration
|
||||
*/
|
||||
#define UART_RX_FILT_REG (DR_REG_UART_BASE + 0x18)
|
||||
#define UART_RX_FILT_REG(i) (REG_UART_BASE(i) + 0x18)
|
||||
/** UART_GLITCH_FILT : R/W; bitpos: [7:0]; default: 8;
|
||||
* Configures the width of a pulse to be filtered.\\Measurement unit: UART Core's
|
||||
* clock cycle.\\Pulses whose width is lower than this value will be ignored.
|
||||
|
|
@ -648,7 +648,7 @@ extern "C" {
|
|||
/** UART_STATUS_REG register
|
||||
* UART status register
|
||||
*/
|
||||
#define UART_STATUS_REG (DR_REG_UART_BASE + 0x1c)
|
||||
#define UART_STATUS_REG(i) (REG_UART_BASE(i) + 0x1c)
|
||||
/** UART_RXFIFO_CNT : RO; bitpos: [7:0]; default: 0;
|
||||
* Represents the number of valid data bytes in RX FIFO.
|
||||
*/
|
||||
|
|
@ -709,7 +709,7 @@ extern "C" {
|
|||
/** UART_CONF0_SYNC_REG register
|
||||
* Configuration register 0
|
||||
*/
|
||||
#define UART_CONF0_SYNC_REG (DR_REG_UART_BASE + 0x20)
|
||||
#define UART_CONF0_SYNC_REG(i) (REG_UART_BASE(i) + 0x20)
|
||||
/** UART_PARITY : R/W; bitpos: [0]; default: 0;
|
||||
* Configures the parity check mode.\\
|
||||
* 0: Even parity\\
|
||||
|
|
@ -918,7 +918,7 @@ extern "C" {
|
|||
/** UART_CONF1_REG register
|
||||
* Configuration register 1
|
||||
*/
|
||||
#define UART_CONF1_REG (DR_REG_UART_BASE + 0x24)
|
||||
#define UART_CONF1_REG(i) (REG_UART_BASE(i) + 0x24)
|
||||
/** UART_RXFIFO_FULL_THRHD : R/W; bitpos: [7:0]; default: 96;
|
||||
* Configures the threshold for RX FIFO being full.\\Measurement unit: byte.
|
||||
*/
|
||||
|
|
@ -991,7 +991,7 @@ extern "C" {
|
|||
/** UART_HWFC_CONF_SYNC_REG register
|
||||
* Hardware flow control configuration
|
||||
*/
|
||||
#define UART_HWFC_CONF_SYNC_REG (DR_REG_UART_BASE + 0x2c)
|
||||
#define UART_HWFC_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x2c)
|
||||
/** UART_RX_FLOW_THRHD : R/W; bitpos: [7:0]; default: 0;
|
||||
* Configures the maximum number of data bytes that can be received during hardware
|
||||
* flow control.\\Measurement unit: byte.
|
||||
|
|
@ -1013,7 +1013,7 @@ extern "C" {
|
|||
/** UART_SLEEP_CONF0_REG register
|
||||
* UART sleep configuration register 0
|
||||
*/
|
||||
#define UART_SLEEP_CONF0_REG (DR_REG_UART_BASE + 0x30)
|
||||
#define UART_SLEEP_CONF0_REG(i) (REG_UART_BASE(i) + 0x30)
|
||||
/** UART_WK_CHAR1 : R/W; bitpos: [7:0]; default: 0;
|
||||
* Configures wakeup character 1.
|
||||
*/
|
||||
|
|
@ -1046,7 +1046,7 @@ extern "C" {
|
|||
/** UART_SLEEP_CONF1_REG register
|
||||
* UART sleep configuration register 1
|
||||
*/
|
||||
#define UART_SLEEP_CONF1_REG (DR_REG_UART_BASE + 0x34)
|
||||
#define UART_SLEEP_CONF1_REG(i) (REG_UART_BASE(i) + 0x34)
|
||||
/** UART_WK_CHAR0 : R/W; bitpos: [7:0]; default: 0;
|
||||
* Configures wakeup character 0.
|
||||
*/
|
||||
|
|
@ -1058,7 +1058,7 @@ extern "C" {
|
|||
/** UART_SLEEP_CONF2_REG register
|
||||
* UART sleep configuration register 2
|
||||
*/
|
||||
#define UART_SLEEP_CONF2_REG (DR_REG_UART_BASE + 0x38)
|
||||
#define UART_SLEEP_CONF2_REG(i) (REG_UART_BASE(i) + 0x38)
|
||||
/** UART_ACTIVE_THRESHOLD : R/W; bitpos: [9:0]; default: 240;
|
||||
* Configures the number of RXD edge changes to wake up the chip in wakeup mode 0.
|
||||
*/
|
||||
|
|
@ -1104,7 +1104,7 @@ extern "C" {
|
|||
/** UART_SWFC_CONF0_SYNC_REG register
|
||||
* Software flow control character configuration
|
||||
*/
|
||||
#define UART_SWFC_CONF0_SYNC_REG (DR_REG_UART_BASE + 0x3c)
|
||||
#define UART_SWFC_CONF0_SYNC_REG(i) (REG_UART_BASE(i) + 0x3c)
|
||||
/** UART_XON_CHAR : R/W; bitpos: [7:0]; default: 17;
|
||||
* Configures the XON character for flow control.
|
||||
*/
|
||||
|
|
@ -1188,7 +1188,7 @@ extern "C" {
|
|||
/** UART_SWFC_CONF1_REG register
|
||||
* Software flow control character configuration
|
||||
*/
|
||||
#define UART_SWFC_CONF1_REG (DR_REG_UART_BASE + 0x40)
|
||||
#define UART_SWFC_CONF1_REG(i) (REG_UART_BASE(i) + 0x40)
|
||||
/** UART_XON_THRESHOLD : R/W; bitpos: [7:0]; default: 0;
|
||||
* Configures the threshold for data in RX FIFO to send XON characters in software
|
||||
* flow control.\\Measurement unit: byte.
|
||||
|
|
@ -1209,7 +1209,7 @@ extern "C" {
|
|||
/** UART_TXBRK_CONF_SYNC_REG register
|
||||
* TX break character configuration
|
||||
*/
|
||||
#define UART_TXBRK_CONF_SYNC_REG (DR_REG_UART_BASE + 0x44)
|
||||
#define UART_TXBRK_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x44)
|
||||
/** UART_TX_BRK_NUM : R/W; bitpos: [7:0]; default: 10;
|
||||
* Configures the number of NULL characters to be sent after finishing data
|
||||
* transmission.\\Valid only when UART_TXD_BRK is 1.
|
||||
|
|
@ -1222,7 +1222,7 @@ extern "C" {
|
|||
/** UART_IDLE_CONF_SYNC_REG register
|
||||
* Frame end idle time configuration
|
||||
*/
|
||||
#define UART_IDLE_CONF_SYNC_REG (DR_REG_UART_BASE + 0x48)
|
||||
#define UART_IDLE_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x48)
|
||||
/** UART_RX_IDLE_THRHD : R/W; bitpos: [9:0]; default: 256;
|
||||
* Configures the threshold to generate a frame end signal when the receiver takes
|
||||
* more time to receive one data byte data.\\Measurement unit: bit time (the time to
|
||||
|
|
@ -1244,7 +1244,7 @@ extern "C" {
|
|||
/** UART_RS485_CONF_SYNC_REG register
|
||||
* RS485 mode configuration
|
||||
*/
|
||||
#define UART_RS485_CONF_SYNC_REG (DR_REG_UART_BASE + 0x4c)
|
||||
#define UART_RS485_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x4c)
|
||||
/** UART_RS485_EN : R/W; bitpos: [0]; default: 0;
|
||||
* Configures whether or not to enable RS485 mode.\\
|
||||
* 0: Disable\\
|
||||
|
|
@ -1312,7 +1312,7 @@ extern "C" {
|
|||
/** UART_AT_CMD_PRECNT_SYNC_REG register
|
||||
* Pre-sequence timing configuration
|
||||
*/
|
||||
#define UART_AT_CMD_PRECNT_SYNC_REG (DR_REG_UART_BASE + 0x50)
|
||||
#define UART_AT_CMD_PRECNT_SYNC_REG(i) (REG_UART_BASE(i) + 0x50)
|
||||
/** UART_PRE_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305;
|
||||
* Configures the idle time before the receiver receives the first
|
||||
* AT_CMD.\\Measurement unit: bit time (the time to transmit 1 bit).
|
||||
|
|
@ -1325,7 +1325,7 @@ extern "C" {
|
|||
/** UART_AT_CMD_POSTCNT_SYNC_REG register
|
||||
* Post-sequence timing configuration
|
||||
*/
|
||||
#define UART_AT_CMD_POSTCNT_SYNC_REG (DR_REG_UART_BASE + 0x54)
|
||||
#define UART_AT_CMD_POSTCNT_SYNC_REG(i) (REG_UART_BASE(i) + 0x54)
|
||||
/** UART_POST_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305;
|
||||
* Configures the interval between the last AT_CMD and subsequent data.\\Measurement
|
||||
* unit: bit time (the time to transmit 1 bit).
|
||||
|
|
@ -1338,7 +1338,7 @@ extern "C" {
|
|||
/** UART_AT_CMD_GAPTOUT_SYNC_REG register
|
||||
* Timeout configuration
|
||||
*/
|
||||
#define UART_AT_CMD_GAPTOUT_SYNC_REG (DR_REG_UART_BASE + 0x58)
|
||||
#define UART_AT_CMD_GAPTOUT_SYNC_REG(i) (REG_UART_BASE(i) + 0x58)
|
||||
/** UART_RX_GAP_TOUT : R/W; bitpos: [15:0]; default: 11;
|
||||
* Configures the interval between two AT_CMD characters.\\Measurement unit: bit time
|
||||
* (the time to transmit 1 bit).
|
||||
|
|
@ -1351,7 +1351,7 @@ extern "C" {
|
|||
/** UART_AT_CMD_CHAR_SYNC_REG register
|
||||
* AT escape sequence detection configuration
|
||||
*/
|
||||
#define UART_AT_CMD_CHAR_SYNC_REG (DR_REG_UART_BASE + 0x5c)
|
||||
#define UART_AT_CMD_CHAR_SYNC_REG(i) (REG_UART_BASE(i) + 0x5c)
|
||||
/** UART_AT_CMD_CHAR : R/W; bitpos: [7:0]; default: 43;
|
||||
* Configures the AT_CMD character.
|
||||
*/
|
||||
|
|
@ -1370,7 +1370,7 @@ extern "C" {
|
|||
/** UART_MEM_CONF_REG register
|
||||
* UART memory power configuration
|
||||
*/
|
||||
#define UART_MEM_CONF_REG (DR_REG_UART_BASE + 0x60)
|
||||
#define UART_MEM_CONF_REG(i) (REG_UART_BASE(i) + 0x60)
|
||||
/** UART_MEM_FORCE_PD : R/W; bitpos: [25]; default: 0;
|
||||
* Set this bit to force power down UART memory.
|
||||
*/
|
||||
|
|
@ -1389,7 +1389,7 @@ extern "C" {
|
|||
/** UART_TOUT_CONF_SYNC_REG register
|
||||
* UART threshold and allocation configuration
|
||||
*/
|
||||
#define UART_TOUT_CONF_SYNC_REG (DR_REG_UART_BASE + 0x64)
|
||||
#define UART_TOUT_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x64)
|
||||
/** UART_RX_TOUT_EN : R/W; bitpos: [0]; default: 0;
|
||||
* Configures whether or not to enable UART receiver's timeout function.\\
|
||||
* 0: Disable\\
|
||||
|
|
@ -1418,7 +1418,7 @@ extern "C" {
|
|||
/** UART_MEM_TX_STATUS_REG register
|
||||
* TX FIFO write and read offset address
|
||||
*/
|
||||
#define UART_MEM_TX_STATUS_REG (DR_REG_UART_BASE + 0x68)
|
||||
#define UART_MEM_TX_STATUS_REG(i) (REG_UART_BASE(i) + 0x68)
|
||||
/** UART_TX_SRAM_WADDR : RO; bitpos: [7:0]; default: 0;
|
||||
* Represents the offset address to write TX FIFO.
|
||||
*/
|
||||
|
|
@ -1437,7 +1437,7 @@ extern "C" {
|
|||
/** UART_MEM_RX_STATUS_REG register
|
||||
* Rx FIFO write and read offset address
|
||||
*/
|
||||
#define UART_MEM_RX_STATUS_REG (DR_REG_UART_BASE + 0x6c)
|
||||
#define UART_MEM_RX_STATUS_REG(i) (REG_UART_BASE(i) + 0x6c)
|
||||
/** UART_RX_SRAM_RADDR : RO; bitpos: [7:0]; default: 128;
|
||||
* Represents the offset address to read RX FIFO.
|
||||
*/
|
||||
|
|
@ -1456,7 +1456,7 @@ extern "C" {
|
|||
/** UART_FSM_STATUS_REG register
|
||||
* UART transmit and receive status
|
||||
*/
|
||||
#define UART_FSM_STATUS_REG (DR_REG_UART_BASE + 0x70)
|
||||
#define UART_FSM_STATUS_REG(i) (REG_UART_BASE(i) + 0x70)
|
||||
/** UART_ST_URX_OUT : RO; bitpos: [3:0]; default: 0;
|
||||
* Represents the status of the receiver.
|
||||
*/
|
||||
|
|
@ -1475,7 +1475,7 @@ extern "C" {
|
|||
/** UART_POSPULSE_REG register
|
||||
* Autobaud high pulse register
|
||||
*/
|
||||
#define UART_POSPULSE_REG (DR_REG_UART_BASE + 0x74)
|
||||
#define UART_POSPULSE_REG(i) (REG_UART_BASE(i) + 0x74)
|
||||
/** UART_POSEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
|
||||
* Represents the minimal input clock counter value between two positive edges. It is
|
||||
* used for baud rate detection.
|
||||
|
|
@ -1488,7 +1488,7 @@ extern "C" {
|
|||
/** UART_NEGPULSE_REG register
|
||||
* Autobaud low pulse register
|
||||
*/
|
||||
#define UART_NEGPULSE_REG (DR_REG_UART_BASE + 0x78)
|
||||
#define UART_NEGPULSE_REG(i) (REG_UART_BASE(i) + 0x78)
|
||||
/** UART_NEGEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
|
||||
* Represents the minimal input clock counter value between two negative edges. It is
|
||||
* used for baud rate detection.
|
||||
|
|
@ -1501,7 +1501,7 @@ extern "C" {
|
|||
/** UART_LOWPULSE_REG register
|
||||
* Autobaud minimum low pulse duration register
|
||||
*/
|
||||
#define UART_LOWPULSE_REG (DR_REG_UART_BASE + 0x7c)
|
||||
#define UART_LOWPULSE_REG(i) (REG_UART_BASE(i) + 0x7c)
|
||||
/** UART_LOWPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
|
||||
* Represents the minimum duration time of a low-level pulse. It is used for baud rate
|
||||
* detection.\\Measurement unit: APB_CLK clock cycle.
|
||||
|
|
@ -1514,7 +1514,7 @@ extern "C" {
|
|||
/** UART_HIGHPULSE_REG register
|
||||
* Autobaud minimum high pulse duration register
|
||||
*/
|
||||
#define UART_HIGHPULSE_REG (DR_REG_UART_BASE + 0x80)
|
||||
#define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x80)
|
||||
/** UART_HIGHPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
|
||||
* Represents the maximum duration time for a high-level pulse. It is used for baud
|
||||
* rate detection.\\Measurement unit: APB_CLK clock cycle.
|
||||
|
|
@ -1527,7 +1527,7 @@ extern "C" {
|
|||
/** UART_RXD_CNT_REG register
|
||||
* Autobaud edge change count register
|
||||
*/
|
||||
#define UART_RXD_CNT_REG (DR_REG_UART_BASE + 0x84)
|
||||
#define UART_RXD_CNT_REG(i) (REG_UART_BASE(i) + 0x84)
|
||||
/** UART_RXD_EDGE_CNT : RO; bitpos: [9:0]; default: 0;
|
||||
* Represents the number of RXD edge changes. It is used for baud rate detection.
|
||||
*/
|
||||
|
|
@ -1539,7 +1539,7 @@ extern "C" {
|
|||
/** UART_CLK_CONF_REG register
|
||||
* UART core clock configuration
|
||||
*/
|
||||
#define UART_CLK_CONF_REG (DR_REG_UART_BASE + 0x88)
|
||||
#define UART_CLK_CONF_REG(i) (REG_UART_BASE(i) + 0x88)
|
||||
/** UART_TX_SCLK_EN : R/W; bitpos: [24]; default: 1;
|
||||
* Configures whether or not to enable UART TX clock.\\
|
||||
* 0: Disable\\
|
||||
|
|
@ -1576,7 +1576,7 @@ extern "C" {
|
|||
/** UART_DATE_REG register
|
||||
* UART version control register
|
||||
*/
|
||||
#define UART_DATE_REG (DR_REG_UART_BASE + 0x8c)
|
||||
#define UART_DATE_REG(i) (REG_UART_BASE(i) + 0x8c)
|
||||
/** UART_DATE : R/W; bitpos: [31:0]; default: 36774432;
|
||||
* Version control register.
|
||||
*/
|
||||
|
|
@ -1588,7 +1588,7 @@ extern "C" {
|
|||
/** UART_AFIFO_STATUS_REG register
|
||||
* UART asynchronous FIFO status
|
||||
*/
|
||||
#define UART_AFIFO_STATUS_REG (DR_REG_UART_BASE + 0x90)
|
||||
#define UART_AFIFO_STATUS_REG(i) (REG_UART_BASE(i) + 0x90)
|
||||
/** UART_TX_AFIFO_FULL : RO; bitpos: [0]; default: 0;
|
||||
* Represents whether or not the APB TX asynchronous FIFO is full.\\
|
||||
* 0: Not full\\
|
||||
|
|
@ -1629,7 +1629,7 @@ extern "C" {
|
|||
/** UART_REG_UPDATE_REG register
|
||||
* UART register configuration update
|
||||
*/
|
||||
#define UART_REG_UPDATE_REG (DR_REG_UART_BASE + 0x98)
|
||||
#define UART_REG_UPDATE_REG(i) (REG_UART_BASE(i) + 0x98)
|
||||
/** UART_REG_UPDATE : R/W/SC; bitpos: [0]; default: 0;
|
||||
* Configures whether or not to synchronize registers.\\
|
||||
* 0: Not synchronize\\
|
||||
|
|
@ -1643,7 +1643,7 @@ extern "C" {
|
|||
/** UART_ID_REG register
|
||||
* UART ID register
|
||||
*/
|
||||
#define UART_ID_REG (DR_REG_UART_BASE + 0x9c)
|
||||
#define UART_ID_REG(i) (REG_UART_BASE(i) + 0x9c)
|
||||
/** UART_ID : R/W; bitpos: [31:0]; default: 1280;
|
||||
* Configures the UART ID.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -442,7 +442,7 @@ typedef union {
|
|||
/** clkdiv : R/W; bitpos: [11:0]; default: 694;
|
||||
* Configures the integral part of the divisor for baud rate generation.
|
||||
*/
|
||||
uint32_t clkdiv:12;
|
||||
uint32_t clkdiv_int:12;
|
||||
uint32_t reserved_12:8;
|
||||
/** clkdiv_frag : R/W; bitpos: [23:20]; default: 0;
|
||||
* Configures the fractional part of the divisor for baud rate generation.
|
||||
|
|
@ -1294,7 +1294,7 @@ typedef union {
|
|||
} uart_id_reg_t;
|
||||
|
||||
|
||||
typedef struct {
|
||||
typedef struct uart_dev_s {
|
||||
volatile uart_fifo_reg_t fifo;
|
||||
volatile uart_int_raw_reg_t int_raw;
|
||||
volatile uart_int_st_reg_t int_st;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,13 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "soc.h"
|
||||
#include "soc/lpperi_reg.h"
|
||||
|
||||
/* Hardware random number generator register */
|
||||
#define WDEV_RND_REG LPPERI_RNG_DATA_REG
|
||||
|
|
@ -0,0 +1,128 @@
|
|||
/**
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define XTS_AES_PLAIN_MEM(i) (REG_SPI_MEM_BASE(i) + 0x300)
|
||||
/* XTS_AES_PLAIN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: This field is only used to generate include file in c case. This field is useles
|
||||
s. Please do not use this field..*/
|
||||
#define XTS_AES_PLAIN 0xFFFFFFFF
|
||||
#define XTS_AES_PLAIN_M ((XTS_AES_PLAIN_V)<<(XTS_AES_PLAIN_S))
|
||||
#define XTS_AES_PLAIN_V 0xFFFFFFFF
|
||||
#define XTS_AES_PLAIN_S 0
|
||||
|
||||
#define XTS_AES_LINESIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x340)
|
||||
/* XTS_AES_LINESIZE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
|
||||
/*description: This bits stores the line-size parameter which will be used in manual encryption
|
||||
calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes,
|
||||
1: 32-bytes, 2: 64-bytes, 3:reserved..*/
|
||||
#define XTS_AES_LINESIZE 0x00000003
|
||||
#define XTS_AES_LINESIZE_M ((XTS_AES_LINESIZE_V)<<(XTS_AES_LINESIZE_S))
|
||||
#define XTS_AES_LINESIZE_V 0x3
|
||||
#define XTS_AES_LINESIZE_S 0
|
||||
|
||||
#define XTS_AES_DESTINATION_REG(i) (REG_SPI_MEM_BASE(i) + 0x344)
|
||||
/* XTS_AES_DESTINATION : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: This bit stores the destination parameter which will be used in manual encryptio
|
||||
n calculation. 0: flash(default), 1: psram(reserved). Only default value can be
|
||||
used..*/
|
||||
#define XTS_AES_DESTINATION (BIT(0))
|
||||
#define XTS_AES_DESTINATION_M (BIT(0))
|
||||
#define XTS_AES_DESTINATION_V 0x1
|
||||
#define XTS_AES_DESTINATION_S 0
|
||||
|
||||
#define XTS_AES_PHYSICAL_ADDRESS_REG(i) (REG_SPI_MEM_BASE(i) + 0x348)
|
||||
/* XTS_AES_PHYSICAL_ADDRESS : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
|
||||
/*description: This bits stores the physical-address parameter which will be used in manual enc
|
||||
ryption calculation. This value should aligned with byte number decided by line-
|
||||
size parameter..*/
|
||||
#define XTS_AES_PHYSICAL_ADDRESS 0x03FFFFFF
|
||||
#define XTS_AES_PHYSICAL_ADDRESS_M ((XTS_AES_PHYSICAL_ADDRESS_V)<<(XTS_AES_PHYSICAL_ADDRESS_S))
|
||||
#define XTS_AES_PHYSICAL_ADDRESS_V 0x3FFFFFF
|
||||
#define XTS_AES_PHYSICAL_ADDRESS_S 0
|
||||
|
||||
#define XTS_AES_TRIGGER_REG(i) (REG_SPI_MEM_BASE(i) + 0x34C)
|
||||
/* XTS_AES_TRIGGER : WT ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to trigger the process of manual encryption calculation. This actio
|
||||
n should only be asserted when manual encryption status is 0. After this action,
|
||||
manual encryption status becomes 1. After calculation is done, manual encryptio
|
||||
n status becomes 2..*/
|
||||
#define XTS_AES_TRIGGER (BIT(0))
|
||||
#define XTS_AES_TRIGGER_M (BIT(0))
|
||||
#define XTS_AES_TRIGGER_V 0x1
|
||||
#define XTS_AES_TRIGGER_S 0
|
||||
|
||||
#define XTS_AES_RELEASE_REG(i) (REG_SPI_MEM_BASE(i) + 0x350)
|
||||
/* XTS_AES_RELEASE : WT ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to release encrypted result to mspi. This action should only be ass
|
||||
erted when manual encryption status is 2. After this action, manual encryption s
|
||||
tatus will become 3..*/
|
||||
#define XTS_AES_RELEASE (BIT(0))
|
||||
#define XTS_AES_RELEASE_M (BIT(0))
|
||||
#define XTS_AES_RELEASE_V 0x1
|
||||
#define XTS_AES_RELEASE_S 0
|
||||
|
||||
#define XTS_AES_DESTROY_REG(i) (REG_SPI_MEM_BASE(i) + 0x354)
|
||||
/* XTS_AES_DESTROY : WT ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to destroy encrypted result. This action should be asserted only wh
|
||||
en manual encryption status is 3. After this action, manual encryption status wi
|
||||
ll become 0..*/
|
||||
#define XTS_AES_DESTROY (BIT(0))
|
||||
#define XTS_AES_DESTROY_M (BIT(0))
|
||||
#define XTS_AES_DESTROY_V 0x1
|
||||
#define XTS_AES_DESTROY_S 0
|
||||
|
||||
#define XTS_AES_STATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x358)
|
||||
/* XTS_AES_STATE : RO ;bitpos:[1:0] ;default: 2'h0 ; */
|
||||
/*description: This bits stores the status of manual encryption. 0: idle, 1: busy of encryption
|
||||
calculation, 2: encryption calculation is done but the encrypted result is invi
|
||||
sible to mspi, 3: the encrypted result is visible to mspi..*/
|
||||
#define XTS_AES_STATE 0x00000003
|
||||
#define XTS_AES_STATE_M ((XTS_AES_STATE_V)<<(XTS_AES_STATE_S))
|
||||
#define XTS_AES_STATE_V 0x3
|
||||
#define XTS_AES_STATE_S 0
|
||||
|
||||
#define XTS_AES_DATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x35C)
|
||||
/* XTS_AES_DATE : R/W ;bitpos:[29:0] ;default: 30'h20201010 ; */
|
||||
/*description: This bits stores the last modified-time of manual encryption feature..*/
|
||||
#define XTS_AES_DATE 0x3FFFFFFF
|
||||
#define XTS_AES_DATE_M ((XTS_AES_DATE_V)<<(XTS_AES_DATE_S))
|
||||
#define XTS_AES_DATE_V 0x3FFFFFFF
|
||||
|
||||
#define XTS_AES_DPA_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x388)
|
||||
/* XTS_AES_CRYPT_DPA_SELECT_REGISTER : R/W ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYP
|
||||
T_SECURITY_LEVEL. 0: Controlled by efuse bits..*/
|
||||
#define XTS_AES_CRYPT_DPA_SELECT_REGISTER (BIT(4))
|
||||
#define XTS_AES_CRYPT_DPA_SELECT_REGISTER_M (BIT(4))
|
||||
#define XTS_AES_CRYPT_DPA_SELECT_REGISTER_V 0x1
|
||||
#define XTS_AES_CRYPT_DPA_SELECT_REGISTER_S 4
|
||||
/* XTS_AES_CRYPT_CALC_D_DPA_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
|
||||
/*description: Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calc
|
||||
ulation that using key 1 or key 2. 0: Enable DPA only in the calculation that us
|
||||
ing key 1..*/
|
||||
#define XTS_AES_CRYPT_CALC_D_DPA_EN (BIT(3))
|
||||
#define XTS_AES_CRYPT_CALC_D_DPA_EN_M (BIT(3))
|
||||
#define XTS_AES_CRYPT_CALC_D_DPA_EN_V 0x1
|
||||
#define XTS_AES_CRYPT_CALC_D_DPA_EN_S 3
|
||||
/* XTS_AES_CRYPT_SECURITY_LEVEL : R/W ;bitpos:[2:0] ;default: 3'd7 ; */
|
||||
/*description: Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-
|
||||
7: The bigger the number is, the more secure the cryption is. (Note that the per
|
||||
formance of cryption will decrease together with this number increasing).*/
|
||||
#define XTS_AES_CRYPT_SECURITY_LEVEL 0x00000007
|
||||
#define XTS_AES_CRYPT_SECURITY_LEVEL_M ((XTS_AES_CRYPT_SECURITY_LEVEL_V)<<(XTS_AES_CRYPT_SECURITY_LEVEL_S))
|
||||
#define XTS_AES_CRYPT_SECURITY_LEVEL_V 0x7
|
||||
#define XTS_AES_CRYPT_SECURITY_LEVEL_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -19,7 +19,7 @@ PROVIDE ( ADC = 0x6000E000 );
|
|||
PROVIDE ( USB_SERIAL_JTAG = 0x6000F000 );
|
||||
PROVIDE ( INTMTX = 0x60010000 );
|
||||
PROVIDE ( SOC_ETM = 0x60013000 );
|
||||
PROVIDE ( PVT = 0x60019000 );
|
||||
PROVIDE ( PVT_MONITOR = 0x60019000 );
|
||||
PROVIDE ( PSRAM_MEM_MONITOR = 0x6001A000 );
|
||||
PROVIDE ( GDMA = 0x60080000 );
|
||||
PROVIDE ( GPSPI2 = 0x60081000 );
|
||||
|
|
@ -50,9 +50,9 @@ PROVIDE ( LP_TEE = 0x600B3400 );
|
|||
PROVIDE ( LP_APM = 0x600B3800 );
|
||||
PROVIDE ( LP_IO_MUX = 0x600B4000 );
|
||||
PROVIDE ( LP_GPIO = 0x600B4400 );
|
||||
PROVIDE ( EFUSE_AND_OTP_DEBUG0= 0x600B4800 );
|
||||
PROVIDE ( EFUSE_AND_OTP_DEBUG1= 0x600B4C00 );
|
||||
PROVIDE ( EFUSE0 = 0x600B4800 );
|
||||
PROVIDE ( EFUSE1 = 0x600B4C00 );
|
||||
PROVIDE ( TRACE = 0x600C0000 );
|
||||
PROVIDE ( ASSIST_DEBUG = 0x600C2000 );
|
||||
PROVIDE ( INTPRI = 0x600C5000 );
|
||||
PROVIDE ( CACHE_CFG = 0x600C8000 );
|
||||
PROVIDE ( CACHE = 0x600C8000 );
|
||||
|
|
|
|||
Ładowanie…
Reference in New Issue