kopia lustrzana https://github.com/espressif/esp-idf
refactor(riscv): refactor crosscore interrupt
rodzic
298931596a
commit
5cdf145f55
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@ -10,7 +10,7 @@
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#include "esp_intr_alloc.h"
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#include "esp_debug_helpers.h"
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#include "soc/periph_defs.h"
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#include "hal/crosscore_int_ll.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/portmacro.h"
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@ -19,15 +19,6 @@
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#include "esp_gdbstub.h"
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#endif
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#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2
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#include "soc/dport_reg.h"
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#else
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#include "soc/system_reg.h"
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#endif
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#if CONFIG_IDF_TARGET_ESP32P4
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#include "soc/hp_system_reg.h"
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#endif
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#define REASON_YIELD BIT(0)
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#define REASON_FREQ_SWITCH BIT(1)
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#define REASON_PRINT_BACKTRACE BIT(2)
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@ -53,29 +44,7 @@ static void IRAM_ATTR esp_crosscore_isr(void *arg) {
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volatile uint32_t *my_reason=arg;
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//Clear the interrupt first.
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#if CONFIG_IDF_TARGET_ESP32
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if (esp_cpu_get_core_id()==0) {
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DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, 0);
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} else {
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DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_1_REG, 0);
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}
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#elif CONFIG_IDF_TARGET_ESP32S2
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DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, 0);
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#elif CONFIG_IDF_TARGET_ESP32S3
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if (esp_cpu_get_core_id()==0) {
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WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, 0);
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} else {
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WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_1_REG, 0);
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}
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#elif CONFIG_IDF_TARGET_ESP32P4
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if (esp_cpu_get_core_id() == 0) {
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WRITE_PERI_REG(HP_SYSTEM_CPU_INT_FROM_CPU_0_REG, 0);
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} else {
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WRITE_PERI_REG(HP_SYSTEM_CPU_INT_FROM_CPU_1_REG, 0);
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}
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#elif CONFIG_IDF_TARGET_ARCH_RISCV
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WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, 0);
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#endif
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crosscore_int_ll_clear_interrupt(esp_cpu_get_core_id());
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//Grab the reason and clear it.
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portENTER_CRITICAL_ISR(&reason_spinlock);
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@ -142,29 +111,7 @@ static void IRAM_ATTR esp_crosscore_int_send(int core_id, uint32_t reason_mask)
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reason[core_id] |= reason_mask;
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portEXIT_CRITICAL_ISR(&reason_spinlock);
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//Poke the other CPU.
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#if CONFIG_IDF_TARGET_ESP32
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if (core_id==0) {
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DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, DPORT_CPU_INTR_FROM_CPU_0);
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} else {
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DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_1_REG, DPORT_CPU_INTR_FROM_CPU_1);
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}
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#elif CONFIG_IDF_TARGET_ESP32S2
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DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, DPORT_CPU_INTR_FROM_CPU_0);
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#elif CONFIG_IDF_TARGET_ESP32S3
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if (core_id==0) {
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WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, SYSTEM_CPU_INTR_FROM_CPU_0);
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} else {
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WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_1_REG, SYSTEM_CPU_INTR_FROM_CPU_1);
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}
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#elif CONFIG_IDF_TARGET_ESP32P4
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if (core_id==0) {
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WRITE_PERI_REG(HP_SYSTEM_CPU_INT_FROM_CPU_0_REG, HP_SYSTEM_CPU_INT_FROM_CPU_0);
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} else {
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WRITE_PERI_REG(HP_SYSTEM_CPU_INT_FROM_CPU_1_REG, HP_SYSTEM_CPU_INT_FROM_CPU_1);
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}
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#elif CONFIG_IDF_TARGET_ARCH_RISCV
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WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, SYSTEM_CPU_INTR_FROM_CPU_0);
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#endif
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crosscore_int_ll_trigger_interrupt(core_id);
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}
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void IRAM_ATTR esp_crosscore_int_send_yield(int core_id)
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@ -50,7 +50,7 @@ void esp_crosscore_int_send_freq_switch(int core_id);
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void esp_crosscore_int_send_gdb_call(int core_id);
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#if !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32C2 && !CONFIG_IDF_TARGET_ESP32C6 && !CONFIG_IDF_TARGET_ESP32H2
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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/**
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* Send an interrupt to a CPU indicating it should print its current backtrace
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*
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@ -75,7 +75,7 @@ void esp_crosscore_int_send_print_backtrace(int core_id);
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void esp_crosscore_int_send_twdt_abort(int core_id);
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#endif // CONFIG_ESP_TASK_WDT_EN
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#endif // !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32C2 && !CONFIG_IDF_TARGET_ESP32C6
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#endif // !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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#ifdef __cplusplus
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}
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@ -9,7 +9,7 @@
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#include "soc/soc_caps.h"
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#include "soc/periph_defs.h"
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#include "soc/system_reg.h"
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#include "soc/interrupt_reg.h"
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#include "hal/crosscore_int_ll.h"
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#include "hal/systimer_hal.h"
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#include "hal/systimer_ll.h"
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#include "riscv/rvruntime-frames.h"
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@ -184,6 +184,9 @@ void IRAM_ATTR vPortReleaseLock( portMUX_TYPE *lock )
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void vPortYield(void)
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{
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// TODO: IDF-8113
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const int core_id = 0;
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if (uxInterruptNesting) {
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vPortYieldFromISR();
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} else {
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@ -199,7 +202,7 @@ void vPortYield(void)
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for an instant yield, and if that happens then the WFI would be
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waiting for the next interrupt to occur...)
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*/
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while (uxSchedulerRunning && REG_READ(SYSTEM_CPU_INTR_FROM_CPU_0_REG) != 0) {}
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while (uxSchedulerRunning && crosscore_int_ll_get_state(core_id) != 0) {}
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}
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}
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@ -46,6 +46,7 @@
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#include "riscv/rv_utils.h"
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#include "riscv/interrupt.h"
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#include "esp_private/crosscore_int.h"
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#include "hal/crosscore_int_ll.h"
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#include "esp_attr.h"
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#include "esp_system.h"
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#include "esp_intr_alloc.h"
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@ -623,13 +624,6 @@ void vPortExitCritical(void)
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void vPortYield(void)
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{
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BaseType_t coreID = xPortGetCoreID();
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int system_cpu_int_reg;
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#if !CONFIG_IDF_TARGET_ESP32P4
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system_cpu_int_reg = SYSTEM_CPU_INTR_FROM_CPU_0_REG;
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#else
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system_cpu_int_reg = HP_SYSTEM_CPU_INT_FROM_CPU_0_REG;
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#endif /* !CONFIG_IDF_TARGET_ESP32P4 */
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if (port_uxInterruptNesting[coreID]) {
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vPortYieldFromISR();
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@ -645,7 +639,7 @@ void vPortYield(void)
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for an instant yield, and if that happens then the WFI would be
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waiting for the next interrupt to occur...)
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*/
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while (port_xSchedulerRunning[coreID] && port_uxCriticalNesting[coreID] == 0 && REG_READ(system_cpu_int_reg + 4 * coreID) != 0) {}
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while (port_xSchedulerRunning[coreID] && port_uxCriticalNesting[coreID] == 0 && crosscore_int_ll_get_state(coreID) != 0) {}
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}
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}
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@ -0,0 +1,45 @@
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/*
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "esp_attr.h"
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#include "soc/dport_reg.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Clear the crosscore interrupt that just occurred on the current core
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*/
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FORCE_INLINE_ATTR void crosscore_int_ll_clear_interrupt(int core_id)
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{
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if (core_id == 0) {
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DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, 0);
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} else {
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DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_1_REG, 0);
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}
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}
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/**
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* @brief Trigger a crosscore interrupt on the given core
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*
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* @param core_id Core to trigger an interrupt on. Ignored on single core targets.
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*/
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FORCE_INLINE_ATTR void crosscore_int_ll_trigger_interrupt(int core_id)
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{
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if (core_id == 0) {
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DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, DPORT_CPU_INTR_FROM_CPU_0);
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} else {
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DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_1_REG, DPORT_CPU_INTR_FROM_CPU_1);
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}
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}
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#ifdef __cplusplus
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}
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#endif
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@ -0,0 +1,52 @@
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/*
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include "esp_attr.h"
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#include "soc/system_reg.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Clear the crosscore interrupt that just occurred on the current core
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*/
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FORCE_INLINE_ATTR void crosscore_int_ll_clear_interrupt(int core_id)
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{
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WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, 0);
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}
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/**
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* @brief Trigger a crosscore interrupt on the given core
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*
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* @param core_id Core to trigger an interrupt on. Ignored on single core targets.
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*/
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FORCE_INLINE_ATTR void crosscore_int_ll_trigger_interrupt(int core_id)
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{
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WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, SYSTEM_CPU_INTR_FROM_CPU_0);
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}
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/**
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* @brief Get the state of the crosscore interrupt register for the given core
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*
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* @param core_id Core to get the crosscore interrupt state of. Ignored on single core targets.
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*
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* @return Non zero value if a software interrupt is pending on the given core,
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* 0 if no software interrupt is pending.
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*/
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FORCE_INLINE_ATTR uint32_t crosscore_int_ll_get_state(int core_id)
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{
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return REG_READ(SYSTEM_CPU_INTR_FROM_CPU_0_REG);
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}
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#ifdef __cplusplus
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}
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#endif
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@ -0,0 +1,52 @@
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/*
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include "esp_attr.h"
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#include "soc/system_reg.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Clear the crosscore interrupt that just occurred on the current core
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*/
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FORCE_INLINE_ATTR void crosscore_int_ll_clear_interrupt(int core_id)
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{
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WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, 0);
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}
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/**
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* @brief Trigger a crosscore interrupt on the given core
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*
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* @param core_id Core to trigger an interrupt on. Ignored on single core targets.
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*/
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FORCE_INLINE_ATTR void crosscore_int_ll_trigger_interrupt(int core_id)
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{
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WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, SYSTEM_CPU_INTR_FROM_CPU_0);
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}
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/**
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* @brief Get the state of the crosscore interrupt register for the given core
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*
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* @param core_id Core to get the crosscore interrupt state of. Ignored on single core targets.
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*
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* @return Non zero value if a software interrupt is pending on the given core,
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* 0 if no software interrupt is pending.
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*/
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FORCE_INLINE_ATTR uint32_t crosscore_int_ll_get_state(int core_id)
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{
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return REG_READ(SYSTEM_CPU_INTR_FROM_CPU_0_REG);
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}
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#ifdef __cplusplus
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}
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#endif
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@ -0,0 +1,52 @@
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/*
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include "esp_attr.h"
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#include "soc/intpri_reg.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Clear the crosscore interrupt that just occurred on the current core
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*/
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FORCE_INLINE_ATTR void crosscore_int_ll_clear_interrupt(int core_id)
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{
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WRITE_PERI_REG(INTPRI_CPU_INTR_FROM_CPU_0_REG, 0);
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}
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/**
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* @brief Trigger a crosscore interrupt on the given core
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*
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* @param core_id Core to trigger an interrupt on. Ignored on single core targets.
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*/
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FORCE_INLINE_ATTR void crosscore_int_ll_trigger_interrupt(int core_id)
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{
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WRITE_PERI_REG(INTPRI_CPU_INTR_FROM_CPU_0_REG, INTPRI_CPU_INTR_FROM_CPU_0);
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}
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/**
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* @brief Get the state of the crosscore interrupt register for the given core
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*
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* @param core_id Core to get the crosscore interrupt state of. Ignored on single core targets.
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*
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* @return Non zero value if a software interrupt is pending on the given core,
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* 0 if no software interrupt is pending.
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*/
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FORCE_INLINE_ATTR uint32_t crosscore_int_ll_get_state(int core_id)
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{
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return REG_READ(INTPRI_CPU_INTR_FROM_CPU_0_REG);
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}
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#ifdef __cplusplus
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}
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#endif
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@ -0,0 +1,52 @@
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/*
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include "esp_attr.h"
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#include "soc/intpri_reg.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Clear the crosscore interrupt that just occurred on the current core
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*/
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FORCE_INLINE_ATTR void crosscore_int_ll_clear_interrupt(int core_id)
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{
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WRITE_PERI_REG(INTPRI_CPU_INTR_FROM_CPU_0_REG, 0);
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}
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/**
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* @brief Trigger a crosscore interrupt on the given core
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*
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* @param core_id Core to trigger an interrupt on. Ignored on single core targets.
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*/
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FORCE_INLINE_ATTR void crosscore_int_ll_trigger_interrupt(int core_id)
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{
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WRITE_PERI_REG(INTPRI_CPU_INTR_FROM_CPU_0_REG, INTPRI_CPU_INTR_FROM_CPU_0);
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}
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/**
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* @brief Get the state of the crosscore interrupt register for the given core
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*
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* @param core_id Core to get the crosscore interrupt state of. Ignored on single core targets.
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*
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* @return Non zero value if a software interrupt is pending on the given core,
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* 0 if no software interrupt is pending.
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*/
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FORCE_INLINE_ATTR uint32_t crosscore_int_ll_get_state(int core_id)
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{
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return REG_READ(INTPRI_CPU_INTR_FROM_CPU_0_REG);
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}
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#ifdef __cplusplus
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}
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#endif
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@ -0,0 +1,68 @@
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/*
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include "esp_attr.h"
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#include "soc/hp_system_reg.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Clear the crosscore interrupt that just occurred on the current core
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*/
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FORCE_INLINE_ATTR void crosscore_int_ll_clear_interrupt(int core_id)
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{
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if (core_id == 0) {
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WRITE_PERI_REG(HP_SYSTEM_CPU_INT_FROM_CPU_0_REG, 0);
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} else {
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WRITE_PERI_REG(HP_SYSTEM_CPU_INT_FROM_CPU_1_REG, 0);
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}
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}
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/**
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* @brief Trigger a crosscore interrupt on the given core
|
||||
*
|
||||
* @param core_id Core to trigger an interrupt on. Ignored on single core targets.
|
||||
*/
|
||||
FORCE_INLINE_ATTR void crosscore_int_ll_trigger_interrupt(int core_id)
|
||||
{
|
||||
if (core_id == 0) {
|
||||
WRITE_PERI_REG(HP_SYSTEM_CPU_INT_FROM_CPU_0_REG, HP_SYSTEM_CPU_INT_FROM_CPU_0);
|
||||
} else {
|
||||
WRITE_PERI_REG(HP_SYSTEM_CPU_INT_FROM_CPU_1_REG, HP_SYSTEM_CPU_INT_FROM_CPU_1);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get the state of the crosscore interrupt register for the given core
|
||||
*
|
||||
* @param core_id Core to get the crosscore interrupt state of. Ignored on single core targets.
|
||||
*
|
||||
* @return Non zero value if a software interrupt is pending on the given core,
|
||||
* 0 if no software interrupt is pending.
|
||||
*/
|
||||
FORCE_INLINE_ATTR uint32_t crosscore_int_ll_get_state(int core_id)
|
||||
{
|
||||
uint32_t reg = 0;
|
||||
|
||||
if (core_id == 0) {
|
||||
reg = REG_READ(HP_SYSTEM_CPU_INT_FROM_CPU_0_REG);
|
||||
} else {
|
||||
reg = REG_READ(HP_SYSTEM_CPU_INT_FROM_CPU_1_REG);
|
||||
}
|
||||
|
||||
return reg;
|
||||
}
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
|
@ -0,0 +1,37 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include "soc/dport_reg.h"
|
||||
#include "esp_attr.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* @brief Clear the crosscore interrupt that just occurred on the current core
|
||||
*/
|
||||
static inline void crosscore_int_ll_clear_interrupt(int core_id)
|
||||
{
|
||||
DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, 0);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Trigger a crosscore interrupt on the given core
|
||||
*
|
||||
* @param core_id Core to trigger an interrupt on. Ignored on single core targets.
|
||||
*/
|
||||
static inline void crosscore_int_ll_trigger_interrupt(int core_id)
|
||||
{
|
||||
DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, DPORT_CPU_INTR_FROM_CPU_0);
|
||||
}
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
|
@ -0,0 +1,44 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include "soc/system_reg.h"
|
||||
#include "esp_attr.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* @brief Clear the crosscore interrupt that just occurred on the current core
|
||||
*/
|
||||
FORCE_INLINE_ATTR void crosscore_int_ll_clear_interrupt(int core_id)
|
||||
{
|
||||
if (core_id == 0) {
|
||||
WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, 0);
|
||||
} else {
|
||||
WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_1_REG, 0);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Trigger a crosscore interrupt on the given core
|
||||
*
|
||||
* @param core_id Core to trigger an interrupt on.
|
||||
*/
|
||||
FORCE_INLINE_ATTR void crosscore_int_ll_trigger_interrupt(int core_id)
|
||||
{
|
||||
if (core_id == 0) {
|
||||
WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, SYSTEM_CPU_INTR_FROM_CPU_0);
|
||||
} else {
|
||||
WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_1_REG, SYSTEM_CPU_INTR_FROM_CPU_1);
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
|
@ -6,6 +6,7 @@
|
|||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "soc/soc_caps.h"
|
||||
#include "xtensa/config/core-isa.h"
|
||||
#include "xtensa/config/core.h"
|
||||
|
|
Ładowanie…
Reference in New Issue