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esp_hw_support: move test to pytest

pull/8689/merge
Marius Vikhammer 2022-10-25 16:20:44 +08:00
rodzic 26e5d16c47
commit 59e40fafba
96 zmienionych plików z 995 dodań i 902 usunięć
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46
.gitlab/ci/target-test.yml
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@ -362,6 +362,22 @@ component_ut_pytest_esp32_flash_multi:
- build_pytest_components_esp32
tags: [ esp32, flash_mutli ]
component_ut_pytest_esp32_xtal32k:
extends:
- .pytest_components_dir_template
- .rules:test:component_ut-esp32
needs:
- build_pytest_components_esp32
tags: [ esp32, xtal32k ]
component_ut_pytest_esp32_no32kXtal:
extends:
- .pytest_components_dir_template
- .rules:test:component_ut-esp32
needs:
- build_pytest_components_esp32
tags: [ esp32, no32kXtal ]
component_ut_pytest_esp32_rs485_multi:
extends:
- .pytest_components_dir_template
@ -370,6 +386,15 @@ component_ut_pytest_esp32_rs485_multi:
- build_pytest_components_esp32
tags: [ esp32, multi_dut_modbus_rs485 ]
component_ut_pytest_esp32_psramv0:
extends:
- .pytest_components_dir_template
- .rules:test:component_ut-esp32
needs:
- build_pytest_components_esp32
tags: [ esp32, psramv0 ]
component_ut_pytest_esp32s2_generic:
extends:
- .pytest_components_dir_template
@ -1042,33 +1067,12 @@ UT_035:
- ESP32S2_IDF
- UT_T1_1
UT_036:
extends: .unit_test_esp32_template
tags:
- ESP32_IDF
- UT_T1_PSRAMV0
- psram
UT_038:
extends: .unit_test_esp32s2_template
tags:
- ESP32S2_IDF
- UT_T1_ESP_FLASH
UT_041:
extends: .unit_test_esp32_template
tags:
- ESP32_IDF
- UT_T1_no32kXTAL
- psram
UT_043:
extends: .unit_test_esp32_template
tags:
- ESP32_IDF
- UT_T1_32kXTAL
- psram
UT_S2_SDSPI:
extends: .unit_test_esp32s2_template
tags:

6
components/esp_hw_support/.build-test-rules.yml
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@ -9,3 +9,9 @@ components/esp_hw_support/test_apps/dma:
components/esp_hw_support/test_apps/etm:
disable:
- if: SOC_ETM_SUPPORTED != 1
components/esp_hw_support/test_apps/rtc_clk:
disable:
- if: IDF_TARGET in ["esp32c6"]
temporary: true
reason: Unsupported on C6 for now. TODO IDF-5645

6
components/esp_hw_support/test/CMakeLists.txt
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@ -1,6 +0,0 @@
idf_component_register(SRC_DIRS "."
PRIV_INCLUDE_DIRS "${include_dirs}"
PRIV_REQUIRES cmock test_utils esp_hw_support driver efuse esp_timer esp_psram spi_flash)
target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format")
target_link_libraries(${COMPONENT_LIB} INTERFACE "-u ld_include_test_dport_xt_highint5")

300
components/esp_hw_support/test/test_ahb_arb.c
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@ -1,300 +0,0 @@
/*
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "sdkconfig.h"
#if CONFIG_IDF_TARGET_ESP32
#include <esp_types.h>
#include <stdio.h>
#include <stdlib.h>
#include "esp32/rom/lldesc.h"
#include "esp_private/periph_ctrl.h"
#include "hal/gpio_hal.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/semphr.h"
#include "freertos/queue.h"
#include "freertos/xtensa_api.h"
#include "unity.h"
#include "soc/uart_periph.h"
#include "soc/dport_reg.h"
#include "soc/gpio_periph.h"
#include "soc/i2s_periph.h"
#define DPORT_I2S0_CLK_EN (BIT(4))
#define DPORT_I2S0_RST (BIT(4))
/*
This test tests the s32c1i instruction when the AHB bus is also used. To create some AHB traffic, we use the I2S interface
to copy bytes over from one memory location to another. DO NOT USE the i2s routines inhere, they've been trial-and-error'ed until
the point where they happened to do what I want.
*/
static void lcdIfaceInit(void)
{
periph_module_enable(PERIPH_I2S0_MODULE);
//Init pins to i2s functions
SET_PERI_REG_MASK(GPIO_ENABLE_W1TS_REG, (1 << 11) | (1 << 3) | (1 << 0) | (1 << 2) | (1 << 5) | (1 << 16) | (1 << 17) | (1 << 18) | (1 << 19) | (1 << 20)); //ENABLE GPIO oe_enable
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO0_U, 0);
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO2_U, 0);
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO5_U, 0);
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO16_U, 0);
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO17_U, 0);
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO18_U, 0);
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO19_U, 0);
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO20_U, 0);
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_CMD_U, 2); //11
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO26_U, 0); //RS
WRITE_PERI_REG(GPIO_FUNC0_OUT_SEL_CFG_REG, (148 << GPIO_FUNC0_OUT_SEL_S));
WRITE_PERI_REG(GPIO_FUNC2_OUT_SEL_CFG_REG, (149 << GPIO_FUNC0_OUT_SEL_S));
WRITE_PERI_REG(GPIO_FUNC5_OUT_SEL_CFG_REG, (150 << GPIO_FUNC0_OUT_SEL_S));
WRITE_PERI_REG(GPIO_FUNC16_OUT_SEL_CFG_REG, (151 << GPIO_FUNC0_OUT_SEL_S));
WRITE_PERI_REG(GPIO_FUNC17_OUT_SEL_CFG_REG, (152 << GPIO_FUNC0_OUT_SEL_S));
WRITE_PERI_REG(GPIO_FUNC18_OUT_SEL_CFG_REG, (153 << GPIO_FUNC0_OUT_SEL_S));
WRITE_PERI_REG(GPIO_FUNC19_OUT_SEL_CFG_REG, (154 << GPIO_FUNC0_OUT_SEL_S));
WRITE_PERI_REG(GPIO_FUNC20_OUT_SEL_CFG_REG, (155 << GPIO_FUNC0_OUT_SEL_S));
WRITE_PERI_REG(GPIO_FUNC26_OUT_SEL_CFG_REG, (156 << GPIO_FUNC0_OUT_SEL_S)); //RS
WRITE_PERI_REG(GPIO_FUNC11_OUT_SEL_CFG_REG, (I2S0O_WS_OUT_IDX << GPIO_FUNC0_OUT_SEL_S));
// WRITE_PERI_REG(GPIO_FUNC11_OUT_SEL_CFG, (I2S0O_BCK_OUT_IDX<<GPIO_GPIO_FUNC0_OUT_SEL_S));
//GPIO_SET_GPIO_FUNC11_OUT_INV_SEL(1); //old
WRITE_PERI_REG(GPIO_FUNC11_OUT_SEL_CFG_REG, READ_PERI_REG(GPIO_FUNC11_OUT_SEL_CFG_REG) | GPIO_FUNC11_OUT_INV_SEL);
//Reset I2S subsystem
CLEAR_PERI_REG_MASK(I2S_CONF_REG(0), I2S_RX_RESET | I2S_TX_RESET);
SET_PERI_REG_MASK(I2S_CONF_REG(0), I2S_RX_RESET | I2S_TX_RESET);
CLEAR_PERI_REG_MASK(I2S_CONF_REG(0), I2S_RX_RESET | I2S_TX_RESET);
WRITE_PERI_REG(I2S_CONF_REG(0), 0);//I2S_SIG_LOOPBACK);
WRITE_PERI_REG(I2S_CONF2_REG(0), 0);
WRITE_PERI_REG(I2S_SAMPLE_RATE_CONF_REG(0),
(16 << I2S_RX_BITS_MOD_S) |
(16 << I2S_TX_BITS_MOD_S) |
(1 << I2S_RX_BCK_DIV_NUM_S) |
(1 << I2S_TX_BCK_DIV_NUM_S));
WRITE_PERI_REG(I2S_CLKM_CONF_REG(0),
I2S_CLKA_ENA | I2S_CLK_EN |
(1 << I2S_CLKM_DIV_A_S) |
(1 << I2S_CLKM_DIV_B_S) |
(1 << I2S_CLKM_DIV_NUM_S));
WRITE_PERI_REG(I2S_FIFO_CONF_REG(0),
(32 << I2S_TX_DATA_NUM_S) | //Low watermark for IRQ
(32 << I2S_RX_DATA_NUM_S));
WRITE_PERI_REG(I2S_CONF1_REG(0), I2S_RX_PCM_BYPASS | I2S_TX_PCM_BYPASS);
WRITE_PERI_REG(I2S_CONF_CHAN_REG(0), (2 << I2S_TX_CHAN_MOD_S) | (2 << I2S_RX_CHAN_MOD_S));
//Invert WS to active-low
SET_PERI_REG_MASK(I2S_CONF_REG(0), I2S_TX_RIGHT_FIRST | I2S_RX_RIGHT_FIRST);
WRITE_PERI_REG(I2S_TIMING_REG(0), 0);
}
static volatile lldesc_t dmaDesc[2];
static void finishDma(void)
{
//No need to finish if no DMA transfer going on
if (!(READ_PERI_REG(I2S_FIFO_CONF_REG(0))&I2S_DSCR_EN)) {
return;
}
//Wait till fifo done
while (!(READ_PERI_REG(I2S_INT_RAW_REG(0))&I2S_TX_REMPTY_INT_RAW)) ;
//Wait for last bytes to leave i2s xmit thing
//ToDo: poll bit in next hw
// for (i=0; i<(1<<8); i++);
while (!(READ_PERI_REG(I2S_STATE_REG(0))&I2S_TX_IDLE));
//Reset I2S for next transfer
CLEAR_PERI_REG_MASK(I2S_CONF_REG(0), I2S_TX_START | I2S_RX_START);
CLEAR_PERI_REG_MASK(I2S_OUT_LINK_REG(0), I2S_OUTLINK_START | I2S_INLINK_START);
SET_PERI_REG_MASK(I2S_CONF_REG(0), I2S_TX_RESET | I2S_TX_FIFO_RESET | I2S_RX_RESET | I2S_RX_FIFO_RESET);
CLEAR_PERI_REG_MASK(I2S_CONF_REG(0), I2S_TX_RESET | I2S_TX_FIFO_RESET | I2S_RX_RESET | I2S_RX_FIFO_RESET);
// for (i=0; i<(1<<8); i++);
while ((READ_PERI_REG(I2S_STATE_REG(0))&I2S_TX_FIFO_RESET_BACK));
}
/*
This is a very, very, very hacked up LCD routine which ends up basically doing a memcpy from sbuf to rbuf.
*/
static void sendRecvBufDma(uint16_t *sbuf, uint16_t *rbuf, int len)
{
//Fill DMA descriptor
dmaDesc[0].length = len * 2;
dmaDesc[0].size = len * 2;
dmaDesc[0].owner = 1;
dmaDesc[0].sosf = 0;
dmaDesc[0].buf = (uint8_t *)sbuf;
dmaDesc[0].offset = 0; //unused in hw
dmaDesc[0].empty = 0;
dmaDesc[0].eof = 1;
dmaDesc[1].length = len * 2;
dmaDesc[1].size = len * 2;
dmaDesc[1].owner = 1;
dmaDesc[1].sosf = 0;
dmaDesc[1].buf = (uint8_t *)rbuf;
dmaDesc[1].offset = 0; //unused in hw
dmaDesc[1].empty = 0;
dmaDesc[1].eof = 1;
//Reset DMA
SET_PERI_REG_MASK(I2S_LC_CONF_REG(0), I2S_IN_RST | I2S_OUT_RST | I2S_AHBM_RST | I2S_AHBM_FIFO_RST);
CLEAR_PERI_REG_MASK(I2S_LC_CONF_REG(0), I2S_IN_RST | I2S_OUT_RST | I2S_AHBM_RST | I2S_AHBM_FIFO_RST);
//Reset I2S FIFO
SET_PERI_REG_MASK(I2S_CONF_REG(0), I2S_RX_RESET | I2S_TX_RESET | I2S_TX_FIFO_RESET | I2S_RX_FIFO_RESET);
CLEAR_PERI_REG_MASK(I2S_CONF_REG(0), I2S_RX_RESET | I2S_TX_RESET | I2S_TX_FIFO_RESET | I2S_RX_FIFO_RESET);
//Set desc addr
CLEAR_PERI_REG_MASK(I2S_OUT_LINK_REG(0), I2S_OUTLINK_ADDR);
SET_PERI_REG_MASK(I2S_OUT_LINK_REG(0), ((uint32_t)(&dmaDesc[0]))&I2S_OUTLINK_ADDR);
CLEAR_PERI_REG_MASK(I2S_IN_LINK_REG(0), I2S_INLINK_ADDR);
SET_PERI_REG_MASK(I2S_IN_LINK_REG(0), ((uint32_t)(&dmaDesc[1]))&I2S_INLINK_ADDR);
SET_PERI_REG_MASK(I2S_FIFO_CONF_REG(0), I2S_DSCR_EN); //Enable DMA mode
WRITE_PERI_REG(I2S_RXEOF_NUM_REG(0), len);
//Enable and configure DMA
WRITE_PERI_REG(I2S_LC_CONF_REG(0), I2S_OUT_DATA_BURST_EN |
I2S_OUT_EOF_MODE | I2S_OUTDSCR_BURST_EN | I2S_OUT_DATA_BURST_EN |
I2S_INDSCR_BURST_EN | I2S_MEM_TRANS_EN);
//Start transmission
SET_PERI_REG_MASK(I2S_OUT_LINK_REG(0), I2S_OUTLINK_START);
SET_PERI_REG_MASK(I2S_IN_LINK_REG(0), I2S_INLINK_START);
SET_PERI_REG_MASK(I2S_CONF_REG(0), I2S_TX_START | I2S_RX_START);
//Clear int flags
WRITE_PERI_REG(I2S_INT_CLR_REG(0), 0xFFFFFFFF);
}
#define DMALEN (2048-2)
static void tskLcd(void *pvParameters)
{
uint16_t *sbuf = malloc(DMALEN * 2);
uint16_t *rbuf = malloc(DMALEN * 2);
uint16_t xorval = 0;
int x;
lcdIfaceInit();
// lcdFlush();
while (1) {
for (x = 0; x < DMALEN; x++) {
sbuf[x] = x ^ xorval;
}
for (x = 0; x < DMALEN; x++) {
rbuf[x] = 0; //clear rbuf
}
sendRecvBufDma(sbuf, rbuf, DMALEN);
vTaskDelay(20 / portTICK_PERIOD_MS);
finishDma();
for (x = 0; x < DMALEN; x++) if (rbuf[x] != (x ^ xorval)) {
printf("Rxbuf err! pos %d val %x xor %x", x, (int)rbuf[x], (int)xorval);
}
printf(".");
fflush(stdout);
xorval++;
}
}
void test_s32c1i_lock(volatile int *lockvar, int lockval, int unlockval, volatile int *ctr);
static volatile int ctr = 0, state = 0;
static volatile int lock = 0;
static void tskOne(void *pvParameters)
{
int x;
int err = 0, run = 0;
while (1) {
ctr = 0; lock = 0;
state = 1;
for (x = 0; x < 16 * 1024; x++) {
test_s32c1i_lock(&lock, 1, 0, &ctr);
}
vTaskDelay(60 / portTICK_PERIOD_MS);
state = 2;
if (ctr != 16 * 1024 * 2) {
printf("Lock malfunction detected! Ctr=0x%x instead of %x\n", ctr, 16 * 1024 * 2);
err++;
}
run++;
printf("Run %d err %d\n", run, err);
vTaskDelay(20 / portTICK_PERIOD_MS);
}
}
#define FB2ADDR 0x40098000
static void tskTwo(void *pvParameters)
{
int x;
int *p = (int *)FB2ADDR;
int *s = (int *)test_s32c1i_lock;
void (*test_s32c1i_lock2)(volatile int * lockvar, int lockval, int unlockval, volatile int * ctr) = (void *)FB2ADDR;
volatile int w;
int delay;
for (x = 0; x < 100; x++) {
*p++ = *s++; //copy routine to different pool
}
while (1) {
while (state != 1) ;
for (x = 0; x < 16 * 1024; x++) {
test_s32c1i_lock2(&lock, 2, 0, &ctr);
//Some random delay to increase chance of weirdness
if ((x & 0x1f) == 0) {
delay = rand() & 0x1f;
for (w = 0; w < delay; w++);
}
}
while (state != 2);
}
}
TEST_CASE("S32C1I vs AHB test (needs I2S)", "[hw][ignore]")
{
int i;
TaskHandle_t th[3];
state = 0;
printf("Creating tasks\n");
xTaskCreatePinnedToCore(tskTwo , "tsktwo" , 2048, NULL, 3, &th[1], 1);
xTaskCreatePinnedToCore(tskOne , "tskone" , 2048, NULL, 3, &th[0], 0);
xTaskCreatePinnedToCore(tskLcd , "tsklcd" , 2048, NULL, 3, &th[2], 0);
// Let stuff run for 20s
while (1) {
vTaskDelay(20000 / portTICK_PERIOD_MS);
}
//Shut down all the tasks
for (i = 0; i < 3; i++) {
vTaskDelete(th[i]);
}
}
#endif // CONFIG_IDF_TARGET_ESP32

57
components/esp_hw_support/test/test_ahb_arb_asm.S
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@ -1,57 +0,0 @@
#include "sdkconfig.h"
#if CONFIG_IDF_TARGET_ESP32
/*
This little bit of code is executed in-place by one CPU, but copied to a different memory region
by the other CPU. Make sure it stays position-independent.
*/
.text
.align 4
.global test_s32c1i_lock
.type test_s32c1i_lock,@function
//Args:
//a2 - lock addr
//a3 - val to lock with
//a4 - val to unlock with
//a5 - addr to increase
test_s32c1i_lock:
entry a1, 64
wsr a4, SCOMPARE1
lockloop:
mov a6, a3
s32c1i a6, a2, 0
bne a4, a6, lockloop
l32i a6, a5, 0
//Give other CPU the time to mess up the inc if the lock somehow malfunctions
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
addi a6, a6, 1
s32i a6, a5, 0
//No need to actually let this loop but hey, a hang indicates an error, right?
wsr a3, SCOMPARE1
unlockloop:
mov a6, a4
s32c1i a6, a2, 0
bne a3, a6, unlockloop
retw
#endif // CONFIG_IDF_TARGET_ESP32

141
components/esp_hw_support/test/test_fastbus.c
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@ -1,141 +0,0 @@
/*
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "sdkconfig.h"
#if CONFIG_IDF_TARGET_ESP32
#include <stdio.h>
#include "esp_types.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/semphr.h"
#include "freertos/queue.h"
#include "freertos/xtensa_api.h"
#include "unity.h"
#include "soc/uart_periph.h"
#include "soc/dport_reg.h"
#include "hal/gpio_hal.h"
#include "driver/gpio.h"
/*
This test tests the 'fast' peripherial bus at 0x3ff40000. This bus is connected directly to the core, and as such
can receive 'speculative' reads, that is, reads that may or may not actually be executed in the code flow. This
may mess with any FIFOs mapped in the region: if a byte gets dropped due to a missed speculative read, the fifo
may advance to the next byte anyway.
This code tests reading/writing from the UART1 FIFO, using both cores. For this to work, it's required that the
UARTs RX and TX lines are connected.
*/
void test_fastbus_cp(int fifo_addr, unsigned char *buf, int len, int *dummy);
static volatile int state = 0;
static volatile int xor = 0;
static unsigned char res[128];
static void tskOne(void *pvParameters)
{
int run = 0, err = 0;
int x;
int ct[256];
volatile int w;
int dummy;
while (1) {
state = 1;
for (x = 0; x < 64; x++) {
WRITE_PERI_REG(UART_FIFO_REG(1), x ^ xor);
}
for (w = 0; w < (1 << 14); w++); //delay
state = 2;
test_fastbus_cp(UART_FIFO_REG(1), &res[0], 64, &dummy);
for (w = 0; w < (1 << 10); w++); //delay
for (x = 0; x < 255; x++) {
ct[x] = 0; //zero ctrs
}
for (x = 0; x < 128; x++) {
ct[(int)res[x]^xor]++; //count values
}
for (x = 0; x < 255; x++) { //check counts
if (ct[x] != (x < 128 ? 1 : 0)) {
//Disregard first few loops; there may be crap in the fifo.
if (run > 2) {
err++;
printf("Error! Received value %d %d times!\n", x, ct[x]);
}
}
}
run++;
if ((run & 255) == 0) {
printf("Loop %d errct %d\n", run, err);
}
xor = (xor + 1) & 0xff;
}
}
#define FB2ADDR 0x40098000
static void tskTwo(void *pvParameters)
{
int x;
int dummy;
int *p = (int *)FB2ADDR;
int *s = (int *)test_fastbus_cp;
for (x = 0; x < 100; x++) {
*p++ = *s++;
}
void (*test_fastbus_cp2)(int fifo_addr, unsigned char * buf, int len, int * dummy) = (void *)FB2ADDR;
while (1) {
while (state != 1) ;
for (x = 64; x < 128; x++) {
WRITE_PERI_REG(UART_FIFO_REG(1), x ^ xor);
}
while (state != 2);
test_fastbus_cp2(UART_FIFO_REG(1), &res[64], 64, &dummy);
}
}
// TODO: split this thing into separate orthogonal tests
TEST_CASE("Fast I/O bus test", "[hw][ignore]")
{
int i;
if ((REG_UART_BASE(0) >> 16) != 0x3ff4) {
printf("Error! Uart base isn't on fast bus.\n");
TEST_ASSERT(0);
}
gpio_pullup_dis(10);
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA2_U, FUNC_SD_DATA2_U1RXD);
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA3_U, FUNC_SD_DATA3_U1TXD);
int reg_val = (1 << UART_RXFIFO_FULL_THRHD_S);
WRITE_PERI_REG(UART_CONF1_REG(1), reg_val);
WRITE_PERI_REG(UART_CLKDIV_REG(1), 0x30); //semi-random
// CLEAR_PERI_REG_MASK(UART_INT_ENA_REG(1), UART_TXFIFO_EMPTY_INT_ENA|UART_RXFIFO_TOUT_INT_ENA);
TaskHandle_t th[2];
printf("Creating tasks\n");
xTaskCreatePinnedToCore(tskOne , "tskone" , 2048, NULL, 3, &th[0], 0);
xTaskCreatePinnedToCore(tskTwo , "tsktwo" , 2048, NULL, 3, &th[1], 1);
// Let stuff run for 20s
while (1) {
vTaskDelay(20000 / portTICK_PERIOD_MS);
}
//Shut down all the tasks
for (i = 0; i < 2; i++) {
vTaskDelete(th[i]);
}
xt_ints_off(1 << ETS_UART0_INUM);
}
#endif // CONFIG_IDF_TARGET_ESP32

38
components/esp_hw_support/test/test_fastbus_asm.S
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@ -1,38 +0,0 @@
#include "sdkconfig.h"
#if CONFIG_IDF_TARGET_ESP32
/*
This little bit of code is executed in-place by one CPU, but copied to a different memory region
by the other CPU. Make sure it stays position-independent.
*/
.text
.align 4
.global test_fastbus_cp
.type test_fastbus_cp,@function
//Args:
//a2 - fifo addr
//a3 - buf addr
//a4 - len
//a5 - ptr to int to use
test_fastbus_cp:
entry a1,64
back:
beqi a4, 0, out //check if loop done
s32i a4, a5, 0 //store value, for shits and/or giggles
memw //make sure write happens
l32i a4, a5, 0 //load value again, to thwart any prediction in the pipeline
bbsi a4, 0, pred //Random jump to check predictive reads. Both branches should do the same.
l32i a6, a2, 0 //read from fifo 1
j predout
pred:
l32i a6, a2, 0 //read from fifo 2
predout:
s8i a6, a3, 0 //store result
addi a3, a3, 1 //inc ptr
addi a4, a4, -1 //next
j back //loop again
out:
retw //and we are done
#endif // CONFIG_IDF_TARGET_ESP32

32
components/esp_hw_support/test/test_tsens.c
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@ -1,32 +0,0 @@
/*
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "sdkconfig.h"
#if CONFIG_IDF_TARGET_ESP32
#include <stdio.h>
#include "unity.h"
#include "esp_rom_sys.h"
#include "soc/rtc_periph.h"
#include "soc/sens_periph.h"
TEST_CASE("can control TSENS using registers", "[rtc][ignore]")
{
SET_PERI_REG_BITS(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_SAR, 3, SENS_FORCE_XPD_SAR_S);
SET_PERI_REG_BITS(SENS_SAR_TSENS_CTRL_REG, SENS_TSENS_CLK_DIV, 10, SENS_TSENS_CLK_DIV_S);
CLEAR_PERI_REG_MASK(SENS_SAR_TSENS_CTRL_REG, SENS_TSENS_POWER_UP);
CLEAR_PERI_REG_MASK(SENS_SAR_TSENS_CTRL_REG, SENS_TSENS_DUMP_OUT);
SET_PERI_REG_MASK(SENS_SAR_TSENS_CTRL_REG, SENS_TSENS_POWER_UP_FORCE);
SET_PERI_REG_MASK(SENS_SAR_TSENS_CTRL_REG, SENS_TSENS_POWER_UP);
esp_rom_delay_us(100);
SET_PERI_REG_MASK(SENS_SAR_TSENS_CTRL_REG, SENS_TSENS_DUMP_OUT);
esp_rom_delay_us(5);
int res = GET_PERI_REG_BITS2(SENS_SAR_SLAVE_ADDR3_REG, SENS_TSENS_OUT, SENS_TSENS_OUT_S);
printf("res=%d\n", res);
}
#endif // CONFIG_IDF_TARGET_ESP32

210
components/esp_hw_support/test/test_unal_dma.c
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@ -1,210 +0,0 @@
/*
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "sdkconfig.h"
#if CONFIG_IDF_TARGET_ESP32
#include <esp_types.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "esp32/rom/lldesc.h"
#include "esp_private/periph_ctrl.h"
#include "hal/gpio_hal.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/semphr.h"
#include "freertos/queue.h"
#include "freertos/xtensa_api.h"
#include "unity.h"
#include "soc/dport_reg.h"
#include "soc/gpio_periph.h"
#include "soc/i2s_periph.h"
#define DPORT_I2S0_CLK_EN (BIT(4))
#define DPORT_I2S0_RST (BIT(4))
static volatile lldesc_t dmaDesc[2];
//hacked up routine to essentially do a memcpy() using dma. Supports max 4K-1 bytes.
static void dmaMemcpy(void *in, void *out, int len)
{
volatile int i;
periph_module_enable(PERIPH_I2S0_MODULE);
//Init pins to i2s functions
SET_PERI_REG_MASK(GPIO_ENABLE_W1TS_REG, (1 << 11) | (1 << 3) | (1 << 0) | (1 << 2) | (1 << 5) | (1 << 16) | (1 << 17) | (1 << 18) | (1 << 19) | (1 << 20)); //ENABLE GPIO oe_enable
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO0_U, 0);
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO2_U, 0);
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO5_U, 0);
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO16_U, 0);
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO17_U, 0);
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO18_U, 0);
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO19_U, 0);
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO20_U, 0);
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_CMD_U, 2); //11
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO26_U, 0); //RS
WRITE_PERI_REG(GPIO_FUNC0_OUT_SEL_CFG_REG, (148 << GPIO_FUNC0_OUT_SEL_S));
WRITE_PERI_REG(GPIO_FUNC2_OUT_SEL_CFG_REG, (149 << GPIO_FUNC0_OUT_SEL_S));
WRITE_PERI_REG(GPIO_FUNC5_OUT_SEL_CFG_REG, (150 << GPIO_FUNC0_OUT_SEL_S));
WRITE_PERI_REG(GPIO_FUNC16_OUT_SEL_CFG_REG, (151 << GPIO_FUNC0_OUT_SEL_S));
WRITE_PERI_REG(GPIO_FUNC17_OUT_SEL_CFG_REG, (152 << GPIO_FUNC0_OUT_SEL_S));
WRITE_PERI_REG(GPIO_FUNC18_OUT_SEL_CFG_REG, (153 << GPIO_FUNC0_OUT_SEL_S));
WRITE_PERI_REG(GPIO_FUNC19_OUT_SEL_CFG_REG, (154 << GPIO_FUNC0_OUT_SEL_S));
WRITE_PERI_REG(GPIO_FUNC20_OUT_SEL_CFG_REG, (155 << GPIO_FUNC0_OUT_SEL_S));
WRITE_PERI_REG(GPIO_FUNC26_OUT_SEL_CFG_REG, (156 << GPIO_FUNC0_OUT_SEL_S)); //RS
WRITE_PERI_REG(GPIO_FUNC11_OUT_SEL_CFG_REG, (I2S0O_WS_OUT_IDX << GPIO_FUNC0_OUT_SEL_S));
// WRITE_PERI_REG(GPIO_FUNC11_OUT_SEL_CFG, (I2S0O_BCK_OUT_IDX<<GPIO_GPIO_FUNC0_OUT_SEL_S));
//GPIO_SET_GPIO_FUNC11_OUT_INV_SEL(1); //old
WRITE_PERI_REG(GPIO_FUNC11_OUT_SEL_CFG_REG, READ_PERI_REG(GPIO_FUNC11_OUT_SEL_CFG_REG) | GPIO_FUNC11_OUT_INV_SEL);
//Reset I2S subsystem
CLEAR_PERI_REG_MASK(I2S_CONF_REG(0), I2S_RX_RESET | I2S_TX_RESET);
SET_PERI_REG_MASK(I2S_CONF_REG(0), I2S_RX_RESET | I2S_TX_RESET);
CLEAR_PERI_REG_MASK(I2S_CONF_REG(0), I2S_RX_RESET | I2S_TX_RESET);
WRITE_PERI_REG(I2S_CONF_REG(0), 0);//I2S_I2S_SIG_LOOPBACK);
WRITE_PERI_REG(I2S_CONF2_REG(0), 0);
WRITE_PERI_REG(I2S_SAMPLE_RATE_CONF_REG(0),
(16 << I2S_RX_BITS_MOD_S) |
(16 << I2S_TX_BITS_MOD_S) |
(1 << I2S_RX_BCK_DIV_NUM_S) |
(1 << I2S_TX_BCK_DIV_NUM_S));
WRITE_PERI_REG(I2S_CLKM_CONF_REG(0),
I2S_CLKA_ENA | I2S_CLK_EN |
(1 << I2S_CLKM_DIV_A_S) |
(1 << I2S_CLKM_DIV_B_S) |
(1 << I2S_CLKM_DIV_NUM_S));
WRITE_PERI_REG(I2S_FIFO_CONF_REG(0),
(32 << I2S_TX_DATA_NUM_S) | //Low watermark for IRQ
(32 << I2S_RX_DATA_NUM_S));
WRITE_PERI_REG(I2S_CONF1_REG(0), I2S_RX_PCM_BYPASS | I2S_TX_PCM_BYPASS);
WRITE_PERI_REG(I2S_CONF_CHAN_REG(0), (2 << I2S_TX_CHAN_MOD_S) | (2 << I2S_RX_CHAN_MOD_S));
//Invert WS to active-low
SET_PERI_REG_MASK(I2S_CONF_REG(0), I2S_TX_RIGHT_FIRST | I2S_RX_RIGHT_FIRST);
WRITE_PERI_REG(I2S_TIMING_REG(0), 0);
//--
//Fill DMA descriptor
dmaDesc[0].length = len;
dmaDesc[0].size = len;
dmaDesc[0].owner = 1;
dmaDesc[0].sosf = 0;
dmaDesc[0].buf = (uint8_t *)in;
dmaDesc[0].offset = 0; //unused in hw
dmaDesc[0].empty = 0;
dmaDesc[0].eof = 1;
dmaDesc[1].length = len;
dmaDesc[1].size = len;
dmaDesc[1].owner = 1;
dmaDesc[1].sosf = 0;
dmaDesc[1].buf = (uint8_t *)out;
dmaDesc[1].offset = 0; //unused in hw
dmaDesc[1].empty = 0;
dmaDesc[1].eof = 1;
//Reset DMA
SET_PERI_REG_MASK(I2S_LC_CONF_REG(0), I2S_IN_RST | I2S_OUT_RST | I2S_AHBM_RST | I2S_AHBM_FIFO_RST);
CLEAR_PERI_REG_MASK(I2S_LC_CONF_REG(0), I2S_IN_RST | I2S_OUT_RST | I2S_AHBM_RST | I2S_AHBM_FIFO_RST);
//Reset I2S FIFO
SET_PERI_REG_MASK(I2S_CONF_REG(0), I2S_RX_RESET | I2S_TX_RESET | I2S_TX_FIFO_RESET | I2S_RX_FIFO_RESET);
CLEAR_PERI_REG_MASK(I2S_CONF_REG(0), I2S_RX_RESET | I2S_TX_RESET | I2S_TX_FIFO_RESET | I2S_RX_FIFO_RESET);
//Set desc addr
CLEAR_PERI_REG_MASK(I2S_OUT_LINK_REG(0), I2S_OUTLINK_ADDR);
SET_PERI_REG_MASK(I2S_OUT_LINK_REG(0), ((uint32_t)(&dmaDesc[0]))&I2S_OUTLINK_ADDR);
CLEAR_PERI_REG_MASK(I2S_IN_LINK_REG(0), I2S_INLINK_ADDR);
SET_PERI_REG_MASK(I2S_IN_LINK_REG(0), ((uint32_t)(&dmaDesc[1]))&I2S_INLINK_ADDR);
SET_PERI_REG_MASK(I2S_FIFO_CONF_REG(0), I2S_DSCR_EN); //Enable DMA mode
WRITE_PERI_REG(I2S_RXEOF_NUM_REG(0), len);
//Enable and configure DMA
WRITE_PERI_REG(I2S_LC_CONF_REG(0), I2S_OUT_DATA_BURST_EN |
I2S_OUT_EOF_MODE | I2S_OUTDSCR_BURST_EN | I2S_OUT_DATA_BURST_EN |
I2S_INDSCR_BURST_EN | I2S_MEM_TRANS_EN);
//Start transmission
SET_PERI_REG_MASK(I2S_OUT_LINK_REG(0), I2S_OUTLINK_START);
SET_PERI_REG_MASK(I2S_IN_LINK_REG(0), I2S_INLINK_START);
SET_PERI_REG_MASK(I2S_CONF_REG(0), I2S_TX_START | I2S_RX_START);
//Clear int flags
WRITE_PERI_REG(I2S_INT_CLR_REG(0), 0xFFFFFFFF);
//--
//No need to finish if no DMA transfer going on
if (!(READ_PERI_REG(I2S_FIFO_CONF_REG(0))&I2S_DSCR_EN)) {
return;
}
//Wait till fifo done
while (!(READ_PERI_REG(I2S_INT_RAW_REG(0))&I2S_TX_REMPTY_INT_RAW)) ;
//Wait for last bytes to leave i2s xmit thing
//ToDo: poll bit in next hw
for (i = 0; i < (1 << 8); i++);
while (!(READ_PERI_REG(I2S_STATE_REG(0))&I2S_TX_IDLE));
//Reset I2S for next transfer
CLEAR_PERI_REG_MASK(I2S_CONF_REG(0), I2S_TX_START | I2S_RX_START);
CLEAR_PERI_REG_MASK(I2S_OUT_LINK_REG(0), I2S_OUTLINK_START | I2S_INLINK_START);
SET_PERI_REG_MASK(I2S_CONF_REG(0), I2S_TX_RESET | I2S_TX_FIFO_RESET | I2S_RX_RESET | I2S_RX_FIFO_RESET);
CLEAR_PERI_REG_MASK(I2S_CONF_REG(0), I2S_TX_RESET | I2S_TX_FIFO_RESET | I2S_RX_RESET | I2S_RX_FIFO_RESET);
// for (i=0; i<(1<<8); i++);
while ((READ_PERI_REG(I2S_STATE_REG(0))&I2S_TX_FIFO_RESET_BACK));
}
int mymemcmp(char *a, char *b, int len)
{
int x;
for (x = 0; x < len; x++) {
if (a[x] != b[x]) {
printf("Not equal at byte %d. a=%x, b=%x\n", x, (int)a[x], (int)b[x]);
return 1;
}
}
return 0;
}
TEST_CASE("Unaligned DMA test (needs I2S)", "[hw][ignore]")
{
int x;
char src[2049], dest[2049];
for (x = 0; x < sizeof(src); x++) {
src[x] = x & 0xff;
}
printf("Aligned dma\n");
memset(dest, 0, 2049);
dmaMemcpy(src, dest, 2048 + 1);
TEST_ASSERT(mymemcmp(src, dest, 2048) == 0);
printf("Src unaligned\n");
dmaMemcpy(src + 1, dest, 2048 + 1);
TEST_ASSERT(mymemcmp(src + 1, dest, 2048) == 0);
printf("Dst unaligned\n");
dmaMemcpy(src, dest + 1, 2048 + 2);
TEST_ASSERT(mymemcmp(src, dest + 1, 2048) == 0);
}
#endif // CONFIG_IDF_TARGET_ESP32

2
components/esp_hw_support/test_apps/dma/sdkconfig.ci.release
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@ -1,4 +1,4 @@
# set compilier optimization level
# set compiler optimization level
CONFIG_COMPILER_OPTIMIZATION_SIZE=y
CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y

11
components/esp_hw_support/test_apps/esp_hw_support_unity_tests/CMakeLists.txt 100644
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@ -0,0 +1,11 @@
# This is the project CMakeLists.txt file for the test subproject
cmake_minimum_required(VERSION 3.16)
set(COMPONENTS main)
set(EXTRA_COMPONENT_DIRS "$ENV{IDF_PATH}/tools/unit-test-app/components")
set(SDKCONFIG_DEFAULTS "$ENV{IDF_PATH}/tools/test_apps/configs/sdkconfig.debug_helpers")
list(APPEND SDKCONFIG_DEFAULTS "sdkconfig.defaults")
include($ENV{IDF_PATH}/tools/cmake/project.cmake)
project(esp_hw_support_unity)

2
components/esp_hw_support/test_apps/esp_hw_support_unity_tests/README.md 100644
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@ -0,0 +1,2 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- |

12
components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/CMakeLists.txt 100644
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@ -0,0 +1,12 @@
set(srcs "test_app_main.c"
"test_dport.c"
"test_fp.c"
"test_intr_alloc.c"
"test_dport_xt_highint5.S"
)
# In order for the cases defined by `TEST_CASE` to be linked into the final elf,
# the component can be registered as WHOLE_ARCHIVE
idf_component_register(SRCS ${srcs}
REQUIRES unity driver test_utils efuse
WHOLE_ARCHIVE)

75
components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_app_main.c 100644
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@ -0,0 +1,75 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "unity.h"
#include "unity_test_runner.h"
#include "esp_heap_caps.h"
#include "esp_log.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "test_config.h"
#ifdef CONFIG_HEAP_TRACING
#include "memory_checks.h"
#include "esp_heap_trace.h"
#endif
#define TEST_MEMORY_LEAK_THRESHOLD_DEFAULT -400
static int leak_threshold = TEST_MEMORY_LEAK_THRESHOLD_DEFAULT;
void set_leak_threshold(int threshold)
{
leak_threshold = threshold;
}
static size_t before_free_8bit;
static size_t before_free_32bit;
static const char* TAG = "esp_hw_support_test_app";
static void check_leak(size_t before_free, size_t after_free, const char *type)
{
ssize_t delta = after_free - before_free;
printf("MALLOC_CAP_%s: Before %u bytes free, After %u bytes free (delta %d)\n", type, before_free, after_free, delta);
TEST_ASSERT_MESSAGE(delta >= leak_threshold, "memory leak");
}
void setUp(void)
{
// If heap tracing is enabled in kconfig, leak trace the test
#ifdef CONFIG_HEAP_TRACING
setup_heap_record();
heap_trace_start(HEAP_TRACE_LEAKS);
#endif
leak_threshold = TEST_MEMORY_LEAK_THRESHOLD_DEFAULT;
before_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT);
before_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT);
}
void tearDown(void)
{
/*Give idle task time to clean up*/
vTaskDelay(10);
#ifdef CONFIG_HEAP_TRACING
heap_trace_stop();
heap_trace_dump();
#endif
size_t after_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT);
size_t after_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT);
check_leak(before_free_8bit, after_free_8bit, "8BIT");
check_leak(before_free_32bit, after_free_32bit, "32BIT");
}
void app_main(void)
{
vTaskPrioritySet(NULL, TEST_TASK_PRIORITY);
ESP_LOGI(TAG, "Running esp-hw-support test app");
unity_run_menu();
}

9
components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_config.h 100644
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@ -0,0 +1,9 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Unlicense OR CC0-1.0
*/
#pragma once
#define TEST_TASK_PRIORITY 5

30
components/esp_hw_support/test/test_dport.c → components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_dport.c
Wyświetl plik

@ -8,6 +8,7 @@
#if CONFIG_IDF_TARGET_ESP32
#include <stdio.h>
#include <stdlib.h>
#include <inttypes.h>
#include "xtensa/core-macros.h"
#include "xtensa/hal.h"
#include "esp_types.h"
@ -28,7 +29,8 @@
#include "soc/rtc.h"
#include "esp_cpu.h"
#include "esp_intr_alloc.h"
#include "esp_task.h"
#include "test_config.h"
#define MHZ (1000000)
static volatile bool exit_flag;
@ -91,15 +93,15 @@ void run_tasks(const char *task1_description, void (* task1_func)(void *), const
#ifndef CONFIG_FREERTOS_UNICORE
printf("assign task accessing DPORT to core 0 and task accessing APB to core 1\n");
if(task1_func != NULL) xTaskCreatePinnedToCore(task1_func, task1_description, 2048, &exit_sema[0], UNITY_FREERTOS_PRIORITY - 1, &th[0], 0);
if(task2_func != NULL) xTaskCreatePinnedToCore(task2_func, task2_description, 2048, &exit_sema[1], UNITY_FREERTOS_PRIORITY - 1, &th[1], 1);
if(task1_func != NULL) xTaskCreatePinnedToCore(task1_func, task1_description, 2048, &exit_sema[0], TEST_TASK_PRIORITY - 1, &th[0], 0);
if(task2_func != NULL) xTaskCreatePinnedToCore(task2_func, task2_description, 2048, &exit_sema[1], TEST_TASK_PRIORITY - 1, &th[1], 1);
#else
printf("assign task accessing DPORT and accessing APB\n");
if(task1_func != NULL) xTaskCreate(task1_func, task1_description, 2048, &exit_sema[0], UNITY_FREERTOS_PRIORITY - 1, &th[0]);
if(task2_func != NULL) xTaskCreate(task2_func, task2_description, 2048, &exit_sema[1], UNITY_FREERTOS_PRIORITY - 1, &th[1]);
if(task1_func != NULL) xTaskCreate(task1_func, task1_description, 2048, &exit_sema[0], TEST_TASK_PRIORITY - 1, &th[0]);
if(task2_func != NULL) xTaskCreate(task2_func, task2_description, 2048, &exit_sema[1], TEST_TASK_PRIORITY - 1, &th[1]);
#endif
printf("start wait for %d seconds [Test %s and %s]\n", delay_ms/1000, task1_description, task2_description);
printf("start wait for %"PRIu32" seconds [Test %s and %s]\n", delay_ms/1000, task1_description, task2_description);
vTaskDelay(delay_ms / portTICK_PERIOD_MS);
// set exit flag to let thread exit
@ -131,7 +133,7 @@ void run_tasks_with_change_freq_cpu(int cpu_freq_mhz)
rtc_cpu_freq_config_t old_config;
rtc_clk_cpu_freq_get_config(&old_config);
printf("CPU_FREQ = %d MHz\n", old_config.freq_mhz);
printf("CPU_FREQ = %"PRIu32" MHz\n", old_config.freq_mhz);
if (cpu_freq_mhz != old_config.freq_mhz) {
rtc_cpu_freq_config_t new_config;
@ -281,16 +283,16 @@ TEST_CASE("test for DPORT access performance", "[esp32]")
printf("\nPerformance table: \n"
"The number of simultaneous read operations of the APB and DPORT registers\n"
"by different methods for %d seconds.\n", delay_ms/1000);
"by different methods for %"PRIu32" seconds.\n", delay_ms/1000);
printf("+-----------------------+----------+----------+----------+\n");
printf("| Method read DPORT | DPORT | APB | SUMM |\n");
printf("+-----------------------+----------+----------+----------+\n");
printf("|1.Only accessAPB |%10d|%10d|%10d|\n", t[0].dport, t[0].apb, t[0].summ);
printf("|2.Only STALL_OTHER_CPU |%10d|%10d|%10d|\n", t[1].dport, t[1].apb, t[1].summ);
printf("|3.Only PRE_READ_APB_REG|%10d|%10d|%10d|\n", t[2].dport, t[2].apb, t[2].summ);
printf("|1.Only accessAPB |%10"PRIu32"|%10"PRIu32"|%10"PRIu32"|\n", t[0].dport, t[0].apb, t[0].summ);
printf("|2.Only STALL_OTHER_CPU |%10"PRIu32"|%10"PRIu32"|%10"PRIu32"|\n", t[1].dport, t[1].apb, t[1].summ);
printf("|3.Only PRE_READ_APB_REG|%10"PRIu32"|%10"PRIu32"|%10"PRIu32"|\n", t[2].dport, t[2].apb, t[2].summ);
printf("+-----------------------+----------+----------+----------+\n");
printf("|4.STALL_OTHER_CPU |%10d|%10d|%10d|\n", t[3].dport, t[3].apb, t[3].summ);
printf("|5.PRE_READ_APB_REG |%10d|%10d|%10d|\n", t[4].dport, t[4].apb, t[4].summ);
printf("|4.STALL_OTHER_CPU |%10"PRIu32"|%10"PRIu32"|%10"PRIu32"|\n", t[3].dport, t[3].apb, t[3].summ);
printf("|5.PRE_READ_APB_REG |%10"PRIu32"|%10"PRIu32"|%10"PRIu32"|\n", t[4].dport, t[4].apb, t[4].summ);
printf("+-----------------------+----------+----------+----------+\n");
printf("| ratio=PRE_READ/STALL |%10f|%10f|%10f|\n", (float)t[4].dport/t[3].dport, (float)t[4].apb/t[3].apb, (float)t[4].summ/t[3].summ);
printf("+-----------------------+----------+----------+----------+\n");
@ -306,7 +308,7 @@ static uint32_t start, end;
#define BENCHMARK_END(OPERATION) do { \
RSR(CCOUNT, end); \
printf("%s took %d cycles/op (%d cycles for %d ops)\n", \
printf("%s took %"PRIu32" cycles/op (%"PRIu32" cycles for %d ops)\n", \
OPERATION, (end - start)/REPEAT_OPS, \
(end - start), REPEAT_OPS); \
} while(0)

5
components/esp_hw_support/test/test_dport_xt_highint5.S → components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_dport_xt_highint5.S
Wyświetl plik

@ -1,3 +1,8 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Unlicense OR CC0-1.0
*/
#include "sdkconfig.h"
#if CONFIG_IDF_TARGET_ESP32

0
components/esp_hw_support/test/test_ds.c → components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_ds.c
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11
components/esp_hw_support/test/test_fp.c → components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_fp.c
Wyświetl plik

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -227,11 +227,17 @@ float IRAM_ATTR test_fp_benchmark_fp_divide(int counts, unsigned *cycles)
return f;
}
extern void set_leak_threshold(int threshold);
TEST_CASE("floating point division performance", "[fp]")
{
const unsigned COUNTS = 1000;
unsigned cycles = 0;
/*From lazy allocating resources when printing floats*/
set_leak_threshold(-850);
// initialize fpu
volatile __attribute__((unused)) float dummy = sqrtf(rand());
@ -265,6 +271,9 @@ TEST_CASE("floating point square root performance", "[fp]")
const unsigned COUNTS = 200;
unsigned cycles = 0;
/*From lazy allocating resources when printing floats*/
set_leak_threshold(-850);
// initialize fpu
volatile float __attribute__((unused)) dummy = sqrtf(rand());

0
components/esp_hw_support/test/test_intr_alloc.c → components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_intr_alloc.c
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21
components/esp_hw_support/test_apps/esp_hw_support_unity_tests/pytest_esp_hw_support.py 100644
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@ -0,0 +1,21 @@
# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
# SPDX-License-Identifier: CC0-1.0
import pytest
from pytest_embedded import Dut
@pytest.mark.generic
@pytest.mark.parametrize(
'config',
[
pytest.param('single_core_esp32', marks=[pytest.mark.esp32]),
pytest.param('default', marks=[pytest.mark.supported_targets]),
pytest.param('release', marks=[pytest.mark.supported_targets]),
],
indirect=True,
)
def test_esp_hw_support(dut: Dut) -> None:
dut.expect_exact('Press ENTER to see the list of tests')
dut.write('![ignore]')
dut.expect_unity_test_output(timeout=120)

1
components/esp_hw_support/test_apps/esp_hw_support_unity_tests/sdkconfig.ci.default 100644
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@ -0,0 +1 @@
# Empty file to be able to parametrize "default" config

6
components/esp_hw_support/test_apps/esp_hw_support_unity_tests/sdkconfig.ci.release 100644
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@ -0,0 +1,6 @@
# set compiler optimization level
CONFIG_COMPILER_OPTIMIZATION_SIZE=y
CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y
# we can silent the assertion to save the binary footprint
CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y

2
components/esp_hw_support/test_apps/esp_hw_support_unity_tests/sdkconfig.ci.single_core_esp32 100644
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@ -0,0 +1,2 @@
CONFIG_IDF_TARGET="esp32"
CONFIG_FREERTOS_UNICORE=y

2
components/esp_hw_support/test_apps/esp_hw_support_unity_tests/sdkconfig.defaults 100644
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@ -0,0 +1,2 @@
CONFIG_ESP_TASK_WDT_INIT=n
CONFIG_ESP_MAIN_TASK_STACK_SIZE=8192

2
components/esp_hw_support/test_apps/esp_hw_support_unity_tests/sdkconfig.defaults.esp32 100644
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@ -0,0 +1,2 @@
# Set CPU frequency to max for performance tests
# CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240=y

2
components/esp_hw_support/test_apps/esp_hw_support_unity_tests/sdkconfig.defaults.esp32s2 100644
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@ -0,0 +1,2 @@
# Set CPU frequency to max for performance tests
CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240=y

11
components/esp_hw_support/test_apps/rtc_clk/CMakeLists.txt 100644
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@ -0,0 +1,11 @@
# This is the project CMakeLists.txt file for the test subproject
cmake_minimum_required(VERSION 3.16)
set(COMPONENTS main)
set(EXTRA_COMPONENT_DIRS "$ENV{IDF_PATH}/tools/unit-test-app/components")
set(SDKCONFIG_DEFAULTS "$ENV{IDF_PATH}/tools/test_apps/configs/sdkconfig.debug_helpers")
list(APPEND SDKCONFIG_DEFAULTS "sdkconfig.defaults")
include($ENV{IDF_PATH}/tools/cmake/project.cmake)
project(rtc_clk)

2
components/esp_hw_support/test_apps/rtc_clk/README.md 100644
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@ -0,0 +1,2 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- |

8
components/esp_hw_support/test_apps/rtc_clk/main/CMakeLists.txt 100644
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@ -0,0 +1,8 @@
set(srcs "test_app_main.c"
"test_rtc_clk.c")
# In order for the cases defined by `TEST_CASE` to be linked into the final elf,
# the component can be registered as WHOLE_ARCHIVE
idf_component_register(SRCS ${srcs}
REQUIRES unity driver test_utils
WHOLE_ARCHIVE)

67
components/esp_hw_support/test_apps/rtc_clk/main/test_app_main.c 100644
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@ -0,0 +1,67 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "unity.h"
#include "unity_test_runner.h"
#include "esp_heap_caps.h"
#include "esp_log.h"
#ifdef CONFIG_HEAP_TRACING
#include "memory_checks.h"
#include "esp_heap_trace.h"
#endif
#define TEST_MEMORY_LEAK_THRESHOLD_DEFAULT -300
static int leak_threshold = TEST_MEMORY_LEAK_THRESHOLD_DEFAULT;
void set_leak_threshold(int threshold)
{
leak_threshold = threshold;
}
static size_t before_free_8bit;
static size_t before_free_32bit;
static const char* TAG = "esp_hw_support_test_app";
static void check_leak(size_t before_free, size_t after_free, const char *type)
{
ssize_t delta = after_free - before_free;
printf("MALLOC_CAP_%s: Before %u bytes free, After %u bytes free (delta %d)\n", type, before_free, after_free, delta);
TEST_ASSERT_MESSAGE(delta >= leak_threshold, "memory leak");
}
void setUp(void)
{
// If heap tracing is enabled in kconfig, leak trace the test
#ifdef CONFIG_HEAP_TRACING
setup_heap_record();
heap_trace_start(HEAP_TRACE_LEAKS);
#endif
leak_threshold = TEST_MEMORY_LEAK_THRESHOLD_DEFAULT;
before_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT);
before_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT);
}
void tearDown(void)
{
#ifdef CONFIG_HEAP_TRACING
heap_trace_stop();
heap_trace_dump();
#endif
size_t after_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT);
size_t after_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT);
check_leak(before_free_8bit, after_free_8bit, "8BIT");
check_leak(before_free_32bit, after_free_32bit, "32BIT");
}
void app_main(void)
{
ESP_LOGI(TAG, "Running esp-hw-support test app");
unity_run_menu();
}

37
components/esp_hw_support/test/test_rtc_clk.c → components/esp_hw_support/test_apps/rtc_clk/main/test_rtc_clk.c
Wyświetl plik

@ -4,6 +4,7 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdio.h>
#include <inttypes.h>
#include "unity.h"
#include "esp_attr.h"
@ -16,14 +17,13 @@
#include "soc/gpio_periph.h"
#include "hal/gpio_ll.h"
#include "driver/rtc_io.h"
#include "test_utils.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/semphr.h"
#include "esp_rom_gpio.h"
#include "esp_rom_sys.h"
#include "esp_rom_uart.h"
#include "test_utils.h"
#include "esp_sleep.h"
#include "esp_system.h"
#include "esp_private/esp_clk.h"
@ -136,18 +136,18 @@ static void pull_out_clk(int sel)
REG_SET_FIELD(RTC_IO_RTC_DEBUG_SEL_REG, RTC_IO_DEBUG_SEL0, sel);
}
TEST_CASE("Output 150k clock to GPIO25", "[rtc_clk][ignore]")
TEST_CASE("Output 150k clock to GPIO25", "[ignore]")
{
pull_out_clk(RTC_IO_DEBUG_SEL0_150K_OSC);
}
TEST_CASE("Output 32k XTAL clock to GPIO25", "[rtc_clk][ignore]")
TEST_CASE("Output 32k XTAL clock to GPIO25", "[ignore]")
{
rtc_clk_32k_enable(true);
pull_out_clk(RTC_IO_DEBUG_SEL0_32K_XTAL);
}
TEST_CASE("Output 8M XTAL clock to GPIO25", "[rtc_clk][ignore]")
TEST_CASE("Output 8M XTAL clock to GPIO25", "[ignore]")
{
rtc_clk_8m_enable(true, true);
SET_PERI_REG_MASK(RTC_IO_RTC_DEBUG_SEL_REG, RTC_IO_DEBUG_12M_NO_GATING);
@ -184,7 +184,7 @@ TEST_CASE("Calculate 8M clock frequency", "[rtc_clk]")
// calibrate 8M/256 clock against XTAL, get 8M/256 clock period
uint32_t rtc_8md256_period = rtc_clk_cal(RTC_CAL_8MD256, 100);
uint32_t rtc_fast_freq_hz = 1000000ULL * (1 << RTC_CLK_CAL_FRACT) * 256 / rtc_8md256_period;
printf("RTC_FAST_CLK=%d Hz\n", rtc_fast_freq_hz);
printf("RTC_FAST_CLK=%"PRIu32" Hz\n", rtc_fast_freq_hz);
TEST_ASSERT_INT32_WITHIN(650000, SOC_CLK_RC_FAST_FREQ_APPROX, rtc_fast_freq_hz);
}
@ -231,12 +231,12 @@ static void start_freq(soc_rtc_slow_clk_src_t required_src, uint32_t start_delay
stop_rtc_external_quartz();
#ifdef CONFIG_RTC_CLK_SRC_EXT_CRYS
uint32_t bootstrap_cycles = CONFIG_ESP_SYSTEM_RTC_EXT_XTAL_BOOTSTRAP_CYCLES;
printf("Test is started. Kconfig settings:\n External 32K crystal is selected,\n Oscillation cycles = %d,\n Calibration cycles = %d.\n",
printf("Test is started. Kconfig settings:\n External 32K crystal is selected,\n Oscillation cycles = %"PRIu32",\n Calibration cycles = %d.\n",
bootstrap_cycles,
CONFIG_RTC_CLK_CAL_CYCLES);
#else
uint32_t bootstrap_cycles = 5;
printf("Test is started. Kconfig settings:\n Internal RC is selected,\n Oscillation cycles = %d,\n Calibration cycles = %d.\n",
printf("Test is started. Kconfig settings:\n Internal RC is selected,\n Oscillation cycles = %"PRIu32",\n Calibration cycles = %d.\n",
bootstrap_cycles,
CONFIG_RTC_CLK_CAL_CYCLES);
#endif // CONFIG_RTC_CLK_SRC_EXT_CRYS
@ -253,7 +253,7 @@ static void start_freq(soc_rtc_slow_clk_src_t required_src, uint32_t start_delay
rtc_clk_select_rtc_slow_clk();
selected_src = rtc_clk_slow_src_get();
end_time = xTaskGetTickCount() * (1000 / configTICK_RATE_HZ);
printf(" [time=%d] ", (end_time - start_time) - start_delay_ms);
printf(" [time=%"PRIu32"] ", (end_time - start_time) - start_delay_ms);
if(selected_src != required_src){
printf("FAIL. Time measurement...");
fail = 1;
@ -276,7 +276,7 @@ static void start_freq(soc_rtc_slow_clk_src_t required_src, uint32_t start_delay
if(fail_measure == 0) {
printf("PASS");
}
printf(" [calibration val = %d] \n", esp_clk_slowclk_cal_get());
printf(" [calibration val = %"PRIu32"] \n", esp_clk_slowclk_cal_get());
stop_rtc_external_quartz();
esp_rom_delay_us(500000);
}
@ -284,7 +284,7 @@ static void start_freq(soc_rtc_slow_clk_src_t required_src, uint32_t start_delay
printf("Test passed successfully\n");
}
TEST_CASE("Test starting external RTC quartz", "[rtc_clk][test_env=UT_T1_32kXTAL]")
TEST_CASE("Test starting external RTC quartz", "[test_env=xtal32k]")
{
int i = 0, fail = 0;
uint32_t start_time;
@ -292,12 +292,12 @@ TEST_CASE("Test starting external RTC quartz", "[rtc_clk][test_env=UT_T1_32kXTAL
stop_rtc_external_quartz();
#ifdef CONFIG_RTC_CLK_SRC_EXT_CRYS
uint32_t bootstrap_cycles = CONFIG_ESP_SYSTEM_RTC_EXT_XTAL_BOOTSTRAP_CYCLES;
printf("Test is started. Kconfig settings:\n External 32K crystal is selected,\n Oscillation cycles = %d,\n Calibration cycles = %d.\n",
printf("Test is started. Kconfig settings:\n External 32K crystal is selected,\n Oscillation cycles = %"PRIu32",\n Calibration cycles = %d.\n",
bootstrap_cycles,
CONFIG_RTC_CLK_CAL_CYCLES);
#else
uint32_t bootstrap_cycles = 5;
printf("Test is started. Kconfig settings:\n Internal RC is selected,\n Oscillation cycles = %d,\n Calibration cycles = %d.\n",
printf("Test is started. Kconfig settings:\n Internal RC is selected,\n Oscillation cycles = %"PRIu32",\n Calibration cycles = %d.\n",
bootstrap_cycles,
CONFIG_RTC_CLK_CAL_CYCLES);
#endif // CONFIG_RTC_CLK_SRC_EXT_CRYS
@ -311,7 +311,7 @@ TEST_CASE("Test starting external RTC quartz", "[rtc_clk][test_env=UT_T1_32kXTAL
rtc_clk_32k_bootstrap(bootstrap_cycles);
rtc_clk_select_rtc_slow_clk();
end_time = xTaskGetTickCount() * (1000 / configTICK_RATE_HZ);
printf(" [time=%d] ", end_time - start_time);
printf(" [time=%"PRIu32"] ", end_time - start_time);
if((end_time - start_time) > TIMEOUT_TEST_MS){
printf("FAIL\n");
fail = 1;
@ -325,13 +325,13 @@ TEST_CASE("Test starting external RTC quartz", "[rtc_clk][test_env=UT_T1_32kXTAL
printf("Test passed successfully\n");
}
TEST_CASE("Test starting 'External 32kHz XTAL' on the board with it.", "[rtc_clk][test_env=UT_T1_32kXTAL]")
TEST_CASE("Test starting 'External 32kHz XTAL' on the board with it.", "[test_env=xtal32k]")
{
start_freq(SOC_RTC_SLOW_CLK_SRC_XTAL32K, 200);
start_freq(SOC_RTC_SLOW_CLK_SRC_XTAL32K, 0);
}
TEST_CASE("Test starting 'External 32kHz XTAL' on the board without it.", "[rtc_clk][test_env=UT_T1_no32kXTAL]")
TEST_CASE("Test starting 'External 32kHz XTAL' on the board without it.", "[test_env=noXtal32k]")
{
printf("Tries to start the 'External 32kHz XTAL' on the board without it. "
"Clock switching to 'Internal 150 kHz RC oscillator'.\n");
@ -378,8 +378,6 @@ TEST_CASE("Test rtc clk calibration compensation", "[rtc_clk]")
TEST_ASSERT_GREATER_THAN(t1, t2);
}
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3)
/* Disabled until deep sleep is brought up TODO ESP32-S3 IDF-2691 */
static RTC_NOINIT_ATTR int64_t start = 0;
static void trigger_deepsleep(void)
@ -429,7 +427,6 @@ static void check_time_deepsleep_2(void)
TEST_ASSERT_GREATER_THAN(start, end);
}
TEST_CASE_MULTIPLE_STAGES("Test rtc clk calibration compensation across deep sleep", "[rtc_clk][reset=DEEPSLEEP_RESET, DEEPSLEEP_RESET]", trigger_deepsleep, check_time_deepsleep_1, check_time_deepsleep_2);
TEST_CASE_MULTIPLE_STAGES("Test rtc clk calibration compensation across deep sleep", "", trigger_deepsleep, check_time_deepsleep_1, check_time_deepsleep_2);
#endif // !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3)
#endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2)

37
components/esp_hw_support/test_apps/rtc_clk/pytest_rtc_clk.py 100644
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@ -0,0 +1,37 @@
# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
# SPDX-License-Identifier: CC0-1.0
from typing import Any
import pytest
from pytest_embedded import Dut
@pytest.mark.generic
@pytest.mark.esp32
def test_rtc_clk(dut: Dut) -> None:
dut.expect_exact('Press ENTER to see the list of tests')
dut.write('[rtc_clk]')
dut.expect_unity_test_output()
@pytest.mark.esp32
@pytest.mark.xtal32k
def test_rtc_xtal32k(dut: Dut) -> None:
dut.expect_exact('Press ENTER to see the list of tests')
dut.write('[test_env=xtal32k]')
dut.expect_unity_test_output()
@pytest.mark.esp32
@pytest.mark.no32kXtal
def test_rtc_no_xtal32k(dut: Dut) -> None:
dut.expect_exact('Press ENTER to see the list of tests')
dut.write('[test_env=noXtal32k]')
dut.expect_unity_test_output()
@pytest.mark.generic
@pytest.mark.supported_targets
def test_rtc_calib(case_tester: Any) -> None:
case_tester.run_all_multi_stage_cases()

2
components/esp_hw_support/test_apps/rtc_clk/sdkconfig.defaults 100644
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@ -0,0 +1,2 @@
CONFIG_ESP_TASK_WDT_INIT=n
CONFIG_FREERTOS_HZ=1000

11
components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/CMakeLists.txt 100644
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@ -0,0 +1,11 @@
# This is the project CMakeLists.txt file for the test subproject
cmake_minimum_required(VERSION 3.16)
set(COMPONENTS main)
set(EXTRA_COMPONENT_DIRS "$ENV{IDF_PATH}/tools/unit-test-app/components")
set(SDKCONFIG_DEFAULTS "$ENV{IDF_PATH}/tools/test_apps/configs/sdkconfig.debug_helpers")
list(APPEND SDKCONFIG_DEFAULTS "sdkconfig.defaults")
include($ENV{IDF_PATH}/tools/cmake/project.cmake)
project(test_app_security_support)

2
components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/README.md 100644
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@ -0,0 +1,2 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- |

11
components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/main/CMakeLists.txt 100644
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@ -0,0 +1,11 @@
set(srcs "test_app_main.c"
"test_ds.c"
"test_hmac.c"
"test_random.c"
)
# In order for the cases defined by `TEST_CASE` to be linked into the final elf,
# the component can be registered as WHOLE_ARCHIVE
idf_component_register(SRCS ${srcs}
REQUIRES unity driver test_utils efuse
WHOLE_ARCHIVE)

0
components/esp_hw_support/test/digital_signature_test_cases_3072.h → components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/main/digital_signature_test_cases_3072.h
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0
components/esp_hw_support/test/digital_signature_test_cases_4096.h → components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/main/digital_signature_test_cases_4096.h
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0
components/esp_hw_support/test/gen_digital_signature_tests.py → components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/main/gen_digital_signature_tests.py
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75
components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/main/test_app_main.c 100644
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@ -0,0 +1,75 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "unity.h"
#include "unity_test_runner.h"
#include "esp_heap_caps.h"
#include "esp_log.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "test_config.h"
#ifdef CONFIG_HEAP_TRACING
#include "memory_checks.h"
#include "esp_heap_trace.h"
#endif
#define TEST_MEMORY_LEAK_THRESHOLD_DEFAULT -400
static int leak_threshold = TEST_MEMORY_LEAK_THRESHOLD_DEFAULT;
void set_leak_threshold(int threshold)
{
leak_threshold = threshold;
}
static size_t before_free_8bit;
static size_t before_free_32bit;
static const char* TAG = "esp_hw_support_test_app";
static void check_leak(size_t before_free, size_t after_free, const char *type)
{
ssize_t delta = after_free - before_free;
printf("MALLOC_CAP_%s: Before %u bytes free, After %u bytes free (delta %d)\n", type, before_free, after_free, delta);
TEST_ASSERT_MESSAGE(delta >= leak_threshold, "memory leak");
}
void setUp(void)
{
// If heap tracing is enabled in kconfig, leak trace the test
#ifdef CONFIG_HEAP_TRACING
setup_heap_record();
heap_trace_start(HEAP_TRACE_LEAKS);
#endif
leak_threshold = TEST_MEMORY_LEAK_THRESHOLD_DEFAULT;
before_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT);
before_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT);
}
void tearDown(void)
{
/*Give idle task time to clean up*/
vTaskDelay(10);
#ifdef CONFIG_HEAP_TRACING
heap_trace_stop();
heap_trace_dump();
#endif
size_t after_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT);
size_t after_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT);
check_leak(before_free_8bit, after_free_8bit, "8BIT");
check_leak(before_free_32bit, after_free_32bit, "32BIT");
}
void app_main(void)
{
vTaskPrioritySet(NULL, TEST_TASK_PRIORITY);
ESP_LOGI(TAG, "Running esp-hw-support test app");
unity_run_menu();
}

9
components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/main/test_config.h 100644
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@ -0,0 +1,9 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Unlicense OR CC0-1.0
*/
#pragma once
#define TEST_TASK_PRIORITY 5

443
components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/main/test_ds.c 100644
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@ -0,0 +1,443 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <string.h>
#include "unity.h"
#include "soc/soc_caps.h"
#if SOC_DIG_SIGN_SUPPORTED
#if CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/efuse.h"
#include "esp32s2/rom/digital_signature.h"
#include "esp32s2/rom/aes.h"
#include "esp32s2/rom/sha.h"
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rom/efuse.h"
#include "esp32c3/rom/digital_signature.h"
#include "esp32c3/rom/hmac.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/efuse.h"
#include "esp32s3/rom/digital_signature.h"
#include "esp32s3/rom/aes.h"
#include "esp32s3/rom/sha.h"
#endif
#include "esp_ds.h"
#define NUM_RESULTS 10
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
#define DS_MAX_BITS (4096)
#elif CONFIG_IDF_TARGET_ESP32C3
#define DS_MAX_BITS (ETS_DS_MAX_BITS)
#endif
typedef struct {
uint8_t iv[ETS_DS_IV_LEN];
ets_ds_p_data_t p_data;
uint8_t expected_c[ETS_DS_C_LEN];
uint8_t hmac_key_idx;
uint32_t expected_results[NUM_RESULTS][DS_MAX_BITS / 32];
} encrypt_testcase_t;
// Generated header digital_signature_test_cases_<bits>.h (by gen_digital_signature_tests.py) defines
// NUM_HMAC_KEYS, test_hmac_keys, NUM_MESSAGES, NUM_CASES, test_messages[], test_cases[]
// Some adaptations were made: removed the 512 bit case and changed RSA lengths to the enums from esp_ds.h
#if DS_MAX_BITS == 4096
#define RSA_LEN (ESP_DS_RSA_4096)
#include "digital_signature_test_cases_4096.h"
#elif DS_MAX_BITS == 3072
#define RSA_LEN (ESP_DS_RSA_3072)
#include "digital_signature_test_cases_3072.h"
#endif
_Static_assert(NUM_RESULTS == NUM_MESSAGES, "expected_results size should be the same as NUM_MESSAGES in generated header");
TEST_CASE("Digital Signature Parameter Encryption data NULL", "[hw_crypto] [ds]")
{
const char iv [32] = {0};
esp_ds_p_data_t p_data = {0};
const char key [32] = {0};
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_encrypt_params(NULL, iv, &p_data, key));
}
TEST_CASE("Digital Signature Parameter Encryption iv NULL", "[hw_crypto] [ds]")
{
esp_ds_data_t data = {0};
esp_ds_p_data_t p_data = {0};
const char key [32] = {0};
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_encrypt_params(&data, NULL, &p_data, key));
}
TEST_CASE("Digital Signature Parameter Encryption p_data NULL", "[hw_crypto] [ds]")
{
esp_ds_data_t data = {0};
const char iv [32] = {0};
const char key [32] = {0};
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_encrypt_params(&data, iv, NULL, key));
}
TEST_CASE("Digital Signature Parameter Encryption key NULL", "[hw_crypto] [ds]")
{
esp_ds_data_t data = {0};
const char iv [32] = {0};
esp_ds_p_data_t p_data = {0};
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_encrypt_params(&data, iv, &p_data, NULL));
}
TEST_CASE("Digital Signature Parameter Encryption", "[hw_crypto] [ds]")
{
for (int i = 0; i < NUM_CASES; i++) {
printf("Encrypting test case %d...\n", i);
const encrypt_testcase_t *t = &test_cases[i];
esp_ds_data_t result = { };
esp_ds_p_data_t p_data;
memcpy(p_data.Y, t->p_data.Y, DS_MAX_BITS / 8);
memcpy(p_data.M, t->p_data.M, DS_MAX_BITS / 8);
memcpy(p_data.Rb, t->p_data.Rb, DS_MAX_BITS / 8);
p_data.M_prime = t->p_data.M_prime;
p_data.length = t->p_data.length;
esp_err_t r = esp_ds_encrypt_params(&result, t->iv, &p_data,
test_hmac_keys[t->hmac_key_idx]);
printf("Encrypting test case %d done\n", i);
TEST_ASSERT_EQUAL(ESP_OK, r);
TEST_ASSERT_EQUAL(t->p_data.length, result.rsa_length);
TEST_ASSERT_EQUAL_HEX8_ARRAY(t->iv, result.iv, ETS_DS_IV_LEN);
TEST_ASSERT_EQUAL_HEX8_ARRAY(t->expected_c, result.c, ETS_DS_C_LEN);
}
}
TEST_CASE("Digital Signature start Invalid message", "[hw_crypto] [ds]")
{
esp_ds_data_t ds_data = { };
ds_data.rsa_length = RSA_LEN;
esp_ds_context_t *ctx;
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_start_sign(NULL, &ds_data, HMAC_KEY1, &ctx));
}
TEST_CASE("Digital Signature start Invalid data", "[hw_crypto] [ds]")
{
const char *message = "test";
esp_ds_context_t *ctx;
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_start_sign(message, NULL, HMAC_KEY1, &ctx));
}
TEST_CASE("Digital Signature start Invalid context", "[hw_crypto] [ds]")
{
esp_ds_data_t ds_data = {};
ds_data.rsa_length = RSA_LEN;
const char *message = "test";
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_start_sign(message, &ds_data, HMAC_KEY1, NULL));
}
TEST_CASE("Digital Signature RSA length 0", "[hw_crypto] [ds]")
{
esp_ds_data_t ds_data = {};
ds_data.rsa_length = 0;
const char *message = "test";
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_start_sign(message, &ds_data, HMAC_KEY1, NULL));
}
TEST_CASE("Digital Signature RSA length too long", "[hw_crypto] [ds]")
{
esp_ds_data_t ds_data = {};
ds_data.rsa_length = 128;
const char *message = "test";
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_start_sign(message, &ds_data, HMAC_KEY1, NULL));
}
TEST_CASE("Digital Signature start HMAC key out of range", "[hw_crypto] [ds]")
{
esp_ds_data_t ds_data = {};
ds_data.rsa_length = RSA_LEN;
esp_ds_context_t *ctx;
const char *message = "test";
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_start_sign(message, &ds_data, HMAC_KEY5 + 1, &ctx));
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_start_sign(message, &ds_data, HMAC_KEY0 - 1, &ctx));
}
TEST_CASE("Digital Signature finish Invalid signature ptr", "[hw_crypto] [ds]")
{
esp_ds_context_t *ctx = NULL;
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_finish_sign(NULL, ctx));
}
TEST_CASE("Digital Signature finish Invalid context", "[hw_crypto] [ds]")
{
uint8_t signature_data [128 * 4];
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_finish_sign(signature_data, NULL));
}
TEST_CASE("Digital Signature Blocking Invalid message", "[hw_crypto] [ds]")
{
esp_ds_data_t ds_data = { };
ds_data.rsa_length = RSA_LEN;
uint8_t signature_data [128 * 4];
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_sign(NULL, &ds_data, HMAC_KEY1, signature_data));
}
TEST_CASE("Digital Signature Blocking Invalid data", "[hw_crypto] [ds]")
{
const char *message = "test";
uint8_t signature_data [128 * 4];
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_sign(message, NULL, HMAC_KEY1, signature_data));
}
TEST_CASE("Digital Signature Blocking Invalid signature ptr", "[hw_crypto] [ds]")
{
esp_ds_data_t ds_data = {};
ds_data.rsa_length = RSA_LEN;
const char *message = "test";
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_sign(message, &ds_data, HMAC_KEY1, NULL));
}
TEST_CASE("Digital Signature Blocking RSA length 0", "[hw_crypto] [ds]")
{
esp_ds_data_t ds_data = {};
ds_data.rsa_length = 0;
const char *message = "test";
uint8_t signature_data [128 * 4];
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_sign(message, &ds_data, HMAC_KEY1, signature_data));
}
TEST_CASE("Digital Signature Blocking RSA length too long", "[hw_crypto] [ds]")
{
esp_ds_data_t ds_data = {};
ds_data.rsa_length = 128;
const char *message = "test";
uint8_t signature_data [128 * 4];
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_sign(message, &ds_data, HMAC_KEY1, signature_data));
}
TEST_CASE("Digital Signature Blocking HMAC key out of range", "[hw_crypto] [ds]")
{
esp_ds_data_t ds_data = {};
ds_data.rsa_length = 127;
const char *message = "test";
uint8_t signature_data [128 * 4];
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_sign(message, &ds_data, HMAC_KEY5 + 1, signature_data));
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_sign(message, &ds_data, HMAC_KEY0 - 1, signature_data));
}
#if CONFIG_IDF_ENV_FPGA
static void burn_hmac_keys(void)
{
printf("Burning %d HMAC keys to efuse...\n", NUM_HMAC_KEYS);
for (int i = 0; i < NUM_HMAC_KEYS; i++) {
// TODO: vary the purpose across the keys
ets_efuse_purpose_t purpose = ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE;
// starting from block 1, block 0 occupied with HMAC upstream test key
int __attribute__((unused)) ets_status = ets_efuse_write_key(ETS_EFUSE_BLOCK_KEY1 + i,
purpose,
test_hmac_keys[i], 32);
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
if (ets_status == ESP_OK) {
printf("written DS test key to block [%d]!\n", ETS_EFUSE_BLOCK_KEY1 + i);
} else {
printf("writing DS test key to block [%d] failed, maybe written already\n", ETS_EFUSE_BLOCK_KEY1 + i);
}
#endif
}
#if CONFIG_IDF_TARGET_ESP32C3
/* verify the keys are what we expect (possibly they're already burned, doesn't matter but they have to match) */
uint8_t block_compare[32];
for (int i = 0; i < NUM_HMAC_KEYS; i++) {
printf("Checking key %d...\n", i);
memcpy(block_compare, (void *)ets_efuse_get_read_register_address(ETS_EFUSE_BLOCK_KEY1 + i), 32);
TEST_ASSERT_EQUAL_HEX8_ARRAY(test_hmac_keys[i], block_compare, 32);
}
#endif
}
// This test uses the HMAC_KEY0 eFuse key which hasn't been burned by burn_hmac_keys().
// HMAC_KEY0 is usually used for HMAC upstream (user access) tests.
TEST_CASE("Digital Signature wrong HMAC key purpose (FPGA only)", "[hw_crypto] [ds]")
{
esp_ds_data_t ds_data = {};
ds_data.rsa_length = RSA_LEN;
esp_ds_context_t *ctx;
const char *message = "test";
// HMAC fails in that case because it checks for the correct purpose
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
TEST_ASSERT_EQUAL(ESP_ERR_HW_CRYPTO_DS_HMAC_FAIL, esp_ds_start_sign(message, &ds_data, HMAC_KEY0, &ctx));
#elif CONFIG_IDF_TARGET_ESP32C3
TEST_ASSERT_EQUAL(ESP32C3_ERR_HW_CRYPTO_DS_HMAC_FAIL, esp_ds_start_sign(message, &ds_data, HMAC_KEY0, &ctx));
#endif
}
// This test uses the HMAC_KEY0 eFuse key which hasn't been burned by burn_hmac_keys().
// HMAC_KEY0 is usually used for HMAC upstream (user access) tests.
TEST_CASE("Digital Signature Blocking wrong HMAC key purpose (FPGA only)", "[hw_crypto] [ds]")
{
esp_ds_data_t ds_data = {};
ds_data.rsa_length = RSA_LEN;
const char *message = "test";
uint8_t signature_data [128 * 4];
// HMAC fails in that case because it checks for the correct purpose
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
TEST_ASSERT_EQUAL(ESP_ERR_HW_CRYPTO_DS_HMAC_FAIL, esp_ds_sign(message, &ds_data, HMAC_KEY0, signature_data));
#elif CONFIG_IDF_TARGET_ESP32C3
TEST_ASSERT_EQUAL(ESP32C3_ERR_HW_CRYPTO_DS_HMAC_FAIL, esp_ds_sign(message, &ds_data, HMAC_KEY0, signature_data));
#endif
}
TEST_CASE("Digital Signature Operation (FPGA only)", "[hw_crypto] [ds]")
{
burn_hmac_keys();
for (int i = 0; i < NUM_CASES; i++) {
printf("Running test case %d...\n", i);
const encrypt_testcase_t *t = &test_cases[i];
// copy encrypt parameter test case into ds_data structure
esp_ds_data_t ds_data = { };
memcpy(ds_data.iv, t->iv, ETS_DS_IV_LEN);
memcpy(ds_data.c, t->expected_c, ETS_DS_C_LEN);
ds_data.rsa_length = t->p_data.length;
for (int j = 0; j < NUM_MESSAGES; j++) {
uint8_t signature[DS_MAX_BITS / 8] = { 0 };
printf(" ... message %d\n", j);
esp_ds_context_t *esp_ds_ctx;
esp_err_t ds_r = esp_ds_start_sign(test_messages[j],
&ds_data,
t->hmac_key_idx + 1,
&esp_ds_ctx);
TEST_ASSERT_EQUAL(ESP_OK, ds_r);
ds_r = esp_ds_finish_sign(signature, esp_ds_ctx);
TEST_ASSERT_EQUAL(ESP_OK, ds_r);
TEST_ASSERT_EQUAL_HEX8_ARRAY(t->expected_results[j], signature, sizeof(signature));
}
#if CONFIG_IDF_TARGET_ESP32C3
ets_hmac_invalidate_downstream(ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE);
#endif
}
}
TEST_CASE("Digital Signature Blocking Operation (FPGA only)", "[hw_crypto] [ds]")
{
burn_hmac_keys();
for (int i = 0; i < NUM_CASES; i++) {
printf("Running test case %d...\n", i);
const encrypt_testcase_t *t = &test_cases[i];
// copy encrypt parameter test case into ds_data structure
esp_ds_data_t ds_data = { };
memcpy(ds_data.iv, t->iv, ETS_DS_IV_LEN);
memcpy(ds_data.c, t->expected_c, ETS_DS_C_LEN);
ds_data.rsa_length = t->p_data.length;
uint8_t signature[DS_MAX_BITS / 8] = { 0 };
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
esp_ds_context_t *esp_ds_ctx;
esp_err_t ds_r = esp_ds_start_sign(test_messages[0],
&ds_data,
t->hmac_key_idx + 1,
&esp_ds_ctx);
TEST_ASSERT_EQUAL(ESP_OK, ds_r);
ds_r = esp_ds_finish_sign(signature, esp_ds_ctx);
TEST_ASSERT_EQUAL(ESP_OK, ds_r);
#elif CONFIG_IDF_TARGET_ESP32C3
esp_err_t ds_r = esp_ds_sign(test_messages[0],
&ds_data,
t->hmac_key_idx + 1,
signature);
TEST_ASSERT_EQUAL(ESP_OK, ds_r);
#endif
TEST_ASSERT_EQUAL_HEX8_ARRAY(t->expected_results[0], signature, sizeof(signature));
}
}
TEST_CASE("Digital Signature Invalid Data (FPGA only)", "[hw_crypto] [ds]")
{
burn_hmac_keys();
// Set up a valid test case
const encrypt_testcase_t *t = &test_cases[0];
esp_ds_data_t ds_data = { };
memcpy(ds_data.iv, t->iv, ETS_DS_IV_LEN);
memcpy(ds_data.c, t->expected_c, ETS_DS_C_LEN);
ds_data.rsa_length = t->p_data.length;
uint8_t signature[DS_MAX_BITS / 8] = { 0 };
const uint8_t zero[DS_MAX_BITS / 8] = { 0 };
// Corrupt the IV one bit at a time, rerun and expect failure
for (int bit = 0; bit < 128; bit++) {
printf("Corrupting IV bit %d...\n", bit);
ds_data.iv[bit / 8] ^= 1 << (bit % 8);
esp_ds_context_t *esp_ds_ctx;
esp_err_t ds_r = esp_ds_start_sign(test_messages[0], &ds_data, t->hmac_key_idx + 1, &esp_ds_ctx);
TEST_ASSERT_EQUAL(ESP_OK, ds_r);
ds_r = esp_ds_finish_sign(signature, esp_ds_ctx);
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
TEST_ASSERT_EQUAL(ESP_ERR_HW_CRYPTO_DS_INVALID_DIGEST, ds_r);
#elif CONFIG_IDF_TARGET_ESP32C3
TEST_ASSERT_EQUAL(ESP32C3_ERR_HW_CRYPTO_DS_INVALID_DIGEST, ds_r);
#endif
TEST_ASSERT_EQUAL_HEX8_ARRAY(zero, signature, DS_MAX_BITS / 8);
ds_data.iv[bit / 8] ^= 1 << (bit % 8);
}
// Corrupt encrypted key data one bit at a time, rerun and expect failure
printf("Corrupting C...\n");
for (int bit = 0; bit < ETS_DS_C_LEN * 8; bit++) {
printf("Corrupting C bit %d...\n", bit);
ds_data.c[bit / 8] ^= 1 << (bit % 8);
esp_ds_context_t *esp_ds_ctx;
esp_err_t ds_r = esp_ds_start_sign(test_messages[0], &ds_data, t->hmac_key_idx + 1, &esp_ds_ctx);
TEST_ASSERT_EQUAL(ESP_OK, ds_r);
ds_r = esp_ds_finish_sign(signature, esp_ds_ctx);
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
TEST_ASSERT_EQUAL(ESP_ERR_HW_CRYPTO_DS_INVALID_DIGEST, ds_r);
#elif CONFIG_IDF_TARGET_ESP32C3
TEST_ASSERT_EQUAL(ESP32C3_ERR_HW_CRYPTO_DS_INVALID_DIGEST, ds_r);
#endif
TEST_ASSERT_EQUAL_HEX8_ARRAY(zero, signature, DS_MAX_BITS / 8);
ds_data.c[bit / 8] ^= 1 << (bit % 8);
}
}
#endif // CONFIG_IDF_ENV_FPGA
#endif // SOC_DIG_SIGN_SUPPORTED

0
components/esp_hw_support/test/test_hmac.c → components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/main/test_hmac.c
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0
components/esp_hw_support/test/test_random.c → components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/main/test_random.c
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20
components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/pytest_security_support.py 100644
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@ -0,0 +1,20 @@
# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
# SPDX-License-Identifier: CC0-1.0
import pytest
from pytest_embedded import Dut
@pytest.mark.generic
@pytest.mark.parametrize(
'config',
[
pytest.param('default', marks=[pytest.mark.supported_targets]),
pytest.param('release', marks=[pytest.mark.supported_targets]),
],
indirect=True,
)
def test_security_support(dut: Dut) -> None:
dut.expect_exact('Press ENTER to see the list of tests')
dut.write('![ignore]')
dut.expect_unity_test_output(timeout=120)

1
components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/sdkconfig.ci.default 100644
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@ -0,0 +1 @@
# Empty file to be able to parametrize "default" config

6
components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/sdkconfig.ci.release 100644
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@ -0,0 +1,6 @@
# set compiler optimization level
CONFIG_COMPILER_OPTIMIZATION_SIZE=y
CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y
# we can silent the assertion to save the binary footprint
CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y

2
components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/sdkconfig.defaults 100644
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@ -0,0 +1,2 @@
CONFIG_ESP_TASK_WDT_INIT=n
CONFIG_ESP_MAIN_TASK_STACK_SIZE=8192

2
components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/sdkconfig.defaults.esp32 100644
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@ -0,0 +1,2 @@
# Set CPU frequency to max for performance tests
# CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240=y

2
components/esp_hw_support/test_apps/security_support/esp_hw_support_unity_tests/sdkconfig.defaults.esp32s2 100644
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@ -0,0 +1,2 @@
# Set CPU frequency to max for performance tests
CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240=y

2
components/esp_psram/test_apps/psram/main/CMakeLists.txt
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@ -4,7 +4,7 @@ set(srcs "test_app_main.c"
"test_psram.c")
if(${target} STREQUAL "esp32")
list(APPEND srcs "test_himem.c")
list(APPEND srcs "test_himem.c" "test_4mpsram.c")
endif()
# In order for the cases defined by `TEST_CASE` to be linked into the final elf,

2
components/esp_hw_support/test/test_4mpsram.c → components/esp_psram/test_apps/psram/main/test_4mpsram.c
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@ -70,7 +70,7 @@ static void test_spi_bus_occupy(spi_host_device_t expected_occupied_host)
}
#if CONFIG_SPIRAM_OCCUPY_HSPI_HOST || CONFIG_SPIRAM_OCCUPY_VSPI_HOST
TEST_CASE("some spi bus occpied by psram", "[psram_4m][test_env=UT_T1_PSRAMV0]")
TEST_CASE("some spi bus occpied by psram", "[psram_4m]")
{
// NOTE: this unit test rely on the config that PSRAM of 8MB is used only when CONFIG_SPIRAM_BANKSWITCH_ENABLE is set
//currently all 8M psram don't need more SPI peripherals

16
components/esp_psram/test_apps/psram/pytest_psram.py
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@ -66,3 +66,19 @@ def test_psram_esp32s3_octal(dut: Dut) -> None:
dut.expect_exact('Press ENTER to see the list of tests')
dut.write('*')
dut.expect_unity_test_output()
@pytest.mark.esp32
@pytest.mark.psramv0
@pytest.mark.parametrize(
'config',
[
'esp32_hspi',
'esp32_vspi',
],
indirect=True,
)
def test_psram_esp32_psramv0(dut: Dut) -> None:
dut.expect_exact('Press ENTER to see the list of tests')
dut.write('*')
dut.expect_unity_test_output()

3
tools/unit-test-app/configs/psram_hspi → components/esp_psram/test_apps/psram/sdkconfig.ci.esp32_hspi
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@ -1,8 +1,7 @@
CONFIG_IDF_TARGET="esp32"
TEST_COMPONENTS=esp_hw_support
TEST_GROUPS=psram_4m
CONFIG_ESPTOOLPY_FLASHFREQ_80M=y
CONFIG_SPIRAM=y
CONFIG_SPIRAM_SPEED_80M=y
CONFIG_SPIRAM_OCCUPY_HSPI_HOST=y
CONFIG_ESP_INT_WDT_TIMEOUT_MS=800
CONFIG_SPIRAM_BANKSWITCH_ENABLE=n

3
tools/unit-test-app/configs/psram_vspi → components/esp_psram/test_apps/psram/sdkconfig.ci.esp32_vspi
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@ -1,8 +1,7 @@
CONFIG_IDF_TARGET="esp32"
TEST_COMPONENTS=esp_hw_support
TEST_GROUPS=psram_4m
CONFIG_ESPTOOLPY_FLASHFREQ_80M=y
CONFIG_SPIRAM=y
CONFIG_SPIRAM_SPEED_80M=y
CONFIG_SPIRAM_OCCUPY_VSPI_HOST=y
CONFIG_ESP_INT_WDT_TIMEOUT_MS=800
CONFIG_SPIRAM_BANKSWITCH_ENABLE=n

0
components/esp_hw_support/test/test_spiram_cache_flush.c → components/spi_flash/test/test_spiram_cache_flush.c
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5
pytest.ini
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@ -68,7 +68,10 @@ markers =
MSPI_F4R4: runner with Quad Flash and Quad PSRAM
test_jtag_arm: runner where the chip is accessible through JTAG as well
adc: ADC related tests should run on adc runners
multi_dut_modbus_rs485: a pair of runners connectd by RS485 bus
xtal32k: Runner with external 32k crystal connected
no32kXtal: Runner with no external 32k crystal connected
multi_dut_modbus_rs485: a pair of runners connected by RS485 bus
psramv0: Runner with PSRAM version 0
# multi-dut markers
ieee802154: ieee802154 related tests should run on ieee802154 runners.

2
tools/unit-test-app/configs/default
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@ -1,4 +1,4 @@
# This config is split between targets since different component needs to be included (esp32, esp32s2)
# IRAM is full... split some component to default_32_2
CONFIG_IDF_TARGET="esp32"
TEST_COMPONENTS=esp_hw_support esp_ipc esp_system driver
TEST_COMPONENTS=esp_system driver

2
tools/unit-test-app/configs/default_2
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@ -1,3 +1,3 @@
# This config is split between targets since different component needs to be excluded (esp32, esp32s2)
CONFIG_IDF_TARGET="esp32"
TEST_EXCLUDE_COMPONENTS=bt esp_hw_support esp_ipc esp_pm esp_system driver soc spi_flash vfs test_utils experimental_cpp_component
TEST_EXCLUDE_COMPONENTS=bt esp_pm esp_system driver soc spi_flash vfs test_utils experimental_cpp_component

2
tools/unit-test-app/configs/default_2_c3
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@ -1,3 +1,3 @@
# This config is split between targets since different component needs to be excluded
CONFIG_IDF_TARGET="esp32c3"
TEST_EXCLUDE_COMPONENTS=bt esp_pm esp_hw_support esp_ipc esp_system driver soc spi_flash vfs lwip spiffs experimental_cpp_component perfmon test_utils
TEST_EXCLUDE_COMPONENTS=bt esp_pm esp_system driver soc spi_flash vfs lwip spiffs experimental_cpp_component perfmon test_utils

2
tools/unit-test-app/configs/default_2_s2
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@ -1,3 +1,3 @@
# This config is split between targets since different component needs to be excluded (esp32, esp32s2)
CONFIG_IDF_TARGET="esp32s2"
TEST_EXCLUDE_COMPONENTS=bt esp_hw_support esp_ipc esp_pm esp_system driver soc spi_flash vfs experimental_cpp_component
TEST_EXCLUDE_COMPONENTS=bt esp_pm esp_system driver soc spi_flash vfs experimental_cpp_component

2
tools/unit-test-app/configs/default_2_s3
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@ -1,3 +1,3 @@
# This config is split between targets since different component needs to be excluded (esp32, esp32s2)
CONFIG_IDF_TARGET="esp32s3"
TEST_EXCLUDE_COMPONENTS=bt esp32s3 esp_ipc esp_pm esp_system driver soc spi_flash vfs experimental_cpp_component test_utils
TEST_EXCLUDE_COMPONENTS=bt esp32s3 esp_pm esp_system driver soc spi_flash vfs experimental_cpp_component test_utils

2
tools/unit-test-app/configs/default_3_c2
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@ -1,3 +1,3 @@
# This config is split between targets since different component needs to be included
CONFIG_IDF_TARGET="esp32c2"
TEST_EXCLUDE_COMPONENTS=app_trace esp_eth esp_hid esp_netif esp_phy esp_ringbuf esp_wifi espcoredump hal lwip mdns mqtt newlib nvs_flash partition_table sdmmc esp_hw_support esp_ipc esp_system driver soc spi_flash vfs
TEST_EXCLUDE_COMPONENTS=app_trace esp_eth esp_hid esp_netif esp_phy esp_ringbuf esp_wifi espcoredump hal lwip mdns mqtt newlib nvs_flash partition_table sdmmc esp_system driver soc spi_flash vfs

2
tools/unit-test-app/configs/default_c2
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@ -1,3 +1,3 @@
# This config is split between targets since different component needs to be included
CONFIG_IDF_TARGET="esp32c2"
TEST_COMPONENTS= esp_hw_support esp_ipc esp_system driver soc spi_flash vfs
TEST_COMPONENTS= esp_system driver soc spi_flash vfs

2
tools/unit-test-app/configs/default_c3
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@ -1,3 +1,3 @@
# This config is split between targets since different component needs to be included
CONFIG_IDF_TARGET="esp32c3"
TEST_COMPONENTS=esp_hw_support esp_ipc esp_system driver
TEST_COMPONENTS=esp_system driver

2
tools/unit-test-app/configs/default_s2_1
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@ -1,3 +1,3 @@
# This config is split between targets since different component needs to be included (esp32, esp32s2)
CONFIG_IDF_TARGET="esp32s2"
TEST_COMPONENTS=esp_hw_support esp_system driver
TEST_COMPONENTS=esp_system driver

2
tools/unit-test-app/configs/default_s3
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@ -1,3 +1,3 @@
# This config is split between targets since different component needs to be included
CONFIG_IDF_TARGET="esp32s3"
TEST_COMPONENTS=esp_hw_support esp_ipc esp_system driver soc spi_flash vfs
TEST_COMPONENTS=esp_system driver soc spi_flash vfs

2
tools/unit-test-app/configs/freertos_compliance
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@ -1,4 +1,4 @@
# This config is split between targets since different component needs to be included (esp32, esp32s2)
CONFIG_IDF_TARGET="esp32"
TEST_COMPONENTS=driver esp_hw_support esp_ipc spi_flash
TEST_COMPONENTS=driver spi_flash
CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE=y

2
tools/unit-test-app/configs/freertos_compliance_c2
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@ -1,4 +1,4 @@
# This config is split between targets since different component needs to be included (esp32, esp32s2)
CONFIG_IDF_TARGET="esp32c2"
TEST_COMPONENTS=driver esp_hw_support esp_system spi_flash
TEST_COMPONENTS=driver esp_system spi_flash
CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE=y

2
tools/unit-test-app/configs/freertos_compliance_c3
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@ -1,4 +1,4 @@
# This config is split between targets since different component needs to be included (esp32, esp32s2)
CONFIG_IDF_TARGET="esp32c3"
TEST_COMPONENTS=driver esp_hw_support esp_system spi_flash
TEST_COMPONENTS=driver esp_system spi_flash
CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE=y

2
tools/unit-test-app/configs/freertos_compliance_s2
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@ -1,4 +1,4 @@
# This config is split between targets since different component needs to be included (esp32, esp32s2)
CONFIG_IDF_TARGET="esp32s2"
TEST_COMPONENTS=driver esp_hw_support esp_system spi_flash
TEST_COMPONENTS=driver esp_system spi_flash
CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE=y

2
tools/unit-test-app/configs/no_optimization_c2
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@ -1,3 +1,3 @@
CONFIG_IDF_TARGET="esp32c2"
TEST_COMPONENTS=esp_ipc spi_flash
TEST_COMPONENTS=spi_flash
CONFIG_COMPILER_OPTIMIZATION_NONE=y

2
tools/unit-test-app/configs/no_optimization_c3
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@ -1,3 +1,3 @@
CONFIG_IDF_TARGET="esp32c3"
TEST_COMPONENTS=esp_ipc spi_flash
TEST_COMPONENTS=spi_flash
CONFIG_COMPILER_OPTIMIZATION_NONE=y

2
tools/unit-test-app/configs/no_optimization_esp32
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@ -1,3 +1,3 @@
CONFIG_IDF_TARGET="esp32"
TEST_COMPONENTS=esp_ipc spi_flash
TEST_COMPONENTS=spi_flash
CONFIG_COMPILER_OPTIMIZATION_NONE=y

2
tools/unit-test-app/configs/psram
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@ -1,5 +1,5 @@
CONFIG_IDF_TARGET="esp32"
TEST_EXCLUDE_COMPONENTS=bt driver esp_hw_support esp_ipc esp_pm esp_system spi_flash test_utils soc experimental_cpp_component esp-tls sdmmc
TEST_EXCLUDE_COMPONENTS=bt driver esp_pm esp_system spi_flash test_utils soc experimental_cpp_component esp-tls sdmmc
CONFIG_SPIRAM=y
CONFIG_ESP_INT_WDT_TIMEOUT_MS=800
CONFIG_SPIRAM_OCCUPY_NO_HOST=y

2
tools/unit-test-app/configs/psram_2
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@ -1,5 +1,5 @@
CONFIG_IDF_TARGET="esp32"
TEST_COMPONENTS=esp_hw_support esp_ipc esp_system spi_flash soc
TEST_COMPONENTS=esp_system spi_flash soc
CONFIG_SPIRAM=y
CONFIG_ESP_INT_WDT_TIMEOUT_MS=800
CONFIG_SPIRAM_OCCUPY_NO_HOST=y

7
tools/unit-test-app/configs/psram_8m
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@ -1,7 +0,0 @@
CONFIG_IDF_TARGET="esp32"
TEST_COMPONENTS=esp_hw_support
CONFIG_SPIRAM=y
CONFIG_SPIRAM_BANKSWITCH_ENABLE=y
CONFIG_SPIRAM_BANKSWITCH_RESERVE=8
CONFIG_ESP_INT_WDT_TIMEOUT_MS=800
CONFIG_SPIRAM_OCCUPY_NO_HOST=y

2
tools/unit-test-app/configs/psram_all_ext_1
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@ -1,5 +1,5 @@
CONFIG_IDF_TARGET="esp32"
TEST_COMPONENTS=driver esp_hw_support esp_system
TEST_COMPONENTS=driver esp_system
CONFIG_SPIRAM=y
CONFIG_ESP_INT_WDT_TIMEOUT_MS=800
CONFIG_SPIRAM_OCCUPY_NO_HOST=y

6
tools/unit-test-app/configs/psram_s2_advanced
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@ -1,6 +0,0 @@
CONFIG_IDF_TARGET="esp32s2"
TEST_COMPONENTS=esp_hw_support
CONFIG_SPIRAM=y
CONFIG_SPIRAM_FETCH_INSTRUCTIONS=y
CONFIG_SPIRAM_RODATA=y
CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY=y

2
tools/unit-test-app/configs/psram_s2_base
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@ -1,3 +1,3 @@
CONFIG_IDF_TARGET="esp32s2"
TEST_COMPONENTS=esp_hw_support esp_system
TEST_COMPONENTS=esp_system
CONFIG_SPIRAM=y

2
tools/unit-test-app/configs/psram_s3_base
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@ -1,3 +1,3 @@
CONFIG_IDF_TARGET="esp32s3"
TEST_COMPONENTS=esp_hw_support esp_system
TEST_COMPONENTS=esp_system
CONFIG_SPIRAM=y

2
tools/unit-test-app/configs/release
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@ -1,5 +1,5 @@
CONFIG_IDF_TARGET="esp32"
TEST_COMPONENTS=esp_hw_support esp_system esp_ipc driver soc spi_flash vfs
TEST_COMPONENTS=esp_system driver soc spi_flash vfs
CONFIG_COMPILER_OPTIMIZATION_SIZE=y
CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y
CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y

2
tools/unit-test-app/configs/release_2
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@ -1,6 +1,6 @@
# This config is split between targets since different component needs to be included (esp32, esp32s2)
CONFIG_IDF_TARGET="esp32"
TEST_EXCLUDE_COMPONENTS=bt esp_hw_support esp_ipc esp_pm esp_system driver soc spi_flash vfs test_utils experimental_cpp_component
TEST_EXCLUDE_COMPONENTS=bt esp_pm esp_system driver soc spi_flash vfs test_utils experimental_cpp_component
CONFIG_COMPILER_OPTIMIZATION_SIZE=y
CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y
CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y

2
tools/unit-test-app/configs/release_2_s2
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@ -1,6 +1,6 @@
# This config is split between targets since different component needs to be excluded (esp32, esp32s2)
CONFIG_IDF_TARGET="esp32s2"
TEST_EXCLUDE_COMPONENTS=bt esp_hw_support esp_ipc esp_pm esp_system driver soc spi_flash vfs test_utils experimental_cpp_component
TEST_EXCLUDE_COMPONENTS=bt esp_pm esp_system driver soc spi_flash vfs test_utils experimental_cpp_component
CONFIG_COMPILER_OPTIMIZATION_SIZE=y
CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y
CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y

2
tools/unit-test-app/configs/release_c2
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@ -1,5 +1,5 @@
CONFIG_IDF_TARGET="esp32c2"
TEST_COMPONENTS=esp_hw_support esp_system esp_ipc driver soc spi_flash vfs sdmmc
TEST_COMPONENTS=esp_system driver soc spi_flash vfs sdmmc
CONFIG_COMPILER_OPTIMIZATION_SIZE=y
CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y
CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y

2
tools/unit-test-app/configs/release_c3
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@ -1,5 +1,5 @@
CONFIG_IDF_TARGET="esp32c3"
TEST_COMPONENTS=esp_hw_support esp_ipc esp_system driver
TEST_COMPONENTS=esp_system driver
CONFIG_COMPILER_OPTIMIZATION_SIZE=y
CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y
CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y

2
tools/unit-test-app/configs/release_s2
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@ -1,6 +1,6 @@
# This config is split between targets since different component needs to be included (esp32, esp32s2)
CONFIG_IDF_TARGET="esp32s2"
TEST_COMPONENTS=esp_hw_support esp_system driver soc spi_flash vfs
TEST_COMPONENTS=esp_system driver soc spi_flash vfs
CONFIG_COMPILER_OPTIMIZATION_SIZE=y
CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y
CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y

2
tools/unit-test-app/configs/release_s3
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@ -1,5 +1,5 @@
CONFIG_IDF_TARGET="esp32s3"
TEST_COMPONENTS=esp_hw_support esp_system esp_ipc driver soc spi_flash vfs
TEST_COMPONENTS=esp_system driver soc spi_flash vfs
CONFIG_COMPILER_OPTIMIZATION_SIZE=y
CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y
CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y

2
tools/unit-test-app/configs/single_core
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@ -1,6 +1,6 @@
# This config is split between targets since different component needs to be included (esp32, esp32s2)
CONFIG_IDF_TARGET="esp32"
TEST_COMPONENTS=esp_hw_support esp_system driver soc spi_flash vfs
TEST_COMPONENTS=esp_system driver soc spi_flash vfs
CONFIG_FREERTOS_UNICORE=y
CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY=y
CONFIG_ESP32_RTCDATA_IN_FAST_MEM=y

2
tools/unit-test-app/configs/single_core_2
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@ -1,5 +1,5 @@
# This config is split between targets since different component needs to be excluded (esp32, esp32s2)
CONFIG_IDF_TARGET="esp32"
TEST_EXCLUDE_COMPONENTS=bt esp_hw_support esp_system esp_pm esp_ipc driver soc spi_flash vfs test_utils experimental_cpp_component
TEST_EXCLUDE_COMPONENTS=bt esp_system esp_pm driver soc spi_flash vfs test_utils experimental_cpp_component
CONFIG_FREERTOS_UNICORE=y
CONFIG_ESP32_RTCDATA_IN_FAST_MEM=y

2
tools/unit-test-app/configs/single_core_2_s2
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@ -1,5 +1,5 @@
# This config is split between targets since different component needs to be excluded (esp32, esp32s2)
CONFIG_IDF_TARGET="esp32s2"
TEST_EXCLUDE_COMPONENTS=bt esp_hw_support esp_ipc esp_system esp_pm driver soc spi_flash vfs experimental_cpp_component
TEST_EXCLUDE_COMPONENTS=bt esp_system esp_pm driver soc spi_flash vfs experimental_cpp_component
CONFIG_FREERTOS_UNICORE=y
CONFIG_ESP32S2_RTCDATA_IN_FAST_MEM=y

2
tools/unit-test-app/configs/single_core_s2
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@ -1,4 +1,4 @@
# This config is split between targets since different component needs to be included (esp32, esp32s2)
CONFIG_IDF_TARGET="esp32s2"
TEST_COMPONENTS=esp_hw_support esp_system driver soc spi_flash test_utils
TEST_COMPONENTS=esp_system driver soc spi_flash test_utils
CONFIG_ESP32S2_RTCDATA_IN_FAST_MEM=y

2
tools/unit-test-app/disabled_configs/psram_2_s2
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@ -1,4 +1,4 @@
TEST_COMPONENTS=driver esp_hw_support spi_flash mbedtls
TEST_COMPONENTS=driver spi_flash mbedtls
CONFIG_SPIRAM=y
CONFIG_IDF_TARGET="esp32s2"
CONFIG_SPIRAM_OCCUPY_NO_HOST=y

6
tools/unit-test-app/disabled_configs/psram_8m_s2
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@ -1,6 +0,0 @@
TEST_COMPONENTS=esp_hw_support
CONFIG_SPIRAM=y
CONFIG_SPIRAM_BANKSWITCH_ENABLE=y
CONFIG_SPIRAM_BANKSWITCH_RESERVE=8
CONFIG_IDF_TARGET="esp32s2"
CONFIG_SPIRAM_OCCUPY_NO_HOST=y

2
tools/unit-test-app/disabled_configs/psram_s2
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@ -1,4 +1,4 @@
TEST_EXCLUDE_COMPONENTS=libsodium bt app_update driver esp_hw_support spi_flash
TEST_EXCLUDE_COMPONENTS=libsodium bt app_update driver spi_flash
CONFIG_SPIRAM=y
CONFIG_IDF_TARGET="esp32s2"
CONFIG_SPIRAM_OCCUPY_NO_HOST=y