Merge branch 'bugfix/update_esp_rom_c6_caps' into 'master'

esp_rom: update esp32c6 rom caps

See merge request espressif/esp-idf!20133

components/esp_rom/esp32c6/Kconfig.soc_caps.in

@@ -27,10 +27,6 @@ config ESP_ROM_HAS_RETARGETABLE_LOCKING
     bool
     default y
 
-config ESP_ROM_HAS_ERASE_0_REGION_BUG
-    bool
-    default y
-
 config ESP_ROM_GET_CLK_FREQ
     bool
     default y

components/esp_rom/esp32c6/esp_rom_caps.h

@@ -12,5 +12,4 @@
 #define ESP_ROM_UART_CLK_IS_XTAL            (1) // UART clock source is selected to XTAL in ROM
 #define ESP_ROM_USB_SERIAL_DEVICE_NUM       (3) // UART uses USB_SERIAL_JTAG port in ROM.
 #define ESP_ROM_HAS_RETARGETABLE_LOCKING    (1) // ROM was built with retargetable locking
-#define ESP_ROM_HAS_ERASE_0_REGION_BUG      (1) // ROM has esp_flash_erase_region(size=0) bug
 #define ESP_ROM_GET_CLK_FREQ                (1) // Get clk frequency with rom function `ets_get_cpu_frequency`