From 49e7228be97715dc6e1be8d0f4e137ff8b45e6b8 Mon Sep 17 00:00:00 2001 From: morris Date: Sun, 18 Feb 2024 18:12:03 +0800 Subject: [PATCH] feat(gptimer): basic driver support on esp32c5 --- components/driver/Kconfig | 12 + components/esp_driver_gptimer/Kconfig | 8 - components/hal/esp32/include/hal/timer_ll.h | 5 +- components/hal/esp32c2/include/hal/timer_ll.h | 5 +- components/hal/esp32c3/include/hal/timer_ll.h | 5 +- components/hal/esp32c5/include/hal/timer_ll.h | 317 ++++++++++++++++-- components/hal/esp32c6/include/hal/timer_ll.h | 5 +- components/hal/esp32h2/include/hal/timer_ll.h | 5 +- components/hal/esp32p4/include/hal/timer_ll.h | 5 +- components/hal/esp32s2/include/hal/timer_ll.h | 5 +- components/hal/esp32s3/include/hal/timer_ll.h | 5 +- .../esp32c5/include/soc/Kconfig.soc_caps.in | 16 + .../soc/esp32c5/include/soc/clk_tree_defs.h | 6 +- components/soc/esp32c5/include/soc/soc_caps.h | 9 +- components/soc/esp32c5/timer_periph.c | 24 ++ 15 files changed, 380 insertions(+), 52 deletions(-) create mode 100644 components/soc/esp32c5/timer_periph.c diff --git a/components/driver/Kconfig b/components/driver/Kconfig index ad75325615..aa2f02c62c 100644 --- a/components/driver/Kconfig +++ b/components/driver/Kconfig @@ -74,4 +74,16 @@ menu "Driver Configurations" you can enable this option. endmenu # Legacy MCPWM Driver Configurations + menu "Legacy Timer Group Driver Configurations" + depends on SOC_GPTIMER_SUPPORTED + config GPTIMER_SUPPRESS_DEPRECATE_WARN + bool "Suppress legacy driver deprecated warning" + default n + help + Wether to suppress the deprecation warnings when using legacy timer group driver (driver/timer.h). + If you want to continue using the legacy driver, and don't want to see related deprecation warnings, + you can enable this option. + + endmenu # Legacy Timer Group Driver Configurations + endmenu # Driver configurations diff --git a/components/esp_driver_gptimer/Kconfig b/components/esp_driver_gptimer/Kconfig index 8aa5f2d9ba..84f5421257 100644 --- a/components/esp_driver_gptimer/Kconfig +++ b/components/esp_driver_gptimer/Kconfig @@ -22,14 +22,6 @@ menu "ESP-Driver:GPTimer Configurations" Ensure the GPTimer interrupt is IRAM-Safe by allowing the interrupt handler to be executable when the cache is disabled (e.g. SPI Flash write). - config GPTIMER_SUPPRESS_DEPRECATE_WARN - bool "Suppress legacy driver deprecated warning" - default n - help - Wether to suppress the deprecation warnings when using legacy timer group driver (driver/timer.h). - If you want to continue using the legacy driver, and don't want to see related deprecation warnings, - you can enable this option. - config GPTIMER_ENABLE_DEBUG_LOG bool "Enable debug log" default n diff --git a/components/hal/esp32/include/hal/timer_ll.h b/components/hal/esp32/include/hal/timer_ll.h index 4a52141152..d5d34c8150 100644 --- a/components/hal/esp32/include/hal/timer_ll.h +++ b/components/hal/esp32/include/hal/timer_ll.h @@ -1,10 +1,11 @@ /* - * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -// Note that most of the register operations in this layer are non-atomic operations. +// Attention: Timer Group has 3 independent functions: General Purpose Timer, Watchdog Timer and Clock calibration. +// This Low Level driver only serve the General Purpose Timer function. #pragma once diff --git a/components/hal/esp32c2/include/hal/timer_ll.h b/components/hal/esp32c2/include/hal/timer_ll.h index c6f7645cc4..fb289baa1b 100644 --- a/components/hal/esp32c2/include/hal/timer_ll.h +++ b/components/hal/esp32c2/include/hal/timer_ll.h @@ -1,10 +1,11 @@ /* - * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -// Note that most of the register operations in this layer are non-atomic operations. +// Attention: Timer Group has 3 independent functions: General Purpose Timer, Watchdog Timer and Clock calibration. +// This Low Level driver only serve the General Purpose Timer function. #pragma once diff --git a/components/hal/esp32c3/include/hal/timer_ll.h b/components/hal/esp32c3/include/hal/timer_ll.h index c8e7cd86e8..184472d9d3 100644 --- a/components/hal/esp32c3/include/hal/timer_ll.h +++ b/components/hal/esp32c3/include/hal/timer_ll.h @@ -1,10 +1,11 @@ /* - * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -// Note that most of the register operations in this layer are non-atomic operations. +// Attention: Timer Group has 3 independent functions: General Purpose Timer, Watchdog Timer and Clock calibration. +// This Low Level driver only serve the General Purpose Timer function. #pragma once diff --git a/components/hal/esp32c5/include/hal/timer_ll.h b/components/hal/esp32c5/include/hal/timer_ll.h index b25e146246..4672bffb54 100644 --- a/components/hal/esp32c5/include/hal/timer_ll.h +++ b/components/hal/esp32c5/include/hal/timer_ll.h @@ -1,10 +1,11 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -// Note that most of the register operations in this layer are non-atomic operations. +// Attention: Timer Group has 3 independent functions: General Purpose Timer, Watchdog Timer and Clock calibration. +// This Low Level driver only serve the General Purpose Timer function. #pragma once @@ -25,8 +26,6 @@ extern "C" { #define TIMER_LL_GET_HW(group_id) ((group_id == 0) ? (&TIMERG0) : (&TIMERG1)) #define TIMER_LL_EVENT_ALARM(timer_id) (1 << (timer_id)) -// TODO: [ESP32C5] IDF-8693 - /** * @brief Enable the bus clock for timer group module * @@ -35,12 +34,11 @@ extern "C" { */ static inline void timer_ll_enable_bus_clock(int group_id, bool enable) { - // TODO: [ESP32C5] IDF-8705 - // if (group_id == 0) { - // PCR.timergroup0_conf.tg0_clk_en = enable; - // } else { - // PCR.timergroup1_conf.tg1_clk_en = enable; - // } + if (group_id == 0) { + PCR.timergroup0_conf.tg0_clk_en = enable; + } else { + PCR.timergroup1_conf.tg1_clk_en = enable; + } } /// use a macro to wrap the function, force the caller to use it in a critical section @@ -58,22 +56,301 @@ static inline void timer_ll_enable_bus_clock(int group_id, bool enable) */ static inline void timer_ll_reset_register(int group_id) { - // TODO: [ESP32C5] IDF-8705 - // if (group_id == 0) { - // PCR.timergroup0_conf.tg0_rst_en = 1; - // PCR.timergroup0_conf.tg0_rst_en = 0; - // TIMERG0.wdtconfig0.wdt_flashboot_mod_en = 0; - // } else { - // PCR.timergroup1_conf.tg1_rst_en = 1; - // PCR.timergroup1_conf.tg1_rst_en = 0; - // TIMERG1.wdtconfig0.wdt_flashboot_mod_en = 0; - // } + if (group_id == 0) { + PCR.timergroup0_conf.tg0_rst_en = 1; + PCR.timergroup0_conf.tg0_rst_en = 0; + TIMERG0.wdtconfig0.wdt_flashboot_mod_en = 0; + } else { + PCR.timergroup1_conf.tg1_rst_en = 1; + PCR.timergroup1_conf.tg1_rst_en = 0; + TIMERG1.wdtconfig0.wdt_flashboot_mod_en = 0; + } } /// use a macro to wrap the function, force the caller to use it in a critical section /// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance #define timer_ll_reset_register(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; timer_ll_reset_register(__VA_ARGS__) +/** + * @brief Set clock source for timer + * + * @param hw Timer Group register base address + * @param timer_num Timer number in the group + * @param clk_src Clock source + */ +static inline void timer_ll_set_clock_source(timg_dev_t *hw, uint32_t timer_num, gptimer_clock_source_t clk_src) +{ + (void)timer_num; // only one timer in each group + uint8_t clk_id = 0; + switch (clk_src) { + case GPTIMER_CLK_SRC_XTAL: + clk_id = 0; + break; + case GPTIMER_CLK_SRC_RC_FAST: + clk_id = 1; + break; + case GPTIMER_CLK_SRC_PLL_F80M: + clk_id = 2; + break; + default: + HAL_ASSERT(false); + break; + } + if (hw == &TIMERG0) { + PCR.timergroup0_timer_clk_conf.tg0_timer_clk_sel = clk_id; + } else { + PCR.timergroup1_timer_clk_conf.tg1_timer_clk_sel = clk_id; + } +} + +/** + * @brief Enable Timer Group (GPTimer) module clock + * + * @param hw Timer Group register base address + * @param timer_num Timer index in the group + * @param en true to enable, false to disable + */ +static inline void timer_ll_enable_clock(timg_dev_t *hw, uint32_t timer_num, bool en) +{ + (void)timer_num; // only one timer in each group + if (hw == &TIMERG0) { + PCR.timergroup0_timer_clk_conf.tg0_timer_clk_en = en; + } else { + PCR.timergroup1_timer_clk_conf.tg1_timer_clk_en = en; + } +} + +/** + * @brief Enable alarm event + * + * @param hw Timer Group register base address + * @param timer_num Timer number in the group + * @param en True: enable alarm + * False: disable alarm + */ +__attribute__((always_inline)) +static inline void timer_ll_enable_alarm(timg_dev_t *hw, uint32_t timer_num, bool en) +{ + hw->hw_timer[timer_num].config.tx_alarm_en = en; +} + +/** + * @brief Set clock prescale for timer + * + * @param hw Timer Group register base address + * @param timer_num Timer number in the group + * @param divider Prescale value (0 and 1 are not valid) + */ +static inline void timer_ll_set_clock_prescale(timg_dev_t *hw, uint32_t timer_num, uint32_t divider) +{ + HAL_ASSERT(divider >= 2 && divider <= 65536); + if (divider >= 65536) { + divider = 0; + } + HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hw_timer[timer_num].config, tx_divider, divider); + hw->hw_timer[timer_num].config.tx_divcnt_rst = 1; +} + +/** + * @brief Enable auto-reload mode + * + * @param hw Timer Group register base address + * @param timer_num Timer number in the group + * @param en True: enable auto reload mode + * False: disable auto reload mode + */ +__attribute__((always_inline)) +static inline void timer_ll_enable_auto_reload(timg_dev_t *hw, uint32_t timer_num, bool en) +{ + hw->hw_timer[timer_num].config.tx_autoreload = en; +} + +/** + * @brief Set count direction + * + * @param hw Timer peripheral register base address + * @param timer_num Timer number in the group + * @param direction Count direction + */ +static inline void timer_ll_set_count_direction(timg_dev_t *hw, uint32_t timer_num, gptimer_count_direction_t direction) +{ + hw->hw_timer[timer_num].config.tx_increase = (direction == GPTIMER_COUNT_UP); +} + +/** + * @brief Enable timer, start couting + * + * @param hw Timer Group register base address + * @param timer_num Timer number in the group + * @param en True: enable the counter + * False: disable the counter + */ +__attribute__((always_inline)) +static inline void timer_ll_enable_counter(timg_dev_t *hw, uint32_t timer_num, bool en) +{ + hw->hw_timer[timer_num].config.tx_en = en; +} + +/** + * @brief Trigger software capture event + * + * @param hw Timer Group register base address + * @param timer_num Timer number in the group + */ +__attribute__((always_inline)) +static inline void timer_ll_trigger_soft_capture(timg_dev_t *hw, uint32_t timer_num) +{ + hw->hw_timer[timer_num].update.tx_update = 1; + // Timer register is in a different clock domain from Timer hardware logic + // We need to wait for the update to take effect before fetching the count value + while (hw->hw_timer[timer_num].update.tx_update) { + } +} + +/** + * @brief Get counter value + * + * @param hw Timer Group register base address + * @param timer_num Timer number in the group + * + * @return counter value + */ +__attribute__((always_inline)) +static inline uint64_t timer_ll_get_counter_value(timg_dev_t *hw, uint32_t timer_num) +{ + return ((uint64_t)hw->hw_timer[timer_num].hi.tx_hi << 32) | (hw->hw_timer[timer_num].lo.tx_lo); +} + +/** + * @brief Set alarm value + * + * @param hw Timer Group register base address + * @param timer_num Timer number in the group + * @param alarm_value When counter reaches alarm value, alarm event will be triggered + */ +__attribute__((always_inline)) +static inline void timer_ll_set_alarm_value(timg_dev_t *hw, uint32_t timer_num, uint64_t alarm_value) +{ + hw->hw_timer[timer_num].alarmhi.tx_alarm_hi = (uint32_t)(alarm_value >> 32); + hw->hw_timer[timer_num].alarmlo.tx_alarm_lo = (uint32_t)alarm_value; +} + +/** + * @brief Set reload value + * + * @param hw Timer Group register base address + * @param timer_num Timer number in the group + * @param reload_val Reload counter value + */ +__attribute__((always_inline)) +static inline void timer_ll_set_reload_value(timg_dev_t *hw, uint32_t timer_num, uint64_t reload_val) +{ + hw->hw_timer[timer_num].loadhi.tx_load_hi = (uint32_t)(reload_val >> 32); + hw->hw_timer[timer_num].loadlo.tx_load_lo = (uint32_t)reload_val; +} + +/** + * @brief Get reload value + * + * @param hw Timer Group register base address + * @param timer_num Timer number in the group + * @return reload count value + */ +__attribute__((always_inline)) +static inline uint64_t timer_ll_get_reload_value(timg_dev_t *hw, uint32_t timer_num) +{ + return ((uint64_t)hw->hw_timer[timer_num].loadhi.tx_load_hi << 32) | (hw->hw_timer[timer_num].loadlo.tx_load_lo); +} + +/** + * @brief Trigger software reload, value set by `timer_ll_set_reload_value()` will be reflected into counter immediately + * + * @param hw Timer Group register base address + * @param timer_num Timer number in the group + */ +__attribute__((always_inline)) +static inline void timer_ll_trigger_soft_reload(timg_dev_t *hw, uint32_t timer_num) +{ + hw->hw_timer[timer_num].load.tx_load = 1; +} + +/** + * @brief Enable ETM module + * + * @param hw Timer Group register base address + * @param en True: enable ETM module, False: disable ETM module + */ +static inline void timer_ll_enable_etm(timg_dev_t *hw, bool en) +{ + hw->regclk.etm_en = en; +} + +/** + * @brief Enable timer interrupt by mask + * + * @param hw Timer Group register base address + * @param mask Mask of interrupt events + * @param en True: enable interrupt + * False: disable interrupt + */ +__attribute__((always_inline)) +static inline void timer_ll_enable_intr(timg_dev_t *hw, uint32_t mask, bool en) +{ + if (en) { + hw->int_ena_timers.val |= mask; + } else { + hw->int_ena_timers.val &= ~mask; + } +} + +/** + * @brief Get interrupt status + * + * @param hw Timer Group register base address + * + * @return Interrupt status + */ +__attribute__((always_inline)) +static inline uint32_t timer_ll_get_intr_status(timg_dev_t *hw) +{ + return hw->int_st_timers.val & 0x01; +} + +/** + * @brief Clear interrupt status by mask + * + * @param hw Timer Group register base address + * @param mask Interrupt events mask + */ +__attribute__((always_inline)) +static inline void timer_ll_clear_intr_status(timg_dev_t *hw, uint32_t mask) +{ + hw->int_clr_timers.val = mask; +} + +/** + * @brief Enable the register clock forever + * + * @param hw Timer Group register base address + * @param en True: Enable the register clock forever + * False: Register clock is enabled only when register operation happens + */ +static inline void timer_ll_enable_register_clock_always_on(timg_dev_t *hw, bool en) +{ + hw->regclk.clk_en = en; +} + +/** + * @brief Get interrupt status register address + * + * @param hw Timer Group register base address + * + * @return Interrupt status register address + */ +static inline volatile void *timer_ll_get_intr_status_reg(timg_dev_t *hw) +{ + return &hw->int_st_timers; +} #ifdef __cplusplus } diff --git a/components/hal/esp32c6/include/hal/timer_ll.h b/components/hal/esp32c6/include/hal/timer_ll.h index d255f6a0b5..ec55eef0b6 100644 --- a/components/hal/esp32c6/include/hal/timer_ll.h +++ b/components/hal/esp32c6/include/hal/timer_ll.h @@ -1,10 +1,11 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -// Note that most of the register operations in this layer are non-atomic operations. +// Attention: Timer Group has 3 independent functions: General Purpose Timer, Watchdog Timer and Clock calibration. +// This Low Level driver only serve the General Purpose Timer function. #pragma once diff --git a/components/hal/esp32h2/include/hal/timer_ll.h b/components/hal/esp32h2/include/hal/timer_ll.h index 7c27843c03..ea3cd5514a 100644 --- a/components/hal/esp32h2/include/hal/timer_ll.h +++ b/components/hal/esp32h2/include/hal/timer_ll.h @@ -1,10 +1,11 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -// Note that most of the register operations in this layer are non-atomic operations. +// Attention: Timer Group has 3 independent functions: General Purpose Timer, Watchdog Timer and Clock calibration. +// This Low Level driver only serve the General Purpose Timer function. #pragma once diff --git a/components/hal/esp32p4/include/hal/timer_ll.h b/components/hal/esp32p4/include/hal/timer_ll.h index 60ed09bfc6..978c89722b 100644 --- a/components/hal/esp32p4/include/hal/timer_ll.h +++ b/components/hal/esp32p4/include/hal/timer_ll.h @@ -1,10 +1,11 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -// Note that most of the register operations in this layer are non-atomic operations. +// Attention: Timer Group has 3 independent functions: General Purpose Timer, Watchdog Timer and Clock calibration. +// This Low Level driver only serve the General Purpose Timer function. #pragma once diff --git a/components/hal/esp32s2/include/hal/timer_ll.h b/components/hal/esp32s2/include/hal/timer_ll.h index aae6114a2e..9a14793168 100644 --- a/components/hal/esp32s2/include/hal/timer_ll.h +++ b/components/hal/esp32s2/include/hal/timer_ll.h @@ -1,10 +1,11 @@ /* - * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -// Note that most of the register operations in this layer are non-atomic operations. +// Attention: Timer Group has 3 independent functions: General Purpose Timer, Watchdog Timer and Clock calibration. +// This Low Level driver only serve the General Purpose Timer function. #pragma once diff --git a/components/hal/esp32s3/include/hal/timer_ll.h b/components/hal/esp32s3/include/hal/timer_ll.h index 0da727256c..73621a977b 100644 --- a/components/hal/esp32s3/include/hal/timer_ll.h +++ b/components/hal/esp32s3/include/hal/timer_ll.h @@ -1,10 +1,11 @@ /* - * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -// Note that most of the register operations in this layer are non-atomic operations. +// Attention: Timer Group has 3 independent functions: General Purpose Timer, Watchdog Timer and Clock calibration. +// This Low Level driver only serve the General Purpose Timer function. #pragma once diff --git a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in index 2294333d62..7d59c51278 100644 --- a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in @@ -7,6 +7,10 @@ config SOC_UART_SUPPORTED bool default y +config SOC_GPTIMER_SUPPORTED + bool + default y + config SOC_EFUSE_KEY_PURPOSE_FIELD bool default y @@ -215,6 +219,18 @@ config SOC_TIMER_GROUP_TIMERS_PER_GROUP int default 1 +config SOC_TIMER_GROUP_COUNTER_BIT_WIDTH + int + default 54 + +config SOC_TIMER_GROUP_SUPPORT_XTAL + bool + default y + +config SOC_TIMER_GROUP_TOTAL_TIMERS + int + default 2 + config SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS int default 3 diff --git a/components/soc/esp32c5/include/soc/clk_tree_defs.h b/components/soc/esp32c5/include/soc/clk_tree_defs.h index acda20271a..9eb3e85f2d 100644 --- a/components/soc/esp32c5/include/soc/clk_tree_defs.h +++ b/components/soc/esp32c5/include/soc/clk_tree_defs.h @@ -167,12 +167,12 @@ typedef enum { // TODO: [ESP32C5] IDF-8676 (inherit from C6) * } * @endcode */ -#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL} +#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_PLL_F80M/*, SOC_MOD_CLK_RC_FAST*/, SOC_MOD_CLK_XTAL} /** * @brief Type of GPTimer clock source */ -typedef enum { // TODO: [ESP32C5] IDF-8705 (inherit from C6) +typedef enum { GPTIMER_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */ GPTIMER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ GPTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ @@ -182,7 +182,7 @@ typedef enum { // TODO: [ESP32C5] IDF-8705 (inherit from C6) /** * @brief Type of Timer Group clock source, reserved for the legacy timer group driver */ -typedef enum { // TODO: [ESP32C5] IDF-8705 (inherit from C6) +typedef enum { TIMER_SRC_CLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Timer group clock source is PLL_F80M */ TIMER_SRC_CLK_XTAL = SOC_MOD_CLK_XTAL, /*!< Timer group clock source is XTAL */ TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Timer group clock source default choice is PLL_F80M */ diff --git a/components/soc/esp32c5/include/soc/soc_caps.h b/components/soc/esp32c5/include/soc/soc_caps.h index e9028f8478..b7c3c2efcd 100644 --- a/components/soc/esp32c5/include/soc/soc_caps.h +++ b/components/soc/esp32c5/include/soc/soc_caps.h @@ -22,7 +22,7 @@ #define SOC_UART_SUPPORTED 1 // TODO: [ESP32C5] IDF-8722 // #define SOC_GDMA_SUPPORTED 1 // TODO: [ESP32C5] IDF-8710 // #define SOC_AHB_GDMA_SUPPORTED 1 // TODO: [ESP32C5] IDF-8710 -// #define SOC_GPTIMER_SUPPORTED 1 // TODO: [ESP32C5] IDF-8705 +#define SOC_GPTIMER_SUPPORTED 1 // #define SOC_PCNT_SUPPORTED 1 // TODO: [ESP32C5] IDF-8683 // #define SOC_MCPWM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8709 // #define SOC_TWAI_SUPPORTED 1 // TODO: [ESP32C5] IDF-8691 @@ -426,10 +426,10 @@ /*--------------------------- TIMER GROUP CAPS ---------------------------------------*/ #define SOC_TIMER_GROUPS (2) #define SOC_TIMER_GROUP_TIMERS_PER_GROUP (1U) -// #define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54) -// #define SOC_TIMER_GROUP_SUPPORT_XTAL (1) +#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54) +#define SOC_TIMER_GROUP_SUPPORT_XTAL (1) // #define SOC_TIMER_GROUP_SUPPORT_RC_FAST (1) -// #define SOC_TIMER_GROUP_TOTAL_TIMERS (2) +#define SOC_TIMER_GROUP_TOTAL_TIMERS (2) // #define SOC_TIMER_SUPPORT_ETM (1) /*--------------------------- WATCHDOG CAPS ---------------------------------------*/ @@ -516,7 +516,6 @@ /* macro redefine for pass esp_wifi headers md5sum check */ // #define MAC_SUPPORT_PMU_MODEM_STATE SOC_PM_SUPPORT_PMU_MODEM_STATE - // #define SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY (1) /*!