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fix(console): enable to select UART1 port for console output 

This feature was only enabled for esp32, esp32s2, esp32s3 previously.
Now, enabling this feature for all targets.
pull/12666/head
Song Ruo Jing 2023-10-24 11:40:35 +08:00
rodzic 455cc345f7
commit 46d33e46ef
28 zmienionych plików z 132 dodań i 149 usunięć
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12
components/bootloader_support/src/bootloader_console.c
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@ -38,6 +38,7 @@ void bootloader_console_init(void)
void bootloader_console_init(void)
{
const int uart_num = CONFIG_ESP_CONSOLE_UART_NUM;
int __DECLARE_RCC_ATOMIC_ENV __attribute__ ((unused)); // To avoid build errors/warnings about __DECLARE_RCC_ATOMIC_ENV
// Install rom uart printf as console.
esp_rom_install_uart_printf();
@ -59,8 +60,8 @@ void bootloader_console_init(void)
uart_tx_gpio != UART_NUM_0_TXD_DIRECT_GPIO_NUM ||
uart_rx_gpio != UART_NUM_0_RXD_DIRECT_GPIO_NUM) {
// Change default UART pins back to GPIOs
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_U0RXD_U, PIN_FUNC_GPIO);
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_U0TXD_U, PIN_FUNC_GPIO);
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[UART_NUM_0_RXD_DIRECT_GPIO_NUM], PIN_FUNC_GPIO);
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[UART_NUM_0_TXD_DIRECT_GPIO_NUM], PIN_FUNC_GPIO);
// Route GPIO signals to/from pins
const uint32_t tx_idx = UART_PERIPH_SIGNAL(uart_num, SOC_UART_TX_PIN_IDX);
const uint32_t rx_idx = UART_PERIPH_SIGNAL(uart_num, SOC_UART_RX_PIN_IDX);
@ -71,7 +72,11 @@ void bootloader_console_init(void)
esp_rom_gpio_connect_in_signal(uart_rx_gpio, rx_idx, 0);
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[uart_tx_gpio], PIN_FUNC_GPIO);
// Enable the peripheral
periph_ll_enable_clk_clear_rst(PERIPH_UART0_MODULE + uart_num);
uart_ll_enable_bus_clock(uart_num, true);
uart_ll_reset_register(uart_num);
// Reset TX and RX FIFOs
uart_ll_txfifo_rst(UART_LL_GET_HW(uart_num));
uart_ll_rxfifo_rst(UART_LL_GET_HW(uart_num));
}
#endif // CONFIG_ESP_CONSOLE_UART_CUSTOM
@ -80,7 +85,6 @@ void bootloader_console_init(void)
#if ESP_ROM_UART_CLK_IS_XTAL
clock_hz = (uint32_t)rtc_clk_xtal_freq_get() * MHZ; // From esp32-s3 on, UART clk source is selected to XTAL in ROM
#endif
int __DECLARE_RCC_ATOMIC_ENV __attribute__ ((unused)); // To avoid build errors/warnings about __DECLARE_RCC_ATOMIC_ENV
esp_rom_uart_set_clock_baudrate(uart_num, clock_hz, CONFIG_ESP_CONSOLE_UART_BAUDRATE);
}
#endif // CONFIG_ESP_CONSOLE_UART

14
components/driver/uart/uart.c
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@ -183,23 +183,9 @@ static void uart_module_enable(uart_port_t uart_num)
uart_ll_enable_bus_clock(uart_num, true);
}
if (uart_num != CONFIG_ESP_CONSOLE_UART_NUM) {
// Workaround for ESP32C3/S3: enable core reset before enabling uart module clock to prevent uart output
// garbage value.
#if SOC_UART_REQUIRE_CORE_RESET
HP_UART_SRC_CLK_ATOMIC(){
uart_hal_set_reset_core(&(uart_context[uart_num].hal), true);
}
HP_UART_BUS_CLK_ATOMIC() {
uart_ll_reset_register(uart_num);
}
HP_UART_SRC_CLK_ATOMIC(){
uart_hal_set_reset_core(&(uart_context[uart_num].hal), false);
}
#else
HP_UART_BUS_CLK_ATOMIC() {
uart_ll_reset_register(uart_num);
}
#endif
}
}
#if (SOC_UART_LP_NUM >= 1)

11
components/esp_system/Kconfig
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@ -275,13 +275,9 @@ menu "ESP System Settings"
bool
default y if ESP_CONSOLE_UART_DEFAULT || ESP_CONSOLE_UART_CUSTOM
config ESP_CONSOLE_MULTIPLE_UART
bool
default y if !IDF_TARGET_ESP32C3 && !IDF_TARGET_ESP32H2 && !IDF_TARGET_ESP32C2 && !IDF_TARGET_ESP32C6
choice ESP_CONSOLE_UART_NUM
prompt "UART peripheral to use for console output (0-1)"
depends on ESP_CONSOLE_UART_CUSTOM && ESP_CONSOLE_MULTIPLE_UART
depends on ESP_CONSOLE_UART_CUSTOM
default ESP_CONSOLE_UART_CUSTOM_NUM_0
help
This UART peripheral is used for console output from the ESP-IDF Bootloader and the app.
@ -301,7 +297,6 @@ menu "ESP System Settings"
config ESP_CONSOLE_UART_NUM
int
default 0 if ESP_CONSOLE_UART_DEFAULT
default 0 if !ESP_CONSOLE_MULTIPLE_UART
default 0 if ESP_CONSOLE_UART_CUSTOM_NUM_0
default 1 if ESP_CONSOLE_UART_CUSTOM_NUM_1
default -1 if !ESP_CONSOLE_UART
@ -309,7 +304,7 @@ menu "ESP System Settings"
config ESP_CONSOLE_UART_TX_GPIO
int "UART TX on GPIO#"
depends on ESP_CONSOLE_UART_CUSTOM
range 0 46
range 0 SOC_GPIO_OUT_RANGE_MAX
default 1 if IDF_TARGET_ESP32
default 20 if IDF_TARGET_ESP32C2
default 21 if IDF_TARGET_ESP32C3
@ -327,7 +322,7 @@ menu "ESP System Settings"
config ESP_CONSOLE_UART_RX_GPIO
int "UART RX on GPIO#"
depends on ESP_CONSOLE_UART_CUSTOM
range 0 46
range 0 SOC_GPIO_IN_RANGE_MAX
default 3 if IDF_TARGET_ESP32
default 19 if IDF_TARGET_ESP32C2
default 20 if IDF_TARGET_ESP32C3

13
components/hal/esp32c2/include/hal/uart_ll.h
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@ -121,19 +121,6 @@ static inline void uart_ll_reset_register(uart_port_t uart_num)
// SYSTEM.perip_rst_en0 is a shared register, so this function must be used in an atomic way
#define uart_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; uart_ll_reset_register(__VA_ARGS__)
/**
* @brief Configure the UART core reset.
*
* @param hw Beginning address of the peripheral registers.
* @param core_rst_en True to enable the core reset, otherwise set it false.
*
* @return None.
*/
FORCE_INLINE_ATTR void uart_ll_set_reset_core(uart_dev_t *hw, bool core_rst_en)
{
hw->clk_conf.rst_core = core_rst_en;
}
/**
* @brief Enable the UART clock.
*

18
components/hal/esp32c3/include/hal/uart_ll.h
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@ -104,14 +104,19 @@ static inline void uart_ll_enable_bus_clock(uart_port_t uart_num, bool enable)
*/
static inline void uart_ll_reset_register(uart_port_t uart_num)
{
// ESP32C3 requires a workaround: enable core reset before enabling uart module clock to prevent uart output garbage value
switch (uart_num) {
case 0:
UART0.clk_conf.rst_core = 1;
SYSTEM.perip_rst_en0.reg_uart_rst = 1;
SYSTEM.perip_rst_en0.reg_uart_rst = 0;
UART0.clk_conf.rst_core = 0;
break;
case 1:
UART1.clk_conf.rst_core = 1;
SYSTEM.perip_rst_en0.reg_uart1_rst = 1;
SYSTEM.perip_rst_en0.reg_uart1_rst = 0;
UART1.clk_conf.rst_core = 0;
break;
default:
abort();
@ -121,19 +126,6 @@ static inline void uart_ll_reset_register(uart_port_t uart_num)
// SYSTEM.perip_rst_enx are shared registers, so this function must be used in an atomic way
#define uart_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; uart_ll_reset_register(__VA_ARGS__)
/**
* @brief Configure the UART core reset.
*
* @param hw Beginning address of the peripheral registers.
* @param core_rst_en True to enable the core reset, otherwise set it false.
*
* @return None.
*/
FORCE_INLINE_ATTR void uart_ll_set_reset_core(uart_dev_t *hw, bool core_rst_en)
{
hw->clk_conf.rst_core = core_rst_en;
}
/**
* @brief Enable the UART clock.
*

25
components/hal/esp32c6/include/hal/uart_ll.h
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@ -265,25 +265,6 @@ static inline void uart_ll_reset_register(uart_port_t uart_num)
}
}
/**
* @brief Configure the UART core reset.
*
* @param hw Beginning address of the peripheral registers.
* @param core_rst_en True to enable the core reset, otherwise set it false.
*
* @return None.
*/
FORCE_INLINE_ATTR void uart_ll_set_reset_core(uart_dev_t *hw, bool core_rst_en)
{
if ((hw) != &LP_UART) {
UART_LL_PCR_REG_SET(hw, conf, rst_en, core_rst_en);
} else {
// LP_UART reset shares the same register with other LP peripherals
// Needs to be protected with a lock, therefore, it has its unique LL function, and must be called from lp_periph_ctrl.c
abort();
}
}
/**
* @brief Enable the UART clock.
*
@ -297,7 +278,7 @@ FORCE_INLINE_ATTR void uart_ll_sclk_enable(uart_dev_t *hw)
UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_en, 1);
} else {
// LP_UART clk_en shares the same register with other LP peripherals
// Needs to be protected with a lock, therefore, it has its unique LL function, and must be called from lp_periph_ctrl.c
// Needs to be protected with a lock, therefore, it has its unique LL function
abort();
}
}
@ -315,7 +296,7 @@ FORCE_INLINE_ATTR void uart_ll_sclk_disable(uart_dev_t *hw)
UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_en, 0);
} else {
// LP_UART clk_en shares the same register with other LP peripherals
// Needs to be protected with a lock, therefore, it has its unique LL function, and must be called from lp_periph_ctrl.c
// Needs to be protected with a lock, therefore, it has its unique LL function
abort();
}
}
@ -350,7 +331,7 @@ FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, soc_module_clk_t source_
UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_sel, sel_value);
} else {
// LP_UART clk_sel shares the same register with other LP peripherals
// Needs to be protected with a lock, therefore, it has its unique LL function, and must be called from lp_periph_ctrl.c
// Needs to be protected with a lock, therefore, it has its unique LL function
abort();
}
}

13
components/hal/esp32h2/include/hal/uart_ll.h
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@ -154,19 +154,6 @@ FORCE_INLINE_ATTR void uart_ll_update(uart_dev_t *hw)
while (hw->reg_update.reg_update);
}
/**
* @brief Configure the UART core reset.
*
* @param hw Beginning address of the peripheral registers.
* @param core_rst_en True to enable the core reset, otherwise set it false.
*
* @return None.
*/
FORCE_INLINE_ATTR void uart_ll_set_reset_core(uart_dev_t *hw, bool core_rst_en)
{
UART_LL_PCR_REG_SET(hw, conf, rst_en, core_rst_en);
}
/**
* @brief Enable the UART clock.
*

28
components/hal/esp32p4/include/hal/uart_ll.h
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@ -315,34 +315,6 @@ static inline void uart_ll_reset_register(uart_port_t uart_num)
// HP_SYS_CLKRST.hp_rst_en1 is a shared register, so this function must be used in an atomic way
#define uart_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; uart_ll_reset_register(__VA_ARGS__)
/**
* @brief Configure the UART core reset.
*
* @param hw Beginning address of the peripheral registers.
* @param core_rst_en True to enable the core reset, otherwise set it false.
*
* @return None.
*/
FORCE_INLINE_ATTR void uart_ll_set_reset_core(uart_dev_t *hw, bool core_rst_en)
{
if ((hw) == &UART0) {
HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_uart0_core = core_rst_en;
} else if ((hw) == &UART1) {
HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_uart1_core = core_rst_en;
} else if ((hw) == &UART2) {
HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_uart2_core = core_rst_en;
} else if ((hw) == &UART3) {
HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_uart3_core = core_rst_en;
} else if ((hw) == &UART4) {
HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_uart4_core = core_rst_en;
} else {
// Not going to implement LP_UART reset in this function, it will have its own LL function
abort();
}
}
// HP_SYS_CLKRST.hp_rst_en1 is a shared register, so this function must be used in an atomic way
#define uart_ll_set_reset_core(...) (void)__DECLARE_RCC_ATOMIC_ENV; uart_ll_set_reset_core(__VA_ARGS__)
/**
* @brief Enable the UART clock.
*

20
components/hal/esp32s3/include/hal/uart_ll.h
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@ -109,18 +109,25 @@ static inline void uart_ll_enable_bus_clock(uart_port_t uart_num, bool enable)
*/
static inline void uart_ll_reset_register(uart_port_t uart_num)
{
// ESP32S3 requires a workaround: enable core reset before enabling uart module clock to prevent uart output garbage value
switch (uart_num) {
case 0:
UART0.clk_conf.rst_core = 1;
SYSTEM.perip_rst_en0.uart_rst = 1;
SYSTEM.perip_rst_en0.uart_rst = 0;
UART0.clk_conf.rst_core = 0;
break;
case 1:
UART1.clk_conf.rst_core = 1;
SYSTEM.perip_rst_en0.uart1_rst = 1;
SYSTEM.perip_rst_en0.uart1_rst = 0;
UART1.clk_conf.rst_core = 0;
break;
case 2:
UART2.clk_conf.rst_core = 1;
SYSTEM.perip_rst_en1.uart2_rst = 1;
SYSTEM.perip_rst_en1.uart2_rst = 0;
UART2.clk_conf.rst_core = 0;
break;
default:
abort();
@ -130,19 +137,6 @@ static inline void uart_ll_reset_register(uart_port_t uart_num)
// SYSTEM.perip_rst_enx are shared registers, so this function must be used in an atomic way
#define uart_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; uart_ll_reset_register(__VA_ARGS__)
/**
* @brief Configure the UART core reset.
*
* @param hw Beginning address of the peripheral registers.
* @param core_rst_en True to enable the core reset, otherwise set it false.
*
* @return None.
*/
static inline void uart_ll_set_reset_core(uart_dev_t *hw, bool core_rst_en)
{
hw->clk_conf.rst_core = core_rst_en;
}
/**
* @brief Set the UART source clock.
*

10
components/hal/include/hal/uart_hal.h
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@ -145,16 +145,6 @@ typedef struct {
*/
#define uart_hal_is_tx_idle(hal) uart_ll_is_tx_idle((hal)->dev)
/**
* @brief Configure the UART core reset
*
* @param hal Context of the HAL layer
* @param core_rst_en true to enable the core reset, otherwise set it false
*
* @return None
*/
#define uart_hal_set_reset_core(hal, core_rst_en) uart_ll_set_reset_core((hal)->dev, core_rst_en)
/**
* @brief Read data from the UART rxfifo
*

8
components/soc/esp32/include/soc/Kconfig.soc_caps.in
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@ -311,6 +311,14 @@ config SOC_GPIO_VALID_GPIO_MASK
hex
default 0xFFFFFFFFFF
config SOC_GPIO_IN_RANGE_MAX
int
default 39
config SOC_GPIO_OUT_RANGE_MAX
int
default 33
config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
hex
default 0xEF0FEA

3
components/soc/esp32/include/soc/soc_caps.h
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@ -178,6 +178,9 @@
// GPIO >= 34 are input only
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK (SOC_GPIO_VALID_GPIO_MASK & ~(0ULL | BIT34 | BIT35 | BIT36 | BIT37 | BIT38 | BIT39))
#define SOC_GPIO_IN_RANGE_MAX 39
#define SOC_GPIO_OUT_RANGE_MAX 33
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM: 1, 3, 5, 6, 7, 8, 9, 10, 11, 16, 17, 18, 19, 21, 22, 23)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0xEF0FEAULL

8
components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
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@ -271,6 +271,14 @@ config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
bool
default y
config SOC_GPIO_IN_RANGE_MAX
int
default 20
config SOC_GPIO_OUT_RANGE_MAX
int
default 20
config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
int
default 0

4
components/soc/esp32c2/include/soc/soc_caps.h
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@ -131,6 +131,10 @@
#define SOC_GPIO_VALID_GPIO_MASK ((1U<<SOC_GPIO_PIN_COUNT) - 1)
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
#define SOC_GPIO_IN_RANGE_MAX 20
#define SOC_GPIO_OUT_RANGE_MAX 20
#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5)
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_6~GPIO_NUM_20)

12
components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
Wyświetl plik

@ -363,6 +363,14 @@ config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
bool
default y
config SOC_GPIO_IN_RANGE_MAX
int
default 21
config SOC_GPIO_OUT_RANGE_MAX
int
default 21
config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
int
default 0
@ -907,10 +915,6 @@ config SOC_UART_SUPPORT_WAKEUP_INT
bool
default y
config SOC_UART_REQUIRE_CORE_RESET
bool
default y
config SOC_UART_SUPPORT_FSM_TX_WAIT_SEND
bool
default y

5
components/soc/esp32c3/include/soc/soc_caps.h
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@ -169,6 +169,10 @@
#define SOC_GPIO_VALID_GPIO_MASK ((1U<<SOC_GPIO_PIN_COUNT) - 1)
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
#define SOC_GPIO_IN_RANGE_MAX 21
#define SOC_GPIO_OUT_RANGE_MAX 21
#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5)
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_6~GPIO_NUM_21)
@ -392,7 +396,6 @@
#define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */
#define SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */
#define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */
#define SOC_UART_REQUIRE_CORE_RESET (1)
// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1)

8
components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
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@ -459,6 +459,14 @@ config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
bool
default y
config SOC_GPIO_IN_RANGE_MAX
int
default 30
config SOC_GPIO_OUT_RANGE_MAX
int
default 30
config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
int
default 0

4
components/soc/esp32c6/include/soc/soc_caps.h
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@ -198,6 +198,10 @@
#define SOC_GPIO_VALID_GPIO_MASK ((1U<<SOC_GPIO_PIN_COUNT) - 1)
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
#define SOC_GPIO_IN_RANGE_MAX 30
#define SOC_GPIO_OUT_RANGE_MAX 30
#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7)
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_8~GPIO_NUM_30)

8
components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
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@ -463,6 +463,14 @@ config SOC_GPIO_SUPPORT_RTC_INDEPENDENT
bool
default y
config SOC_GPIO_IN_RANGE_MAX
int
default 27
config SOC_GPIO_OUT_RANGE_MAX
int
default 27
config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
hex
default 0x000000000FFF807F

3
components/soc/esp32h2/include/soc/soc_caps.h
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@ -204,6 +204,9 @@
#define SOC_GPIO_VALID_GPIO_MASK ((1U << SOC_GPIO_PIN_COUNT) - 1)
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
#define SOC_GPIO_IN_RANGE_MAX 27
#define SOC_GPIO_OUT_RANGE_MAX 27
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_0~6. GPIO_NUM_15~27)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x000000000FFF807FULL

8
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
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@ -399,6 +399,14 @@ config SOC_GPIO_VALID_GPIO_MASK
hex
default 0x01FFFFFFFFFFFFFF
config SOC_GPIO_IN_RANGE_MAX
int
default 56
config SOC_GPIO_OUT_RANGE_MAX
int
default 56
config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
int
default 0

4
components/soc/esp32p4/include/soc/soc_caps.h
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@ -204,6 +204,10 @@
#define SOC_GPIO_VALID_GPIO_MASK (0x01FFFFFFFFFFFFFF)
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
#define SOC_GPIO_IN_RANGE_MAX 56
#define SOC_GPIO_OUT_RANGE_MAX 56
#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | 0xFFFF)
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_16~GPIO_NUM_56)

8
components/soc/esp32s2/include/soc/Kconfig.soc_caps.in
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@ -363,6 +363,14 @@ config SOC_GPIO_VALID_GPIO_MASK
hex
default 0x7FFFFFFFFFFF
config SOC_GPIO_IN_RANGE_MAX
int
default 46
config SOC_GPIO_OUT_RANGE_MAX
int
default 45
config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
hex
default 0x00007FFFFC000000

3
components/soc/esp32s2/include/soc/soc_caps.h
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@ -168,6 +168,9 @@
// GPIO 46 is input only
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK (SOC_GPIO_VALID_GPIO_MASK & ~(0ULL | BIT46))
#define SOC_GPIO_IN_RANGE_MAX 46
#define SOC_GPIO_OUT_RANGE_MAX 45
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_26~GPIO_NUM_46)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x00007FFFFC000000ULL

12
components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
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@ -431,6 +431,14 @@ config SOC_GPIO_VALID_GPIO_MASK
hex
default 0x1FFFFFFFFFFFF
config SOC_GPIO_IN_RANGE_MAX
int
default 48
config SOC_GPIO_OUT_RANGE_MAX
int
default 48
config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
hex
default 0x0001FFFFFC000000
@ -967,10 +975,6 @@ config SOC_UART_SUPPORT_XTAL_CLK
bool
default y
config SOC_UART_REQUIRE_CORE_RESET
bool
default y
config SOC_USB_PERIPH_NUM
bool
default y

5
components/soc/esp32s3/include/soc/soc_caps.h
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@ -174,6 +174,10 @@
#define SOC_GPIO_VALID_GPIO_MASK (0x1FFFFFFFFFFFFULL & ~(0ULL | BIT22 | BIT23 | BIT24 | BIT25))
// No GPIO is input only
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK (SOC_GPIO_VALID_GPIO_MASK)
#define SOC_GPIO_IN_RANGE_MAX 48
#define SOC_GPIO_OUT_RANGE_MAX 48
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_26~GPIO_NUM_48)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x0001FFFFFC000000ULL
@ -380,7 +384,6 @@
#define SOC_UART_SUPPORT_APB_CLK (1) /*!< Support APB as the clock source */
#define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */
#define SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */
#define SOC_UART_REQUIRE_CORE_RESET (1)
/*-------------------------- USB CAPS ----------------------------------------*/
#define SOC_USB_PERIPH_NUM 1

8
components/soc/linux/include/soc/Kconfig.soc_caps.in
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@ -2,3 +2,11 @@
# This file is auto-generated from SoC caps
# using gen_soc_caps_kconfig.py, do not edit manually
#####################################################
config SOC_GPIO_IN_RANGE_MAX
int
default 65535
config SOC_GPIO_OUT_RANGE_MAX
int
default 65535

6
components/soc/linux/include/soc/soc_caps.h
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -23,3 +23,7 @@
*/
#pragma once
// No meaning to define GPIO number for Linux target, only to avoid build warning on Kconfig ESP_CONSOLE_UART_TX_GPIO, ESP_CONSOLE_UART_RX_GPIO
#define SOC_GPIO_IN_RANGE_MAX (65535)
#define SOC_GPIO_OUT_RANGE_MAX (65535)