mirror
/
esp-idf
kopia lustrzana https://github.com/espressif/esp-idf
1
0
Forkuj 0
Kod Zgłoszenia Projekty Wydania Wiki Aktywność

rmt: fix error in rmt register file 

Closes https://github.com/espressif/esp-idf/issues/9100
pull/9179/head
morris 2022-06-07 11:00:57 +08:00
rodzic aa2cf79e13
commit 4094f13fd3
8 zmienionych plików z 1742 dodań i 1740 usunięć
Pokaż statystyki Ściągnij plik aktualizacji Ściągnij plik porównania Expand all files Collapse all files

2
components/driver/gptimer.c
Wyświetl plik

@ -489,7 +489,7 @@ IRAM_ATTR static void gptimer_default_isr(void *args)
uint32_t intr_status = timer_ll_get_intr_status(timer->hal.dev);
if (intr_status & TIMER_LL_EVENT_ALARM(timer->timer_id)) {
// Note: when alarm event happends, the alarm will be disabled automatically by hardware
// Note: when alarm event happens, the alarm will be disabled automatically by hardware
gptimer_alarm_event_data_t edata = {
.count_value = timer_ll_get_counter_value(timer->hal.dev, timer->timer_id),
.alarm_value = timer->alarm_count,

1
components/driver/rmt/rmt_common.c
Wyświetl plik

@ -52,6 +52,7 @@ rmt_group_t *rmt_acquire_group_handle(int group_id)
group->clk_src = RMT_CLK_SRC_NONE;
// enable APB access RMT registers
periph_module_enable(rmt_periph_signals.groups[group_id].module);
periph_module_reset(rmt_periph_signals.groups[group_id].module);
// hal layer initialize
rmt_hal_init(&group->hal);
}

104
components/hal/esp32s2/include/hal/rmt_ll.h
Wyświetl plik

@ -93,10 +93,10 @@ static inline void rmt_ll_set_group_clock_src(rmt_dev_t *dev, uint32_t channel,
(void)divider_numerator;
switch (src) {
case RMT_CLK_SRC_APB:
dev->conf_ch[channel].conf1.ref_always_on = 1;
dev->conf_ch[channel].conf1.ref_always_on_chn = 1;
break;
case RMT_CLK_SRC_REF_TICK:
dev->conf_ch[channel].conf1.ref_always_on = 0;
dev->conf_ch[channel].conf1.ref_always_on_chn = 0;
break;
default:
HAL_ASSERT(false && "unsupported RMT clock source");
@ -132,7 +132,7 @@ static inline void rmt_ll_tx_set_channel_clock_div(rmt_dev_t *dev, uint32_t chan
if (div >= 256) {
div = 0; // 0 means 256 division
}
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt, div);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt_chn, div);
}
/**
@ -143,10 +143,10 @@ static inline void rmt_ll_tx_set_channel_clock_div(rmt_dev_t *dev, uint32_t chan
*/
static inline void rmt_ll_tx_reset_pointer(rmt_dev_t *dev, uint32_t channel)
{
dev->conf_ch[channel].conf1.mem_rd_rst = 1;
dev->conf_ch[channel].conf1.mem_rd_rst = 0;
dev->conf_ch[channel].conf1.apb_mem_rst = 1;
dev->conf_ch[channel].conf1.apb_mem_rst = 0;
dev->conf_ch[channel].conf1.mem_rd_rst_chn = 1;
dev->conf_ch[channel].conf1.mem_rd_rst_chn = 0;
dev->conf_ch[channel].conf1.apb_mem_rst_chn = 1;
dev->conf_ch[channel].conf1.apb_mem_rst_chn = 0;
}
/**
@ -157,7 +157,7 @@ static inline void rmt_ll_tx_reset_pointer(rmt_dev_t *dev, uint32_t channel)
*/
static inline void rmt_ll_tx_start(rmt_dev_t *dev, uint32_t channel)
{
dev->conf_ch[channel].conf1.tx_start = 1;
dev->conf_ch[channel].conf1.tx_start_chn = 1;
}
/**
@ -168,7 +168,7 @@ static inline void rmt_ll_tx_start(rmt_dev_t *dev, uint32_t channel)
*/
static inline void rmt_ll_tx_stop(rmt_dev_t *dev, uint32_t channel)
{
dev->conf_ch[channel].conf1.tx_stop = 1;
dev->conf_ch[channel].conf1.tx_stop_chn = 1;
}
/**
@ -180,7 +180,7 @@ static inline void rmt_ll_tx_stop(rmt_dev_t *dev, uint32_t channel)
*/
static inline void rmt_ll_tx_set_mem_blocks(rmt_dev_t *dev, uint32_t channel, uint8_t block_num)
{
dev->conf_ch[channel].conf0.mem_size = block_num;
dev->conf_ch[channel].conf0.mem_size_chn = block_num;
}
/**
@ -204,7 +204,7 @@ static inline void rmt_ll_tx_enable_wrap(rmt_dev_t *dev, uint32_t channel, bool
*/
static inline void rmt_ll_tx_enable_loop(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->conf_ch[channel].conf1.tx_conti_mode = enable;
dev->conf_ch[channel].conf1.tx_conti_mode_chn = enable;
}
/**
@ -217,7 +217,7 @@ static inline void rmt_ll_tx_enable_loop(rmt_dev_t *dev, uint32_t channel, bool
static inline void rmt_ll_tx_set_loop_count(rmt_dev_t *dev, uint32_t channel, uint32_t count)
{
HAL_ASSERT(count <= RMT_LL_MAX_LOOP_COUNT_PER_BATCH && "loop count out of range");
dev->tx_lim_ch[channel].tx_loop_num = count;
dev->chn_tx_lim[channel].tx_loop_num_chn = count;
}
/**
@ -228,8 +228,8 @@ static inline void rmt_ll_tx_set_loop_count(rmt_dev_t *dev, uint32_t channel, ui
*/
static inline void rmt_ll_tx_reset_loop_count(rmt_dev_t *dev, uint32_t channel)
{
dev->tx_lim_ch[channel].loop_count_reset = 1;
dev->tx_lim_ch[channel].loop_count_reset = 0;
dev->chn_tx_lim[channel].loop_count_reset_chn = 1;
dev->chn_tx_lim[channel].loop_count_reset_chn = 0;
}
/**
@ -241,7 +241,7 @@ static inline void rmt_ll_tx_reset_loop_count(rmt_dev_t *dev, uint32_t channel)
*/
static inline void rmt_ll_tx_enable_loop_count(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->tx_lim_ch[channel].tx_loop_cnt_en = enable;
dev->chn_tx_lim[channel].tx_loop_cnt_en_chn = enable;
}
/**
@ -252,7 +252,7 @@ static inline void rmt_ll_tx_enable_loop_count(rmt_dev_t *dev, uint32_t channel,
*/
static inline void rmt_ll_tx_enable_sync(rmt_dev_t *dev, bool enable)
{
dev->tx_sim.en = enable;
dev->tx_sim.tx_sim_en = enable;
}
/**
@ -297,8 +297,8 @@ static inline void rmt_ll_tx_sync_group_remove_channels(rmt_dev_t *dev, uint32_t
*/
static inline void rmt_ll_tx_fix_idle_level(rmt_dev_t *dev, uint32_t channel, uint8_t level, bool enable)
{
dev->conf_ch[channel].conf1.idle_out_en = enable;
dev->conf_ch[channel].conf1.idle_out_lv = level;
dev->conf_ch[channel].conf1.idle_out_en_chn = enable;
dev->conf_ch[channel].conf1.idle_out_lv_chn = level;
}
/**
@ -310,7 +310,7 @@ static inline void rmt_ll_tx_fix_idle_level(rmt_dev_t *dev, uint32_t channel, ui
*/
static inline void rmt_ll_tx_set_limit(rmt_dev_t *dev, uint32_t channel, uint32_t limit)
{
dev->tx_lim_ch[channel].tx_lim = limit;
dev->chn_tx_lim[channel].tx_lim_chn = limit;
}
/**
@ -331,8 +331,8 @@ static inline void rmt_ll_tx_set_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t
if (low_ticks >= 65536) {
low_ticks = 0;
}
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->carrier_duty_ch[channel], high, high_ticks);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->carrier_duty_ch[channel], low, low_ticks);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->chncarrier_duty[channel], carrier_high_chn, high_ticks);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->chncarrier_duty[channel], carrier_low_chn, low_ticks);
}
/**
@ -344,7 +344,7 @@ static inline void rmt_ll_tx_set_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t
*/
static inline void rmt_ll_tx_enable_carrier_modulation(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->conf_ch[channel].conf0.carrier_en = enable;
dev->conf_ch[channel].conf0.carrier_en_chn = enable;
}
/**
@ -356,7 +356,7 @@ static inline void rmt_ll_tx_enable_carrier_modulation(rmt_dev_t *dev, uint32_t
*/
static inline void rmt_ll_tx_set_carrier_level(rmt_dev_t *dev, uint32_t channel, uint8_t level)
{
dev->conf_ch[channel].conf0.carrier_out_lv = level;
dev->conf_ch[channel].conf0.carrier_out_lv_chn = level;
}
/**
@ -368,7 +368,7 @@ static inline void rmt_ll_tx_set_carrier_level(rmt_dev_t *dev, uint32_t channel,
*/
static inline void rmt_ll_tx_enable_carrier_always_on(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->conf_ch[channel].conf0.carrier_eff_en = !enable;
dev->conf_ch[channel].conf0.carrier_eff_en_chn = !enable;
}
////////////////////////////////////////RX Channel Specific/////////////////////////////////////////////////////////////
@ -399,7 +399,7 @@ static inline void rmt_ll_rx_set_channel_clock_div(rmt_dev_t *dev, uint32_t chan
if (div >= 256) {
div = 0; // 0 means 256 division
}
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt, div);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt_chn, div);
}
/**
@ -410,10 +410,10 @@ static inline void rmt_ll_rx_set_channel_clock_div(rmt_dev_t *dev, uint32_t chan
*/
static inline void rmt_ll_rx_reset_pointer(rmt_dev_t *dev, uint32_t channel)
{
dev->conf_ch[channel].conf1.mem_wr_rst = 1;
dev->conf_ch[channel].conf1.mem_wr_rst = 0;
dev->conf_ch[channel].conf1.apb_mem_rst = 1;
dev->conf_ch[channel].conf1.apb_mem_rst = 0;
dev->conf_ch[channel].conf1.mem_wr_rst_chn = 1;
dev->conf_ch[channel].conf1.mem_wr_rst_chn = 0;
dev->conf_ch[channel].conf1.apb_mem_rst_chn = 1;
dev->conf_ch[channel].conf1.apb_mem_rst_chn = 0;
}
/**
@ -425,7 +425,7 @@ static inline void rmt_ll_rx_reset_pointer(rmt_dev_t *dev, uint32_t channel)
*/
static inline void rmt_ll_rx_enable(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->conf_ch[channel].conf1.rx_en = enable;
dev->conf_ch[channel].conf1.rx_en_chn = enable;
}
/**
@ -437,7 +437,7 @@ static inline void rmt_ll_rx_enable(rmt_dev_t *dev, uint32_t channel, bool enabl
*/
static inline void rmt_ll_rx_set_mem_blocks(rmt_dev_t *dev, uint32_t channel, uint8_t block_num)
{
dev->conf_ch[channel].conf0.mem_size = block_num;
dev->conf_ch[channel].conf0.mem_size_chn = block_num;
}
/**
@ -449,7 +449,7 @@ static inline void rmt_ll_rx_set_mem_blocks(rmt_dev_t *dev, uint32_t channel, ui
*/
static inline void rmt_ll_rx_set_idle_thres(rmt_dev_t *dev, uint32_t channel, uint32_t thres)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->conf_ch[channel].conf0, idle_thres, thres);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->conf_ch[channel].conf0, idle_thres_chn, thres);
}
/**
@ -461,7 +461,7 @@ static inline void rmt_ll_rx_set_idle_thres(rmt_dev_t *dev, uint32_t channel, ui
*/
static inline void rmt_ll_rx_set_mem_owner(rmt_dev_t *dev, uint32_t channel, rmt_ll_mem_owner_t owner)
{
dev->conf_ch[channel].conf1.mem_owner = owner;
dev->conf_ch[channel].conf1.mem_owner_chn = owner;
}
/**
@ -473,7 +473,7 @@ static inline void rmt_ll_rx_set_mem_owner(rmt_dev_t *dev, uint32_t channel, rmt
*/
static inline void rmt_ll_rx_enable_filter(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->conf_ch[channel].conf1.rx_filter_en = enable;
dev->conf_ch[channel].conf1.rx_filter_en_chn = enable;
}
/**
@ -485,7 +485,7 @@ static inline void rmt_ll_rx_enable_filter(rmt_dev_t *dev, uint32_t channel, boo
*/
static inline void rmt_ll_rx_set_filter_thres(rmt_dev_t *dev, uint32_t channel, uint32_t thres)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->conf_ch[channel].conf1, rx_filter_thres, thres);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->conf_ch[channel].conf1, rx_filter_thres_chn, thres);
}
/**
@ -497,7 +497,7 @@ static inline void rmt_ll_rx_set_filter_thres(rmt_dev_t *dev, uint32_t channel,
*/
static inline uint32_t rmt_ll_rx_get_memory_writer_offset(rmt_dev_t *dev, uint32_t channel)
{
return dev->status_ch[channel].mem_waddr_ex - (channel) * 64;
return dev->chnstatus[channel].mem_waddr_ex_chn - (channel) * 64;
}
/**
@ -511,8 +511,8 @@ static inline uint32_t rmt_ll_rx_get_memory_writer_offset(rmt_dev_t *dev, uint32
static inline void rmt_ll_rx_set_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t high_ticks, uint32_t low_ticks)
{
HAL_ASSERT(high_ticks >= 1 && high_ticks <= 65536 && low_ticks >= 1 && low_ticks <= 65536 && "out of range high/low ticks");
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->ch_rx_carrier_rm[channel], carrier_high_thres_ch, high_ticks - 1);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->ch_rx_carrier_rm[channel], carrier_low_thres_ch, low_ticks - 1);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->chn_rx_carrier_rm[channel], carrier_high_thres_chn, high_ticks - 1);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->chn_rx_carrier_rm[channel], carrier_low_thres_chn, low_ticks - 1);
}
/**
@ -524,7 +524,7 @@ static inline void rmt_ll_rx_set_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t
*/
static inline void rmt_ll_rx_enable_carrier_demodulation(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->conf_ch[channel].conf0.carrier_en = enable;
dev->conf_ch[channel].conf0.carrier_en_chn = enable;
}
/**
@ -536,7 +536,7 @@ static inline void rmt_ll_rx_enable_carrier_demodulation(rmt_dev_t *dev, uint32_
*/
static inline void rmt_ll_rx_set_carrier_level(rmt_dev_t *dev, uint32_t channel, uint8_t level)
{
dev->conf_ch[channel].conf0.carrier_out_lv = level;
dev->conf_ch[channel].conf0.carrier_out_lv_chn = level;
}
//////////////////////////////////////////Interrupt Specific////////////////////////////////////////////////////////////
@ -634,49 +634,49 @@ static inline uint32_t rmt_ll_rx_get_interrupt_status(rmt_dev_t *dev, uint32_t c
static inline uint32_t rmt_ll_tx_get_status_word(rmt_dev_t *dev, uint32_t channel)
{
return dev->status_ch[channel].val;
return dev->chnstatus[channel].val;
}
static inline uint32_t rmt_ll_rx_get_status_word(rmt_dev_t *dev, uint32_t channel)
{
return dev->status_ch[channel].val;
return dev->chnstatus[channel].val;
}
static inline uint32_t rmt_ll_tx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel)
{
uint32_t div = HAL_FORCE_READ_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt);
uint32_t div = HAL_FORCE_READ_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt_chn);
return div == 0 ? 256 : div;
}
static inline uint32_t rmt_ll_rx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel)
{
uint32_t div = HAL_FORCE_READ_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt);
uint32_t div = HAL_FORCE_READ_U32_REG_FIELD(dev->conf_ch[channel].conf0, div_cnt_chn);
return div == 0 ? 256 : div;
}
static inline uint32_t rmt_ll_rx_get_idle_thres(rmt_dev_t *dev, uint32_t channel)
{
return HAL_FORCE_READ_U32_REG_FIELD(dev->conf_ch[channel].conf0, idle_thres);
return HAL_FORCE_READ_U32_REG_FIELD(dev->conf_ch[channel].conf0, idle_thres_chn);
}
static inline uint32_t rmt_ll_tx_get_mem_blocks(rmt_dev_t *dev, uint32_t channel)
{
return dev->conf_ch[channel].conf0.mem_size;
return dev->conf_ch[channel].conf0.mem_size_chn;
}
static inline uint32_t rmt_ll_rx_get_mem_blocks(rmt_dev_t *dev, uint32_t channel)
{
return dev->conf_ch[channel].conf0.mem_size;
return dev->conf_ch[channel].conf0.mem_size_chn;
}
static inline bool rmt_ll_tx_is_loop_enabled(rmt_dev_t *dev, uint32_t channel)
{
return dev->conf_ch[channel].conf1.tx_conti_mode;
return dev->conf_ch[channel].conf1.tx_conti_mode_chn;
}
static inline rmt_clock_source_t rmt_ll_get_group_clock_src(rmt_dev_t *dev, uint32_t channel)
{
if (dev->conf_ch[channel].conf1.ref_always_on) {
if (dev->conf_ch[channel].conf1.ref_always_on_chn) {
return RMT_CLK_SRC_APB;
}
return RMT_CLK_SRC_REF_TICK;
@ -684,12 +684,12 @@ static inline rmt_clock_source_t rmt_ll_get_group_clock_src(rmt_dev_t *dev, uint
static inline bool rmt_ll_tx_is_idle_enabled(rmt_dev_t *dev, uint32_t channel)
{
return dev->conf_ch[channel].conf1.idle_out_en;
return dev->conf_ch[channel].conf1.idle_out_en_chn;
}
static inline uint32_t rmt_ll_tx_get_idle_level(rmt_dev_t *dev, uint32_t channel)
{
return dev->conf_ch[channel].conf1.idle_out_lv;
return dev->conf_ch[channel].conf1.idle_out_lv_chn;
}
static inline bool rmt_ll_is_mem_powered_down(rmt_dev_t *dev)
@ -702,7 +702,7 @@ static inline bool rmt_ll_is_mem_powered_down(rmt_dev_t *dev)
static inline uint32_t rmt_ll_rx_get_mem_owner(rmt_dev_t *dev, uint32_t channel)
{
return dev->conf_ch[channel].conf1.mem_owner;
return dev->conf_ch[channel].conf1.mem_owner_chn;
}
static inline uint32_t rmt_ll_get_tx_end_interrupt_status(rmt_dev_t *dev)

92
components/hal/esp32s3/include/hal/rmt_ll.h
Wyświetl plik

@ -139,7 +139,7 @@ static inline void rmt_ll_tx_set_channel_clock_div(rmt_dev_t *dev, uint32_t chan
if (div >= 256) {
div = 0; // 0 means 256 division
}
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->chnconf0[channel], div_cnt_n, div);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->chnconf0[channel], div_cnt_chn, div);
}
/**
@ -150,10 +150,10 @@ static inline void rmt_ll_tx_set_channel_clock_div(rmt_dev_t *dev, uint32_t chan
*/
static inline void rmt_ll_tx_reset_pointer(rmt_dev_t *dev, uint32_t channel)
{
dev->chnconf0[channel].mem_rd_rst_n = 1;
dev->chnconf0[channel].mem_rd_rst_n = 0;
dev->chnconf0[channel].apb_mem_rst_n = 1;
dev->chnconf0[channel].apb_mem_rst_n = 0;
dev->chnconf0[channel].mem_rd_rst_chn = 1;
dev->chnconf0[channel].mem_rd_rst_chn = 0;
dev->chnconf0[channel].apb_mem_rst_chn = 1;
dev->chnconf0[channel].apb_mem_rst_chn = 0;
}
/**
@ -166,7 +166,7 @@ static inline void rmt_ll_tx_reset_pointer(rmt_dev_t *dev, uint32_t channel)
static inline void rmt_ll_tx_enable_dma(rmt_dev_t *dev, uint32_t channel, bool enable)
{
HAL_ASSERT(channel == 3 && "only TX channel 3 has DMA ability");
dev->chnconf0[channel].dma_access_en_n = enable;
dev->chnconf0[channel].dma_access_en_chn = enable;
}
/**
@ -178,8 +178,8 @@ static inline void rmt_ll_tx_enable_dma(rmt_dev_t *dev, uint32_t channel, bool e
static inline void rmt_ll_tx_start(rmt_dev_t *dev, uint32_t channel)
{
// update other configuration registers before start transmitting
dev->chnconf0[channel].conf_update_n = 1;
dev->chnconf0[channel].tx_start_n = 1;
dev->chnconf0[channel].conf_update_chn = 1;
dev->chnconf0[channel].tx_start_chn = 1;
}
/**
@ -190,9 +190,9 @@ static inline void rmt_ll_tx_start(rmt_dev_t *dev, uint32_t channel)
*/
static inline void rmt_ll_tx_stop(rmt_dev_t *dev, uint32_t channel)
{
dev->chnconf0[channel].tx_stop_n = 1;
dev->chnconf0[channel].tx_stop_chn = 1;
// stop won't take place until configurations updated
dev->chnconf0[channel].conf_update_n = 1;
dev->chnconf0[channel].conf_update_chn = 1;
}
/**
@ -204,7 +204,7 @@ static inline void rmt_ll_tx_stop(rmt_dev_t *dev, uint32_t channel)
*/
static inline void rmt_ll_tx_set_mem_blocks(rmt_dev_t *dev, uint32_t channel, uint8_t block_num)
{
dev->chnconf0[channel].mem_size_n = block_num;
dev->chnconf0[channel].mem_size_chn = block_num;
}
/**
@ -216,7 +216,7 @@ static inline void rmt_ll_tx_set_mem_blocks(rmt_dev_t *dev, uint32_t channel, ui
*/
static inline void rmt_ll_tx_enable_wrap(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->chnconf0[channel].mem_tx_wrap_en_n = enable;
dev->chnconf0[channel].mem_tx_wrap_en_chn = enable;
}
/**
@ -228,7 +228,7 @@ static inline void rmt_ll_tx_enable_wrap(rmt_dev_t *dev, uint32_t channel, bool
*/
static inline void rmt_ll_tx_enable_loop(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->chnconf0[channel].tx_conti_mode_n = enable;
dev->chnconf0[channel].tx_conti_mode_chn = enable;
}
/**
@ -333,8 +333,8 @@ static inline void rmt_ll_tx_sync_group_remove_channels(rmt_dev_t *dev, uint32_t
*/
static inline void rmt_ll_tx_fix_idle_level(rmt_dev_t *dev, uint32_t channel, uint8_t level, bool enable)
{
dev->chnconf0[channel].idle_out_en_n = enable;
dev->chnconf0[channel].idle_out_lv_n = level;
dev->chnconf0[channel].idle_out_en_chn = enable;
dev->chnconf0[channel].idle_out_lv_chn = level;
}
/**
@ -380,7 +380,7 @@ static inline void rmt_ll_tx_set_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t
*/
static inline void rmt_ll_tx_enable_carrier_modulation(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->chnconf0[channel].carrier_en_n = enable;
dev->chnconf0[channel].carrier_en_chn = enable;
}
/**
@ -392,7 +392,7 @@ static inline void rmt_ll_tx_enable_carrier_modulation(rmt_dev_t *dev, uint32_t
*/
static inline void rmt_ll_tx_set_carrier_level(rmt_dev_t *dev, uint32_t channel, uint8_t level)
{
dev->chnconf0[channel].carrier_out_lv_n = level;
dev->chnconf0[channel].carrier_out_lv_chn = level;
}
/**
@ -404,7 +404,7 @@ static inline void rmt_ll_tx_set_carrier_level(rmt_dev_t *dev, uint32_t channel,
*/
static inline void rmt_ll_tx_enable_carrier_always_on(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->chnconf0[channel].carrier_eff_en_n = !enable;
dev->chnconf0[channel].carrier_eff_en_chn = !enable;
}
////////////////////////////////////////RX Channel Specific/////////////////////////////////////////////////////////////
@ -434,7 +434,7 @@ static inline void rmt_ll_rx_set_channel_clock_div(rmt_dev_t *dev, uint32_t chan
if (div >= 256) {
div = 0; // 0 means 256 division
}
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->chmconf[channel].conf0, div_cnt_m, div);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->chmconf[channel].conf0, div_cnt_chm, div);
}
/**
@ -445,10 +445,10 @@ static inline void rmt_ll_rx_set_channel_clock_div(rmt_dev_t *dev, uint32_t chan
*/
static inline void rmt_ll_rx_reset_pointer(rmt_dev_t *dev, uint32_t channel)
{
dev->chmconf[channel].conf1.mem_wr_rst_m = 1;
dev->chmconf[channel].conf1.mem_wr_rst_m = 0;
dev->chmconf[channel].conf1.apb_mem_rst_m = 1;
dev->chmconf[channel].conf1.apb_mem_rst_m = 0;
dev->chmconf[channel].conf1.mem_wr_rst_chm = 1;
dev->chmconf[channel].conf1.mem_wr_rst_chm = 0;
dev->chmconf[channel].conf1.apb_mem_rst_chm = 1;
dev->chmconf[channel].conf1.apb_mem_rst_chm = 0;
}
/**
@ -461,7 +461,7 @@ static inline void rmt_ll_rx_reset_pointer(rmt_dev_t *dev, uint32_t channel)
static inline void rmt_ll_rx_enable_dma(rmt_dev_t *dev, uint32_t channel, bool enable)
{
HAL_ASSERT(channel == 3 && "only RX channel 3 has DMA ability");
dev->chmconf[channel].conf0.dma_access_en_m = enable;
dev->chmconf[channel].conf0.dma_access_en_chm = enable;
}
/**
@ -473,9 +473,9 @@ static inline void rmt_ll_rx_enable_dma(rmt_dev_t *dev, uint32_t channel, bool e
*/
static inline void rmt_ll_rx_enable(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->chmconf[channel].conf1.rx_en_m = enable;
dev->chmconf[channel].conf1.rx_en_chm = enable;
// rx won't be enabled until configurations updated
dev->chmconf[channel].conf1.conf_update_m = 1;
dev->chmconf[channel].conf1.conf_update_chm = 1;
}
/**
@ -487,7 +487,7 @@ static inline void rmt_ll_rx_enable(rmt_dev_t *dev, uint32_t channel, bool enabl
*/
static inline void rmt_ll_rx_set_mem_blocks(rmt_dev_t *dev, uint32_t channel, uint8_t block_num)
{
dev->chmconf[channel].conf0.mem_size_m = block_num;
dev->chmconf[channel].conf0.mem_size_chm = block_num;
}
/**
@ -499,7 +499,7 @@ static inline void rmt_ll_rx_set_mem_blocks(rmt_dev_t *dev, uint32_t channel, ui
*/
static inline void rmt_ll_rx_set_idle_thres(rmt_dev_t *dev, uint32_t channel, uint32_t thres)
{
dev->chmconf[channel].conf0.idle_thres_m = thres;
dev->chmconf[channel].conf0.idle_thres_chm = thres;
}
/**
@ -511,7 +511,7 @@ static inline void rmt_ll_rx_set_idle_thres(rmt_dev_t *dev, uint32_t channel, ui
*/
static inline void rmt_ll_rx_set_mem_owner(rmt_dev_t *dev, uint32_t channel, rmt_ll_mem_owner_t owner)
{
dev->chmconf[channel].conf1.mem_owner_m = owner;
dev->chmconf[channel].conf1.mem_owner_chm = owner;
}
/**
@ -523,7 +523,7 @@ static inline void rmt_ll_rx_set_mem_owner(rmt_dev_t *dev, uint32_t channel, rmt
*/
static inline void rmt_ll_rx_enable_filter(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->chmconf[channel].conf1.rx_filter_en_m = enable;
dev->chmconf[channel].conf1.rx_filter_en_chm = enable;
}
/**
@ -535,7 +535,7 @@ static inline void rmt_ll_rx_enable_filter(rmt_dev_t *dev, uint32_t channel, boo
*/
static inline void rmt_ll_rx_set_filter_thres(rmt_dev_t *dev, uint32_t channel, uint32_t thres)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->chmconf[channel].conf1, rx_filter_thres_m, thres);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->chmconf[channel].conf1, rx_filter_thres_chm, thres);
}
/**
@ -547,7 +547,7 @@ static inline void rmt_ll_rx_set_filter_thres(rmt_dev_t *dev, uint32_t channel,
*/
static inline uint32_t rmt_ll_rx_get_memory_writer_offset(rmt_dev_t *dev, uint32_t channel)
{
return dev->chmstatus[channel].mem_waddr_ex_m - (channel + 4) * 48;
return dev->chmstatus[channel].mem_waddr_ex_chm - (channel + 4) * 48;
}
/**
@ -559,7 +559,7 @@ static inline uint32_t rmt_ll_rx_get_memory_writer_offset(rmt_dev_t *dev, uint32
*/
static inline void rmt_ll_rx_set_limit(rmt_dev_t *dev, uint32_t channel, uint32_t limit)
{
dev->chm_rx_lim[channel].chm_rx_lim_reg = limit;
dev->chm_rx_lim[channel].rx_lim_chm = limit;
}
/**
@ -586,7 +586,7 @@ static inline void rmt_ll_rx_set_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t
*/
static inline void rmt_ll_rx_enable_carrier_demodulation(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->chmconf[channel].conf0.carrier_en_m = enable;
dev->chmconf[channel].conf0.carrier_en_chm = enable;
}
/**
@ -598,7 +598,7 @@ static inline void rmt_ll_rx_enable_carrier_demodulation(rmt_dev_t *dev, uint32_
*/
static inline void rmt_ll_rx_set_carrier_level(rmt_dev_t *dev, uint32_t channel, uint8_t level)
{
dev->chmconf[channel].conf0.carrier_out_lv_m = level;
dev->chmconf[channel].conf0.carrier_out_lv_chm = level;
}
/**
@ -610,7 +610,7 @@ static inline void rmt_ll_rx_set_carrier_level(rmt_dev_t *dev, uint32_t channel,
*/
static inline void rmt_ll_rx_enable_wrap(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->chmconf[channel].conf1.mem_rx_wrap_en_m = enable;
dev->chmconf[channel].conf1.mem_rx_wrap_en_chm = enable;
}
//////////////////////////////////////////Interrupt Specific////////////////////////////////////////////////////////////
@ -718,34 +718,34 @@ static inline uint32_t rmt_ll_rx_get_status_word(rmt_dev_t *dev, uint32_t channe
static inline uint32_t rmt_ll_tx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel)
{
uint32_t div = HAL_FORCE_READ_U32_REG_FIELD(dev->chnconf0[channel], div_cnt_n);
uint32_t div = HAL_FORCE_READ_U32_REG_FIELD(dev->chnconf0[channel], div_cnt_chn);
return div == 0 ? 256 : div;
}
static inline uint32_t rmt_ll_rx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel)
{
uint32_t div = HAL_FORCE_READ_U32_REG_FIELD(dev->chmconf[channel].conf0, div_cnt_m);
uint32_t div = HAL_FORCE_READ_U32_REG_FIELD(dev->chmconf[channel].conf0, div_cnt_chm);
return div == 0 ? 256 : div;
}
static inline uint32_t rmt_ll_rx_get_idle_thres(rmt_dev_t *dev, uint32_t channel)
{
return dev->chmconf[channel].conf0.idle_thres_m;
return dev->chmconf[channel].conf0.idle_thres_chm;
}
static inline uint32_t rmt_ll_tx_get_mem_blocks(rmt_dev_t *dev, uint32_t channel)
{
return dev->chnconf0[channel].mem_size_n;
return dev->chnconf0[channel].mem_size_chn;
}
static inline uint32_t rmt_ll_rx_get_mem_blocks(rmt_dev_t *dev, uint32_t channel)
{
return dev->chmconf[channel].conf0.mem_size_m;
return dev->chmconf[channel].conf0.mem_size_chm;
}
static inline bool rmt_ll_tx_is_loop_enabled(rmt_dev_t *dev, uint32_t channel)
{
return dev->chnconf0[channel].tx_conti_mode_n;
return dev->chnconf0[channel].tx_conti_mode_chn;
}
static inline rmt_clock_source_t rmt_ll_get_group_clock_src(rmt_dev_t *dev, uint32_t channel)
@ -767,12 +767,12 @@ static inline rmt_clock_source_t rmt_ll_get_group_clock_src(rmt_dev_t *dev, uint
static inline bool rmt_ll_tx_is_idle_enabled(rmt_dev_t *dev, uint32_t channel)
{
return dev->chnconf0[channel].idle_out_en_n;
return dev->chnconf0[channel].idle_out_en_chn;
}
static inline uint32_t rmt_ll_tx_get_idle_level(rmt_dev_t *dev, uint32_t channel)
{
return dev->chnconf0[channel].idle_out_lv_n;
return dev->chnconf0[channel].idle_out_lv_chn;
}
static inline bool rmt_ll_is_mem_powered_down(rmt_dev_t *dev)
@ -785,12 +785,12 @@ static inline bool rmt_ll_is_mem_powered_down(rmt_dev_t *dev)
static inline uint32_t rmt_ll_rx_get_mem_owner(rmt_dev_t *dev, uint32_t channel)
{
return dev->chmconf[channel].conf1.mem_owner_m;
return dev->chmconf[channel].conf1.mem_owner_chm;
}
static inline uint32_t rmt_ll_rx_get_limit(rmt_dev_t *dev, uint32_t channel)
{
return dev->chm_rx_lim[channel].chm_rx_lim_reg;
return dev->chm_rx_lim[channel].rx_lim_chm;
}
static inline uint32_t rmt_ll_get_tx_end_interrupt_status(rmt_dev_t *dev)

1170
components/soc/esp32s2/include/soc/rmt_reg.h
Wyświetl plik

Plik diff jest za duży Load Diff

172
components/soc/esp32s2/include/soc/rmt_struct.h
Wyświetl plik

@ -1,7 +1,7 @@
/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
@ -31,40 +31,40 @@ typedef union {
*/
typedef union {
struct {
/** div_cnt : R/W; bitpos: [7:0]; default: 2;
/** div_cnt_chn : R/W; bitpos: [7:0]; default: 2;
* This field is used to configure clock divider for channel n.
*/
uint32_t div_cnt: 8;
/** idle_thres : R/W; bitpos: [23:8]; default: 4096;
uint32_t div_cnt_chn: 8;
/** idle_thres_chn : R/W; bitpos: [23:8]; default: 4096;
* Receiving ends when no edge is detected on input signals for continuous clock
* cycles longer than this field value.
*/
uint32_t idle_thres: 16;
/** mem_size : R/W; bitpos: [26:24]; default: 1;
uint32_t idle_thres_chn: 16;
/** mem_size_chn : R/W; bitpos: [26:24]; default: 1;
* This field is used to configure the maximum blocks allocated to channel n. The
* valid range is from 1 ~ 4-n.
*/
uint32_t mem_size: 3;
/** carrier_eff_en : R/W; bitpos: [27]; default: 1;
uint32_t mem_size_chn: 3;
/** carrier_eff_en_chn : R/W; bitpos: [27]; default: 1;
* 1: Add carrier modulation on output signals only at data sending state for channel
* n. 0: Add carrier modulation on signals at all states for channel n. States here
* include idle state (ST_IDLE), reading data from RAM (ST_RD_MEM), and sending data
* stored in RAM (ST_SEND). Only valid when RMT_CARRIER_EN_CHn is set to 1.
*/
uint32_t carrier_eff_en: 1;
/** carrier_en : R/W; bitpos: [28]; default: 1;
uint32_t carrier_eff_en_chn: 1;
/** carrier_en_chn : R/W; bitpos: [28]; default: 1;
* This bit is used to enable carrier modulation for channel n. 1: Add carrier
* modulation on output signals. 0: No carrier modulation is added on output signals.
*/
uint32_t carrier_en: 1;
/** carrier_out_lv : R/W; bitpos: [29]; default: 1;
uint32_t carrier_en_chn: 1;
/** carrier_out_lv_chn : R/W; bitpos: [29]; default: 1;
* This bit is used to configure the position of carrier wave for channel n.
*
* 1'h0: Add carrier wave on low-level output signals.
*
* 1'h1: Add carrier wave on high-level output signals.
*/
uint32_t carrier_out_lv: 1;
uint32_t carrier_out_lv_chn: 1;
uint32_t reserved_30: 2;
};
uint32_t val;
@ -75,72 +75,72 @@ typedef union {
*/
typedef union {
struct {
/** tx_start : R/W; bitpos: [0]; default: 0;
/** tx_start_chn : R/W; bitpos: [0]; default: 0;
* Set this bit to start sending data on channel n.
*/
uint32_t tx_start: 1;
/** rx_en : R/W; bitpos: [1]; default: 0;
uint32_t tx_start_chn: 1;
/** rx_en_chn : R/W; bitpos: [1]; default: 0;
* Set this bit to enable receiver to receive data on channel n.
*/
uint32_t rx_en: 1;
/** mem_wr_rst : WO; bitpos: [2]; default: 0;
uint32_t rx_en_chn: 1;
/** mem_wr_rst_chn : WO; bitpos: [2]; default: 0;
* Set this bit to reset RAM write address accessed by the receiver for channel n.
*/
uint32_t mem_wr_rst: 1;
/** mem_rd_rst : WO; bitpos: [3]; default: 0;
uint32_t mem_wr_rst_chn: 1;
/** mem_rd_rst_chn : WO; bitpos: [3]; default: 0;
* Set this bit to reset RAM read address accessed by the transmitter for channel n.
*/
uint32_t mem_rd_rst: 1;
/** apb_mem_rst : WO; bitpos: [4]; default: 0;
uint32_t mem_rd_rst_chn: 1;
/** apb_mem_rst_chn : WO; bitpos: [4]; default: 0;
* Set this bit to reset W/R ram address for channel n by accessing apb fifo.
*/
uint32_t apb_mem_rst: 1;
/** mem_owner : R/W; bitpos: [5]; default: 1;
uint32_t apb_mem_rst_chn: 1;
/** mem_owner_chn : R/W; bitpos: [5]; default: 1;
* This bit marks the ownership of channel n's RAM block.
*
* 1'h1: Receiver is using the RAM.
*
* 1'h0: Transmitter is using the RAM.
*/
uint32_t mem_owner: 1;
/** tx_conti_mode : R/W; bitpos: [6]; default: 0;
uint32_t mem_owner_chn: 1;
/** tx_conti_mode_chn : R/W; bitpos: [6]; default: 0;
* Set this bit to restart transmission in continuous node from the first data in
* channel n.
*/
uint32_t tx_conti_mode: 1;
/** rx_filter_en : R/W; bitpos: [7]; default: 0;
uint32_t tx_conti_mode_chn: 1;
/** rx_filter_en_chn : R/W; bitpos: [7]; default: 0;
* Set this bit to enable the receiver's filter for channel n.
*/
uint32_t rx_filter_en: 1;
/** rx_filter_thres : R/W; bitpos: [15:8]; default: 15;
uint32_t rx_filter_en_chn: 1;
/** rx_filter_thres_chn : R/W; bitpos: [15:8]; default: 15;
* Set this field to ignore the input pulse when its width is less than
* RMT_RX_FILTER_THRES_CHn APB clock cycles in receive mode.
*/
uint32_t rx_filter_thres: 8;
/** chk_rx_carrier_en : R/W; bitpos: [16]; default: 0;
uint32_t rx_filter_thres_chn: 8;
/** chk_rx_carrier_en_chn : R/W; bitpos: [16]; default: 0;
* Set this bit to enable memory loop read mode when carrier modulation is enabled for
* channel n.
*/
uint32_t chk_rx_carrier_en: 1;
/** ref_always_on : R/W; bitpos: [17]; default: 0;
uint32_t chk_rx_carrier_en_chn: 1;
/** ref_always_on_chn : R/W; bitpos: [17]; default: 0;
* Set this bit to select a base clock for channel n.
*
* 1'h1: APB_CLK 1'h0: REF_TICK
*/
uint32_t ref_always_on: 1;
/** idle_out_lv : R/W; bitpos: [18]; default: 0;
uint32_t ref_always_on_chn: 1;
/** idle_out_lv_chn : R/W; bitpos: [18]; default: 0;
* This bit configures the level of output signals in channel n when the transmitter
* is in idle state.
*/
uint32_t idle_out_lv: 1;
/** idle_out_en : R/W; bitpos: [19]; default: 0;
uint32_t idle_out_lv_chn: 1;
/** idle_out_en_chn : R/W; bitpos: [19]; default: 0;
* This is the output enable bit for channel n in idle state.
*/
uint32_t idle_out_en: 1;
/** tx_stop : R/W; bitpos: [20]; default: 0;
uint32_t idle_out_en_chn: 1;
/** tx_stop_chn : R/W; bitpos: [20]; default: 0;
* Set this bit to stop the transmitter of channel n sending data out.
*/
uint32_t tx_stop: 1;
uint32_t tx_stop_chn: 1;
uint32_t reserved_21: 11;
};
uint32_t val;
@ -214,16 +214,16 @@ typedef union {
*/
typedef union {
struct {
/** carrier_low_thres_ch : R/W; bitpos: [15:0]; default: 0;
/** carrier_low_thres_chn : R/W; bitpos: [15:0]; default: 0;
* The low level period in carrier modulation mode is (RMT_CARRIER_LOW_THRES_CHn + 1)
* clock cycles for channel n.
*/
uint32_t carrier_low_thres_ch: 16;
/** carrier_high_thres_ch : R/W; bitpos: [31:16]; default: 0;
uint32_t carrier_low_thres_chn: 16;
/** carrier_high_thres_chn : R/W; bitpos: [31:16]; default: 0;
* The high level period in carrier modulation mode is (RMT_CARRIER_HIGH_THRES_CHn +
* 1) clock cycles for channel n.
*/
uint32_t carrier_high_thres_ch: 16;
uint32_t carrier_high_thres_chn: 16;
};
uint32_t val;
} rmt_chn_rx_carrier_rm_reg_t;
@ -235,46 +235,46 @@ typedef union {
*/
typedef union {
struct {
/** mem_waddr_ex : RO; bitpos: [8:0]; default: 0;
/** mem_waddr_ex_chn : RO; bitpos: [8:0]; default: 0;
* This field records the memory address offset when receiver of channel n is using
* the RAM.
*/
uint32_t mem_waddr_ex: 9;
uint32_t mem_waddr_ex_chn: 9;
uint32_t reserved_9: 1;
/** mem_raddr_ex : RO; bitpos: [18:10]; default: 0;
/** mem_raddr_ex_chn : RO; bitpos: [18:10]; default: 0;
* This field records the memory address offset when transmitter of channel n is using
* the RAM.
*/
uint32_t mem_raddr_ex: 9;
uint32_t mem_raddr_ex_chn: 9;
uint32_t reserved_19: 1;
/** state : RO; bitpos: [22:20]; default: 0;
/** state_chn : RO; bitpos: [22:20]; default: 0;
* This field records the FSM status of channel n.
*/
uint32_t state: 3;
/** mem_owner_err : RO; bitpos: [23]; default: 0;
uint32_t state_chn: 3;
/** mem_owner_err_chn : RO; bitpos: [23]; default: 0;
* This status bit will be set when the ownership of memory block is violated.
*/
uint32_t mem_owner_err: 1;
/** mem_full : RO; bitpos: [24]; default: 0;
uint32_t mem_owner_err_chn: 1;
/** mem_full_chn : RO; bitpos: [24]; default: 0;
* This status bit will be set if the receiver receives more data than the memory
* allows.
*/
uint32_t mem_full: 1;
/** mem_empty : RO; bitpos: [25]; default: 0;
uint32_t mem_full_chn: 1;
/** mem_empty_chn : RO; bitpos: [25]; default: 0;
* This status bit will be set when the data to be sent is more than memory allows and
* the wrap mode is disabled.
*/
uint32_t mem_empty: 1;
/** apb_mem_wr_err : RO; bitpos: [26]; default: 0;
uint32_t mem_empty_chn: 1;
/** apb_mem_wr_err_chn : RO; bitpos: [26]; default: 0;
* This status bit will be set if the offset address out of memory size when writes
* RAM via APB bus.
*/
uint32_t apb_mem_wr_err: 1;
/** apb_mem_rd_err : RO; bitpos: [27]; default: 0;
uint32_t apb_mem_wr_err_chn: 1;
/** apb_mem_rd_err_chn : RO; bitpos: [27]; default: 0;
* This status bit will be set if the offset address out of memory size when reads RAM
* via APB bus.
*/
uint32_t apb_mem_rd_err: 1;
uint32_t apb_mem_rd_err_chn: 1;
uint32_t reserved_28: 4;
};
uint32_t val;
@ -285,15 +285,15 @@ typedef union {
*/
typedef union {
struct {
/** apb_mem_waddr_ch0 : RO; bitpos: [8:0]; default: 0;
/** apb_mem_waddr_chn : RO; bitpos: [8:0]; default: 0;
* This field records the memory address offset when channel n writes RAM via APB bus.
*/
uint32_t apb_mem_waddr_ch0: 9;
uint32_t apb_mem_waddr_chn: 9;
uint32_t reserved_9: 1;
/** apb_mem_raddr_ch0 : RO; bitpos: [18:10]; default: 0;
/** apb_mem_raddr_chn : RO; bitpos: [18:10]; default: 0;
* This field records the memory address offset when channel n reads RAM via APB bus.
*/
uint32_t apb_mem_raddr_ch0: 9;
uint32_t apb_mem_raddr_chn: 9;
uint32_t reserved_19: 13;
};
uint32_t val;
@ -676,16 +676,16 @@ typedef union {
*/
typedef union {
struct {
/** low : R/W; bitpos: [15:0]; default: 64;
/** carrier_low_chn : R/W; bitpos: [15:0]; default: 64;
* This field is used to configure the clock cycles of carrier wave at low level for
* channel n.
*/
uint32_t low: 16;
/** high : R/W; bitpos: [31:16]; default: 64;
uint32_t carrier_low_chn: 16;
/** carrier_high_chn : R/W; bitpos: [31:16]; default: 64;
* This field is used to configure the clock cycles of carrier wave at high level for
* channel n.
*/
uint32_t high: 16;
uint32_t carrier_high_chn: 16;
};
uint32_t val;
} rmt_chncarrier_duty_reg_t;
@ -697,26 +697,26 @@ typedef union {
*/
typedef union {
struct {
/** tx_lim : R/W; bitpos: [8:0]; default: 128;
/** tx_lim_chn : R/W; bitpos: [8:0]; default: 128;
* This field is used to configure the maximum entries that channel n can send out.
* When RMT_MEM_SIZE_CHn = 1, this field can be set to any value among 0 ~ 128
* (64*32/16 = 128). When RMT_MEM_SIZE_CHn > 1, this field can be set to any value
* among (0 ~ 128)*RMT_MEM_SIZE_CHn.
*/
uint32_t tx_lim: 9;
/** tx_loop_num : R/W; bitpos: [18:9]; default: 0;
uint32_t tx_lim_chn: 9;
/** tx_loop_num_chn : R/W; bitpos: [18:9]; default: 0;
* This field is used to configure the maximum loop times when continuous transmission
* mode is enabled.
*/
uint32_t tx_loop_num: 10;
/** tx_loop_cnt_en : R/W; bitpos: [19]; default: 0;
uint32_t tx_loop_num_chn: 10;
/** tx_loop_cnt_en_chn : R/W; bitpos: [19]; default: 0;
* This bit is used to enable loop counting.
*/
uint32_t tx_loop_cnt_en: 1;
/** loop_count_reset : WO; bitpos: [20]; default: 0;
uint32_t tx_loop_cnt_en_chn: 1;
/** loop_count_reset_chn : WO; bitpos: [20]; default: 0;
* This bit is used to reset loop counting when continuous transmission mode is valid.
*/
uint32_t loop_count_reset: 1;
uint32_t loop_count_reset_chn: 1;
uint32_t reserved_21: 11;
};
uint32_t val;
@ -750,7 +750,7 @@ typedef union {
/** tx_sim_en : R/W; bitpos: [4]; default: 0;
* This bit is used to enable multiple channels to start sending data simultaneously.
*/
uint32_t en: 1;
uint32_t tx_sim_en: 1;
uint32_t reserved_5: 27;
};
uint32_t val;
@ -773,23 +773,23 @@ typedef union {
typedef struct rmt_dev_t {
volatile rmt_chndata_reg_t data_ch[4];
volatile rmt_chndata_reg_t chndata[4];
volatile struct {
volatile rmt_chnconf0_reg_t conf0;
volatile rmt_chnconf1_reg_t conf1;
rmt_chnconf0_reg_t conf0;
rmt_chnconf1_reg_t conf1;
} conf_ch[4];
volatile rmt_chnstatus_reg_t status_ch[4];
volatile rmt_chnaddr_reg_t apb_mem_addr_ch[4];
volatile rmt_chnstatus_reg_t chnstatus[4];
volatile rmt_chnaddr_reg_t chnaddr[4];
volatile rmt_int_raw_reg_t int_raw;
volatile rmt_int_st_reg_t int_st;
volatile rmt_int_ena_reg_t int_ena;
volatile rmt_int_clr_reg_t int_clr;
volatile rmt_chncarrier_duty_reg_t carrier_duty_ch[4];
volatile rmt_chn_tx_lim_reg_t tx_lim_ch[4];
volatile rmt_chncarrier_duty_reg_t chncarrier_duty[4];
volatile rmt_chn_tx_lim_reg_t chn_tx_lim[4];
volatile rmt_apb_conf_reg_t apb_conf;
volatile rmt_tx_sim_reg_t tx_sim;
volatile rmt_ref_cnt_rst_reg_t ref_cnt_rst;
volatile rmt_chn_rx_carrier_rm_reg_t ch_rx_carrier_rm[4];
volatile rmt_chn_rx_carrier_rm_reg_t chn_rx_carrier_rm[4];
uint32_t reserved_09c[24];
volatile rmt_date_reg_t date;
} rmt_dev_t;

1640
components/soc/esp32s3/include/soc/rmt_reg.h
Wyświetl plik

Plik diff jest za duży Load Diff

301
components/soc/esp32s3/include/soc/rmt_struct.h
Wyświetl plik

@ -44,178 +44,176 @@ typedef union {
*/
typedef union {
struct {
/** tx_start_n : WT; bitpos: [0]; default: 0;
/** tx_start_chn : WT; bitpos: [0]; default: 0;
* Set this bit to start sending data on CHANNELn.
*/
uint32_t tx_start_n: 1;
/** mem_rd_rst_n : WT; bitpos: [1]; default: 0;
uint32_t tx_start_chn: 1;
/** mem_rd_rst_chn : WT; bitpos: [1]; default: 0;
* Set this bit to reset read ram address for CHANNELn by accessing transmitter.
*/
uint32_t mem_rd_rst_n: 1;
/** apb_mem_rst_n : WT; bitpos: [2]; default: 0;
uint32_t mem_rd_rst_chn: 1;
/** apb_mem_rst_chn : WT; bitpos: [2]; default: 0;
* Set this bit to reset W/R ram address for CHANNELn by accessing apb fifo.
*/
uint32_t apb_mem_rst_n: 1;
/** tx_conti_mode_n : R/W; bitpos: [3]; default: 0;
uint32_t apb_mem_rst_chn: 1;
/** tx_conti_mode_chn : R/W; bitpos: [3]; default: 0;
* Set this bit to restart transmission from the first data to the last data in
* CHANNELn.
*/
uint32_t tx_conti_mode_n: 1;
/** mem_tx_wrap_en_n : R/W; bitpos: [4]; default: 0;
uint32_t tx_conti_mode_chn: 1;
/** mem_tx_wrap_en_chn : R/W; bitpos: [4]; default: 0;
* This is the channel n enable bit for wraparound mode: it will resume sending at the
* start when the data to be sent is more than its memory size.
*/
uint32_t mem_tx_wrap_en_n: 1;
/** idle_out_lv_n : R/W; bitpos: [5]; default: 0;
uint32_t mem_tx_wrap_en_chn: 1;
/** idle_out_lv_chn : R/W; bitpos: [5]; default: 0;
* This bit configures the level of output signal in CHANNELn when the latter is in
* IDLE state.
*/
uint32_t idle_out_lv_n: 1;
/** idle_out_en_n : R/W; bitpos: [6]; default: 0;
uint32_t idle_out_lv_chn: 1;
/** idle_out_en_chn : R/W; bitpos: [6]; default: 0;
* This is the output enable-control bit for CHANNELn in IDLE state.
*/
uint32_t idle_out_en_n: 1;
/** tx_stop_n : R/W/SC; bitpos: [7]; default: 0;
uint32_t idle_out_en_chn: 1;
/** tx_stop_chn : R/W/SC; bitpos: [7]; default: 0;
* Set this bit to stop the transmitter of CHANNELn sending data out.
*/
uint32_t tx_stop_n: 1;
/** div_cnt_n : R/W; bitpos: [15:8]; default: 2;
uint32_t tx_stop_chn: 1;
/** div_cnt_chn : R/W; bitpos: [15:8]; default: 2;
* This register is used to configure the divider for clock of CHANNELn.
*/
uint32_t div_cnt_n: 8;
/** mem_size_n : R/W; bitpos: [19:16]; default: 1;
uint32_t div_cnt_chn: 8;
/** mem_size_chn : R/W; bitpos: [19:16]; default: 1;
* This register is used to configure the maximum size of memory allocated to CHANNELn.
*/
uint32_t mem_size_n: 4;
/** carrier_eff_en_n : R/W; bitpos: [20]; default: 1;
uint32_t mem_size_chn: 4;
/** carrier_eff_en_chn : R/W; bitpos: [20]; default: 1;
* 1: Add carrier modulation on the output signal only at the send data state for
* CHANNELn. 0: Add carrier modulation on the output signal at all state for CHANNELn.
* Only valid when RMT_CARRIER_EN_CHn is 1.
*/
uint32_t carrier_eff_en_n: 1;
/** carrier_en_n : R/W; bitpos: [21]; default: 1;
uint32_t carrier_eff_en_chn: 1;
/** carrier_en_chn : R/W; bitpos: [21]; default: 1;
* This is the carrier modulation enable-control bit for CHANNELn. 1: Add carrier
* modulation in the output signal. 0: No carrier modulation in sig_out.
*/
uint32_t carrier_en_n: 1;
/** carrier_out_lv_n : R/W; bitpos: [22]; default: 1;
uint32_t carrier_en_chn: 1;
/** carrier_out_lv_chn : R/W; bitpos: [22]; default: 1;
* This bit is used to configure the position of carrier wave for CHANNELn.
*
* 1'h0: add carrier wave on low level.
*
* 1'h1: add carrier wave on high level.
*/
uint32_t carrier_out_lv_n: 1;
/** afifo_rst_n : WT; bitpos: [23]; default: 0;
uint32_t carrier_out_lv_chn: 1;
/** afifo_rst_chn : WT; bitpos: [23]; default: 0;
* Reserved
*/
uint32_t afifo_rst_n: 1;
/** conf_update_n : WT; bitpos: [24]; default: 0;
uint32_t afifo_rst_chn: 1;
/** conf_update_chn : WT; bitpos: [24]; default: 0;
* synchronization bit for CHANNELn
*/
uint32_t conf_update_n: 1;
/** dma_access_en_n : WT; bitpos: [25]; default: 0;
* DMA access control bit for CHANNELn
uint32_t conf_update_chn: 1;
/** dma_access_en_chn : WT; bitpos: [25]; default: 0;
* DMA access control bit for CHANNELn (only CHANNEL3 has this control bit)
*/
uint32_t dma_access_en_n: 1;
uint32_t dma_access_en_chn: 1;
uint32_t reserved_26: 6;
};
uint32_t val;
} rmt_chnconf0_reg_t;
typedef struct {
/** Type of chmconf0 register
* Channel m configure register 0
*/
union {
struct {
/** div_cnt_m : R/W; bitpos: [7:0]; default: 2;
* This register is used to configure the divider for clock of CHANNELm.
*/
uint32_t div_cnt_m: 8;
/** idle_thres_m : R/W; bitpos: [22:8]; default: 32767;
* When no edge is detected on the input signal and continuous clock cycles is longer
* than this register value, received process is finished.
*/
uint32_t idle_thres_m: 15;
/** dma_access_en_m : WT; bitpos: [23]; default: 0;
* DMA access control bit for CHANNELm
*/
uint32_t dma_access_en_m: 1;
/** mem_size_m : R/W; bitpos: [27:24]; default: 1;
* This register is used to configure the maximum size of memory allocated to CHANNELm.
*/
uint32_t mem_size_m: 4;
/** carrier_en_m : R/W; bitpos: [28]; default: 1;
* This is the carrier modulation enable-control bit for CHANNELm. 1: Add carrier
* modulation in the output signal. 0: No carrier modulation in sig_out.
*/
uint32_t carrier_en_m: 1;
/** carrier_out_lv_m : R/W; bitpos: [29]; default: 1;
* This bit is used to configure the position of carrier wave for CHANNELm.
*
* 1'h0: add carrier wave on low level.
*
* 1'h1: add carrier wave on high level.
*/
uint32_t carrier_out_lv_m: 1;
uint32_t reserved_30: 2;
};
uint32_t val;
} conf0;
/** Type of chmconf0 register
* Channel m configure register 0
*/
typedef union {
struct {
/** div_cnt_chm : R/W; bitpos: [7:0]; default: 2;
* This register is used to configure the divider for clock of CHANNELm.
*/
uint32_t div_cnt_chm: 8;
/** idle_thres_chm : R/W; bitpos: [22:8]; default: 32767;
* When no edge is detected on the input signal and continuous clock cycles is longer
* than this register value, received process is finished.
*/
uint32_t idle_thres_chm: 15;
/** dma_access_en_m : WT; bitpos: [23]; default: 0;
* DMA access control bit for CHANNELm (only channel7 has this control bit)
*/
uint32_t dma_access_en_chm: 1;
/** mem_size_chm : R/W; bitpos: [27:24]; default: 1;
* This register is used to configure the maximum size of memory allocated to CHANNELm.
*/
uint32_t mem_size_chm: 4;
/** carrier_en_chm : R/W; bitpos: [28]; default: 1;
* This is the carrier modulation enable-control bit for CHANNELm. 1: Add carrier
* modulation in the output signal. 0: No carrier modulation in sig_out.
*/
uint32_t carrier_en_chm: 1;
/** carrier_out_lv_chm : R/W; bitpos: [29]; default: 1;
* This bit is used to configure the position of carrier wave for CHANNELm.
*
* 1'h0: add carrier wave on low level.
*
* 1'h1: add carrier wave on high level.
*/
uint32_t carrier_out_lv_chm: 1;
uint32_t reserved_30: 2;
};
uint32_t val;
} rmt_chmconf0_reg_t;
/** Type of chmconf1 register
* Channel m configure register 1
*/
union {
struct {
/** rx_en_m : R/W; bitpos: [0]; default: 0;
* Set this bit to enable receiver to receive data on CHANNELm.
*/
uint32_t rx_en_m: 1;
/** mem_wr_rst_m : WT; bitpos: [1]; default: 0;
* Set this bit to reset write ram address for CHANNELm by accessing receiver.
*/
uint32_t mem_wr_rst_m: 1;
/** apb_mem_rst_m : WT; bitpos: [2]; default: 0;
* Set this bit to reset W/R ram address for CHANNELm by accessing apb fifo.
*/
uint32_t apb_mem_rst_m: 1;
/** mem_owner_m : R/W/SC; bitpos: [3]; default: 1;
* This register marks the ownership of CHANNELm's ram block.
*
* 1'h1: Receiver is using the ram.
*
* 1'h0: APB bus is using the ram.
*/
uint32_t mem_owner_m: 1;
/** rx_filter_en_m : R/W; bitpos: [4]; default: 0;
* This is the receive filter's enable bit for CHANNELm.
*/
uint32_t rx_filter_en_m: 1;
/** rx_filter_thres_m : R/W; bitpos: [12:5]; default: 15;
* Ignores the input pulse when its width is smaller than this register value in APB
* clock periods (in receive mode).
*/
uint32_t rx_filter_thres_m: 8;
/** mem_rx_wrap_en_m : R/W; bitpos: [13]; default: 0;
* This is the channel m enable bit for wraparound mode: it will resume receiving at
* the start when the data to be received is more than its memory size.
*/
uint32_t mem_rx_wrap_en_m: 1;
/** afifo_rst_m : WT; bitpos: [14]; default: 0;
* Reserved
*/
uint32_t afifo_rst_m: 1;
/** conf_update_m : WT; bitpos: [15]; default: 0;
* synchronization bit for CHANNELm
*/
uint32_t conf_update_m: 1;
uint32_t reserved_16: 16;
};
uint32_t val;
} conf1;
} rmt_chmconf_reg_t;
/** Type of chmconf1 register
* Channel m configure register 1
*/
typedef union {
struct {
/** rx_en_chm : R/W; bitpos: [0]; default: 0;
* Set this bit to enable receiver to receive data on CHANNELm.
*/
uint32_t rx_en_chm: 1;
/** mem_wr_rst_chm : WT; bitpos: [1]; default: 0;
* Set this bit to reset write ram address for CHANNELm by accessing receiver.
*/
uint32_t mem_wr_rst_chm: 1;
/** apb_mem_rst_chm : WT; bitpos: [2]; default: 0;
* Set this bit to reset W/R ram address for CHANNELm by accessing apb fifo.
*/
uint32_t apb_mem_rst_chm: 1;
/** mem_owner_chm : R/W/SC; bitpos: [3]; default: 1;
* This register marks the ownership of CHANNELm's ram block.
*
* 1'h1: Receiver is using the ram.
*
* 1'h0: APB bus is using the ram.
*/
uint32_t mem_owner_chm: 1;
/** rx_filter_en_chm : R/W; bitpos: [4]; default: 0;
* This is the receive filter's enable bit for CHANNELm.
*/
uint32_t rx_filter_en_chm: 1;
/** rx_filter_thres_chm : R/W; bitpos: [12:5]; default: 15;
* Ignores the input pulse when its width is smaller than this register value in APB
* clock periods (in receive mode).
*/
uint32_t rx_filter_thres_chm: 8;
/** mem_rx_wrap_en_chm : R/W; bitpos: [13]; default: 0;
* This is the channel m enable bit for wraparound mode: it will resume receiving at
* the start when the data to be received is more than its memory size.
*/
uint32_t mem_rx_wrap_en_chm: 1;
/** afifo_rst_chm : WT; bitpos: [14]; default: 0;
* Reserved
*/
uint32_t afifo_rst_chm: 1;
/** conf_update_chm : WT; bitpos: [15]; default: 0;
* synchronization bit for CHANNELm
*/
uint32_t conf_update_chm: 1;
uint32_t reserved_16: 16;
};
uint32_t val;
} rmt_chmconf1_reg_t;
/** Type of chm_rx_carrier_rm register
* Channel m carrier remove register
@ -337,31 +335,31 @@ typedef union {
*/
typedef union {
struct {
/** mem_raddr_ex_n : RO; bitpos: [9:0]; default: 0;
/** mem_raddr_ex_chn : RO; bitpos: [9:0]; default: 0;
* This register records the memory address offset when transmitter of CHANNELn is
* using the RAM.
*/
uint32_t mem_raddr_ex_n: 10;
uint32_t mem_raddr_ex_chn: 10;
uint32_t reserved_10: 1;
/** apb_mem_waddr_n : RO; bitpos: [20:11]; default: 0;
/** apb_mem_waddr_chn : RO; bitpos: [20:11]; default: 0;
* This register records the memory address offset when writes RAM over APB bus.
*/
uint32_t apb_mem_waddr_n: 10;
uint32_t apb_mem_waddr_chn: 10;
uint32_t reserved_21: 1;
/** state_n : RO; bitpos: [24:22]; default: 0;
/** state_chn : RO; bitpos: [24:22]; default: 0;
* This register records the FSM status of CHANNELn.
*/
uint32_t state_n: 3;
/** mem_empty_n : RO; bitpos: [25]; default: 0;
uint32_t state_chn: 3;
/** mem_empty_chn : RO; bitpos: [25]; default: 0;
* This status bit will be set when the data to be set is more than memory size and
* the wraparound mode is disabled.
*/
uint32_t mem_empty_n: 1;
/** apb_mem_wr_err_n : RO; bitpos: [26]; default: 0;
uint32_t mem_empty_chn: 1;
/** apb_mem_wr_err_chn : RO; bitpos: [26]; default: 0;
* This status bit will be set if the offset address out of memory size when writes
* via APB bus.
*/
uint32_t apb_mem_wr_err_n: 1;
uint32_t apb_mem_wr_err_chn: 1;
uint32_t reserved_27: 5;
};
uint32_t val;
@ -372,34 +370,34 @@ typedef union {
*/
typedef union {
struct {
/** mem_waddr_ex_m : RO; bitpos: [9:0]; default: 192;
/** mem_waddr_ex_chm : RO; bitpos: [9:0]; default: 192;
* This register records the memory address offset when receiver of CHANNELm is using
* the RAM.
*/
uint32_t mem_waddr_ex_m: 10;
uint32_t mem_waddr_ex_chm: 10;
uint32_t reserved_10: 1;
/** apb_mem_raddr_m : RO; bitpos: [20:11]; default: 192;
/** apb_mem_raddr_chm : RO; bitpos: [20:11]; default: 192;
* This register records the memory address offset when reads RAM over APB bus.
*/
uint32_t apb_mem_raddr_m: 10;
uint32_t apb_mem_raddr_chm: 10;
uint32_t reserved_21: 1;
/** state_m : RO; bitpos: [24:22]; default: 0;
/** state_chm : RO; bitpos: [24:22]; default: 0;
* This register records the FSM status of CHANNELm.
*/
uint32_t state_m: 3;
/** mem_owner_err_m : RO; bitpos: [25]; default: 0;
uint32_t state_chm: 3;
/** mem_owner_err_chm : RO; bitpos: [25]; default: 0;
* This status bit will be set when the ownership of memory block is wrong.
*/
uint32_t mem_owner_err_m: 1;
/** mem_full_m : RO; bitpos: [26]; default: 0;
uint32_t mem_owner_err_chm: 1;
/** mem_full_chm : RO; bitpos: [26]; default: 0;
* This status bit will be set if the receiver receives more data than the memory size.
*/
uint32_t mem_full_m: 1;
/** apb_mem_rd_err_m : RO; bitpos: [27]; default: 0;
uint32_t mem_full_chm: 1;
/** apb_mem_rd_err_chm : RO; bitpos: [27]; default: 0;
* This status bit will be set if the offset address out of memory size when reads via
* APB bus.
*/
uint32_t apb_mem_rd_err_m: 1;
uint32_t apb_mem_rd_err_chm: 1;
uint32_t reserved_28: 4;
};
uint32_t val;
@ -1036,10 +1034,10 @@ typedef union {
*/
typedef union {
struct {
/** chm_rx_lim_reg : R/W; bitpos: [8:0]; default: 128;
/** rx_lim_chm : R/W; bitpos: [8:0]; default: 128;
* This register is used to configure the maximum entries that CHANNELm can receive.
*/
uint32_t chm_rx_lim_reg: 9;
uint32_t rx_lim_chm: 9;
uint32_t reserved_9: 23;
};
uint32_t val;
@ -1066,7 +1064,10 @@ typedef struct rmt_dev_t {
volatile rmt_chndata_reg_t chndata[4];
volatile rmt_chmdata_reg_t chmdata[4];
volatile rmt_chnconf0_reg_t chnconf0[4];
volatile rmt_chmconf_reg_t chmconf[4];
volatile struct {
rmt_chmconf0_reg_t conf0;
rmt_chmconf1_reg_t conf1;
} chmconf[4];
volatile rmt_chnstatus_reg_t chnstatus[4];
volatile rmt_chmstatus_reg_t chmstatus[4];
volatile rmt_int_raw_reg_t int_raw;