kopia lustrzana https://github.com/espressif/esp-idf
feat(example): support esp32c5 timer/gpio/uart wakeup
Lou Tianhao
rodzic
86221b2ed7
commit
3fb4909483
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@ -152,8 +152,6 @@ if(NOT BOOTLOADER_BUILD)
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if(CONFIG_IDF_TARGET_ESP32C5)
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list(REMOVE_ITEM srcs
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"sleep_modes.c" # TODO: [ESP32C5] IDF-8638, IDF-8640
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"sleep_wake_stub.c" # TODO: [ESP32C5] IDF-8638, IDF-8640
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"sleep_gpio.c" # TODO: [ESP32C5] IDF-8638, IDF-8640
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"port/esp_clk_tree_common.c" # TODO: [ESP32C5] IDF-8638, IDF-8640
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)
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@ -15,11 +15,6 @@ if(CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP)
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endif()
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endif()
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if(CONFIG_IDF_TARGET_ESP32C5)
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list(REMOVE_ITEM srcs "cpu_retention/port/${target}/sleep_cpu.c" # TODO: [ESP32C5] IDF-8638, IDF-8640
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)
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endif()
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add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}")
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target_sources(${COMPONENT_LIB} PRIVATE "${srcs}")
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@ -2,6 +2,7 @@ set(srcs "rtc_clk_init.c"
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"rtc_clk.c"
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"rtc_time.c"
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"pmu_init.c"
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"pmu_sleep.c"
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"pmu_param.c"
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"chip_info.c"
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)
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@ -11,13 +12,6 @@ if(NOT BOOTLOADER_BUILD)
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"esp_crypto_lock.c")
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endif()
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# TODO: [ESP32C5] IDF-8667
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if(IDF_TARGET STREQUAL "esp32c5")
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list(REMOVE_ITEM srcs "pmu_init.c"
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"pmu_param.c"
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"sar_periph_ctrl.c")
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endif()
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add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}")
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target_sources(${COMPONENT_LIB} PRIVATE "${srcs}")
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@ -134,7 +134,9 @@ typedef enum {
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RTC_CAL_RC32K = SOC_RTC_SLOW_CLK_SRC_RC32K, //!< Internal 32kHz RC oscillator, as one type of 32k clock
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RTC_CAL_32K_XTAL = SOC_RTC_SLOW_CLK_SRC_XTAL32K, //!< External 32kHz XTAL, as one type of 32k clock
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RTC_CAL_32K_OSC_SLOW = SOC_RTC_SLOW_CLK_SRC_OSC_SLOW, //!< External slow clock signal input by lp_pad_gpio0, as one type of 32k clock
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// RTC_CAL_RC_FAST //!< Internal 20MHz RC oscillator
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#if CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
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RTC_CAL_RC_FAST //!< Internal 20MHz RC oscillator
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#endif
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} rtc_cal_sel_t;
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/**
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@ -0,0 +1,294 @@
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/*
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* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include <stdlib.h>
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#include <sys/param.h>
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#include <esp_types.h>
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#include "sdkconfig.h"
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#include "esp_err.h"
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#include "esp_attr.h"
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#include "soc/soc.h"
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#include "soc/rtc.h"
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#include "soc/pmu_struct.h"
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#include "hal/lp_aon_hal.h"
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#include "esp_private/esp_pmu.h"
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#include "pmu_param.h"
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#define HP(state) (PMU_MODE_HP_ ## state)
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#define LP(state) (PMU_MODE_LP_ ## state)
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static bool s_pmu_sleep_regdma_backup_enabled;
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void pmu_sleep_enable_regdma_backup(void)
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{
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if(!s_pmu_sleep_regdma_backup_enabled){
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assert(PMU_instance()->hal);
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/* entry 0, 1, 2 is used by pmu HP_SLEEP and HP_ACTIVE, HP_SLEEP
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* and HP_MODEM or HP_MODEM and HP_ACTIVE states switching,
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* respectively. entry 3 is reserved, not used yet! */
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pmu_hal_hp_set_sleep_active_backup_enable(PMU_instance()->hal);
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pmu_hal_hp_set_sleep_modem_backup_enable(PMU_instance()->hal);
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pmu_hal_hp_set_modem_active_backup_enable(PMU_instance()->hal);
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s_pmu_sleep_regdma_backup_enabled = true;
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}
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}
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void pmu_sleep_disable_regdma_backup(void)
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{
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if(s_pmu_sleep_regdma_backup_enabled){
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assert(PMU_instance()->hal);
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pmu_hal_hp_set_sleep_active_backup_disable(PMU_instance()->hal);
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pmu_hal_hp_set_sleep_modem_backup_disable(PMU_instance()->hal);
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pmu_hal_hp_set_modem_active_backup_disable(PMU_instance()->hal);
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s_pmu_sleep_regdma_backup_enabled = false;
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}
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}
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uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t pd_flags, uint32_t slowclk_period, uint32_t fastclk_period)
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{
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const pmu_sleep_machine_constant_t *mc = (pmu_sleep_machine_constant_t *)PMU_instance()->mc;
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/* LP core hardware wait time, microsecond */
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const int lp_wakeup_wait_time_us = rtc_time_slowclk_to_us(mc->lp.wakeup_wait_cycle, slowclk_period);
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const int lp_clk_switch_time_us = rtc_time_slowclk_to_us(mc->lp.clk_switch_cycle, slowclk_period);
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const int lp_clk_power_on_wait_time_us = (pd_flags & PMU_SLEEP_PD_XTAL) ? mc->lp.xtal_wait_stable_time_us \
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: rtc_time_slowclk_to_us(mc->lp.clk_power_on_wait_cycle, slowclk_period);
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const int lp_hw_wait_time_us = mc->lp.min_slp_time_us + mc->lp.analog_wait_time_us + lp_clk_power_on_wait_time_us \
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+ lp_wakeup_wait_time_us + lp_clk_switch_time_us + mc->lp.power_supply_wait_time_us \
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+ mc->lp.power_up_wait_time_us;
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/* HP core hardware wait time, microsecond */
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const int hp_digital_power_up_wait_time_us = mc->hp.power_supply_wait_time_us + mc->hp.power_up_wait_time_us;
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const int hp_regdma_wait_time_us = MAX(mc->hp.regdma_s2m_work_time_us + mc->hp.regdma_m2a_work_time_us, mc->hp.regdma_s2a_work_time_us);
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const int hp_clock_wait_time_us = mc->hp.xtal_wait_stable_time_us + mc->hp.pll_wait_stable_time_us;
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const int hp_hw_wait_time_us = mc->hp.analog_wait_time_us + MAX(hp_digital_power_up_wait_time_us + hp_regdma_wait_time_us, hp_clock_wait_time_us);
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/* When the SOC wakeup (lp timer or GPIO wakeup) and Modem wakeup (Beacon wakeup) complete, the soc
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* wakeup will be delayed until the RF is turned on in Modem state.
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*
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* modem wakeup TBTT, RF on by HW
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* | |
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* \|/ \|/
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* PMU_HP_ACTIVE /------
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* PMU_HP_MODEM /------------//////////////////
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* PMU_HP_SLEEP ----------------------//////////////////
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* /|\ /|\ /|\ /|\ /|\ /|\
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* |<- some hw wait ->| | | |<- M2A switch ->|
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* | slow cycles & | soc wakeup | |
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* | FOSC cycles |<- S2M switch ->| |
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* | |
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* |<-- PMU guard time, also the maximum time for the SOC -->|
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* | wake-up delay |
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*/
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#if SOC_PM_SUPPORT_PMU_MODEM_STATE && CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP
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const int rf_on_protect_time_us = mc->hp.regdma_rf_on_work_time_us;
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const int total_hw_wait_time_us = lp_hw_wait_time_us + hp_hw_wait_time_us + mc->hp.clock_domain_sync_time_us;
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#else
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const int rf_on_protect_time_us = 0;
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const int total_hw_wait_time_us = lp_hw_wait_time_us + hp_hw_wait_time_us;
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#endif
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return total_hw_wait_time_us + rf_on_protect_time_us;
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}
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#define rtc_time_us_to_fastclk(time_us, period) rtc_time_us_to_slowclk((time_us), (period))
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static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default(
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pmu_sleep_param_config_t *param,
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pmu_sleep_power_config_t *power, /* We'll use the runtime power parameter to determine some hardware parameters */
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const uint32_t pd_flags,
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const uint32_t adjustment,
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const uint32_t slowclk_period,
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const uint32_t fastclk_period
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)
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{
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const pmu_sleep_machine_constant_t *mc = (pmu_sleep_machine_constant_t *)PMU_instance()->mc;
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param->hp_sys.min_slp_slow_clk_cycle = rtc_time_us_to_slowclk(mc->hp.min_slp_time_us, slowclk_period);
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param->hp_sys.analog_wait_target_cycle = rtc_time_us_to_fastclk(mc->hp.analog_wait_time_us, fastclk_period);
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param->hp_sys.digital_power_supply_wait_cycle = rtc_time_us_to_fastclk(mc->hp.power_supply_wait_time_us, fastclk_period);
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param->hp_sys.digital_power_up_wait_cycle = rtc_time_us_to_fastclk(mc->hp.power_up_wait_time_us, fastclk_period);
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param->hp_sys.pll_stable_wait_cycle = rtc_time_us_to_fastclk(mc->hp.pll_wait_stable_time_us, fastclk_period);
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const int hw_wait_time_us = pmu_sleep_calculate_hw_wait_time(pd_flags, slowclk_period, fastclk_period);
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const int modem_state_skip_time_us = mc->hp.regdma_m2a_work_time_us + mc->hp.system_dfs_up_work_time_us + mc->lp.min_slp_time_us;
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const int modem_wakeup_wait_time_us = adjustment - hw_wait_time_us + modem_state_skip_time_us + mc->hp.regdma_rf_on_work_time_us;
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param->hp_sys.modem_wakeup_wait_cycle = rtc_time_us_to_fastclk(modem_wakeup_wait_time_us, fastclk_period);
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param->lp_sys.min_slp_slow_clk_cycle = rtc_time_us_to_slowclk(mc->lp.min_slp_time_us, slowclk_period);
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param->lp_sys.analog_wait_target_cycle = rtc_time_us_to_slowclk(mc->lp.analog_wait_time_us, slowclk_period);
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param->lp_sys.digital_power_supply_wait_cycle = rtc_time_us_to_fastclk(mc->lp.power_supply_wait_time_us, fastclk_period);
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param->lp_sys.digital_power_up_wait_cycle = rtc_time_us_to_fastclk(mc->lp.power_up_wait_time_us, fastclk_period);
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if (power->hp_sys.xtal.xpd_xtal) {
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param->hp_lp.xtal_stable_wait_slow_clk_cycle = rtc_time_us_to_slowclk(mc->lp.xtal_wait_stable_time_us, slowclk_period);
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} else {
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param->hp_lp.xtal_stable_wait_cycle = rtc_time_us_to_fastclk(mc->hp.xtal_wait_stable_time_us, fastclk_period);
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}
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return param;
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}
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const pmu_sleep_config_t* pmu_sleep_config_default(
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pmu_sleep_config_t *config,
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uint32_t pd_flags,
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uint32_t adjustment,
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uint32_t slowclk_period,
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uint32_t fastclk_period,
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bool dslp
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)
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{
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pmu_sleep_power_config_t power_default = PMU_SLEEP_POWER_CONFIG_DEFAULT(pd_flags);
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uint32_t iram_pd_flags = 0;
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iram_pd_flags |= (pd_flags & PMU_SLEEP_PD_MEM_G0) ? BIT(0) : 0;
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iram_pd_flags |= (pd_flags & PMU_SLEEP_PD_MEM_G1) ? BIT(1) : 0;
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iram_pd_flags |= (pd_flags & PMU_SLEEP_PD_MEM_G2) ? BIT(2) : 0;
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iram_pd_flags |= (pd_flags & PMU_SLEEP_PD_MEM_G3) ? BIT(3) : 0;
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config->power = power_default;
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pmu_sleep_param_config_t param_default = PMU_SLEEP_PARAM_CONFIG_DEFAULT(pd_flags);
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config->param = *pmu_sleep_param_config_default(¶m_default, &power_default, pd_flags, adjustment, slowclk_period, fastclk_period);
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if (dslp) {
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config->param.lp_sys.analog_wait_target_cycle = rtc_time_us_to_slowclk(PMU_LP_ANALOG_WAIT_TARGET_TIME_DSLP_US, slowclk_period);
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pmu_sleep_analog_config_t analog_default = PMU_SLEEP_ANALOG_DSLP_CONFIG_DEFAULT(pd_flags);
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config->analog = analog_default;
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} else {
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pmu_sleep_digital_config_t digital_default = PMU_SLEEP_DIGITAL_LSLP_CONFIG_DEFAULT(pd_flags);
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config->digital = digital_default;
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pmu_sleep_analog_config_t analog_default = PMU_SLEEP_ANALOG_LSLP_CONFIG_DEFAULT(pd_flags);
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if (!(pd_flags & PMU_SLEEP_PD_XTAL)){
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analog_default.hp_sys.analog.pd_cur = PMU_PD_CUR_SLEEP_ON;
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analog_default.hp_sys.analog.bias_sleep = PMU_BIASSLP_SLEEP_ON;
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analog_default.hp_sys.analog.dbias = HP_CALI_DBIAS;
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analog_default.lp_sys[LP(SLEEP)].analog.pd_cur = PMU_PD_CUR_SLEEP_ON;
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analog_default.lp_sys[LP(SLEEP)].analog.bias_sleep = PMU_BIASSLP_SLEEP_ON;
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analog_default.lp_sys[LP(SLEEP)].analog.dbias = LP_CALI_DBIAS;
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}
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config->analog = analog_default;
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}
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return config;
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}
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static void pmu_sleep_power_init(pmu_context_t *ctx, const pmu_sleep_power_config_t *power, bool dslp)
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{
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pmu_ll_hp_set_dig_power(ctx->hal->dev, HP(SLEEP), power->hp_sys.dig_power.val);
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pmu_ll_hp_set_clk_power(ctx->hal->dev, HP(SLEEP), power->hp_sys.clk_power.val);
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pmu_ll_hp_set_xtal_xpd (ctx->hal->dev, HP(SLEEP), power->hp_sys.xtal.xpd_xtal);
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pmu_ll_lp_set_dig_power(ctx->hal->dev, LP(ACTIVE), power->lp_sys[LP(ACTIVE)].dig_power.val);
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pmu_ll_lp_set_clk_power(ctx->hal->dev, LP(ACTIVE), power->lp_sys[LP(ACTIVE)].clk_power.val);
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pmu_ll_lp_set_dig_power(ctx->hal->dev, LP(SLEEP), power->lp_sys[LP(SLEEP)].dig_power.val);
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pmu_ll_lp_set_clk_power(ctx->hal->dev, LP(SLEEP), power->lp_sys[LP(SLEEP)].clk_power.val);
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pmu_ll_lp_set_xtal_xpd (ctx->hal->dev, LP(SLEEP), power->lp_sys[LP(SLEEP)].xtal.xpd_xtal);
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}
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static void pmu_sleep_digital_init(pmu_context_t *ctx, const pmu_sleep_digital_config_t *dig)
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{
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pmu_ll_hp_set_dig_pad_slp_sel (ctx->hal->dev, HP(SLEEP), dig->syscntl.dig_pad_slp_sel);
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}
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static void pmu_sleep_analog_init(pmu_context_t *ctx, const pmu_sleep_analog_config_t *analog, bool dslp)
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{
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assert(ctx->hal);
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pmu_ll_hp_set_dbg_atten (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.dbg_atten);
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pmu_ll_hp_set_current_power_off (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.pd_cur);
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pmu_ll_hp_set_bias_sleep_enable (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.bias_sleep);
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pmu_ll_hp_set_regulator_xpd (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.xpd);
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pmu_ll_hp_set_regulator_dbias (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.dbias);
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pmu_ll_hp_set_regulator_driver_bar (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.drv_b);
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pmu_ll_lp_set_dbg_atten (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.dbg_atten);
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pmu_ll_lp_set_current_power_off (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.pd_cur);
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pmu_ll_lp_set_bias_sleep_enable (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.bias_sleep);
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pmu_ll_lp_set_regulator_slp_xpd (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.slp_xpd);
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pmu_ll_lp_set_regulator_xpd (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.xpd);
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pmu_ll_lp_set_regulator_sleep_dbias(ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.slp_dbias);
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pmu_ll_lp_set_regulator_dbias (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.dbias);
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pmu_ll_lp_set_regulator_driver_bar (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.drv_b);
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}
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static void pmu_sleep_param_init(pmu_context_t *ctx, const pmu_sleep_param_config_t *param, bool dslp)
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{
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assert(ctx->hal);
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pmu_ll_hp_set_min_sleep_cycle(ctx->hal->dev, param->hp_sys.min_slp_slow_clk_cycle);
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pmu_ll_lp_set_min_sleep_cycle(ctx->hal->dev, param->lp_sys.min_slp_slow_clk_cycle);
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pmu_ll_hp_set_analog_wait_target_cycle(ctx->hal->dev, param->hp_sys.analog_wait_target_cycle);
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pmu_ll_lp_set_analog_wait_target_cycle(ctx->hal->dev, param->lp_sys.analog_wait_target_cycle);
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pmu_hal_hp_set_digital_power_up_wait_cycle(ctx->hal, param->hp_sys.digital_power_supply_wait_cycle, param->hp_sys.digital_power_up_wait_cycle);
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pmu_hal_lp_set_digital_power_up_wait_cycle(ctx->hal, param->lp_sys.digital_power_supply_wait_cycle, param->lp_sys.digital_power_up_wait_cycle);
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pmu_ll_set_modem_wait_target_cycle(ctx->hal->dev, param->hp_sys.modem_wakeup_wait_cycle);
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pmu_ll_set_xtal_stable_wait_cycle(ctx->hal->dev, param->hp_lp.xtal_stable_wait_slow_clk_cycle);
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pmu_ll_set_pll_stable_wait_cycle(ctx->hal->dev, param->hp_sys.pll_stable_wait_cycle);
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}
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bool pmu_sleep_pll_already_enabled(void)
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{
|
||||
return (pmu_ll_get_sysclk_sleep_select_state(PMU_instance()->hal->dev) != 0);
|
||||
}
|
||||
|
||||
void pmu_sleep_init(const pmu_sleep_config_t *config, bool dslp)
|
||||
{
|
||||
assert(PMU_instance());
|
||||
pmu_sleep_power_init(PMU_instance(), &config->power, dslp);
|
||||
if(!dslp){
|
||||
pmu_sleep_digital_init(PMU_instance(), &config->digital);
|
||||
}
|
||||
pmu_sleep_analog_init(PMU_instance(), &config->analog, dslp);
|
||||
pmu_sleep_param_init(PMU_instance(), &config->param, dslp);
|
||||
}
|
||||
|
||||
uint32_t pmu_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp_mem_inf_fpu, bool dslp)
|
||||
{
|
||||
assert(PMU_instance()->hal);
|
||||
|
||||
lp_aon_hal_inform_wakeup_type(dslp);
|
||||
|
||||
pmu_ll_hp_set_wakeup_enable(PMU_instance()->hal->dev, wakeup_opt);
|
||||
pmu_ll_hp_set_reject_enable(PMU_instance()->hal->dev, reject_opt);
|
||||
|
||||
pmu_ll_hp_clear_wakeup_intr_status(PMU_instance()->hal->dev);
|
||||
pmu_ll_hp_clear_reject_intr_status(PMU_instance()->hal->dev);
|
||||
pmu_ll_hp_clear_reject_cause(PMU_instance()->hal->dev);
|
||||
|
||||
/* Start entry into sleep mode */
|
||||
pmu_ll_hp_set_sleep_enable(PMU_instance()->hal->dev);
|
||||
|
||||
/* In pd_cpu lightsleep and deepsleep mode, we never get here */
|
||||
while (!pmu_ll_hp_is_sleep_wakeup(PMU_instance()->hal->dev) &&
|
||||
!pmu_ll_hp_is_sleep_reject(PMU_instance()->hal->dev)) {
|
||||
;
|
||||
}
|
||||
|
||||
return pmu_sleep_finish();
|
||||
}
|
||||
|
||||
bool pmu_sleep_finish(void)
|
||||
{
|
||||
return pmu_ll_hp_is_sleep_reject(PMU_instance()->hal->dev);
|
||||
}
|
||||
|
||||
void pmu_sleep_enable_hp_sleep_sysclk(bool enable)
|
||||
{
|
||||
pmu_ll_hp_set_icg_sysclk_enable(PMU_instance()->hal->dev, HP(SLEEP), enable);
|
||||
}
|
||||
|
||||
uint32_t pmu_sleep_get_wakup_retention_cost(void)
|
||||
{
|
||||
const pmu_sleep_machine_constant_t *mc = (pmu_sleep_machine_constant_t *)PMU_instance()->mc;
|
||||
return mc->hp.regdma_s2a_work_time_us;
|
||||
}
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define PMU_EXT0_WAKEUP_EN BIT(0)
|
||||
#define PMU_EXT1_WAKEUP_EN BIT(1)
|
||||
#define PMU_GPIO_WAKEUP_EN BIT(2)
|
||||
#define PMU_WIFI_BEACON_WAKEUP_EN BIT(3)
|
||||
#define PMU_LP_TIMER_WAKEUP_EN BIT(4)
|
||||
#define PMU_WIFI_SOC_WAKEUP_EN BIT(5)
|
||||
#define PMU_UART0_WAKEUP_EN BIT(6)
|
||||
#define PMU_UART1_WAKEUP_EN BIT(7)
|
||||
#define PMU_BLE_SOC_WAKEUP_EN BIT(10)
|
||||
#define PMU_LP_CORE_WAKEUP_EN BIT(11)
|
||||
#define PMU_USB_WAKEUP_EN BIT(14)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -245,10 +245,7 @@ uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period)
|
|||
|
||||
uint64_t rtc_time_get(void)
|
||||
{
|
||||
// TODO: [ESP32C5] IDF-8667
|
||||
// return lp_timer_hal_get_cycle_count();
|
||||
ESP_EARLY_LOGW(TAG, "rtc_time_get has not been implemented yet");
|
||||
return 0;
|
||||
return lp_timer_hal_get_cycle_count();
|
||||
}
|
||||
|
||||
void rtc_clk_wait_for_slow_cycle(void) //This function may not by useful any more
|
||||
|
|
|
|||
|
|
@ -17,9 +17,9 @@
|
|||
#include "sdkconfig.h"
|
||||
#include "esp_log.h"
|
||||
#include "freertos/FreeRTOS.h"
|
||||
// #include "esp_private/sar_periph_ctrl.h"
|
||||
// #include "esp_private/esp_modem_clock.h"
|
||||
// #include "hal/sar_ctrl_ll.h"
|
||||
#include "esp_private/sar_periph_ctrl.h"
|
||||
#include "esp_private/esp_modem_clock.h"
|
||||
#include "hal/sar_ctrl_ll.h"
|
||||
|
||||
static const char *TAG = "sar_periph_ctrl";
|
||||
extern portMUX_TYPE rtc_spinlock;
|
||||
|
|
@ -28,26 +28,23 @@ extern portMUX_TYPE rtc_spinlock;
|
|||
|
||||
void sar_periph_ctrl_init(void)
|
||||
{
|
||||
// sar_ctrl_ll_force_power_ctrl_from_pwdet(true);
|
||||
sar_ctrl_ll_force_power_ctrl_from_pwdet(true);
|
||||
|
||||
//Add other periph power control initialisation here
|
||||
ESP_EARLY_LOGW(TAG, "sar_periph_ctrl_init has not implemented on C5 yet");
|
||||
}
|
||||
|
||||
void sar_periph_ctrl_power_enable(void)
|
||||
{
|
||||
// portENTER_CRITICAL_SAFE(&rtc_spinlock);
|
||||
// sar_ctrl_ll_force_power_ctrl_from_pwdet(true);
|
||||
// portEXIT_CRITICAL_SAFE(&rtc_spinlock);
|
||||
ESP_EARLY_LOGW(TAG, "sar_periph_ctrl_power_enable has not implemented on C5 yet");
|
||||
portENTER_CRITICAL_SAFE(&rtc_spinlock);
|
||||
sar_ctrl_ll_force_power_ctrl_from_pwdet(true);
|
||||
portEXIT_CRITICAL_SAFE(&rtc_spinlock);
|
||||
}
|
||||
|
||||
void sar_periph_ctrl_power_disable(void)
|
||||
{
|
||||
// portENTER_CRITICAL_SAFE(&rtc_spinlock);
|
||||
// sar_ctrl_ll_force_power_ctrl_from_pwdet(false);
|
||||
// portEXIT_CRITICAL_SAFE(&rtc_spinlock);
|
||||
ESP_EARLY_LOGW(TAG, "sar_periph_ctrl_power_disable has not implemented on C5 yet");
|
||||
portENTER_CRITICAL_SAFE(&rtc_spinlock);
|
||||
sar_ctrl_ll_force_power_ctrl_from_pwdet(false);
|
||||
portEXIT_CRITICAL_SAFE(&rtc_spinlock);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -60,14 +57,13 @@ static int s_pwdet_power_on_cnt;
|
|||
|
||||
static void s_sar_power_acquire(void)
|
||||
{
|
||||
// modem_clock_module_enable(PERIPH_MODEM_ADC_COMMON_FE_MODULE);
|
||||
modem_clock_module_enable(PERIPH_MODEM_ADC_COMMON_FE_MODULE);
|
||||
portENTER_CRITICAL_SAFE(&rtc_spinlock);
|
||||
s_pwdet_power_on_cnt++;
|
||||
if (s_pwdet_power_on_cnt == 1) {
|
||||
// sar_ctrl_ll_set_power_mode_from_pwdet(SAR_CTRL_LL_POWER_ON);
|
||||
sar_ctrl_ll_set_power_mode_from_pwdet(SAR_CTRL_LL_POWER_ON);
|
||||
}
|
||||
portEXIT_CRITICAL_SAFE(&rtc_spinlock);
|
||||
ESP_EARLY_LOGW(TAG, "s_sar_power_acquire has not implemented on C5 yet");
|
||||
}
|
||||
|
||||
static void s_sar_power_release(void)
|
||||
|
|
@ -79,11 +75,10 @@ static void s_sar_power_release(void)
|
|||
ESP_LOGE(TAG, "%s called, but s_pwdet_power_on_cnt == 0", __func__);
|
||||
abort();
|
||||
} else if (s_pwdet_power_on_cnt == 0) {
|
||||
// sar_ctrl_ll_set_power_mode_from_pwdet(SAR_CTRL_LL_POWER_FSM);
|
||||
sar_ctrl_ll_set_power_mode_from_pwdet(SAR_CTRL_LL_POWER_FSM);
|
||||
}
|
||||
portEXIT_CRITICAL_SAFE(&rtc_spinlock);
|
||||
ESP_EARLY_LOGW(TAG, "s_sar_power_release has not implemented on C5 yet");
|
||||
// modem_clock_module_disable(PERIPH_MODEM_ADC_COMMON_FE_MODULE);
|
||||
modem_clock_module_disable(PERIPH_MODEM_ADC_COMMON_FE_MODULE);
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -890,7 +890,7 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t m
|
|||
esp_sleep_isolate_digital_gpio();
|
||||
#endif
|
||||
|
||||
#if ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB
|
||||
#if ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB && SOC_DEEP_SLEEP_SUPPORTED
|
||||
#if SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY
|
||||
esp_set_deep_sleep_wake_stub_default_entry();
|
||||
#elif !CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP && SOC_RTC_FAST_MEM_SUPPORTED
|
||||
|
|
@ -998,10 +998,12 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t m
|
|||
misc_modules_wake_prepare();
|
||||
}
|
||||
|
||||
#if SOC_SPI_MEM_SUPPORT_TIMING_TUNING
|
||||
if (cpu_freq_config.source == SOC_CPU_CLK_SRC_PLL) {
|
||||
// Turn up MSPI speed if switch to PLL
|
||||
mspi_timing_change_speed_mode_cache_safe(false);
|
||||
}
|
||||
#endif
|
||||
|
||||
// re-enable UART output
|
||||
resume_uarts();
|
||||
|
|
|
|||
|
|
@ -222,14 +222,13 @@ __attribute__((weak)) void esp_perip_clk_init(void)
|
|||
* oscillator (40 MHz) to provide the clock during the sleep process in some
|
||||
* scenarios), the module needs to switch to the required clock source by
|
||||
* itself. */ //TODO - WIFI-5233
|
||||
// soc_rtc_slow_clk_src_t rtc_slow_clk_src = rtc_clk_slow_src_get();
|
||||
// modem_clock_lpclk_src_t modem_lpclk_src = (modem_clock_lpclk_src_t)(
|
||||
// (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) ? MODEM_CLOCK_LPCLK_SRC_RC_SLOW
|
||||
// : (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) ? MODEM_CLOCK_LPCLK_SRC_XTAL32K
|
||||
// : (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) ? MODEM_CLOCK_LPCLK_SRC_RC32K
|
||||
// : (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) ? MODEM_CLOCK_LPCLK_SRC_EXT32K
|
||||
// : SOC_RTC_SLOW_CLK_SRC_RC_SLOW);
|
||||
// modem_clock_select_lp_clock_source(PERIPH_WIFI_MODULE, modem_lpclk_src, 0);
|
||||
soc_rtc_slow_clk_src_t rtc_slow_clk_src = rtc_clk_slow_src_get();
|
||||
modem_clock_lpclk_src_t modem_lpclk_src = (modem_clock_lpclk_src_t)(
|
||||
(rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) ? MODEM_CLOCK_LPCLK_SRC_XTAL32K
|
||||
: (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) ? MODEM_CLOCK_LPCLK_SRC_RC32K
|
||||
: (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) ? MODEM_CLOCK_LPCLK_SRC_EXT32K
|
||||
: MODEM_CLOCK_LPCLK_SRC_RC32K);
|
||||
modem_clock_select_lp_clock_source(PERIPH_WIFI_MODULE, modem_lpclk_src, 0);
|
||||
|
||||
ESP_EARLY_LOGW(TAG, "esp_perip_clk_init() has not been implemented yet");
|
||||
#if 0 // TODO: [ESP32C5] IDF-8844
|
||||
|
|
|
|||
|
|
@ -186,12 +186,12 @@ __attribute__((weak)) void esp_perip_clk_init(void)
|
|||
* scenarios), the module needs to switch to the required clock source by
|
||||
* itself. */ //TODO - WIFI-5233
|
||||
soc_rtc_slow_clk_src_t rtc_slow_clk_src = rtc_clk_slow_src_get();
|
||||
modem_clock_lpclk_src_t modem_lpclk_src = (modem_clock_lpclk_src_t)(\
|
||||
(rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) ? MODEM_CLOCK_LPCLK_SRC_RC_SLOW \
|
||||
: (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) ? MODEM_CLOCK_LPCLK_SRC_XTAL32K \
|
||||
: (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) ? MODEM_CLOCK_LPCLK_SRC_RC32K \
|
||||
: (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) ? MODEM_CLOCK_LPCLK_SRC_EXT32K \
|
||||
: SOC_RTC_SLOW_CLK_SRC_RC_SLOW);
|
||||
modem_clock_lpclk_src_t modem_lpclk_src = (modem_clock_lpclk_src_t)(
|
||||
(rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) ? MODEM_CLOCK_LPCLK_SRC_RC_SLOW
|
||||
: (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) ? MODEM_CLOCK_LPCLK_SRC_XTAL32K
|
||||
: (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) ? MODEM_CLOCK_LPCLK_SRC_RC32K
|
||||
: (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) ? MODEM_CLOCK_LPCLK_SRC_EXT32K
|
||||
: SOC_RTC_SLOW_CLK_SRC_RC_SLOW);
|
||||
modem_clock_select_lp_clock_source(PERIPH_WIFI_MODULE, modem_lpclk_src, 0);
|
||||
|
||||
ESP_EARLY_LOGW(TAG, "esp_perip_clk_init() has not been implemented yet");
|
||||
|
|
|
|||
|
|
@ -0,0 +1,17 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "hal/lp_aon_ll.h"
|
||||
|
||||
#define rtc_hal_ext1_get_wakeup_status() lp_aon_ll_ext1_get_wakeup_status()
|
||||
#define rtc_hal_ext1_clear_wakeup_status() lp_aon_ll_ext1_clear_wakeup_status()
|
||||
#define rtc_hal_ext1_set_wakeup_pins(io_mask, mode_mask) lp_aon_ll_ext1_set_wakeup_pins(io_mask, mode_mask)
|
||||
#define rtc_hal_ext1_clear_wakeup_pins() lp_aon_ll_ext1_clear_wakeup_pins()
|
||||
#define rtc_hal_ext1_get_wakeup_pins() lp_aon_ll_ext1_get_wakeup_pins()
|
||||
|
||||
#define lp_aon_hal_inform_wakeup_type(dslp) lp_aon_ll_inform_wakeup_type(dslp)
|
||||
|
|
@ -0,0 +1,97 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The LL layer for ESP32-C5 LP_AON register operations
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdlib.h>
|
||||
#include "soc/soc.h"
|
||||
#include "soc/lp_aon_struct.h"
|
||||
#include "hal/misc.h"
|
||||
#include "esp32c5/rom/rtc.h"
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Get ext1 wakeup source status
|
||||
* @return The lower 8 bits of the returned value are the bitmap of
|
||||
* the wakeup source status, bit 0~7 corresponds to LP_IO 0~7
|
||||
*/
|
||||
static inline uint32_t lp_aon_ll_ext1_get_wakeup_status(void)
|
||||
{
|
||||
return HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_status);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear the ext1 wakeup source status
|
||||
*/
|
||||
static inline void lp_aon_ll_ext1_clear_wakeup_status(void)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_status_clr, 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the wake-up LP_IO of the ext1 wake-up source
|
||||
* @param io_mask wakeup LP_IO bitmap, bit 0~7 corresponds to LP_IO 0~7
|
||||
* @param level_mask LP_IO wakeup level bitmap, bit 0~7 corresponds to LP_IO 0~7 wakeup level
|
||||
* each bit's corresponding position is set to 0, the wakeup level will be low
|
||||
* on the contrary, each bit's corresponding position is set to 1, the wakeup
|
||||
* level will be high
|
||||
*/
|
||||
static inline void lp_aon_ll_ext1_set_wakeup_pins(uint32_t io_mask, uint32_t level_mask)
|
||||
{
|
||||
uint32_t wakeup_sel_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel);
|
||||
wakeup_sel_mask |= io_mask;
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel, wakeup_sel_mask);
|
||||
|
||||
uint32_t wakeup_level_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_lv);
|
||||
wakeup_level_mask |= io_mask & level_mask;
|
||||
wakeup_level_mask &= ~(io_mask & ~level_mask);
|
||||
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_lv, wakeup_level_mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear all ext1 wakup-source setting
|
||||
*/
|
||||
static inline void lp_aon_ll_ext1_clear_wakeup_pins(void)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel, 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get ext1 wakeup source setting
|
||||
* @return The lower 8 bits of the returned value are the bitmap of
|
||||
* the wakeup source status, bit 0~7 corresponds to LP_IO 0~7
|
||||
*/
|
||||
static inline uint32_t lp_aon_ll_ext1_get_wakeup_pins(void)
|
||||
{
|
||||
return HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief ROM obtains the wake-up type through LP_AON_STORE9_REG[0].
|
||||
* Set the flag to inform
|
||||
* @param true: deepsleep false: lightsleep
|
||||
*/
|
||||
static inline void lp_aon_ll_inform_wakeup_type(bool dslp)
|
||||
{
|
||||
if (dslp) {
|
||||
REG_SET_BIT(RTC_SLEEP_MODE_REG, BIT(0)); /* Tell rom to run deep sleep wake stub */
|
||||
|
||||
} else {
|
||||
REG_CLR_BIT(RTC_SLEEP_MODE_REG, BIT(0)); /* Tell rom to run light sleep wake stub */
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,141 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The LL layer for ESP32-C5 LP_Timer register operations
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdlib.h>
|
||||
#include "soc/soc.h"
|
||||
#include "soc/rtc.h"
|
||||
#include "soc/lp_timer_struct.h"
|
||||
#include "soc/lp_aon_reg.h"
|
||||
#include "hal/lp_timer_types.h"
|
||||
#include "esp_attr.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Set lp_timer alarm target
|
||||
*
|
||||
* @param dev lp_timer source
|
||||
* @param timer_id lp_timer target num
|
||||
* @param value next alarm value
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
FORCE_INLINE_ATTR void lp_timer_ll_set_alarm_target(lp_timer_dev_t *dev, uint8_t timer_id, uint64_t value)
|
||||
{
|
||||
dev->target[timer_id].hi.main_timer_tar_high = (value >> 32) & 0xFFFF;
|
||||
dev->target[timer_id].lo.main_timer_tar_low = value & 0xFFFFFFFF;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable lp_timer alarm
|
||||
*
|
||||
* @param dev lp_timer source
|
||||
* @param timer_id lp_timer target num
|
||||
* @param en enable bit
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
FORCE_INLINE_ATTR void lp_timer_ll_set_target_enable(lp_timer_dev_t *dev, uint8_t timer_id, bool en)
|
||||
{
|
||||
dev->target[timer_id].hi.main_timer_tar_en = en;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get lp_timer low bits value of counter
|
||||
*
|
||||
* @param dev lp_timer source
|
||||
* @param buffer_id lp_timer counter buffer num
|
||||
*
|
||||
* @return The lp_timer low bits value of counter
|
||||
*/
|
||||
FORCE_INLINE_ATTR uint32_t lp_timer_ll_get_counter_value_low(lp_timer_dev_t *dev, uint8_t buffer_id)
|
||||
{
|
||||
return dev->counter[buffer_id].lo.main_timer_buf_low;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get lp_timer high bits value of counter
|
||||
*
|
||||
* @param dev lp_timer source
|
||||
* @param buffer_id lp_timer counter buffer num
|
||||
*
|
||||
* @return The lp_timer high bits value of counter
|
||||
*/
|
||||
FORCE_INLINE_ATTR uint32_t lp_timer_ll_get_counter_value_high(lp_timer_dev_t *dev, uint8_t buffer_id)
|
||||
{
|
||||
return dev->counter[buffer_id].hi.main_timer_buf_high;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update lp_timer counter
|
||||
*
|
||||
* @param dev lp_timer source
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
FORCE_INLINE_ATTR void lp_timer_ll_counter_snapshot(lp_timer_dev_t *dev)
|
||||
{
|
||||
dev->update.main_timer_update = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear lp_timer alarm intr status
|
||||
*
|
||||
* @param dev lp_timer source
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
FORCE_INLINE_ATTR void lp_timer_ll_clear_alarm_intr_status(lp_timer_dev_t *dev)
|
||||
{
|
||||
dev->int_clr.soc_wakeup_int_clr = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear lp_timer overflow intr status
|
||||
*
|
||||
* @param dev lp_timer source
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
FORCE_INLINE_ATTR void lp_timer_ll_clear_overflow_intr_status(lp_timer_dev_t *dev)
|
||||
{
|
||||
dev->int_clr.overflow_clr = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear lp_timer lp_alarm intr status
|
||||
*
|
||||
* @param dev lp_timer source
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
FORCE_INLINE_ATTR void lp_timer_ll_clear_lp_alarm_intr_status(lp_timer_dev_t *dev)
|
||||
{
|
||||
dev->lp_int_clr.main_timer_lp_int_clr = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Convert lp_timer time to count
|
||||
*
|
||||
* @param time_in_us time in us
|
||||
*
|
||||
* @return lp_timer count
|
||||
*/
|
||||
FORCE_INLINE_ATTR uint64_t lp_timer_ll_time_to_count(uint64_t time_in_us)
|
||||
{
|
||||
uint32_t slow_clk_value = REG_READ(LP_AON_STORE1_REG);
|
||||
return ((time_in_us * (1 << RTC_CLK_CAL_FRACT)) / slow_clk_value);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,155 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The LL layer for ESP32-C5 PAU(Power Assist Unit) register operations
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <stdbool.h>
|
||||
#include "soc/soc.h"
|
||||
#include "soc/pau_reg.h"
|
||||
#include "soc/pau_struct.h"
|
||||
#include "hal/pau_types.h"
|
||||
#include "hal/assert.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
static inline uint32_t pau_ll_get_regdma_backup_flow_error(pau_dev_t *dev)
|
||||
{
|
||||
return dev->regdma_conf.flow_err;
|
||||
}
|
||||
|
||||
static inline void pau_ll_select_regdma_entry_link(pau_dev_t *dev, int link)
|
||||
{
|
||||
dev->regdma_conf.link_sel = link;
|
||||
}
|
||||
|
||||
static inline void pau_ll_set_regdma_entry_link_backup_direction(pau_dev_t *dev, bool to_mem)
|
||||
{
|
||||
dev->regdma_conf.to_mem = to_mem ? 1 : 0;
|
||||
}
|
||||
|
||||
static inline void pau_ll_set_regdma_entry_link_backup_start_enable(pau_dev_t *dev)
|
||||
{
|
||||
dev->regdma_conf.start = 1;
|
||||
}
|
||||
|
||||
static inline void pau_ll_set_regdma_entry_link_backup_start_disable(pau_dev_t *dev)
|
||||
{
|
||||
dev->regdma_conf.start = 0;
|
||||
}
|
||||
|
||||
static inline void pau_ll_set_regdma_select_wifimac_link(pau_dev_t *dev)
|
||||
{
|
||||
dev->regdma_conf.sel_mac = 1;
|
||||
}
|
||||
|
||||
static inline void pau_ll_set_regdma_deselect_wifimac_link(pau_dev_t *dev)
|
||||
{
|
||||
dev->regdma_conf.sel_mac = 0;
|
||||
}
|
||||
|
||||
static inline void pau_ll_set_regdma_wifimac_link_backup_direction(pau_dev_t *dev, bool to_mem)
|
||||
{
|
||||
dev->regdma_conf.to_mem_mac = to_mem ? 1 : 0;
|
||||
}
|
||||
|
||||
static inline void pau_ll_set_regdma_wifimac_link_backup_start_enable(pau_dev_t *dev)
|
||||
{
|
||||
dev->regdma_conf.start_mac = 1;
|
||||
}
|
||||
|
||||
static inline void pau_ll_set_regdma_wifimac_link_backup_start_disable(pau_dev_t *dev)
|
||||
{
|
||||
dev->regdma_conf.start_mac = 0;
|
||||
}
|
||||
|
||||
static inline void pau_ll_set_regdma_link0_addr(pau_dev_t *dev, void *link_addr)
|
||||
{
|
||||
dev->regdma_link_0_addr.val = (uint32_t)link_addr;
|
||||
}
|
||||
|
||||
static inline void pau_ll_set_regdma_link1_addr(pau_dev_t *dev, void *link_addr)
|
||||
{
|
||||
dev->regdma_link_1_addr.val = (uint32_t)link_addr;
|
||||
}
|
||||
|
||||
static inline void pau_ll_set_regdma_link2_addr(pau_dev_t *dev, void *link_addr)
|
||||
{
|
||||
dev->regdma_link_2_addr.val = (uint32_t)link_addr;
|
||||
}
|
||||
|
||||
static inline void pau_ll_set_regdma_link3_addr(pau_dev_t *dev, void *link_addr)
|
||||
{
|
||||
dev->regdma_link_3_addr.val = (uint32_t)link_addr;
|
||||
}
|
||||
|
||||
static inline void pau_ll_set_regdma_wifimac_link_addr(pau_dev_t *dev, void *link_addr)
|
||||
{
|
||||
dev->regdma_link_mac_addr.val = (uint32_t)link_addr;
|
||||
}
|
||||
|
||||
static inline uint32_t pau_ll_get_regdma_current_link_addr(pau_dev_t *dev)
|
||||
{
|
||||
return dev->regdma_current_link_addr.val;
|
||||
}
|
||||
|
||||
static inline uint32_t pau_ll_get_regdma_backup_addr(pau_dev_t *dev)
|
||||
{
|
||||
return dev->regdma_backup_addr.val;
|
||||
}
|
||||
|
||||
static inline uint32_t pau_ll_get_regdma_memory_addr(pau_dev_t *dev)
|
||||
{
|
||||
return dev->regdma_mem_addr.val;
|
||||
}
|
||||
|
||||
static inline uint32_t pau_ll_get_regdma_intr_raw_signal(pau_dev_t *dev)
|
||||
{
|
||||
return dev->int_raw.val;
|
||||
}
|
||||
|
||||
static inline uint32_t pau_ll_get_regdma_intr_status(pau_dev_t *dev)
|
||||
{
|
||||
return dev->int_st.val;
|
||||
}
|
||||
|
||||
static inline void pau_ll_set_regdma_backup_done_intr_enable(pau_dev_t *dev)
|
||||
{
|
||||
dev->int_ena.done_int_ena = 1;
|
||||
}
|
||||
|
||||
static inline void pau_ll_set_regdma_backup_done_intr_disable(pau_dev_t *dev)
|
||||
{
|
||||
dev->int_ena.done_int_ena = 0;
|
||||
}
|
||||
|
||||
static inline void pau_ll_set_regdma_backup_error_intr_enable(pau_dev_t *dev)
|
||||
{
|
||||
dev->int_ena.error_int_ena = 1;
|
||||
}
|
||||
|
||||
static inline void pau_ll_set_regdma_backup_error_intr_disable(pau_dev_t *dev)
|
||||
{
|
||||
dev->int_ena.error_int_ena = 0;
|
||||
}
|
||||
|
||||
static inline void pau_ll_clear_regdma_backup_done_intr_state(pau_dev_t *dev)
|
||||
{
|
||||
dev->int_clr.done_int_clr = 1;
|
||||
}
|
||||
|
||||
static inline void pau_ll_clear_regdma_backup_error_intr_state(pau_dev_t *dev)
|
||||
{
|
||||
dev->int_clr.error_int_clr = 1;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,73 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* SAR related peripherals are interdependent.
|
||||
* Related peripherals are:
|
||||
* - ADC
|
||||
* - PWDET
|
||||
*
|
||||
* All of above peripherals require SAR to work correctly.
|
||||
* As SAR has some registers that will influence above mentioned peripherals.
|
||||
* This file gives an abstraction for such registers
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <stdbool.h>
|
||||
#include "soc/soc.h"
|
||||
#include "soc/apb_saradc_struct.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define PWDET_LL_SAR_POWER_FORCE_BIT BIT(24)
|
||||
#define PWDET_LL_SAR_POWER_CNTL_BIT BIT(23)
|
||||
|
||||
|
||||
typedef enum {
|
||||
SAR_CTRL_LL_POWER_FSM, //SAR power controlled by FSM
|
||||
SAR_CTRL_LL_POWER_ON, //SAR power on
|
||||
SAR_CTRL_LL_POWER_OFF, //SAR power off
|
||||
} sar_ctrl_ll_power_t;
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
SAR power control
|
||||
---------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief Set SAR power mode when controlled by PWDET
|
||||
*
|
||||
* @param[in] mode See `sar_ctrl_ll_power_t`
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void sar_ctrl_ll_set_power_mode_from_pwdet(sar_ctrl_ll_power_t mode)
|
||||
{
|
||||
if (mode == SAR_CTRL_LL_POWER_FSM) {
|
||||
REG_CLR_BIT(PWDET_CONF_REG, PWDET_LL_SAR_POWER_FORCE_BIT);
|
||||
} else if (mode == SAR_CTRL_LL_POWER_ON) {
|
||||
REG_SET_BIT(PWDET_CONF_REG, PWDET_LL_SAR_POWER_FORCE_BIT);
|
||||
REG_SET_BIT(PWDET_CONF_REG, PWDET_LL_SAR_POWER_CNTL_BIT);
|
||||
} else if (mode == SAR_CTRL_LL_POWER_OFF) {
|
||||
REG_SET_BIT(PWDET_CONF_REG, PWDET_LL_SAR_POWER_FORCE_BIT);
|
||||
REG_CLR_BIT(PWDET_CONF_REG, PWDET_LL_SAR_POWER_CNTL_BIT);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set SAR power ctrl source
|
||||
*
|
||||
* @param[in] force set PWDET as SAR power ctrl source when force is true
|
||||
*/
|
||||
static inline void sar_ctrl_ll_force_power_ctrl_from_pwdet(bool force)
|
||||
{
|
||||
APB_SARADC.saradc_ctrl.saradc_saradc2_pwdet_drv = force;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,58 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The HAL layer for PAU (ESP32-C6 specific part)
|
||||
|
||||
#include "soc/soc.h"
|
||||
#include "esp_attr.h"
|
||||
#include "hal/pau_hal.h"
|
||||
#include "hal/pau_types.h"
|
||||
|
||||
void pau_hal_set_regdma_entry_link_addr(pau_hal_context_t *hal, pau_regdma_link_addr_t *link_addr)
|
||||
{
|
||||
pau_ll_set_regdma_link0_addr(hal->dev, (*link_addr)[0]);
|
||||
pau_ll_set_regdma_link1_addr(hal->dev, (*link_addr)[1]);
|
||||
pau_ll_set_regdma_link2_addr(hal->dev, (*link_addr)[2]);
|
||||
/* The link 3 of REGDMA is reserved, PMU state switching will not use
|
||||
* REGDMA link 3 */
|
||||
}
|
||||
|
||||
void pau_hal_start_regdma_modem_link(pau_hal_context_t *hal, bool backup_or_restore)
|
||||
{
|
||||
pau_ll_clear_regdma_backup_done_intr_state(hal->dev);
|
||||
pau_ll_set_regdma_select_wifimac_link(hal->dev);
|
||||
pau_ll_set_regdma_wifimac_link_backup_direction(hal->dev, backup_or_restore);
|
||||
pau_ll_set_regdma_wifimac_link_backup_start_enable(hal->dev);
|
||||
|
||||
while (!(pau_ll_get_regdma_intr_raw_signal(hal->dev) & PAU_DONE_INT_RAW));
|
||||
}
|
||||
|
||||
void pau_hal_stop_regdma_modem_link(pau_hal_context_t *hal)
|
||||
{
|
||||
pau_ll_set_regdma_wifimac_link_backup_start_disable(hal->dev);
|
||||
pau_ll_set_regdma_deselect_wifimac_link(hal->dev);
|
||||
pau_ll_clear_regdma_backup_done_intr_state(hal->dev);
|
||||
}
|
||||
|
||||
void pau_hal_start_regdma_extra_link(pau_hal_context_t *hal, bool backup_or_restore)
|
||||
{
|
||||
pau_ll_clear_regdma_backup_done_intr_state(hal->dev);
|
||||
/* The link 3 of REGDMA is reserved, we use it as an extra linked list to
|
||||
* provide backup and restore services for BLE, IEEE802.15.4 and possibly
|
||||
* other modules */
|
||||
pau_ll_select_regdma_entry_link(hal->dev, 3);
|
||||
pau_ll_set_regdma_entry_link_backup_direction(hal->dev, backup_or_restore);
|
||||
pau_ll_set_regdma_entry_link_backup_start_enable(hal->dev);
|
||||
|
||||
while (!(pau_ll_get_regdma_intr_raw_signal(hal->dev) & PAU_DONE_INT_RAW));
|
||||
}
|
||||
|
||||
void pau_hal_stop_regdma_extra_link(pau_hal_context_t *hal)
|
||||
{
|
||||
pau_ll_set_regdma_entry_link_backup_start_disable(hal->dev);
|
||||
pau_ll_select_regdma_entry_link(hal->dev, 0); /* restore link select to default */
|
||||
pau_ll_clear_regdma_backup_done_intr_state(hal->dev);
|
||||
}
|
||||
|
|
@ -91,6 +91,18 @@ config SOC_FLASH_ENC_SUPPORTED
|
|||
bool
|
||||
default y
|
||||
|
||||
config SOC_PMU_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_LP_TIMER_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_LP_AON_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_LP_PERIPHERALS_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
|
@ -519,6 +531,14 @@ config SOC_SYSTIMER_ALARM_MISS_COMPENSATE
|
|||
bool
|
||||
default y
|
||||
|
||||
config SOC_LP_TIMER_BIT_WIDTH_LO
|
||||
int
|
||||
default 32
|
||||
|
||||
config SOC_LP_TIMER_BIT_WIDTH_HI
|
||||
int
|
||||
default 16
|
||||
|
||||
config SOC_TIMER_GROUPS
|
||||
int
|
||||
default 2
|
||||
|
|
@ -631,6 +651,22 @@ config SOC_PM_SUPPORT_RTC_PERIPH_PD
|
|||
bool
|
||||
default y
|
||||
|
||||
config SOC_PM_SUPPORT_PMU_MODEM_STATE
|
||||
bool
|
||||
default n
|
||||
|
||||
config SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_PM_CPU_RETENTION_BY_SW
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_PM_PAU_LINK_NUM
|
||||
int
|
||||
default 4
|
||||
|
||||
config SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
|
||||
bool
|
||||
default y
|
||||
|
|
|
|||
|
|
@ -0,0 +1,77 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include "soc/soc.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/*CLINT MINT*/
|
||||
#define CLINT_MINT_SIP_REG (DR_REG_CLINT_M_BASE + 0x0)
|
||||
/* CLINT_CPU_MINT_SIP : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define CLINT_CPU_MINT_SIP BIT(0)
|
||||
#define CLINT_CPU_MINT_SIP_M BIT(0)
|
||||
#define CLINT_CPU_MINT_SIP_V 1
|
||||
#define CLINT_CPU_MINT_SIP_S 0
|
||||
|
||||
#define CLINT_MINT_MTIMECMP_L_REG (DR_REG_CLINT_M_BASE + 0x4000)
|
||||
/* CLINT_CPU_MINT_MTIMECMP_L : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: .*/
|
||||
#define CLINT_CPU_MINT_MTIMECMP_L 0xFFFFFFFF
|
||||
#define CLINT_CPU_MINT_MTIMECMP_L_M ((CLINT_CPU_MINT_MTIMECMP_L_V)<<(CLINT_CPU_MINT_MTIMECMP_L_S))
|
||||
#define CLINT_CPU_MINT_MTIMECMP_L_V 0xFFFFFFFF
|
||||
#define CLINT_CPU_MINT_MTIMECMP_L_S 0
|
||||
|
||||
#define CLINT_MINT_MTIMECMP_H_REG (DR_REG_CLINT_M_BASE + 0x4004)
|
||||
/* CLINT_CPU_MINT_MTIMECMP_H : RO ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: .*/
|
||||
#define CLINT_CPU_MINT_MTIMECMP_H 0xFFFFFFFF
|
||||
#define CLINT_CPU_MINT_MTIMECMP_H_M ((CLINT_CPU_MINT_MTIMECMP_H_V)<<(CLINT_CPU_MINT_MTIMECMP_H_S))
|
||||
#define CLINT_CPU_MINT_MTIMECMP_H_V 0xFFFFFFFF
|
||||
#define CLINT_CPU_MINT_MTIMECMP_H_S 0
|
||||
|
||||
#define CLINT_MINT_TIMECTL_REG (DR_REG_CLINT_M_BASE + 0x4010)
|
||||
/* CLINT_MINT_SAMPLING_MODE : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
|
||||
/*description: .*/
|
||||
#define CLINT_MINT_SAMPLING_MODE 0x00000003
|
||||
#define CLINT_MINT_SAMPLING_MODE_M ((CLINT_CPU_MINT_TIMECTL_V)<<(CLINT_CPU_MINT_TIMECTL_S))
|
||||
#define CLINT_MINT_SAMPLING_MODE_V 0x3
|
||||
#define CLINT_MINT_SAMPLING_MODE_S 4
|
||||
/* CLINT_MINT_COUNTER_OVERFLOW : R/W ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define CLINT_MINT_COUNTER_OVERFLOW (BIT(3))
|
||||
#define CLINT_MINT_COUNTER_OVERFLOW_M (BIT(3))
|
||||
#define CLINT_MINT_COUNTER_OVERFLOW_V 0x1
|
||||
#define CLINT_MINT_COUNTER_OVERFLOW_S 3
|
||||
/* CLINT_MINT_COUNTER_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define CLINT_MINT_COUNTER_EN (BIT(0))
|
||||
#define CLINT_MINT_COUNTER_EN_M (BIT(0))
|
||||
#define CLINT_MINT_COUNTER_EN_V 0x1
|
||||
#define CLINT_MINT_COUNTER_EN_S 0
|
||||
|
||||
#define CLINT_MINT_MTIME_L_REG (DR_REG_CLINT_M_BASE + 0xBFF8)
|
||||
/* CLINT_CPU_MINT_MTIME_L : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: .*/
|
||||
#define CLINT_CPU_MINT_MTIME_L 0xFFFFFFFF
|
||||
#define CLINT_CPU_MINT_MTIME_L_M ((CLINT_CPU_MINT_MTIME_L_V)<<(CLINT_CPU_MINT_MTIME_L_S))
|
||||
#define CLINT_CPU_MINT_MTIME_L_V 0xFFFFFFFF
|
||||
#define CLINT_CPU_MINT_MTIME_L_S 0
|
||||
|
||||
#define CLINT_MINT_MTIME_H_REG (DR_REG_CLINT_M_BASE + 0xBFFC)
|
||||
/* CLINT_CPU_MINT_MTIME_H : RO ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: .*/
|
||||
#define CLINT_CPU_MINT_MTIME_H 0xFFFFFFFF
|
||||
#define CLINT_CPU_MINT_MTIME_H_M ((CLINT_CPU_MINT_MTIME_H_V)<<(CLINT_CPU_MINT_MTIME_H_S))
|
||||
#define CLINT_CPU_MINT_MTIME_H_V 0xFFFFFFFF
|
||||
#define CLINT_CPU_MINT_MTIME_H_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/**
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
|
@ -71,7 +71,7 @@ extern "C" {
|
|||
* 0: anti-DPA disable. 1~3: anti-DPA enable with different security level. The larger
|
||||
* the number, the stronger the ability to resist DPA attacks and the higher the
|
||||
* security level, but it will increase the computational overhead of the hardware
|
||||
* crypto-accelerators. Only avaliable if HP_SYS_SEC_DPA_CFG_SEL is 0.
|
||||
* crypto-accelerators. Only available if HP_SYS_SEC_DPA_CFG_SEL is 0.
|
||||
*/
|
||||
#define HP_SYS_SEC_DPA_LEVEL 0x00000003U
|
||||
#define HP_SYS_SEC_DPA_LEVEL_M (HP_SYS_SEC_DPA_LEVEL_V << HP_SYS_SEC_DPA_LEVEL_S)
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -72,6 +72,7 @@
|
|||
#define DR_REG_MODEM_PWR_BASE 0x600AD000
|
||||
#define DR_REG_I2C_ANA_MST_BASE 0x600AF800
|
||||
|
||||
#define PWDET_CONF_REG 0x600A0810
|
||||
/**
|
||||
* @brief LP System (RTC) Modules
|
||||
*
|
||||
|
|
@ -101,3 +102,4 @@
|
|||
#define DR_REG_ASSIST_DEBUG_BASE 0x600C2000
|
||||
#define DR_REG_INTPRI_BASE 0x600C5000
|
||||
#define DR_REG_CACHE_BASE 0x600C8000 // CACHE_CONFIG/EXTMEM
|
||||
#define DR_REG_CLINT_M_BASE 0x20000000
|
||||
|
|
|
|||
|
|
@ -58,10 +58,10 @@
|
|||
// #define SOC_SECURE_BOOT_SUPPORTED 1 // TODO: [ESP32C5] IDF-8623
|
||||
// #define SOC_BOD_SUPPORTED 1 // TODO: [ESP32C5] IDF-8647
|
||||
// #define SOC_APM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8614, IDF-8615
|
||||
// #define SOC_PMU_SUPPORTED 1 // TODO: [ESP32C5] IDF-8667
|
||||
#define SOC_PMU_SUPPORTED 1 // TODO: [ESP32C5] IDF-8667
|
||||
// #define SOC_PAU_SUPPORTED 1 // TODO: [ESP32C5] IDF-8638, IDF-8640
|
||||
// #define SOC_LP_TIMER_SUPPORTED 1 // TODO: [ESP32C5] IDF-8636
|
||||
// #define SOC_LP_AON_SUPPORTED 1 // TODO: [ESP32C5] IDF-8638, IDF-8640
|
||||
#define SOC_LP_TIMER_SUPPORTED 1 // TODO: [ESP32C5] IDF-8636
|
||||
#define SOC_LP_AON_SUPPORTED 1 // TODO: [ESP32C5] IDF-8638, IDF-8640
|
||||
#define SOC_LP_PERIPHERALS_SUPPORTED 1
|
||||
// #define SOC_LP_I2C_SUPPORTED 1 // TODO: [ESP32C5] IDF-8634
|
||||
#define SOC_ULP_SUPPORTED 1
|
||||
|
|
@ -430,8 +430,8 @@
|
|||
// #define SOC_SYSTIMER_SUPPORT_ETM 1 // Systimer comparator can generate ETM event
|
||||
|
||||
/*-------------------------- LP_TIMER CAPS ----------------------------------*/
|
||||
// #define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part
|
||||
// #define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part
|
||||
#define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part
|
||||
#define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part
|
||||
|
||||
/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
|
||||
#define SOC_TIMER_GROUPS (2)
|
||||
|
|
@ -523,17 +523,17 @@
|
|||
// #define SOC_PM_SUPPORT_MAC_BB_PD (1)
|
||||
#define SOC_PM_SUPPORT_RTC_PERIPH_PD (1)
|
||||
|
||||
// #define SOC_PM_SUPPORT_PMU_MODEM_STATE (1)
|
||||
#define SOC_PM_SUPPORT_PMU_MODEM_STATE (0)
|
||||
/* macro redefine for pass esp_wifi headers md5sum check */
|
||||
// #define MAC_SUPPORT_PMU_MODEM_STATE SOC_PM_SUPPORT_PMU_MODEM_STATE
|
||||
#define MAC_SUPPORT_PMU_MODEM_STATE SOC_PM_SUPPORT_PMU_MODEM_STATE
|
||||
|
||||
// #define SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY (1) /*!<Supports CRC only the stub code in RTC memory */
|
||||
#define SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY (1) /*!<Supports CRC only the stub code in RTC memory */
|
||||
|
||||
// #define SOC_PM_CPU_RETENTION_BY_SW (1)
|
||||
#define SOC_PM_CPU_RETENTION_BY_SW (1)
|
||||
// #define SOC_PM_MODEM_RETENTION_BY_REGDMA (1)
|
||||
// #define SOC_PM_RETENTION_HAS_CLOCK_BUG (1)
|
||||
|
||||
// #define SOC_PM_PAU_LINK_NUM (4)
|
||||
#define SOC_PM_PAU_LINK_NUM (4)
|
||||
|
||||
/*-------------------------- CLOCK SUBSYSTEM CAPS ----------------------------------------*/
|
||||
#define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION (1)
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/**
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
|
@ -670,10 +670,10 @@ extern "C" {
|
|||
/** TEE_DATE_REG : R/W; bitpos: [27:0]; default: 35725664;
|
||||
* reg_tee_date
|
||||
*/
|
||||
#define TEE_DATE_REG 0x0FFFFFFFU
|
||||
#define TEE_DATE_REG_M (TEE_DATE_REG_V << TEE_DATE_REG_S)
|
||||
#define TEE_DATE_REG_V 0x0FFFFFFFU
|
||||
#define TEE_DATE_REG_S 0
|
||||
#define TEE_DATE 0x0FFFFFFFU
|
||||
#define TEE_DATE_M (TEE_DATE_V << TEE_DATE_S)
|
||||
#define TEE_DATE_V 0x0FFFFFFFU
|
||||
#define TEE_DATE_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
|
|
|||
|
|
@ -315,10 +315,6 @@ config SOC_UART_SUPPORT_XTAL_CLK
|
|||
bool
|
||||
default y
|
||||
|
||||
config SOC_PM_SUPPORT_CPU_PD
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_PM_SUPPORT_MODEM_PD
|
||||
bool
|
||||
default y
|
||||
|
|
|
|||
|
|
@ -107,3 +107,4 @@
|
|||
#define DR_REG_ASSIST_DEBUG_BASE 0x600C2000
|
||||
#define DR_REG_INTPRI_BASE 0x600C5000
|
||||
#define DR_REG_CACHE_BASE 0x600C8000 // CACHE_CONFIG/EXTMEM
|
||||
#define DR_REG_CLINT_M_BASE 0x20000000
|
||||
|
|
|
|||
|
|
@ -503,7 +503,7 @@
|
|||
// #define SOC_PM_SUPPORT_BT_WAKEUP (1)
|
||||
// #define SOC_PM_SUPPORT_EXT1_WAKEUP (1)
|
||||
// #define SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN (1) /*!<Supports one bit per pin to configure the EXT1 trigger level */
|
||||
#define SOC_PM_SUPPORT_CPU_PD (1)
|
||||
// #define SOC_PM_SUPPORT_CPU_PD (1)
|
||||
#define SOC_PM_SUPPORT_MODEM_PD (1)
|
||||
#define SOC_PM_SUPPORT_XTAL32K_PD (1)
|
||||
#define SOC_PM_SUPPORT_RC32K_PD (1)
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Unlicense OR CC0-1.0
|
||||
*/
|
||||
|
|
@ -15,6 +15,10 @@
|
|||
#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32H2 \
|
||||
|| CONFIG_IDF_TARGET_ESP32C6
|
||||
#define BOOT_BUTTON_NUM 9
|
||||
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
|
||||
#define BOOT_BUTTON_NUM 28
|
||||
#elif CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
|
||||
#define BOOT_BUTTON_NUM 7
|
||||
#elif CONFIG_IDF_TARGET_ESP32P4
|
||||
#define BOOT_BUTTON_NUM 35
|
||||
#else
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Unlicense OR CC0-1.0
|
||||
*/
|
||||
|
|
@ -46,7 +46,7 @@ static void light_sleep_task(void *args)
|
|||
break;
|
||||
case ESP_SLEEP_WAKEUP_UART:
|
||||
wakeup_reason = "uart";
|
||||
/* Hang-up for a while to switch and execuse the uart task
|
||||
/* Hang-up for a while to switch and execute the uart task
|
||||
* Otherwise the chip may fall sleep again before running uart task */
|
||||
vTaskDelay(1);
|
||||
break;
|
||||
|
|
@ -68,7 +68,7 @@ static void light_sleep_task(void *args)
|
|||
wakeup_reason, t_after_us / 1000, (t_after_us - t_before_us) / 1000);
|
||||
#endif
|
||||
if (esp_sleep_get_wakeup_cause() == ESP_SLEEP_WAKEUP_GPIO) {
|
||||
/* Waiting for the gpio inactive, or the chip will continously trigger wakeup*/
|
||||
/* Waiting for the gpio inactive, or the chip will continuously trigger wakeup*/
|
||||
example_wait_gpio_inactive();
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Ładowanie…
Reference in New Issue