diff --git a/components/esp_hw_support/esp_clock_output.c b/components/esp_hw_support/esp_clock_output.c index 98f571d8bc..4f628cb6bf 100644 --- a/components/esp_hw_support/esp_clock_output.c +++ b/components/esp_hw_support/esp_clock_output.c @@ -21,7 +21,7 @@ typedef struct clkout_channel_handle { bool is_mapped; soc_clkout_sig_id_t mapped_clock; - uint8_t channel_id; + clock_out_channel_t channel_id; uint8_t ref_cnt; uint64_t mapped_io_bmap; portMUX_TYPE clkout_channel_lock; diff --git a/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_esp_clock_output.c b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_esp_clock_output.c index e3e189283e..06fa1cdde6 100644 --- a/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_esp_clock_output.c +++ b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_esp_clock_output.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Unlicense OR CC0-1.0 */ @@ -20,6 +20,8 @@ static const int test_clk_out_io[] = {0, 1, 3}; #elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 static const int test_clk_out_io[] = {18, 19, 20}; +#elif CONFIG_IDF_TARGET_ESP32P4 +static const int test_clk_out_io[] = {7, 8}; #else static const int test_clk_out_io[] = {3, 4, 5, 6}; #endif @@ -54,6 +56,7 @@ void output_clock_2(void *pvParameter) vTaskDelete(NULL); } +#if SOC_GPIO_CLOCKOUT_CHANNEL_NUM >= 3 void output_clock_3(void *pvParameter) { rtc_dig_clk8m_enable(); @@ -67,7 +70,7 @@ void output_clock_3(void *pvParameter) xSemaphoreGive(test_done_semphr); vTaskDelete(NULL); } - +#endif // This case is now tested only manually TEST_CASE("GPIO output internal clock", "[gpio_output_clock][ignore]") @@ -75,10 +78,12 @@ TEST_CASE("GPIO output internal clock", "[gpio_output_clock][ignore]") test_done_semphr = xSemaphoreCreateCounting(3, 0); xTaskCreate(&output_clock_1, "output_clock_1", 4096, NULL, 4, NULL); xTaskCreate(&output_clock_2, "output_clock_2", 4096, NULL, 4, NULL); +#if SOC_GPIO_CLOCKOUT_CHANNEL_NUM >= 3 xTaskCreate(&output_clock_3, "output_clock_3", 4096, NULL, 4, NULL); +#endif int cnt = 0; - while (cnt < 3) { + while (cnt < SOC_GPIO_CLOCKOUT_CHANNEL_NUM) { if (xSemaphoreTake(test_done_semphr, portMAX_DELAY) == pdTRUE) { cnt++; } @@ -86,8 +91,13 @@ TEST_CASE("GPIO output internal clock", "[gpio_output_clock][ignore]") vTaskDelay(1); vSemaphoreDelete(test_done_semphr); + +#if CONFIG_IDF_TARGET_ESP32 + /* ESP32 clock out channel pin reuses UART TX/RX pin, restore its default + configuration at the end of the test */ gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_U0RXD_U, FUNC_U0RXD_U0RXD); gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_U0TXD_U, FUNC_U0TXD_U0TXD); +#endif } #if SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX diff --git a/components/hal/esp32/clk_tree_hal.c b/components/hal/esp32/clk_tree_hal.c index a70640d80e..1b5b676cea 100644 --- a/components/hal/esp32/clk_tree_hal.c +++ b/components/hal/esp32/clk_tree_hal.c @@ -109,12 +109,12 @@ uint32_t clk_hal_apll_get_freq_hz(void) return apll_freq_hz; } -void clk_hal_clock_output_setup(soc_clkout_sig_id_t clk_sig, uint8_t channel_id) +void clk_hal_clock_output_setup(soc_clkout_sig_id_t clk_sig, clock_out_channel_t channel_id) { gpio_ll_set_pin_ctrl(clk_sig, CLKOUT_CHANNEL_MASK(channel_id), CLKOUT_CHANNEL_SHIFT(channel_id)); } -void clk_hal_clock_output_teardown(uint8_t channel_id) +void clk_hal_clock_output_teardown(clock_out_channel_t channel_id) { gpio_ll_set_pin_ctrl(0, CLKOUT_CHANNEL_MASK(channel_id), CLKOUT_CHANNEL_SHIFT(channel_id)); } diff --git a/components/hal/esp32c2/clk_tree_hal.c b/components/hal/esp32c2/clk_tree_hal.c index 6d12c774e6..e7cdd87702 100644 --- a/components/hal/esp32c2/clk_tree_hal.c +++ b/components/hal/esp32c2/clk_tree_hal.c @@ -84,12 +84,12 @@ uint32_t clk_hal_xtal_get_freq_mhz(void) return freq; } -void clk_hal_clock_output_setup(soc_clkout_sig_id_t clk_sig, uint8_t channel_id) +void clk_hal_clock_output_setup(soc_clkout_sig_id_t clk_sig, clock_out_channel_t channel_id) { gpio_ll_set_pin_ctrl(clk_sig, CLKOUT_CHANNEL_MASK(channel_id), CLKOUT_CHANNEL_SHIFT(channel_id)); } -void clk_hal_clock_output_teardown(uint8_t channel_id) +void clk_hal_clock_output_teardown(clock_out_channel_t channel_id) { gpio_ll_set_pin_ctrl(0, CLKOUT_CHANNEL_MASK(channel_id), CLKOUT_CHANNEL_SHIFT(channel_id)); } diff --git a/components/hal/esp32c3/clk_tree_hal.c b/components/hal/esp32c3/clk_tree_hal.c index cf5fadae90..6ce1f5a11a 100644 --- a/components/hal/esp32c3/clk_tree_hal.c +++ b/components/hal/esp32c3/clk_tree_hal.c @@ -83,12 +83,12 @@ uint32_t clk_hal_xtal_get_freq_mhz(void) return freq; } -void clk_hal_clock_output_setup(soc_clkout_sig_id_t clk_sig, uint8_t channel_id) +void clk_hal_clock_output_setup(soc_clkout_sig_id_t clk_sig, clock_out_channel_t channel_id) { gpio_ll_set_pin_ctrl(clk_sig, CLKOUT_CHANNEL_MASK(channel_id), CLKOUT_CHANNEL_SHIFT(channel_id)); } -void clk_hal_clock_output_teardown(uint8_t channel_id) +void clk_hal_clock_output_teardown(clock_out_channel_t channel_id) { gpio_ll_set_pin_ctrl(0, CLKOUT_CHANNEL_MASK(channel_id), CLKOUT_CHANNEL_SHIFT(channel_id)); } diff --git a/components/hal/esp32c5/clk_tree_hal.c b/components/hal/esp32c5/clk_tree_hal.c index af9bd6fbbb..d68db76ccd 100644 --- a/components/hal/esp32c5/clk_tree_hal.c +++ b/components/hal/esp32c5/clk_tree_hal.c @@ -93,12 +93,12 @@ uint32_t clk_hal_xtal_get_freq_mhz(void) return freq; } -void clk_hal_clock_output_setup(soc_clkout_sig_id_t clk_sig, uint8_t channel_id) +void clk_hal_clock_output_setup(soc_clkout_sig_id_t clk_sig, clock_out_channel_t channel_id) { gpio_ll_set_pin_ctrl(clk_sig, CLKOUT_CHANNEL_MASK(channel_id), CLKOUT_CHANNEL_SHIFT(channel_id)); } -void clk_hal_clock_output_teardown(uint8_t channel_id) +void clk_hal_clock_output_teardown(clock_out_channel_t channel_id) { gpio_ll_set_pin_ctrl(0, CLKOUT_CHANNEL_MASK(channel_id), CLKOUT_CHANNEL_SHIFT(channel_id)); } diff --git a/components/hal/esp32c6/clk_tree_hal.c b/components/hal/esp32c6/clk_tree_hal.c index effe484355..432b75d7b3 100644 --- a/components/hal/esp32c6/clk_tree_hal.c +++ b/components/hal/esp32c6/clk_tree_hal.c @@ -76,12 +76,12 @@ uint32_t clk_hal_xtal_get_freq_mhz(void) return freq; } -void clk_hal_clock_output_setup(soc_clkout_sig_id_t clk_sig, uint8_t channel_id) +void clk_hal_clock_output_setup(soc_clkout_sig_id_t clk_sig, clock_out_channel_t channel_id) { gpio_ll_set_pin_ctrl(clk_sig, CLKOUT_CHANNEL_MASK(channel_id), CLKOUT_CHANNEL_SHIFT(channel_id)); } -void clk_hal_clock_output_teardown(uint8_t channel_id) +void clk_hal_clock_output_teardown(clock_out_channel_t channel_id) { gpio_ll_set_pin_ctrl(0, CLKOUT_CHANNEL_MASK(channel_id), CLKOUT_CHANNEL_SHIFT(channel_id)); } diff --git a/components/hal/esp32h2/clk_tree_hal.c b/components/hal/esp32h2/clk_tree_hal.c index 3ba1b088d6..006d63d261 100644 --- a/components/hal/esp32h2/clk_tree_hal.c +++ b/components/hal/esp32h2/clk_tree_hal.c @@ -76,12 +76,12 @@ uint32_t clk_hal_xtal_get_freq_mhz(void) return freq; } -void clk_hal_clock_output_setup(soc_clkout_sig_id_t clk_sig, uint8_t channel_id) +void clk_hal_clock_output_setup(soc_clkout_sig_id_t clk_sig, clock_out_channel_t channel_id) { gpio_ll_set_pin_ctrl(clk_sig, CLKOUT_CHANNEL_MASK(channel_id), CLKOUT_CHANNEL_SHIFT(channel_id)); } -void clk_hal_clock_output_teardown(uint8_t channel_id) +void clk_hal_clock_output_teardown(clock_out_channel_t channel_id) { gpio_ll_set_pin_ctrl(0, CLKOUT_CHANNEL_MASK(channel_id), CLKOUT_CHANNEL_SHIFT(channel_id)); } diff --git a/components/hal/esp32p4/clk_tree_hal.c b/components/hal/esp32p4/clk_tree_hal.c index a819e3c94b..ba1e57f351 100644 --- a/components/hal/esp32p4/clk_tree_hal.c +++ b/components/hal/esp32p4/clk_tree_hal.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -79,3 +79,14 @@ uint32_t clk_hal_xtal_get_freq_mhz(void) } return freq; } + +void clk_hal_clock_output_setup(soc_clkout_sig_id_t clk_sig, clock_out_channel_t channel_id) +{ + clk_ll_set_dbg_clk_ctrl(clk_sig, channel_id); + clk_ll_enable_dbg_clk_channel(channel_id, true); +} + +void clk_hal_clock_output_teardown(clock_out_channel_t channel_id) +{ + clk_ll_enable_dbg_clk_channel(channel_id, false); +} diff --git a/components/hal/esp32p4/include/hal/clk_tree_ll.h b/components/hal/esp32p4/include/hal/clk_tree_ll.h index cc8675e3df..b155e607a9 100644 --- a/components/hal/esp32p4/include/hal/clk_tree_ll.h +++ b/components/hal/esp32p4/include/hal/clk_tree_ll.h @@ -7,6 +7,7 @@ #pragma once #include +#include "soc/clkout_channel.h" #include "soc/soc.h" #include "soc/clk_tree_defs.h" #include "soc/hp_sys_clkrst_reg.h" @@ -823,6 +824,35 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_rtc_slow_load_cal(v return REG_READ(RTC_SLOW_CLK_CAL_REG); } +/** + * @brief Clock output channel configuration + * @param clk_sig The clock signal source to be mapped to GPIOs + * @param channel_id The clock output channel to setup + */ +static inline __attribute__((always_inline)) void clk_ll_set_dbg_clk_ctrl(soc_clkout_sig_id_t clk_sig, clock_out_channel_t channel_id) +{ + if (channel_id == CLKOUT_CHANNEL_1) { + HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.dbg_clk_ctrl0, reg_dbg_ch0_sel, clk_sig); + HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.dbg_clk_ctrl0, reg_dbg_ch0_div_num, 0); + } else if (channel_id == CLKOUT_CHANNEL_2) { + HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.dbg_clk_ctrl0, reg_dbg_ch1_sel, clk_sig); + HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.dbg_clk_ctrl1, reg_dbg_ch1_div_num, 0); + } else { + abort(); + } +} + +static inline __attribute__((always_inline)) void clk_ll_enable_dbg_clk_channel(clock_out_channel_t channel_id, bool enable) +{ + if (channel_id == CLKOUT_CHANNEL_1) { + HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.dbg_clk_ctrl1, reg_dbg_ch0_en, enable); + } else if (channel_id == CLKOUT_CHANNEL_2) { + HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.dbg_clk_ctrl1, reg_dbg_ch1_en, enable); + } else { + abort(); + } +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32p4/include/hal/gpio_ll.h b/components/hal/esp32p4/include/hal/gpio_ll.h index bc153f32b9..94a4df3918 100644 --- a/components/hal/esp32p4/include/hal/gpio_ll.h +++ b/components/hal/esp32p4/include/hal/gpio_ll.h @@ -124,7 +124,7 @@ static inline void gpio_ll_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num) // which should be checked is USB_INT_PHY0_DM_GPIO_NUM instead. // TODO: read the specific efuse with efuse_ll.h - // One more noticable point is P4 has two internal PHYs connecting to USJ and USB_WRAP(OTG1.1) seperately. + // One more noticeable point is P4 has two internal PHYs connecting to USJ and USB_WRAP(OTG1.1) separately. // We only consider the default connection here: PHY0 -> USJ, PHY1 -> USB_OTG if (gpio_num == USB_USJ_INT_PHY_DP_GPIO_NUM) { USB_SERIAL_JTAG.conf0.pad_pull_override = 1; @@ -569,7 +569,7 @@ static inline void gpio_ll_iomux_in(gpio_dev_t *hw, uint32_t gpio, uint32_t sign static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func) { // Disable USB PHY configuration if pins (24, 25) (26, 27) needs to select an IOMUX function - // P4 has two internal PHYs connecting to USJ and USB_WRAP(OTG1.1) seperately. + // P4 has two internal PHYs connecting to USJ and USB_WRAP(OTG1.1) separately. // We only consider the default connection here: PHY0 -> USJ, PHY1 -> USB_OTG if (pin_name == IO_MUX_GPIO24_REG || pin_name == IO_MUX_GPIO25_REG) { USB_SERIAL_JTAG.conf0.usb_pad_enable = 0; @@ -579,17 +579,6 @@ static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func) PIN_FUNC_SELECT(pin_name, func); } -/** - * @brief Control the pin in the IOMUX - * - * @param bmap write mask of control value - * @param val Control value - * @param shift write mask shift of control value - */ -static inline __attribute__((always_inline)) void gpio_ll_set_pin_ctrl(uint32_t val, uint32_t bmap, uint32_t shift) -{ - // TODO: IDF-8226 -} /** * @brief Select a function for the pin in the IOMUX * @@ -601,7 +590,7 @@ __attribute__((always_inline)) static inline void gpio_ll_func_sel(gpio_dev_t *hw, uint8_t gpio_num, uint32_t func) { // Disable USB PHY configuration if pins (24, 25) (26, 27) needs to select an IOMUX function - // P4 has two internal PHYs connecting to USJ and USB_WRAP(OTG1.1) seperately. + // P4 has two internal PHYs connecting to USJ and USB_WRAP(OTG1.1) separately. // We only consider the default connection here: PHY0 -> USJ, PHY1 -> USB_OTG if (gpio_num == USB_USJ_INT_PHY_DM_GPIO_NUM || gpio_num == USB_USJ_INT_PHY_DP_GPIO_NUM) { USB_SERIAL_JTAG.conf0.usb_pad_enable = 0; diff --git a/components/hal/esp32s2/clk_tree_hal.c b/components/hal/esp32s2/clk_tree_hal.c index 2785725733..b8deecb311 100644 --- a/components/hal/esp32s2/clk_tree_hal.c +++ b/components/hal/esp32s2/clk_tree_hal.c @@ -114,12 +114,12 @@ uint32_t clk_hal_apll_get_freq_hz(void) return apll_freq_hz; } -void clk_hal_clock_output_setup(soc_clkout_sig_id_t clk_sig, uint8_t channel_id) +void clk_hal_clock_output_setup(soc_clkout_sig_id_t clk_sig, clock_out_channel_t channel_id) { gpio_ll_set_pin_ctrl(clk_sig, CLKOUT_CHANNEL_MASK(channel_id), CLKOUT_CHANNEL_SHIFT(channel_id)); } -void clk_hal_clock_output_teardown(uint8_t channel_id) +void clk_hal_clock_output_teardown(clock_out_channel_t channel_id) { gpio_ll_set_pin_ctrl(0, CLKOUT_CHANNEL_MASK(channel_id), CLKOUT_CHANNEL_SHIFT(channel_id)); } diff --git a/components/hal/esp32s3/clk_tree_hal.c b/components/hal/esp32s3/clk_tree_hal.c index dfee9856dd..f72f6f2dd7 100644 --- a/components/hal/esp32s3/clk_tree_hal.c +++ b/components/hal/esp32s3/clk_tree_hal.c @@ -91,12 +91,12 @@ uint32_t clk_hal_xtal_get_freq_mhz(void) return freq; } -void clk_hal_clock_output_setup(soc_clkout_sig_id_t clk_sig, uint8_t channel_id) +void clk_hal_clock_output_setup(soc_clkout_sig_id_t clk_sig, clock_out_channel_t channel_id) { gpio_ll_set_pin_ctrl(clk_sig, CLKOUT_CHANNEL_MASK(channel_id), CLKOUT_CHANNEL_SHIFT(channel_id)); } -void clk_hal_clock_output_teardown(uint8_t channel_id) +void clk_hal_clock_output_teardown(clock_out_channel_t channel_id) { gpio_ll_set_pin_ctrl(0, CLKOUT_CHANNEL_MASK(channel_id), CLKOUT_CHANNEL_SHIFT(channel_id)); } diff --git a/components/hal/include/hal/clk_tree_hal.h b/components/hal/include/hal/clk_tree_hal.h index 6d02532433..2d61fa138b 100644 --- a/components/hal/include/hal/clk_tree_hal.h +++ b/components/hal/include/hal/clk_tree_hal.h @@ -8,6 +8,7 @@ #include #include "soc/clk_tree_defs.h" +#include "soc/clkout_channel.h" #include "soc/soc_caps.h" #ifdef __cplusplus @@ -65,13 +66,13 @@ uint32_t clk_hal_apll_get_freq_hz(void); * @param clk_sig The clock signal source to be mapped to GPIOs * @param channel_id The clock output channel to setup */ -void clk_hal_clock_output_setup(soc_clkout_sig_id_t clk_sig, uint8_t channel_id); +void clk_hal_clock_output_setup(soc_clkout_sig_id_t clk_sig, clock_out_channel_t channel_id); /** * @brief Teardown clock output channel configuration * @param channel_id The clock output channel to teardown */ -void clk_hal_clock_output_teardown(uint8_t channel_id); +void clk_hal_clock_output_teardown(clock_out_channel_t channel_id); #ifdef __cplusplus } diff --git a/components/soc/esp32/include/soc/Kconfig.soc_caps.in b/components/soc/esp32/include/soc/Kconfig.soc_caps.in index 74c4785aa7..3723989bc7 100644 --- a/components/soc/esp32/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32/include/soc/Kconfig.soc_caps.in @@ -351,6 +351,10 @@ config SOC_GPIO_CLOCKOUT_BY_IO_MUX bool default y +config SOC_GPIO_CLOCKOUT_CHANNEL_NUM + int + default 3 + config SOC_I2C_NUM int default 2 diff --git a/components/soc/esp32/include/soc/soc_caps.h b/components/soc/esp32/include/soc/soc_caps.h index 75f7c65f86..b1c18246f4 100644 --- a/components/soc/esp32/include/soc/soc_caps.h +++ b/components/soc/esp32/include/soc/soc_caps.h @@ -190,6 +190,7 @@ // The Clock Out signal is binding to the pin's IO_MUX function #define SOC_GPIO_CLOCKOUT_BY_IO_MUX (1) +#define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3) /*-------------------------- I2C CAPS ----------------------------------------*/ // ESP32 has 2 I2C diff --git a/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in index 8070cc1caa..285d91d292 100644 --- a/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in @@ -315,6 +315,10 @@ config SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX bool default y +config SOC_GPIO_CLOCKOUT_CHANNEL_NUM + int + default 3 + config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM int default 8 diff --git a/components/soc/esp32c2/include/soc/soc_caps.h b/components/soc/esp32c2/include/soc/soc_caps.h index fbc241ce76..46e90f108b 100644 --- a/components/soc/esp32c2/include/soc/soc_caps.h +++ b/components/soc/esp32c2/include/soc/soc_caps.h @@ -140,6 +140,7 @@ // The Clock Out signal is route to the pin by GPIO matrix #define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX (1) +#define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3) /*-------------------------- Dedicated GPIO CAPS -----------------------------*/ #define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */ diff --git a/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in index 114b541887..80a7732c89 100644 --- a/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in @@ -407,6 +407,10 @@ config SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX bool default y +config SOC_GPIO_CLOCKOUT_CHANNEL_NUM + int + default 3 + config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM int default 8 diff --git a/components/soc/esp32c3/include/soc/soc_caps.h b/components/soc/esp32c3/include/soc/soc_caps.h index 721fa33383..de6c54a6ba 100644 --- a/components/soc/esp32c3/include/soc/soc_caps.h +++ b/components/soc/esp32c3/include/soc/soc_caps.h @@ -178,6 +178,7 @@ // The Clock Out signal is route to the pin by GPIO matrix #define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX (1) +#define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3) /*-------------------------- Dedicated GPIO CAPS -----------------------------*/ #define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */ diff --git a/components/soc/esp32c5/beta3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/beta3/include/soc/Kconfig.soc_caps.in index 83d68c6dae..ec09df500b 100644 --- a/components/soc/esp32c5/beta3/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c5/beta3/include/soc/Kconfig.soc_caps.in @@ -287,6 +287,10 @@ config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP bool default y +config SOC_GPIO_CLOCKOUT_CHANNEL_NUM + int + default 3 + config SOC_RTCIO_PIN_COUNT int default 0 diff --git a/components/soc/esp32c5/beta3/include/soc/soc_caps.h b/components/soc/esp32c5/beta3/include/soc/soc_caps.h index 0f5f9f6613..74df08b4f3 100644 --- a/components/soc/esp32c5/beta3/include/soc/soc_caps.h +++ b/components/soc/esp32c5/beta3/include/soc/soc_caps.h @@ -220,6 +220,7 @@ // The Clock Out signal is route to the pin by GPIO matrix // #define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX (1) +#define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3) /*-------------------------- RTCIO CAPS --------------------------------------*/ #define SOC_RTCIO_PIN_COUNT 0UL diff --git a/components/soc/esp32c5/mp/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/mp/include/soc/Kconfig.soc_caps.in index 036953edfa..347785282f 100644 --- a/components/soc/esp32c5/mp/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c5/mp/include/soc/Kconfig.soc_caps.in @@ -127,6 +127,10 @@ config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP bool default y +config SOC_GPIO_CLOCKOUT_CHANNEL_NUM + int + default 3 + config SOC_RTCIO_PIN_COUNT int default 0 diff --git a/components/soc/esp32c5/mp/include/soc/soc_caps.h b/components/soc/esp32c5/mp/include/soc/soc_caps.h index 74d6743bf5..e63311e1e9 100644 --- a/components/soc/esp32c5/mp/include/soc/soc_caps.h +++ b/components/soc/esp32c5/mp/include/soc/soc_caps.h @@ -210,6 +210,7 @@ // The Clock Out signal is route to the pin by GPIO matrix // #define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX (1) +#define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3) /*-------------------------- RTCIO CAPS --------------------------------------*/ #define SOC_RTCIO_PIN_COUNT 0UL diff --git a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in index 3c1dd57518..986ac496d5 100644 --- a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in @@ -523,6 +523,10 @@ config SOC_CLOCKOUT_HAS_SOURCE_GATE bool default y +config SOC_GPIO_CLOCKOUT_CHANNEL_NUM + int + default 3 + config SOC_RTCIO_PIN_COUNT int default 8 diff --git a/components/soc/esp32c6/include/soc/soc_caps.h b/components/soc/esp32c6/include/soc/soc_caps.h index 1d5380c8ff..07deaadfa0 100644 --- a/components/soc/esp32c6/include/soc/soc_caps.h +++ b/components/soc/esp32c6/include/soc/soc_caps.h @@ -215,7 +215,8 @@ // The Clock Out signal is route to the pin by GPIO matrix #define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX (1) -#define SOC_CLOCKOUT_HAS_SOURCE_GATE (1) +#define SOC_CLOCKOUT_HAS_SOURCE_GATE (1) +#define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3) /*-------------------------- RTCIO CAPS --------------------------------------*/ #define SOC_RTCIO_PIN_COUNT 8 diff --git a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in index 6b87a8e502..2fd7ccca92 100644 --- a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in @@ -203,6 +203,10 @@ config SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX bool default y +config SOC_GPIO_CLOCKOUT_CHANNEL_NUM + int + default 3 + config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM int default 8 diff --git a/components/soc/esp32c61/include/soc/soc_caps.h b/components/soc/esp32c61/include/soc/soc_caps.h index c122828598..b50060d940 100644 --- a/components/soc/esp32c61/include/soc/soc_caps.h +++ b/components/soc/esp32c61/include/soc/soc_caps.h @@ -214,6 +214,7 @@ // The Clock Out signal is route to the pin by GPIO matrix #define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX (1) +#define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3) /*-------------------------- RTCIO CAPS --------------------------------------*/ //TODO: [ESP32C61] IDF-9317 diff --git a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in index ffccb5477e..d9eec8f6fd 100644 --- a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in @@ -523,6 +523,10 @@ config SOC_CLOCKOUT_HAS_SOURCE_GATE bool default y +config SOC_GPIO_CLOCKOUT_CHANNEL_NUM + int + default 3 + config SOC_RTCIO_PIN_COUNT int default 8 diff --git a/components/soc/esp32h2/include/soc/soc_caps.h b/components/soc/esp32h2/include/soc/soc_caps.h index 7940868d6c..051657fa7b 100644 --- a/components/soc/esp32h2/include/soc/soc_caps.h +++ b/components/soc/esp32h2/include/soc/soc_caps.h @@ -216,7 +216,8 @@ // The Clock Out signal is route to the pin by GPIO matrix #define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX (1) -#define SOC_CLOCKOUT_HAS_SOURCE_GATE (1) +#define SOC_CLOCKOUT_HAS_SOURCE_GATE (1) +#define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3) /*-------------------------- RTCIO CAPS --------------------------------------*/ /* No dedicated LP_IOMUX subsystem on ESP32-H2. LP functions are still supported diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in index 26b48d5dae..580ca7af45 100644 --- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in @@ -555,6 +555,14 @@ config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK hex default 0x007FFFFFFFFF0000 +config SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX + bool + default y + +config SOC_GPIO_CLOCKOUT_CHANNEL_NUM + int + default 2 + config SOC_GPIO_SUPPORT_FORCE_HOLD bool default y diff --git a/components/soc/esp32p4/include/soc/clk_tree_defs.h b/components/soc/esp32p4/include/soc/clk_tree_defs.h index 374efc01cc..5626e7f2b0 100644 --- a/components/soc/esp32p4/include/soc/clk_tree_defs.h +++ b/components/soc/esp32p4/include/soc/clk_tree_defs.h @@ -672,6 +672,27 @@ typedef enum { TEMPERATURE_SENSOR_CLK_SRC_DEFAULT = SOC_MOD_CLK_LP_PERI, /*!< Select LP_PERI as the default choice */ } soc_periph_temperature_sensor_clk_src_t; +//////////////////////////////////////////////CLOCK OUTPUT/////////////////////////////////////////////////////////// +typedef enum { + CLKOUT_SIG_MPLL = 0, /*!< MPLL is from 40MHz XTAL oscillator frequency multipliers */ + CLKOUT_SIG_SPLL = 1, /*!< SPLL is from 40MHz XTAL oscillator frequency multipliers, it has a "fixed" frequency of 480MHz */ + CLKOUT_SIG_CPLL = 2, /*!< CPLL_CLK is the output of 40MHz crystal oscillator frequency multiplier, can be 320/360/400MHz */ + CLKOUT_SIG_XTAL = 3, /*!< External 40MHz crystal */ + CLKOUT_SIG_RC_FAST = 4, /*!< Internal 17.5MHz RC oscillator */ + CLKOUT_SIG_RC_SLOW = 5, /*!< Internal 136kHz RC oscillator */ + CLKOUT_SIG_RC_32K = 6, /*!< Internal 32kHz RC oscillator */ + CLKOUT_SIG_XTAL32K = 7, /*!< External 32kHz crystal clock */ + CLKOUT_SIG_I2S0 = 16, /*!< I2S0 clock, depends on the i2s driver configuration */ + CLKOUT_SIG_I2S1 = 17, /*!< I2S1 clock, depends on the i2s driver configuration */ + CLKOUT_SIG_I2S2 = 18, /*!< I2S2 clock, depends on the i2s driver configuration */ + CLKOUT_SIG_CPU = 26, /*!< CPU clock */ + CLKOUT_SIG_MEM = 27, /*!< MEM clock */ + CLKOUT_SIG_SYS = 28, /*!< SYS clock */ + CLKOUT_SIG_APB = 29, /*!< APB clock */ + CLKOUT_SIG_PLL_F80M = 105, /*!< From PLL, usually be 80MHz */ + CLKOUT_SIG_INVALID = 0xFF, +} soc_clkout_sig_id_t; + #ifdef __cplusplus } #endif diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h index 61ca9e53c5..594c83481b 100644 --- a/components/soc/esp32p4/include/soc/soc_caps.h +++ b/components/soc/esp32p4/include/soc/soc_caps.h @@ -231,6 +231,10 @@ // digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_16~GPIO_NUM_54) #define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x007FFFFFFFFF0000ULL +// The Clock Out signal is route to the pin by GPIO matrix +#define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX (1) +#define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (2) + // Support to force hold all IOs #define SOC_GPIO_SUPPORT_FORCE_HOLD (1) // Support to hold a single digital I/O when the digital domain is powered off diff --git a/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in index 17f43581b2..dc17829d64 100644 --- a/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in @@ -399,6 +399,10 @@ config SOC_GPIO_CLOCKOUT_BY_IO_MUX bool default y +config SOC_GPIO_CLOCKOUT_CHANNEL_NUM + int + default 3 + config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM int default 8 diff --git a/components/soc/esp32s2/include/soc/soc_caps.h b/components/soc/esp32s2/include/soc/soc_caps.h index dc1c29858f..a3405cddbc 100644 --- a/components/soc/esp32s2/include/soc/soc_caps.h +++ b/components/soc/esp32s2/include/soc/soc_caps.h @@ -179,6 +179,8 @@ // The Clock Out signal is binding to the pin's IO_MUX function #define SOC_GPIO_CLOCKOUT_BY_IO_MUX (1) +#define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3) + /*-------------------------- Dedicated GPIO CAPS ---------------------------------------*/ #define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */ diff --git a/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in index 930d5ce20f..c736f41619 100644 --- a/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in @@ -475,6 +475,10 @@ config SOC_GPIO_CLOCKOUT_BY_IO_MUX bool default y +config SOC_GPIO_CLOCKOUT_CHANNEL_NUM + int + default 3 + config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM int default 8 diff --git a/components/soc/esp32s3/include/soc/soc_caps.h b/components/soc/esp32s3/include/soc/soc_caps.h index 8816802a52..536560d2d1 100644 --- a/components/soc/esp32s3/include/soc/soc_caps.h +++ b/components/soc/esp32s3/include/soc/soc_caps.h @@ -187,6 +187,7 @@ // The Clock Out signal is binding to the pin's IO_MUX function #define SOC_GPIO_CLOCKOUT_BY_IO_MUX (1) +#define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3) /*-------------------------- Dedicated GPIO CAPS -----------------------------*/ #define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */