From 2e83fa1c69e0a1dfa8bb4c706c3fac1873e84e53 Mon Sep 17 00:00:00 2001 From: Cao Sen Miao Date: Thu, 4 Jan 2024 10:24:17 +0800 Subject: [PATCH] refactor(spi_flash): Use new spi_flash register sturct and deperecate the old one --- .../bootloader_flash/src/bootloader_flash.c | 17 +- .../src/bootloader_flash_config_esp32p4.c | 8 +- .../esp_rom/include/esp32p4/rom/spi_flash.h | 47 +- .../hal/esp32/include/hal/spi_flash_ll.h | 22 +- .../hal/esp32c2/include/hal/spi_flash_ll.h | 1 + .../hal/esp32c2/include/hal/spimem_flash_ll.h | 22 +- .../hal/esp32c3/include/hal/spi_flash_ll.h | 1 + .../hal/esp32c3/include/hal/spimem_flash_ll.h | 22 +- .../hal/esp32c5/include/hal/spi_flash_ll.h | 1 + .../hal/esp32c5/include/hal/spimem_flash_ll.h | 22 +- .../hal/esp32c6/include/hal/spi_flash_ll.h | 1 + .../hal/esp32c6/include/hal/spimem_flash_ll.h | 22 +- .../hal/esp32h2/include/hal/spi_flash_ll.h | 1 + .../hal/esp32h2/include/hal/spimem_flash_ll.h | 22 +- .../include/hal/spi_flash_encrypted_ll.h | 22 +- .../hal/esp32p4/include/hal/spi_flash_ll.h | 1 + .../hal/esp32p4/include/hal/spimem_flash_ll.h | 43 +- .../hal/esp32s2/include/hal/spi_flash_ll.h | 1 + .../hal/esp32s2/include/hal/spimem_flash_ll.h | 21 +- .../hal/esp32s3/include/hal/spi_flash_ll.h | 2 + .../hal/esp32s3/include/hal/spimem_flash_ll.h | 22 +- .../soc/esp32p4/include/soc/spi1_mem_c_reg.h | 2 +- .../esp32p4/include/soc/spi1_mem_c_struct.h | 241 +- .../esp32p4/include/soc/spi_mem_c_struct.h | 746 ++-- .../soc/esp32p4/include/soc/spi_mem_reg.h | 3445 +---------------- .../soc/esp32p4/include/soc/spi_mem_struct.h | 1134 +----- components/soc/include/soc/spi_periph.h | 2 +- components/spi_flash/spi_flash_wrap.c | 13 +- 28 files changed, 663 insertions(+), 5241 deletions(-) diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash.c index 3dbaa03f38..26c11a4dd6 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -13,16 +13,21 @@ #include "hal/efuse_ll.h" #include "hal/efuse_hal.h" +#include "hal/spi_flash_ll.h" +#include "rom/spi_flash.h" #if CONFIG_IDF_TARGET_ESP32 # include "soc/spi_struct.h" # include "soc/spi_reg.h" /* SPI flash controller */ # define SPIFLASH SPI1 +# define SPI0 SPI0 #else +# include "hal/spimem_flash_ll.h" # include "soc/spi_mem_struct.h" # include "soc/spi_mem_reg.h" /* SPI flash controller */ # define SPIFLASH SPIMEM1 +# define SPI0 SPIMEM0 #endif // This dependency will be removed in the future. IDF-5025 @@ -581,10 +586,12 @@ IRAM_ATTR uint32_t bootloader_flash_execute_command_common( uint32_t old_user_reg = SPIFLASH.user.val; uint32_t old_user1_reg = SPIFLASH.user1.val; uint32_t old_user2_reg = SPIFLASH.user2.val; + // Clear ctrl regs. + SPIFLASH.ctrl.val = 0; #if CONFIG_IDF_TARGET_ESP32 - SPIFLASH.ctrl.val = SPI_WP_REG_M; // keep WP high while idle, otherwise leave DIO mode + spi_flash_ll_set_wp_level(&SPIFLASH, true); #else - SPIFLASH.ctrl.val = SPI_MEM_WP_REG_M; // keep WP high while idle, otherwise leave DIO mode + spimem_flash_ll_set_wp_level(&SPIFLASH, true); #endif //command phase SPIFLASH.user.usr_command = 1; @@ -634,6 +641,7 @@ IRAM_ATTR uint32_t bootloader_flash_execute_command_common( //set unused bits to 0 ret &= ~(UINT32_MAX << miso_len); } + esp_rom_printf("val is %x\n", SPIFLASH.ctrl.val); return ret; } @@ -832,8 +840,8 @@ bool IRAM_ATTR bootloader_flash_is_octal_mode_enabled(void) esp_rom_spiflash_read_mode_t bootloader_flash_get_spi_mode(void) { esp_rom_spiflash_read_mode_t spi_mode = ESP_ROM_SPIFLASH_FASTRD_MODE; + uint32_t spi_ctrl = spi_flash_ll_get_ctrl_val(&SPI0); #if CONFIG_IDF_TARGET_ESP32 - uint32_t spi_ctrl = REG_READ(SPI_CTRL_REG(0)); if (spi_ctrl & SPI_FREAD_QIO) { spi_mode = ESP_ROM_SPIFLASH_QIO_MODE; } else if (spi_ctrl & SPI_FREAD_QUAD) { @@ -848,7 +856,6 @@ esp_rom_spiflash_read_mode_t bootloader_flash_get_spi_mode(void) spi_mode = ESP_ROM_SPIFLASH_SLOWRD_MODE; } #else - uint32_t spi_ctrl = REG_READ(SPI_MEM_CTRL_REG(0)); if (spi_ctrl & SPI_MEM_FREAD_QIO) { spi_mode = ESP_ROM_SPIFLASH_QIO_MODE; } else if (spi_ctrl & SPI_MEM_FREAD_QUAD) { diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c index 89894d5edd..5e9433ca3f 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -30,9 +30,9 @@ void bootloader_flash_update_id() void IRAM_ATTR bootloader_flash_cs_timing_config() { - SET_PERI_REG_MASK(SPI_MEM_USER_REG(0), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M); - SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_HOLD_TIME_V, 0, SPI_MEM_CS_HOLD_TIME_S); - SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_SETUP_TIME_V, 0, SPI_MEM_CS_SETUP_TIME_S); + SET_PERI_REG_MASK(SPI_MEM_C_USER_REG, SPI_MEM_C_CS_HOLD_M | SPI_MEM_C_CS_SETUP_M); + SET_PERI_REG_BITS(SPI_MEM_C_CTRL2_REG, SPI_MEM_C_CS_HOLD_TIME_V, 0, SPI_MEM_C_CS_HOLD_TIME_S); + SET_PERI_REG_BITS(SPI_MEM_C_CTRL2_REG, SPI_MEM_C_CS_SETUP_TIME_V, 0, SPI_MEM_C_CS_SETUP_TIME_S); } void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr) diff --git a/components/esp_rom/include/esp32p4/rom/spi_flash.h b/components/esp_rom/include/esp32p4/rom/spi_flash.h index 2c22307971..761fc46bc7 100644 --- a/components/esp_rom/include/esp32p4/rom/spi_flash.h +++ b/components/esp_rom/include/esp32p4/rom/spi_flash.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -15,23 +15,34 @@ extern "C" { #endif -#define PERIPHS_SPI_FLASH_CMD SPI_MEM_CMD_REG(1) -#define PERIPHS_SPI_FLASH_ADDR SPI_MEM_ADDR_REG(1) -#define PERIPHS_SPI_FLASH_CTRL SPI_MEM_CTRL_REG(1) -#define PERIPHS_SPI_FLASH_CTRL1 SPI_MEM_CTRL1_REG(1) -#define PERIPHS_SPI_FLASH_STATUS SPI_MEM_RD_STATUS_REG(1) -#define PERIPHS_SPI_FLASH_USRREG SPI_MEM_USER_REG(1) -#define PERIPHS_SPI_FLASH_USRREG1 SPI_MEM_USER1_REG(1) -#define PERIPHS_SPI_FLASH_USRREG2 SPI_MEM_USER2_REG(1) -#define PERIPHS_SPI_FLASH_C0 SPI_MEM_W0_REG(1) -#define PERIPHS_SPI_FLASH_C1 SPI_MEM_W1_REG(1) -#define PERIPHS_SPI_FLASH_C2 SPI_MEM_W2_REG(1) -#define PERIPHS_SPI_FLASH_C3 SPI_MEM_W3_REG(1) -#define PERIPHS_SPI_FLASH_C4 SPI_MEM_W4_REG(1) -#define PERIPHS_SPI_FLASH_C5 SPI_MEM_W5_REG(1) -#define PERIPHS_SPI_FLASH_C6 SPI_MEM_W6_REG(1) -#define PERIPHS_SPI_FLASH_C7 SPI_MEM_W7_REG(1) -#define PERIPHS_SPI_FLASH_TX_CRC SPI_MEM_TX_CRC_REG(1) +#define PERIPHS_SPI_FLASH_CMD SPI1_MEM_C_CMD_REG +#define PERIPHS_SPI_FLASH_ADDR SPI1_MEM_C_ADDR_REG +#define PERIPHS_SPI_FLASH_CTRL SPI1_MEM_C_CTRL_REG +#define PERIPHS_SPI_FLASH_CTRL1 SPI1_MEM_C_CTRL1_REG +#define PERIPHS_SPI_FLASH_STATUS SPI1_MEM_C_RD_STATUS_REG +#define PERIPHS_SPI_FLASH_USRREG SPI1_MEM_C_USER_REG +#define PERIPHS_SPI_FLASH_USRREG1 SPI1_MEM_C_USER1_REG +#define PERIPHS_SPI_FLASH_USRREG2 SPI1_MEM_C_USER2_REG +#define PERIPHS_SPI_FLASH_C0 SPI1_MEM_C_W0_REG +#define PERIPHS_SPI_FLASH_C1 SPI1_MEM_C_W1_REG +#define PERIPHS_SPI_FLASH_C2 SPI1_MEM_C_W2_REG +#define PERIPHS_SPI_FLASH_C3 SPI1_MEM_C_W3_REG +#define PERIPHS_SPI_FLASH_C4 SPI1_MEM_C_W4_REG +#define PERIPHS_SPI_FLASH_C5 SPI1_MEM_C_W5_REG +#define PERIPHS_SPI_FLASH_C6 SPI1_MEM_C_W6_REG +#define PERIPHS_SPI_FLASH_C7 SPI1_MEM_C_W7_REG +#define PERIPHS_SPI_FLASH_TX_CRC SPI1_MEM_C_TX_CRC_REG + +#define SPI_MEM_FREAD_QIO SPI1_MEM_C_FREAD_QIO +#define SPI_MEM_FREAD_DIO SPI1_MEM_C_FREAD_DIO +#define SPI_MEM_FREAD_QUAD SPI1_MEM_C_FREAD_QUAD +#define SPI_MEM_FREAD_DUAL SPI1_MEM_C_FREAD_DUAL +#define SPI_MEM_FWRITE_QIO SPI1_MEM_C_FWRITE_QIO +#define SPI_MEM_FWRITE_DIO SPI1_MEM_C_FWRITE_DIO +#define SPI_MEM_FWRITE_QUAD SPI1_MEM_C_FWRITE_QUAD +#define SPI_MEM_FWRITE_DUAL SPI1_MEM_C_FWRITE_DUAL +#define SPI_MEM_FASTRD_MODE SPI1_MEM_C_FASTRD_MODE + #define SPI0_R_QIO_DUMMY_CYCLELEN 5 #define SPI0_R_QIO_ADDR_BITSLEN 23 diff --git a/components/hal/esp32/include/hal/spi_flash_ll.h b/components/hal/esp32/include/hal/spi_flash_ll.h index c819081895..3a6cf9522d 100644 --- a/components/hal/esp32/include/hal/spi_flash_ll.h +++ b/components/hal/esp32/include/hal/spi_flash_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -447,6 +447,26 @@ static inline void spi_flash_ll_set_extra_address(spi_dev_t *dev, uint32_t extra // Not supported on ESP32. } +/** + * @brief Write protect signal output when SPI is idle + + * @param level 1: 1: output high, 0: output low + */ +static inline void spi_flash_ll_set_wp_level(spi_dev_t *dev, bool level) +{ + dev->ctrl.wp = level; +} + +/** + * @brief Get the ctrl value of mspi + * + * @return uint32_t The value of ctrl register + */ +static inline uint32_t spi_flash_ll_get_ctrl_val(spi_dev_t *dev) +{ + return dev->ctrl.val; +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32c2/include/hal/spi_flash_ll.h b/components/hal/esp32c2/include/hal/spi_flash_ll.h index 0a617a30aa..611c16f5dc 100644 --- a/components/hal/esp32c2/include/hal/spi_flash_ll.h +++ b/components/hal/esp32c2/include/hal/spi_flash_ll.h @@ -91,6 +91,7 @@ typedef union { #define spi_flash_ll_set_dummy_out(dev, en, lev) spimem_flash_ll_set_dummy_out((spi_mem_dev_t*)dev, en, lev) #define spi_flash_ll_set_hold(dev, hold_n) spimem_flash_ll_set_hold((spi_mem_dev_t*)dev, hold_n) #define spi_flash_ll_set_cs_setup(dev, cs_setup_time) spimem_flash_ll_set_cs_setup((spi_mem_dev_t*)dev, cs_setup_time) +#define spi_flash_ll_get_ctrl_val(dev) spimem_flash_ll_get_ctrl_val((spi_mem_dev_t*)dev) #endif diff --git a/components/hal/esp32c2/include/hal/spimem_flash_ll.h b/components/hal/esp32c2/include/hal/spimem_flash_ll.h index 23bddd1ba2..de92fc45cc 100644 --- a/components/hal/esp32c2/include/hal/spimem_flash_ll.h +++ b/components/hal/esp32c2/include/hal/spimem_flash_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -647,6 +647,26 @@ static inline uint32_t spimem_flash_ll_calculate_clock_reg(uint8_t clkdiv) return div_parameter; } +/** + * @brief Write protect signal output when SPI is idle + + * @param level 1: 1: output high, 0: output low + */ +static inline void spimem_flash_ll_set_wp_level(spi_mem_dev_t *dev, bool level) +{ + dev->ctrl.wp = level; +} + +/** + * @brief Get the ctrl value of mspi + * + * @return uint32_t The value of ctrl register + */ +static inline uint32_t spimem_flash_ll_get_ctrl_val(spi_mem_dev_t *dev) +{ + return dev->ctrl.val; +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32c3/include/hal/spi_flash_ll.h b/components/hal/esp32c3/include/hal/spi_flash_ll.h index 0a617a30aa..611c16f5dc 100644 --- a/components/hal/esp32c3/include/hal/spi_flash_ll.h +++ b/components/hal/esp32c3/include/hal/spi_flash_ll.h @@ -91,6 +91,7 @@ typedef union { #define spi_flash_ll_set_dummy_out(dev, en, lev) spimem_flash_ll_set_dummy_out((spi_mem_dev_t*)dev, en, lev) #define spi_flash_ll_set_hold(dev, hold_n) spimem_flash_ll_set_hold((spi_mem_dev_t*)dev, hold_n) #define spi_flash_ll_set_cs_setup(dev, cs_setup_time) spimem_flash_ll_set_cs_setup((spi_mem_dev_t*)dev, cs_setup_time) +#define spi_flash_ll_get_ctrl_val(dev) spimem_flash_ll_get_ctrl_val((spi_mem_dev_t*)dev) #endif diff --git a/components/hal/esp32c3/include/hal/spimem_flash_ll.h b/components/hal/esp32c3/include/hal/spimem_flash_ll.h index 73df69e3e1..873142de39 100644 --- a/components/hal/esp32c3/include/hal/spimem_flash_ll.h +++ b/components/hal/esp32c3/include/hal/spimem_flash_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -662,6 +662,26 @@ static inline uint32_t spimem_flash_ll_calculate_clock_reg(uint8_t clkdiv) return div_parameter; } +/** + * @brief Write protect signal output when SPI is idle + + * @param level 1: 1: output high, 0: output low + */ +static inline void spimem_flash_ll_set_wp_level(spi_mem_dev_t *dev, bool level) +{ + dev->ctrl.wp = level; +} + +/** + * @brief Get the ctrl value of mspi + * + * @return uint32_t The value of ctrl register + */ +static inline uint32_t spimem_flash_ll_get_ctrl_val(spi_mem_dev_t *dev) +{ + return dev->ctrl.val; +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32c5/include/hal/spi_flash_ll.h b/components/hal/esp32c5/include/hal/spi_flash_ll.h index b8dde2bf34..b6d332d5d5 100644 --- a/components/hal/esp32c5/include/hal/spi_flash_ll.h +++ b/components/hal/esp32c5/include/hal/spi_flash_ll.h @@ -94,6 +94,7 @@ typedef union { #define spi_flash_ll_set_hold(dev, hold_n) spimem_flash_ll_set_hold((spi_mem_dev_t*)dev, hold_n) #define spi_flash_ll_set_cs_setup(dev, cs_setup_time) spimem_flash_ll_set_cs_setup((spi_mem_dev_t*)dev, cs_setup_time) #define spi_flash_ll_set_extra_address(dev, extra_addr) spimem_flash_ll_set_extra_address((spi_mem_dev_t*)dev, extra_addr) +#define spi_flash_ll_get_ctrl_val(dev) spimem_flash_ll_get_ctrl_val((spi_mem_dev_t*)dev) #endif diff --git a/components/hal/esp32c5/include/hal/spimem_flash_ll.h b/components/hal/esp32c5/include/hal/spimem_flash_ll.h index f1195261a7..63d02eca74 100644 --- a/components/hal/esp32c5/include/hal/spimem_flash_ll.h +++ b/components/hal/esp32c5/include/hal/spimem_flash_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -651,6 +651,26 @@ static inline uint32_t spimem_flash_ll_calculate_clock_reg(uint8_t clkdiv) return div_parameter; } +/** + * @brief Write protect signal output when SPI is idle + + * @param level 1: 1: output high, 0: output low + */ +static inline void spimem_flash_ll_set_wp_level(spi_mem_dev_t *dev, bool level) +{ + dev->ctrl.wp = level; +} + +/** + * @brief Get the ctrl value of mspi + * + * @return uint32_t The value of ctrl register + */ +static inline uint32_t spimem_flash_ll_get_ctrl_val(spi_mem_dev_t *dev) +{ + return dev->ctrl.val; +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32c6/include/hal/spi_flash_ll.h b/components/hal/esp32c6/include/hal/spi_flash_ll.h index 77f495447b..cb328bffaf 100644 --- a/components/hal/esp32c6/include/hal/spi_flash_ll.h +++ b/components/hal/esp32c6/include/hal/spi_flash_ll.h @@ -92,6 +92,7 @@ typedef union { #define spi_flash_ll_set_hold(dev, hold_n) spimem_flash_ll_set_hold((spi_mem_dev_t*)dev, hold_n) #define spi_flash_ll_set_cs_setup(dev, cs_setup_time) spimem_flash_ll_set_cs_setup((spi_mem_dev_t*)dev, cs_setup_time) #define spi_flash_ll_set_extra_address(dev, extra_addr) spimem_flash_ll_set_extra_address((spi_mem_dev_t*)dev, extra_addr) +#define spi_flash_ll_get_ctrl_val(dev) spimem_flash_ll_get_ctrl_val((spi_mem_dev_t*)dev) #endif diff --git a/components/hal/esp32c6/include/hal/spimem_flash_ll.h b/components/hal/esp32c6/include/hal/spimem_flash_ll.h index b80187f2e0..dae851b685 100644 --- a/components/hal/esp32c6/include/hal/spimem_flash_ll.h +++ b/components/hal/esp32c6/include/hal/spimem_flash_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -681,6 +681,26 @@ static inline uint32_t spimem_flash_ll_calculate_clock_reg(uint8_t clkdiv) return div_parameter; } +/** + * @brief Write protect signal output when SPI is idle + + * @param level 1: 1: output high, 0: output low + */ +static inline void spimem_flash_ll_set_wp_level(spi_mem_dev_t *dev, bool level) +{ + dev->ctrl.wp = level; +} + +/** + * @brief Get the ctrl value of mspi + * + * @return uint32_t The value of ctrl register + */ +static inline uint32_t spimem_flash_ll_get_ctrl_val(spi_mem_dev_t *dev) +{ + return dev->ctrl.val; +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32h2/include/hal/spi_flash_ll.h b/components/hal/esp32h2/include/hal/spi_flash_ll.h index 2dcdf16187..2af2105a63 100644 --- a/components/hal/esp32h2/include/hal/spi_flash_ll.h +++ b/components/hal/esp32h2/include/hal/spi_flash_ll.h @@ -92,6 +92,7 @@ typedef union { #define spi_flash_ll_set_hold(dev, hold_n) spimem_flash_ll_set_hold((spi_mem_dev_t*)dev, hold_n) #define spi_flash_ll_set_cs_setup(dev, cs_setup_time) spimem_flash_ll_set_cs_setup((spi_mem_dev_t*)dev, cs_setup_time) #define spi_flash_ll_set_extra_address(dev, extra_addr) spimem_flash_ll_set_extra_address((spi_mem_dev_t*)dev, extra_addr) +#define spi_flash_ll_get_ctrl_val(dev) spimem_flash_ll_get_ctrl_val((spi_mem_dev_t*)dev) #endif diff --git a/components/hal/esp32h2/include/hal/spimem_flash_ll.h b/components/hal/esp32h2/include/hal/spimem_flash_ll.h index 76fca20e78..95cee518a8 100644 --- a/components/hal/esp32h2/include/hal/spimem_flash_ll.h +++ b/components/hal/esp32h2/include/hal/spimem_flash_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -683,6 +683,26 @@ static inline uint32_t spimem_flash_ll_calculate_clock_reg(uint8_t clkdiv) return div_parameter; } +/** + * @brief Write protect signal output when SPI is idle + + * @param level 1: 1: output high, 0: output low + */ +static inline void spimem_flash_ll_set_wp_level(spi_mem_dev_t *dev, bool level) +{ + dev->ctrl.wp = level; +} + +/** + * @brief Get the ctrl value of mspi + * + * @return uint32_t The value of ctrl register + */ +static inline uint32_t spimem_flash_ll_get_ctrl_val(spi_mem_dev_t *dev) +{ + return dev->ctrl.val; +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32p4/include/hal/spi_flash_encrypted_ll.h b/components/hal/esp32p4/include/hal/spi_flash_encrypted_ll.h index fbdb899098..9c3304832b 100644 --- a/components/hal/esp32p4/include/hal/spi_flash_encrypted_ll.h +++ b/components/hal/esp32p4/include/hal/spi_flash_encrypted_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -15,7 +15,7 @@ #include #include #include "soc/hp_system_reg.h" -#include "soc/spi_mem_reg.h" +#include "soc/spi_mem_c_reg.h" #include "soc/soc.h" #include "soc/soc_caps.h" #include "hal/assert.h" @@ -61,7 +61,7 @@ static inline void spi_flash_encrypt_ll_type(flash_encrypt_ll_type_t type) { // Our hardware only support flash encryption HAL_ASSERT(type == FLASH_ENCRYPTION_MANU); - REG_SET_FIELD(SPI_MEM_XTS_DESTINATION_REG(0), SPI_MEM_SPI_XTS_DESTINATION, type); + REG_SET_FIELD(SPI_MEM_C_XTS_DESTINATION_REG, SPI_MEM_C_XTS_DESTINATION, type); } /** @@ -72,7 +72,7 @@ static inline void spi_flash_encrypt_ll_type(flash_encrypt_ll_type_t type) static inline void spi_flash_encrypt_ll_buffer_length(uint32_t size) { // Desired block should not be larger than the block size. - REG_SET_FIELD(SPI_MEM_XTS_LINESIZE_REG(0), SPI_MEM_SPI_XTS_LINESIZE, size >> 5); + REG_SET_FIELD(SPI_MEM_C_XTS_LINESIZE_REG, SPI_MEM_C_XTS_LINESIZE, size >> 5); } /** @@ -87,7 +87,7 @@ static inline void spi_flash_encrypt_ll_plaintext_save(uint32_t address, const u { uint32_t plaintext_offs = (address % SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX); HAL_ASSERT(plaintext_offs + size <= SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX); - memcpy((void *)(SPI_MEM_XTS_PLAIN_BASE_REG(0) + plaintext_offs), buffer, size); + memcpy((void *)(SPI_MEM_C_XTS_PLAIN_BASE_REG + plaintext_offs), buffer, size); } /** @@ -97,7 +97,7 @@ static inline void spi_flash_encrypt_ll_plaintext_save(uint32_t address, const u */ static inline void spi_flash_encrypt_ll_address_save(uint32_t flash_addr) { - REG_SET_FIELD(SPI_MEM_XTS_PHYSICAL_ADDRESS_REG(0), SPI_MEM_SPI_XTS_PHYSICAL_ADDRESS, flash_addr); + REG_SET_FIELD(SPI_MEM_C_XTS_PHYSICAL_ADDRESS_REG, SPI_MEM_C_XTS_PHYSICAL_ADDRESS, flash_addr); } /** @@ -105,7 +105,7 @@ static inline void spi_flash_encrypt_ll_address_save(uint32_t flash_addr) */ static inline void spi_flash_encrypt_ll_calculate_start(void) { - REG_SET_FIELD(SPI_MEM_XTS_TRIGGER_REG(0), SPI_MEM_SPI_XTS_TRIGGER, 1); + REG_SET_FIELD(SPI_MEM_C_XTS_TRIGGER_REG, SPI_XTS_TRIGGER, 1); } /** @@ -113,7 +113,7 @@ static inline void spi_flash_encrypt_ll_calculate_start(void) */ static inline void spi_flash_encrypt_ll_calculate_wait_idle(void) { - while(REG_GET_FIELD(SPI_MEM_XTS_STATE_REG(0), SPI_MEM_SPI_XTS_STATE) == 0x1) { + while(REG_GET_FIELD(SPI_MEM_C_XTS_STATE_REG, SPI_MEM_C_XTS_STATE) == 0x1) { } } @@ -122,8 +122,8 @@ static inline void spi_flash_encrypt_ll_calculate_wait_idle(void) */ static inline void spi_flash_encrypt_ll_done(void) { - REG_SET_BIT(SPI_MEM_XTS_RELEASE_REG(0), SPI_MEM_SPI_XTS_RELEASE); - while(REG_GET_FIELD(SPI_MEM_XTS_STATE_REG(0), SPI_MEM_SPI_XTS_STATE) != 0x3) { + REG_SET_BIT(SPI_MEM_C_XTS_RELEASE_REG, SPI_MEM_C_XTS_RELEASE); + while(REG_GET_FIELD(SPI_MEM_C_XTS_STATE_REG, SPI_MEM_C_XTS_STATE) != 0x3) { } } @@ -132,7 +132,7 @@ static inline void spi_flash_encrypt_ll_done(void) */ static inline void spi_flash_encrypt_ll_destroy(void) { - REG_SET_BIT(SPI_MEM_XTS_DESTROY_REG(0), SPI_MEM_SPI_XTS_DESTROY); + REG_SET_BIT(SPI_MEM_C_XTS_DESTROY_REG, SPI_MEM_C_XTS_DESTROY); } /** diff --git a/components/hal/esp32p4/include/hal/spi_flash_ll.h b/components/hal/esp32p4/include/hal/spi_flash_ll.h index 7c50962cb3..444099fead 100644 --- a/components/hal/esp32p4/include/hal/spi_flash_ll.h +++ b/components/hal/esp32p4/include/hal/spi_flash_ll.h @@ -92,6 +92,7 @@ typedef union { #define spi_flash_ll_set_hold(dev, hold_n) spimem_flash_ll_set_hold((spi_mem_dev_t*)dev, hold_n) #define spi_flash_ll_set_cs_setup(dev, cs_setup_time) spimem_flash_ll_set_cs_setup((spi_mem_dev_t*)dev, cs_setup_time) #define spi_flash_ll_set_extra_address(dev, extra_addr) spimem_flash_ll_set_extra_address((spi_mem_dev_t*)dev, extra_addr) +#define spi_flash_ll_get_ctrl_val(dev) spimem_flash_ll_get_ctrl_val((spi_mem_dev_t*)dev) #endif diff --git a/components/hal/esp32p4/include/hal/spimem_flash_ll.h b/components/hal/esp32p4/include/hal/spimem_flash_ll.h index f428edde56..74bd456726 100644 --- a/components/hal/esp32p4/include/hal/spimem_flash_ll.h +++ b/components/hal/esp32p4/include/hal/spimem_flash_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -20,7 +20,8 @@ #include #include "soc/spi_periph.h" -#include "soc/spi_mem_struct.h" +#include "soc/spi1_mem_c_struct.h" +#include "soc/spi1_mem_c_reg.h" #include "hal/assert.h" #include "hal/spi_types.h" #include "hal/spi_flash_types.h" @@ -208,7 +209,7 @@ static inline void spimem_flash_ll_res_check_sus_setup(spi_mem_dev_t *dev, bool */ static inline void spimem_flash_ll_set_read_sus_status(spi_mem_dev_t *dev, uint32_t sus_conf) { - dev->flash_sus_ctrl.frd_sus_2b = 0; + dev->flash_sus_ctrl.fmem_rd_sus_2b = 0; HAL_FORCE_MODIFY_U32_REG_FIELD(dev->flash_sus_ctrl, pesr_end_msk, sus_conf); } @@ -454,8 +455,8 @@ static inline void spimem_flash_ll_set_read_mode(spi_mem_dev_t *dev, esp_flash_i { typeof (dev->ctrl) ctrl; ctrl.val = dev->ctrl.val; - ctrl.val &= ~(SPI_MEM_FREAD_QIO_M | SPI_MEM_FREAD_QUAD_M | SPI_MEM_FREAD_DIO_M | SPI_MEM_FREAD_DUAL_M); - ctrl.val |= SPI_MEM_FASTRD_MODE_M; + ctrl.val &= ~(SPI1_MEM_C_FREAD_QIO_M | SPI1_MEM_C_FREAD_QUAD_M | SPI1_MEM_C_FREAD_DIO_M | SPI1_MEM_C_FREAD_DUAL_M); + ctrl.val |= SPI1_MEM_C_FASTRD_MODE_M; switch (read_mode) { case SPI_FLASH_FASTRD: //the default option @@ -565,7 +566,7 @@ static inline void spimem_flash_ll_set_addr_bitlen(spi_mem_dev_t *dev, uint32_t */ static inline void spimem_flash_ll_set_extra_address(spi_mem_dev_t *dev, uint32_t extra_addr) { - dev->cache_fctrl.usr_addr_4byte = 0; + dev->cache_fctrl.cache_usr_addr_4byte = 0; dev->rd_status.wb_mode = extra_addr; } @@ -612,10 +613,7 @@ static inline void spimem_flash_ll_set_dummy(spi_mem_dev_t *dev, uint32_t dummy_ */ static inline void spimem_flash_ll_set_hold(spi_mem_dev_t *dev, uint32_t hold_n) { - if (hold_n > 0) { - dev->ctrl2.cs_hold_time = hold_n - 1; - } - dev->user.cs_hold = hold_n > 0; + // Not supported on esp32p4 } /** @@ -626,10 +624,7 @@ static inline void spimem_flash_ll_set_hold(spi_mem_dev_t *dev, uint32_t hold_n) */ static inline void spimem_flash_ll_set_cs_setup(spi_mem_dev_t *dev, uint32_t cs_setup_time) { - if (cs_setup_time > 0) { - dev->ctrl2.cs_setup_time = cs_setup_time - 1; - } - dev->user.cs_setup = (cs_setup_time > 0 ? 1 : 0); + // Not supported on esp32p4 } /** @@ -664,6 +659,26 @@ static inline uint32_t spimem_flash_ll_calculate_clock_reg(uint8_t clkdiv) return div_parameter; } +/** + * @brief Write protect signal output when SPI is idle + + * @param level 1: 1: output high, 0: output low + */ +static inline void spimem_flash_ll_set_wp_level(spi_mem_dev_t *dev, bool level) +{ + dev->ctrl.wp_reg = level; +} + +/** + * @brief Get the ctrl value of mspi + * + * @return uint32_t The value of ctrl register + */ +static inline uint32_t spimem_flash_ll_get_ctrl_val(spi_mem_dev_t *dev) +{ + return dev->ctrl.val; +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32s2/include/hal/spi_flash_ll.h b/components/hal/esp32s2/include/hal/spi_flash_ll.h index ed4fdf64af..99cdd090df 100644 --- a/components/hal/esp32s2/include/hal/spi_flash_ll.h +++ b/components/hal/esp32s2/include/hal/spi_flash_ll.h @@ -94,6 +94,7 @@ typedef union { #define spi_flash_ll_set_dummy_out(dev, en, lev) spimem_flash_ll_set_dummy_out((spi_mem_dev_t*)dev, en, lev) #define spi_flash_ll_set_hold(dev, hold_n) spimem_flash_ll_set_hold((spi_mem_dev_t*)dev, hold_n) #define spi_flash_ll_set_cs_setup(dev, cs_setup_time) spimem_flash_ll_set_cs_setup((spi_mem_dev_t*)dev, cs_setup_time) +#define spi_flash_ll_get_ctrl_val(dev) spimem_flash_ll_get_ctrl_val((spi_mem_dev_t*)dev) #endif diff --git a/components/hal/esp32s2/include/hal/spimem_flash_ll.h b/components/hal/esp32s2/include/hal/spimem_flash_ll.h index ea0ca5da4c..3b5611146a 100644 --- a/components/hal/esp32s2/include/hal/spimem_flash_ll.h +++ b/components/hal/esp32s2/include/hal/spimem_flash_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -596,6 +596,25 @@ static inline uint32_t spimem_flash_ll_calculate_clock_reg(uint8_t clkdiv) return div_parameter; } +/** + * @brief Write protect signal output when SPI is idle + + * @param level 1: 1: output high, 0: output low + */ +static inline void spimem_flash_ll_set_wp_level(spi_mem_dev_t *dev, bool level) +{ + dev->ctrl.wp = level; +} + +/** + * @brief Get the ctrl value of mspi + * + * @return uint32_t The value of ctrl register + */ +static inline uint32_t spimem_flash_ll_get_ctrl_val(spi_mem_dev_t *dev) +{ + return dev->ctrl.val; +} #ifdef __cplusplus } diff --git a/components/hal/esp32s3/include/hal/spi_flash_ll.h b/components/hal/esp32s3/include/hal/spi_flash_ll.h index a77f031b61..5ca1349ad1 100644 --- a/components/hal/esp32s3/include/hal/spi_flash_ll.h +++ b/components/hal/esp32s3/include/hal/spi_flash_ll.h @@ -91,6 +91,8 @@ typedef union { #define spi_flash_ll_set_dummy_out(dev, en, lev) spimem_flash_ll_set_dummy_out((spi_mem_dev_t*)dev, en, lev) #define spi_flash_ll_set_hold(dev, hold_n) spimem_flash_ll_set_hold((spi_mem_dev_t*)dev, hold_n) #define spi_flash_ll_set_cs_setup(dev, cs_setup_time) spimem_flash_ll_set_cs_setup((spi_mem_dev_t*)dev, cs_setup_time) +#define spi_flash_ll_get_ctrl_val(dev) spimem_flash_ll_get_ctrl_val((spi_mem_dev_t*)dev) + #endif #ifdef __cplusplus diff --git a/components/hal/esp32s3/include/hal/spimem_flash_ll.h b/components/hal/esp32s3/include/hal/spimem_flash_ll.h index eee9d0851d..9b07256b4d 100644 --- a/components/hal/esp32s3/include/hal/spimem_flash_ll.h +++ b/components/hal/esp32s3/include/hal/spimem_flash_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -683,6 +683,26 @@ static inline uint32_t spimem_flash_ll_calculate_clock_reg(uint8_t clkdiv) return div_parameter; } +/** + * @brief Write protect signal output when SPI is idle + + * @param level 1: 1: output high, 0: output low + */ +static inline void spimem_flash_ll_set_wp_level(spi_mem_dev_t *dev, bool level) +{ + dev->ctrl.wp = level; +} + +/** + * @brief Get the ctrl value of mspi + * + * @return uint32_t The value of ctrl register + */ +static inline uint32_t spimem_flash_ll_get_ctrl_val(spi_mem_dev_t *dev) +{ + return dev->ctrl.val; +} + #ifdef __cplusplus } #endif diff --git a/components/soc/esp32p4/include/soc/spi1_mem_c_reg.h b/components/soc/esp32p4/include/soc/spi1_mem_c_reg.h index 09829c5cdc..e3bfc69214 100644 --- a/components/soc/esp32p4/include/soc/spi1_mem_c_reg.h +++ b/components/soc/esp32p4/include/soc/spi1_mem_c_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/components/soc/esp32p4/include/soc/spi1_mem_c_struct.h b/components/soc/esp32p4/include/soc/spi1_mem_c_struct.h index 3d00246003..b78578c082 100644 --- a/components/soc/esp32p4/include/soc/spi1_mem_c_struct.h +++ b/components/soc/esp32p4/include/soc/spi1_mem_c_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -393,10 +393,10 @@ typedef union { */ typedef union { struct { - /** usr_mosi_dbitlen : R/W; bitpos: [9:0]; default: 0; + /** usr_mosi_bit_len : R/W; bitpos: [9:0]; default: 0; * The length in bits of write-data. The register value shall be (bit_num-1). */ - uint32_t usr_mosi_dbitlen:10; + uint32_t usr_mosi_bit_len:10; uint32_t reserved_10:22; }; uint32_t val; @@ -407,10 +407,10 @@ typedef union { */ typedef union { struct { - /** usr_miso_dbitlen : R/W; bitpos: [9:0]; default: 0; + /** usr_miso_bit_len : R/W; bitpos: [9:0]; default: 0; * The length in bits of read-data. The register value shall be (bit_num-1). */ - uint32_t usr_miso_dbitlen:10; + uint32_t usr_miso_bit_len:10; uint32_t reserved_10:22; }; uint32_t val; @@ -807,217 +807,6 @@ typedef union { uint32_t val; } spi1_mem_c_tx_crc_reg_t; - -/** Group: Memory data buffer register */ -/** Type of w0 register - * SPI1 memory data buffer0 - */ -typedef union { - struct { - /** buf0 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf0:32; - }; - uint32_t val; -} spi1_mem_c_w0_reg_t; - -/** Type of w1 register - * SPI1 memory data buffer1 - */ -typedef union { - struct { - /** buf1 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf1:32; - }; - uint32_t val; -} spi1_mem_c_w1_reg_t; - -/** Type of w2 register - * SPI1 memory data buffer2 - */ -typedef union { - struct { - /** buf2 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf2:32; - }; - uint32_t val; -} spi1_mem_c_w2_reg_t; - -/** Type of w3 register - * SPI1 memory data buffer3 - */ -typedef union { - struct { - /** buf3 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf3:32; - }; - uint32_t val; -} spi1_mem_c_w3_reg_t; - -/** Type of w4 register - * SPI1 memory data buffer4 - */ -typedef union { - struct { - /** buf4 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf4:32; - }; - uint32_t val; -} spi1_mem_c_w4_reg_t; - -/** Type of w5 register - * SPI1 memory data buffer5 - */ -typedef union { - struct { - /** buf5 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf5:32; - }; - uint32_t val; -} spi1_mem_c_w5_reg_t; - -/** Type of w6 register - * SPI1 memory data buffer6 - */ -typedef union { - struct { - /** buf6 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf6:32; - }; - uint32_t val; -} spi1_mem_c_w6_reg_t; - -/** Type of w7 register - * SPI1 memory data buffer7 - */ -typedef union { - struct { - /** buf7 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf7:32; - }; - uint32_t val; -} spi1_mem_c_w7_reg_t; - -/** Type of w8 register - * SPI1 memory data buffer8 - */ -typedef union { - struct { - /** buf8 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf8:32; - }; - uint32_t val; -} spi1_mem_c_w8_reg_t; - -/** Type of w9 register - * SPI1 memory data buffer9 - */ -typedef union { - struct { - /** buf9 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf9:32; - }; - uint32_t val; -} spi1_mem_c_w9_reg_t; - -/** Type of w10 register - * SPI1 memory data buffer10 - */ -typedef union { - struct { - /** buf10 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf10:32; - }; - uint32_t val; -} spi1_mem_c_w10_reg_t; - -/** Type of w11 register - * SPI1 memory data buffer11 - */ -typedef union { - struct { - /** buf11 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf11:32; - }; - uint32_t val; -} spi1_mem_c_w11_reg_t; - -/** Type of w12 register - * SPI1 memory data buffer12 - */ -typedef union { - struct { - /** buf12 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf12:32; - }; - uint32_t val; -} spi1_mem_c_w12_reg_t; - -/** Type of w13 register - * SPI1 memory data buffer13 - */ -typedef union { - struct { - /** buf13 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf13:32; - }; - uint32_t val; -} spi1_mem_c_w13_reg_t; - -/** Type of w14 register - * SPI1 memory data buffer14 - */ -typedef union { - struct { - /** buf14 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf14:32; - }; - uint32_t val; -} spi1_mem_c_w14_reg_t; - -/** Type of w15 register - * SPI1 memory data buffer15 - */ -typedef union { - struct { - /** buf15 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf15:32; - }; - uint32_t val; -} spi1_mem_c_w15_reg_t; - - /** Group: Interrupt registers */ /** Type of int_ena register * SPI1 interrupt enable register @@ -1208,7 +997,7 @@ typedef union { typedef struct spi1_mem_c_dev_s { volatile spi1_mem_c_cmd_reg_t cmd; - volatile spi1_mem_c_addr_reg_t addr; + volatile uint32_t addr; volatile spi1_mem_c_ctrl_reg_t ctrl; volatile spi1_mem_c_ctrl1_reg_t ctrl1; volatile spi1_mem_c_ctrl2_reg_t ctrl2; @@ -1224,22 +1013,7 @@ typedef struct spi1_mem_c_dev_s { volatile spi1_mem_c_tx_crc_reg_t tx_crc; volatile spi1_mem_c_cache_fctrl_reg_t cache_fctrl; uint32_t reserved_040[6]; - volatile spi1_mem_c_w0_reg_t w0; - volatile spi1_mem_c_w1_reg_t w1; - volatile spi1_mem_c_w2_reg_t w2; - volatile spi1_mem_c_w3_reg_t w3; - volatile spi1_mem_c_w4_reg_t w4; - volatile spi1_mem_c_w5_reg_t w5; - volatile spi1_mem_c_w6_reg_t w6; - volatile spi1_mem_c_w7_reg_t w7; - volatile spi1_mem_c_w8_reg_t w8; - volatile spi1_mem_c_w9_reg_t w9; - volatile spi1_mem_c_w10_reg_t w10; - volatile spi1_mem_c_w11_reg_t w11; - volatile spi1_mem_c_w12_reg_t w12; - volatile spi1_mem_c_w13_reg_t w13; - volatile spi1_mem_c_w14_reg_t w14; - volatile spi1_mem_c_w15_reg_t w15; + volatile uint32_t data_buf[16]; volatile spi1_mem_c_flash_waiti_ctrl_reg_t flash_waiti_ctrl; volatile spi1_mem_c_flash_sus_ctrl_reg_t flash_sus_ctrl; volatile spi1_mem_c_flash_sus_cmd_reg_t flash_sus_cmd; @@ -1259,7 +1033,6 @@ typedef struct spi1_mem_c_dev_s { volatile spi1_mem_c_date_reg_t date; } spi1_mem_c_dev_t; - #ifndef __cplusplus _Static_assert(sizeof(spi1_mem_c_dev_t) == 0x400, "Invalid size of spi1_mem_c_dev_t structure"); #endif diff --git a/components/soc/esp32p4/include/soc/spi_mem_c_struct.h b/components/soc/esp32p4/include/soc/spi_mem_c_struct.h index 208d6dde4d..c694be7e0a 100644 --- a/components/soc/esp32p4/include/soc/spi_mem_c_struct.h +++ b/components/soc/esp32p4/include/soc/spi_mem_c_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -11,46 +11,46 @@ extern "C" { #endif /** Group: Status and state control register */ -/** Type of mem_cmd register +/** Type of cmd register * SPI0 FSM status register */ typedef union { struct { - /** mem_mst_st : RO; bitpos: [3:0]; default: 0; + /** mst_st : RO; bitpos: [3:0]; default: 0; * The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT , * 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent * data is stored in SPI0 TX FIFO, 5: SPI0 write data state. */ - uint32_t mem_mst_st:4; - /** mem_slv_st : RO; bitpos: [7:4]; default: 0; + uint32_t mst_st:4; + /** slv_st : RO; bitpos: [7:4]; default: 0; * The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation state, * 2: send command state, 3: send address state, 4: wait state, 5: read data state, * 6:write data state, 7: done state, 8: read data end state. */ - uint32_t mem_slv_st:4; + uint32_t slv_st:4; uint32_t reserved_8:10; - /** mem_usr : HRO; bitpos: [18]; default: 0; + /** usr : HRO; bitpos: [18]; default: 0; * SPI0 USR_CMD start bit, only used when spi_mem_c_C_AXI_REQ_EN is cleared. An operation * will be triggered when the bit is set. The bit will be cleared once the operation * done.1: enable 0: disable. */ - uint32_t mem_usr:1; + uint32_t usr:1; uint32_t reserved_19:13; }; uint32_t val; } spi_mem_c_cmd_reg_t; -/** Type of mem_axi_err_addr register +/** Type of axi_err_addr register * SPI0 AXI request error address. */ typedef union { struct { - /** mem_axi_err_addr : R/SS/WTC; bitpos: [26:0]; default: 0; + /** axi_err_addr : R/SS/WTC; bitpos: [26:0]; default: 0; * This bits show the first AXI write/read invalid error or AXI write flash error * address. It is cleared by when spi_mem_c_C_AXI_WADDR_ERR_INT_CLR, * spi_mem_c_C_AXI_WR_FLASH_ERR_IN_CLR or spi_mem_c_C_AXI_RADDR_ERR_IN_CLR bit is set. */ - uint32_t mem_axi_err_addr:27; + uint32_t axi_err_addr:27; uint32_t reserved_27:5; }; uint32_t val; @@ -58,118 +58,118 @@ typedef union { /** Group: Flash Control and configuration registers */ -/** Type of mem_ctrl register +/** Type of ctrl register * SPI0 control register. */ typedef union { struct { - /** mem_wdummy_dqs_always_out : HRO; bitpos: [0]; default: 0; + /** wdummy_dqs_always_out : HRO; bitpos: [0]; default: 0; * In the dummy phase of an MSPI write data transfer when accesses to flash, the level * of SPI_DQS is output by the MSPI controller. */ - uint32_t mem_wdummy_dqs_always_out:1; - /** mem_wdummy_always_out : R/W; bitpos: [1]; default: 0; + uint32_t wdummy_dqs_always_out:1; + /** wdummy_always_out : R/W; bitpos: [1]; default: 0; * In the dummy phase of an MSPI write data transfer when accesses to flash, the level * of SPI_IO[7:0] is output by the MSPI controller. */ - uint32_t mem_wdummy_always_out:1; - /** mem_fdummy_rin : R/W; bitpos: [2]; default: 1; + uint32_t wdummy_always_out:1; + /** fdummy_rin : R/W; bitpos: [2]; default: 1; * In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] is * output by the MSPI controller in the first half part of dummy phase. It is used to * mask invalid SPI_DQS in the half part of dummy phase. */ - uint32_t mem_fdummy_rin:1; - /** mem_fdummy_wout : R/W; bitpos: [3]; default: 1; + uint32_t fdummy_rin:1; + /** fdummy_wout : R/W; bitpos: [3]; default: 1; * In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is * output by the MSPI controller in the second half part of dummy phase. It is used to * pre-drive flash. */ - uint32_t mem_fdummy_wout:1; - /** mem_fdout_oct : HRO; bitpos: [4]; default: 0; + uint32_t fdummy_wout:1; + /** fdout_oct : HRO; bitpos: [4]; default: 0; * Apply 8 signals during write-data phase 1:enable 0: disable */ - uint32_t mem_fdout_oct:1; - /** mem_fdin_oct : HRO; bitpos: [5]; default: 0; + uint32_t fdout_oct:1; + /** fdin_oct : HRO; bitpos: [5]; default: 0; * Apply 8 signals during read-data phase 1:enable 0: disable */ - uint32_t mem_fdin_oct:1; - /** mem_faddr_oct : HRO; bitpos: [6]; default: 0; + uint32_t fdin_oct:1; + /** faddr_oct : HRO; bitpos: [6]; default: 0; * Apply 8 signals during address phase 1:enable 0: disable */ - uint32_t mem_faddr_oct:1; + uint32_t faddr_oct:1; uint32_t reserved_7:1; - /** mem_fcmd_quad : R/W; bitpos: [8]; default: 0; + /** fcmd_quad : R/W; bitpos: [8]; default: 0; * Apply 4 signals during command phase 1:enable 0: disable */ - uint32_t mem_fcmd_quad:1; - /** mem_fcmd_oct : HRO; bitpos: [9]; default: 0; + uint32_t fcmd_quad:1; + /** fcmd_oct : HRO; bitpos: [9]; default: 0; * Apply 8 signals during command phase 1:enable 0: disable */ - uint32_t mem_fcmd_oct:1; + uint32_t fcmd_oct:1; uint32_t reserved_10:3; - /** mem_fastrd_mode : R/W; bitpos: [13]; default: 1; + /** fastrd_mode : R/W; bitpos: [13]; default: 1; * This bit enable the bits: spi_mem_c_C_FREAD_QIO, spi_mem_c_C_FREAD_DIO, spi_mem_c_C_FREAD_QOUT * and spi_mem_c_C_FREAD_DOUT. 1: enable 0: disable. */ - uint32_t mem_fastrd_mode:1; - /** mem_fread_dual : R/W; bitpos: [14]; default: 0; + uint32_t fastrd_mode:1; + /** fread_dual : R/W; bitpos: [14]; default: 0; * In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. */ - uint32_t mem_fread_dual:1; + uint32_t fread_dual:1; uint32_t reserved_15:3; - /** mem_q_pol : R/W; bitpos: [18]; default: 1; + /** q_pol : R/W; bitpos: [18]; default: 1; * The bit is used to set MISO line polarity, 1: high 0, low */ - uint32_t mem_q_pol:1; - /** mem_d_pol : R/W; bitpos: [19]; default: 1; + uint32_t q_pol:1; + /** d_pol : R/W; bitpos: [19]; default: 1; * The bit is used to set MOSI line polarity, 1: high 0, low */ - uint32_t mem_d_pol:1; - /** mem_fread_quad : R/W; bitpos: [20]; default: 0; + uint32_t d_pol:1; + /** fread_quad : R/W; bitpos: [20]; default: 0; * In the read operations read-data phase apply 4 signals. 1: enable 0: disable. */ - uint32_t mem_fread_quad:1; - /** mem_wp_reg : R/W; bitpos: [21]; default: 1; + uint32_t fread_quad:1; + /** wp_reg : R/W; bitpos: [21]; default: 1; * Write protect signal output when SPI is idle. 1: output high, 0: output low. */ - uint32_t mem_wp_reg:1; + uint32_t wp_reg:1; uint32_t reserved_22:1; - /** mem_fread_dio : R/W; bitpos: [23]; default: 0; + /** fread_dio : R/W; bitpos: [23]; default: 0; * In the read operations address phase and read-data phase apply 2 signals. 1: enable * 0: disable. */ - uint32_t mem_fread_dio:1; - /** mem_fread_qio : R/W; bitpos: [24]; default: 0; + uint32_t fread_dio:1; + /** fread_qio : R/W; bitpos: [24]; default: 0; * In the read operations address phase and read-data phase apply 4 signals. 1: enable * 0: disable. */ - uint32_t mem_fread_qio:1; + uint32_t fread_qio:1; uint32_t reserved_25:5; - /** mem_dqs_ie_always_on : HRO; bitpos: [30]; default: 0; + /** dqs_ie_always_on : HRO; bitpos: [30]; default: 0; * When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always * 1. 0: Others. */ - uint32_t mem_dqs_ie_always_on:1; - /** mem_data_ie_always_on : R/W; bitpos: [31]; default: 1; + uint32_t dqs_ie_always_on:1; + /** data_ie_always_on : R/W; bitpos: [31]; default: 1; * When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are * always 1. 0: Others. */ - uint32_t mem_data_ie_always_on:1; + uint32_t data_ie_always_on:1; }; uint32_t val; } spi_mem_c_ctrl_reg_t; -/** Type of mem_ctrl1 register +/** Type of ctrl1 register * SPI0 control1 register. */ typedef union { struct { - /** mem_clk_mode : R/W; bitpos: [1:0]; default: 0; + /** clk_mode : R/W; bitpos: [1:0]; default: 0; * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: * SPI clock is alwasy on. */ - uint32_t mem_clk_mode:2; + uint32_t clk_mode:2; uint32_t reserved_2:19; /** ar_size0_1_support_en : R/W; bitpos: [21]; default: 1; * 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply @@ -185,131 +185,131 @@ typedef union { * Reply AXI read data to AXI bus when all the read data is available. */ uint32_t axi_rdata_back_fast:1; - /** mem_rresp_ecc_err_en : R/W; bitpos: [24]; default: 0; + /** rresp_ecc_err_en : R/W; bitpos: [24]; default: 0; * 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY * when there is a ECC error in AXI read data. The ECC error information is recorded * in spi_mem_c_C_ECC_ERR_ADDR_REG. */ - uint32_t mem_rresp_ecc_err_en:1; - /** mem_ar_splice_en : HRO; bitpos: [25]; default: 0; + uint32_t rresp_ecc_err_en:1; + /** ar_splice_en : HRO; bitpos: [25]; default: 0; * Set this bit to enable AXI Read Splice-transfer. */ - uint32_t mem_ar_splice_en:1; - /** mem_aw_splice_en : HRO; bitpos: [26]; default: 0; + uint32_t ar_splice_en:1; + /** aw_splice_en : HRO; bitpos: [26]; default: 0; * Set this bit to enable AXI Write Splice-transfer. */ - uint32_t mem_aw_splice_en:1; - /** mem_ram0_en : HRO; bitpos: [27]; default: 1; + uint32_t aw_splice_en:1; + /** ram0_en : HRO; bitpos: [27]; default: 1; * When spi_mem_c_C_DUAL_RAM_EN is 0 and spi_mem_c_C_RAM0_EN is 1, only EXT_RAM0 will be * accessed. When spi_mem_c_C_DUAL_RAM_EN is 0 and spi_mem_c_C_RAM0_EN is 0, only EXT_RAM1 * will be accessed. When spi_mem_c_C_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be * accessed at the same time. */ - uint32_t mem_ram0_en:1; - /** mem_dual_ram_en : HRO; bitpos: [28]; default: 0; + uint32_t ram0_en:1; + /** dual_ram_en : HRO; bitpos: [28]; default: 0; * Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at the * same time. */ - uint32_t mem_dual_ram_en:1; - /** mem_fast_write_en : R/W; bitpos: [29]; default: 1; + uint32_t dual_ram_en:1; + /** fast_write_en : R/W; bitpos: [29]; default: 1; * Set this bit to write data faster, do not wait write data has been stored in * tx_bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored * in tx_bus_fifo_l2. */ - uint32_t mem_fast_write_en:1; - /** mem_rxfifo_rst : WT; bitpos: [30]; default: 0; + uint32_t fast_write_en:1; + /** rxfifo_rst : WT; bitpos: [30]; default: 0; * The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to * receive signals from AXI. Set this bit to reset these FIFO. */ - uint32_t mem_rxfifo_rst:1; - /** mem_txfifo_rst : WT; bitpos: [31]; default: 0; + uint32_t rxfifo_rst:1; + /** txfifo_rst : WT; bitpos: [31]; default: 0; * The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to * send signals to AXI. Set this bit to reset these FIFO. */ - uint32_t mem_txfifo_rst:1; + uint32_t txfifo_rst:1; }; uint32_t val; } spi_mem_c_ctrl1_reg_t; -/** Type of mem_ctrl2 register +/** Type of ctrl2 register * SPI0 control2 register. */ typedef union { struct { - /** mem_cs_setup_time : R/W; bitpos: [4:0]; default: 1; + /** cs_setup_time : R/W; bitpos: [4:0]; default: 1; * (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with * spi_mem_c_C_CS_SETUP bit. */ - uint32_t mem_cs_setup_time:5; - /** mem_cs_hold_time : R/W; bitpos: [9:5]; default: 1; + uint32_t cs_setup_time:5; + /** cs_hold_time : R/W; bitpos: [9:5]; default: 1; * SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with * spi_mem_c_C_CS_HOLD bit. */ - uint32_t mem_cs_hold_time:5; - /** mem_ecc_cs_hold_time : HRO; bitpos: [12:10]; default: 3; + uint32_t cs_hold_time:5; + /** ecc_cs_hold_time : HRO; bitpos: [12:10]; default: 3; * spi_mem_c_C_CS_HOLD_TIME + spi_mem_c_C_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC * mode when accessed flash. */ - uint32_t mem_ecc_cs_hold_time:3; - /** mem_ecc_skip_page_corner : HRO; bitpos: [13]; default: 1; + uint32_t ecc_cs_hold_time:3; + /** ecc_skip_page_corner : HRO; bitpos: [13]; default: 1; * 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when * accesses flash. */ - uint32_t mem_ecc_skip_page_corner:1; - /** mem_ecc_16to18_byte_en : HRO; bitpos: [14]; default: 0; + uint32_t ecc_skip_page_corner:1; + /** ecc_16to18_byte_en : HRO; bitpos: [14]; default: 0; * Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when * accesses flash. */ - uint32_t mem_ecc_16to18_byte_en:1; + uint32_t ecc_16to18_byte_en:1; uint32_t reserved_15:9; - /** mem_split_trans_en : R/W; bitpos: [24]; default: 1; + /** split_trans_en : R/W; bitpos: [24]; default: 1; * Set this bit to enable SPI0 split one AXI read flash transfer into two SPI * transfers when one transfer will cross flash or EXT_RAM page corner, valid no * matter whether there is an ECC region or not. */ - uint32_t mem_split_trans_en:1; - /** mem_cs_hold_delay : R/W; bitpos: [30:25]; default: 0; + uint32_t split_trans_en:1; + /** cs_hold_delay : R/W; bitpos: [30:25]; default: 0; * These bits are used to set the minimum CS high time tSHSL between SPI burst * transfer when accesses to flash. tSHSL is (spi_mem_c_C_CS_HOLD_DELAY[5:0] + 1) MSPI * core clock cycles. */ - uint32_t mem_cs_hold_delay:6; - /** mem_sync_reset : WT; bitpos: [31]; default: 0; + uint32_t cs_hold_delay:6; + /** sync_reset : WT; bitpos: [31]; default: 0; * The spi0_mst_st and spi0_slv_st will be reset. */ - uint32_t mem_sync_reset:1; + uint32_t sync_reset:1; }; uint32_t val; } spi_mem_c_ctrl2_reg_t; -/** Type of mem_misc register +/** Type of misc register * SPI0 misc register */ typedef union { struct { uint32_t reserved_0:7; - /** mem_fsub_pin : HRO; bitpos: [7]; default: 0; + /** fsub_pin : HRO; bitpos: [7]; default: 0; * For SPI0, flash is connected to SUBPINs. */ - uint32_t mem_fsub_pin:1; - /** mem_ssub_pin : HRO; bitpos: [8]; default: 0; + uint32_t fsub_pin:1; + /** ssub_pin : HRO; bitpos: [8]; default: 0; * For SPI0, sram is connected to SUBPINs. */ - uint32_t mem_ssub_pin:1; - /** mem_ck_idle_edge : R/W; bitpos: [9]; default: 0; + uint32_t ssub_pin:1; + /** ck_idle_edge : R/W; bitpos: [9]; default: 0; * 1: SPI_CLK line is high when idle 0: spi clk line is low when idle */ - uint32_t mem_ck_idle_edge:1; - /** mem_cs_keep_active : R/W; bitpos: [10]; default: 0; + uint32_t ck_idle_edge:1; + /** cs_keep_active : R/W; bitpos: [10]; default: 0; * SPI_CS line keep low when the bit is set. */ - uint32_t mem_cs_keep_active:1; + uint32_t cs_keep_active:1; uint32_t reserved_11:21; }; uint32_t val; } spi_mem_c_misc_reg_t; -/** Type of mem_cache_fctrl register +/** Type of cache_fctrl register * SPI0 bit mode control register. */ typedef union { @@ -328,7 +328,7 @@ typedef union { uint32_t val; } spi_mem_c_cache_fctrl_reg_t; -/** Type of mem_ddr register +/** Type of ddr register * SPI0 flash DDR mode control register */ typedef union { @@ -414,35 +414,35 @@ typedef union { /** Group: Clock control and configuration registers */ -/** Type of mem_clock register +/** Type of clock register * SPI clock division control register. */ typedef union { struct { - /** mem_clkcnt_l : R/W; bitpos: [7:0]; default: 3; + /** clkcnt_l : R/W; bitpos: [7:0]; default: 3; * In the master mode it must be equal to spi_mem_c_clkcnt_N. */ - uint32_t mem_clkcnt_l:8; - /** mem_clkcnt_h : R/W; bitpos: [15:8]; default: 1; + uint32_t clkcnt_l:8; + /** clkcnt_h : R/W; bitpos: [15:8]; default: 1; * In the master mode it must be floor((spi_mem_c_clkcnt_N+1)/2-1). */ - uint32_t mem_clkcnt_h:8; - /** mem_clkcnt_n : R/W; bitpos: [23:16]; default: 3; + uint32_t clkcnt_h:8; + /** clkcnt_n : R/W; bitpos: [23:16]; default: 3; * In the master mode it is the divider of spi_mem_c_clk. So spi_mem_c_clk frequency is * system/(spi_mem_c_clkcnt_N+1) */ - uint32_t mem_clkcnt_n:8; + uint32_t clkcnt_n:8; uint32_t reserved_24:7; - /** mem_clk_equ_sysclk : R/W; bitpos: [31]; default: 0; + /** clk_equ_sysclk : R/W; bitpos: [31]; default: 0; * 1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module * clock. */ - uint32_t mem_clk_equ_sysclk:1; + uint32_t clk_equ_sysclk:1; }; uint32_t val; } spi_mem_c_clock_reg_t; -/** Type of mem_clock_gate register +/** Type of clock_gate register * SPI0 clock gate register */ typedef union { @@ -458,84 +458,84 @@ typedef union { /** Group: Flash User-defined control registers */ -/** Type of mem_user register +/** Type of user register * SPI0 user register. */ typedef union { struct { uint32_t reserved_0:6; - /** mem_cs_hold : R/W; bitpos: [6]; default: 0; + /** cs_hold : R/W; bitpos: [6]; default: 0; * spi cs keep low when spi is in done phase. 1: enable 0: disable. */ - uint32_t mem_cs_hold:1; - /** mem_cs_setup : R/W; bitpos: [7]; default: 0; + uint32_t cs_hold:1; + /** cs_setup : R/W; bitpos: [7]; default: 0; * spi cs is enable when spi is in prepare phase. 1: enable 0: disable. */ - uint32_t mem_cs_setup:1; + uint32_t cs_setup:1; uint32_t reserved_8:1; - /** mem_ck_out_edge : R/W; bitpos: [9]; default: 0; + /** ck_out_edge : R/W; bitpos: [9]; default: 0; * The bit combined with spi_mem_c_C_CK_IDLE_EDGE bit to control SPI clock mode 0~3. */ - uint32_t mem_ck_out_edge:1; + uint32_t ck_out_edge:1; uint32_t reserved_10:16; - /** mem_usr_dummy_idle : R/W; bitpos: [26]; default: 0; + /** usr_dummy_idle : R/W; bitpos: [26]; default: 0; * spi clock is disable in dummy phase when the bit is enable. */ - uint32_t mem_usr_dummy_idle:1; + uint32_t usr_dummy_idle:1; uint32_t reserved_27:2; - /** mem_usr_dummy : R/W; bitpos: [29]; default: 0; + /** usr_dummy : R/W; bitpos: [29]; default: 0; * This bit enable the dummy phase of an operation. */ - uint32_t mem_usr_dummy:1; + uint32_t usr_dummy:1; uint32_t reserved_30:2; }; uint32_t val; } spi_mem_c_user_reg_t; -/** Type of mem_user1 register +/** Type of user1 register * SPI0 user1 register. */ typedef union { struct { - /** mem_usr_dummy_cyclelen : R/W; bitpos: [5:0]; default: 7; + /** usr_dummy_cyclelen : R/W; bitpos: [5:0]; default: 7; * The length in spi_mem_c_clk cycles of dummy phase. The register value shall be * (cycle_num-1). */ - uint32_t mem_usr_dummy_cyclelen:6; - /** mem_usr_dbytelen : HRO; bitpos: [8:6]; default: 1; + uint32_t usr_dummy_cyclelen:6; + /** usr_dbytelen : HRO; bitpos: [8:6]; default: 1; * SPI0 USR_CMD read or write data byte length -1 */ - uint32_t mem_usr_dbytelen:3; + uint32_t usr_dbytelen:3; uint32_t reserved_9:17; - /** mem_usr_addr_bitlen : R/W; bitpos: [31:26]; default: 23; + /** usr_addr_bitlen : R/W; bitpos: [31:26]; default: 23; * The length in bits of address phase. The register value shall be (bit_num-1). */ - uint32_t mem_usr_addr_bitlen:6; + uint32_t usr_addr_bitlen:6; }; uint32_t val; } spi_mem_c_user1_reg_t; -/** Type of mem_user2 register +/** Type of user2 register * SPI0 user2 register. */ typedef union { struct { - /** mem_usr_command_value : R/W; bitpos: [15:0]; default: 0; + /** usr_command_value : R/W; bitpos: [15:0]; default: 0; * The value of command. */ - uint32_t mem_usr_command_value:16; + uint32_t usr_command_value:16; uint32_t reserved_16:12; - /** mem_usr_command_bitlen : R/W; bitpos: [31:28]; default: 7; + /** usr_command_bitlen : R/W; bitpos: [31:28]; default: 7; * The length in bits of command phase. The register value shall be (bit_num-1) */ - uint32_t mem_usr_command_bitlen:4; + uint32_t usr_command_bitlen:4; }; uint32_t val; } spi_mem_c_user2_reg_t; /** Group: External RAM Control and configuration registers */ -/** Type of mem_sram_cmd register +/** Type of sram_cmd register * SPI0 external RAM mode control register */ typedef union { @@ -709,16 +709,16 @@ typedef union { /** Group: State control register */ -/** Type of mem_fsm register +/** Type of fsm register * SPI0 FSM status register */ typedef union { struct { uint32_t reserved_0:7; - /** mem_lock_delay_time : R/W; bitpos: [11:7]; default: 4; + /** lock_delay_time : R/W; bitpos: [11:7]; default: 4; * The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1. */ - uint32_t mem_lock_delay_time:5; + uint32_t lock_delay_time:5; uint32_t reserved_12:20; }; uint32_t val; @@ -726,102 +726,102 @@ typedef union { /** Group: Interrupt registers */ -/** Type of mem_int_ena register +/** Type of int_ena register * SPI0 interrupt enable register */ typedef union { struct { uint32_t reserved_0:3; - /** mem_slv_st_end_int_ena : R/W; bitpos: [3]; default: 0; + /** slv_st_end_int_ena : R/W; bitpos: [3]; default: 0; * The enable bit for spi_mem_c_C_SLV_ST_END_INT interrupt. */ - uint32_t mem_slv_st_end_int_ena:1; - /** mem_mst_st_end_int_ena : R/W; bitpos: [4]; default: 0; + uint32_t slv_st_end_int_ena:1; + /** mst_st_end_int_ena : R/W; bitpos: [4]; default: 0; * The enable bit for spi_mem_c_C_MST_ST_END_INT interrupt. */ - uint32_t mem_mst_st_end_int_ena:1; - /** mem_ecc_err_int_ena : HRO; bitpos: [5]; default: 0; + uint32_t mst_st_end_int_ena:1; + /** ecc_err_int_ena : HRO; bitpos: [5]; default: 0; * The enable bit for spi_mem_c_C_ECC_ERR_INT interrupt. */ - uint32_t mem_ecc_err_int_ena:1; - /** mem_pms_reject_int_ena : R/W; bitpos: [6]; default: 0; + uint32_t ecc_err_int_ena:1; + /** pms_reject_int_ena : R/W; bitpos: [6]; default: 0; * The enable bit for spi_mem_c_C_PMS_REJECT_INT interrupt. */ - uint32_t mem_pms_reject_int_ena:1; - /** mem_axi_raddr_err_int_ena : R/W; bitpos: [7]; default: 0; + uint32_t pms_reject_int_ena:1; + /** axi_raddr_err_int_ena : R/W; bitpos: [7]; default: 0; * The enable bit for spi_mem_c_C_AXI_RADDR_ERR_INT interrupt. */ - uint32_t mem_axi_raddr_err_int_ena:1; - /** mem_axi_wr_flash_err_int_ena : HRO; bitpos: [8]; default: 0; + uint32_t axi_raddr_err_int_ena:1; + /** axi_wr_flash_err_int_ena : HRO; bitpos: [8]; default: 0; * The enable bit for spi_mem_c_C_AXI_WR_FALSH_ERR_INT interrupt. */ - uint32_t mem_axi_wr_flash_err_int_ena:1; - /** mem_axi_waddr_err_int__ena : HRO; bitpos: [9]; default: 0; + uint32_t axi_wr_flash_err_int_ena:1; + /** axi_waddr_err_int__ena : HRO; bitpos: [9]; default: 0; * The enable bit for spi_mem_c_C_AXI_WADDR_ERR_INT interrupt. */ - uint32_t mem_axi_waddr_err_int__ena:1; + uint32_t axi_waddr_err_int__ena:1; uint32_t reserved_10:22; }; uint32_t val; } spi_mem_c_int_ena_reg_t; -/** Type of mem_int_clr register +/** Type of int_clr register * SPI0 interrupt clear register */ typedef union { struct { uint32_t reserved_0:3; - /** mem_slv_st_end_int_clr : WT; bitpos: [3]; default: 0; + /** slv_st_end_int_clr : WT; bitpos: [3]; default: 0; * The clear bit for spi_mem_c_C_SLV_ST_END_INT interrupt. */ - uint32_t mem_slv_st_end_int_clr:1; - /** mem_mst_st_end_int_clr : WT; bitpos: [4]; default: 0; + uint32_t slv_st_end_int_clr:1; + /** mst_st_end_int_clr : WT; bitpos: [4]; default: 0; * The clear bit for spi_mem_c_C_MST_ST_END_INT interrupt. */ - uint32_t mem_mst_st_end_int_clr:1; - /** mem_ecc_err_int_clr : HRO; bitpos: [5]; default: 0; + uint32_t mst_st_end_int_clr:1; + /** ecc_err_int_clr : HRO; bitpos: [5]; default: 0; * The clear bit for spi_mem_c_C_ECC_ERR_INT interrupt. */ - uint32_t mem_ecc_err_int_clr:1; - /** mem_pms_reject_int_clr : WT; bitpos: [6]; default: 0; + uint32_t ecc_err_int_clr:1; + /** pms_reject_int_clr : WT; bitpos: [6]; default: 0; * The clear bit for spi_mem_c_C_PMS_REJECT_INT interrupt. */ - uint32_t mem_pms_reject_int_clr:1; - /** mem_axi_raddr_err_int_clr : WT; bitpos: [7]; default: 0; + uint32_t pms_reject_int_clr:1; + /** axi_raddr_err_int_clr : WT; bitpos: [7]; default: 0; * The clear bit for spi_mem_c_C_AXI_RADDR_ERR_INT interrupt. */ - uint32_t mem_axi_raddr_err_int_clr:1; - /** mem_axi_wr_flash_err_int_clr : HRO; bitpos: [8]; default: 0; + uint32_t axi_raddr_err_int_clr:1; + /** axi_wr_flash_err_int_clr : HRO; bitpos: [8]; default: 0; * The clear bit for spi_mem_c_C_AXI_WR_FALSH_ERR_INT interrupt. */ - uint32_t mem_axi_wr_flash_err_int_clr:1; - /** mem_axi_waddr_err_int_clr : HRO; bitpos: [9]; default: 0; + uint32_t axi_wr_flash_err_int_clr:1; + /** axi_waddr_err_int_clr : HRO; bitpos: [9]; default: 0; * The clear bit for spi_mem_c_C_AXI_WADDR_ERR_INT interrupt. */ - uint32_t mem_axi_waddr_err_int_clr:1; + uint32_t axi_waddr_err_int_clr:1; uint32_t reserved_10:22; }; uint32_t val; } spi_mem_c_int_clr_reg_t; -/** Type of mem_int_raw register +/** Type of int_raw register * SPI0 interrupt raw register */ typedef union { struct { uint32_t reserved_0:3; - /** mem_slv_st_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + /** slv_st_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0; * The raw bit for spi_mem_c_C_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is * changed from non idle state to idle state. It means that SPI_CS raises high. 0: * Others */ - uint32_t mem_slv_st_end_int_raw:1; - /** mem_mst_st_end_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + uint32_t slv_st_end_int_raw:1; + /** mst_st_end_int_raw : R/WTC/SS; bitpos: [4]; default: 0; * The raw bit for spi_mem_c_C_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is * changed from non idle state to idle state. 0: Others. */ - uint32_t mem_mst_st_end_int_raw:1; - /** mem_ecc_err_int_raw : HRO; bitpos: [5]; default: 0; + uint32_t mst_st_end_int_raw:1; + /** ecc_err_int_raw : HRO; bitpos: [5]; default: 0; * The raw bit for spi_mem_c_C_ECC_ERR_INT interrupt. When SPI_MEM_C_FMEM__ECC_ERR_INT_EN is set * and SPI_MEM_C_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times * of SPI0/1 ECC read flash are equal or bigger than spi_mem_c_C_ECC_ERR_INT_NUM. When @@ -833,66 +833,66 @@ typedef union { * spi_mem_c_C_ECC_ERR_INT_NUM. When SPI_MEM_C_FMEM__ECC_ERR_INT_EN and SPI_MEM_C_SMEM_ECC_ERR_INT_EN * are cleared, this bit will not be triggered. */ - uint32_t mem_ecc_err_int_raw:1; - /** mem_pms_reject_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + uint32_t ecc_err_int_raw:1; + /** pms_reject_int_raw : R/WTC/SS; bitpos: [6]; default: 0; * The raw bit for spi_mem_c_C_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is * rejected. 0: Others. */ - uint32_t mem_pms_reject_int_raw:1; - /** mem_axi_raddr_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + uint32_t pms_reject_int_raw:1; + /** axi_raddr_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0; * The raw bit for spi_mem_c_C_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read * address is invalid by compared to MMU configuration. 0: Others. */ - uint32_t mem_axi_raddr_err_int_raw:1; - /** mem_axi_wr_flash_err_int_raw : HRO; bitpos: [8]; default: 0; + uint32_t axi_raddr_err_int_raw:1; + /** axi_wr_flash_err_int_raw : HRO; bitpos: [8]; default: 0; * The raw bit for spi_mem_c_C_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write * flash request is received. 0: Others. */ - uint32_t mem_axi_wr_flash_err_int_raw:1; - /** mem_axi_waddr_err_int_raw : HRO; bitpos: [9]; default: 0; + uint32_t axi_wr_flash_err_int_raw:1; + /** axi_waddr_err_int_raw : HRO; bitpos: [9]; default: 0; * The raw bit for spi_mem_c_C_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write * address is invalid by compared to MMU configuration. 0: Others. */ - uint32_t mem_axi_waddr_err_int_raw:1; + uint32_t axi_waddr_err_int_raw:1; uint32_t reserved_10:22; }; uint32_t val; } spi_mem_c_int_raw_reg_t; -/** Type of mem_int_st register +/** Type of int_st register * SPI0 interrupt status register */ typedef union { struct { uint32_t reserved_0:3; - /** mem_slv_st_end_int_st : RO; bitpos: [3]; default: 0; + /** slv_st_end_int_st : RO; bitpos: [3]; default: 0; * The status bit for spi_mem_c_C_SLV_ST_END_INT interrupt. */ - uint32_t mem_slv_st_end_int_st:1; - /** mem_mst_st_end_int_st : RO; bitpos: [4]; default: 0; + uint32_t slv_st_end_int_st:1; + /** mst_st_end_int_st : RO; bitpos: [4]; default: 0; * The status bit for spi_mem_c_C_MST_ST_END_INT interrupt. */ - uint32_t mem_mst_st_end_int_st:1; - /** mem_ecc_err_int_st : HRO; bitpos: [5]; default: 0; + uint32_t mst_st_end_int_st:1; + /** ecc_err_int_st : HRO; bitpos: [5]; default: 0; * The status bit for spi_mem_c_C_ECC_ERR_INT interrupt. */ - uint32_t mem_ecc_err_int_st:1; - /** mem_pms_reject_int_st : RO; bitpos: [6]; default: 0; + uint32_t ecc_err_int_st:1; + /** pms_reject_int_st : RO; bitpos: [6]; default: 0; * The status bit for spi_mem_c_C_PMS_REJECT_INT interrupt. */ - uint32_t mem_pms_reject_int_st:1; - /** mem_axi_raddr_err_int_st : RO; bitpos: [7]; default: 0; + uint32_t pms_reject_int_st:1; + /** axi_raddr_err_int_st : RO; bitpos: [7]; default: 0; * The enable bit for spi_mem_c_C_AXI_RADDR_ERR_INT interrupt. */ - uint32_t mem_axi_raddr_err_int_st:1; - /** mem_axi_wr_flash_err_int_st : HRO; bitpos: [8]; default: 0; + uint32_t axi_raddr_err_int_st:1; + /** axi_wr_flash_err_int_st : HRO; bitpos: [8]; default: 0; * The enable bit for spi_mem_c_C_AXI_WR_FALSH_ERR_INT interrupt. */ - uint32_t mem_axi_wr_flash_err_int_st:1; - /** mem_axi_waddr_err_int_st : HRO; bitpos: [9]; default: 0; + uint32_t axi_wr_flash_err_int_st:1; + /** axi_waddr_err_int_st : HRO; bitpos: [9]; default: 0; * The enable bit for spi_mem_c_C_AXI_WADDR_ERR_INT interrupt. */ - uint32_t mem_axi_waddr_err_int_st:1; + uint32_t axi_waddr_err_int_st:1; uint32_t reserved_10:22; }; uint32_t val; @@ -1006,57 +1006,57 @@ typedef union { uint32_t val; } spi_mem_c_smem_pmsn_size_reg_t; -/** Type of mem_pms_reject register +/** Type of pms_reject register * SPI1 access reject register */ typedef union { struct { - /** mem_reject_addr : R/SS/WTC; bitpos: [26:0]; default: 0; + /** reject_addr : R/SS/WTC; bitpos: [26:0]; default: 0; * This bits show the first SPI1 access error address. It is cleared by when * spi_mem_c_C_PMS_REJECT_INT_CLR bit is set. */ - uint32_t mem_reject_addr:27; - /** mem_pm_en : R/W; bitpos: [27]; default: 0; + uint32_t reject_addr:27; + /** pm_en : R/W; bitpos: [27]; default: 0; * Set this bit to enable SPI0/1 transfer permission control function. */ - uint32_t mem_pm_en:1; - /** mem_pms_ld : R/SS/WTC; bitpos: [28]; default: 0; + uint32_t pm_en:1; + /** pms_ld : R/SS/WTC; bitpos: [28]; default: 0; * 1: SPI1 write access error. 0: No write access error. It is cleared by when * spi_mem_c_C_PMS_REJECT_INT_CLR bit is set. */ - uint32_t mem_pms_ld:1; - /** mem_pms_st : R/SS/WTC; bitpos: [29]; default: 0; + uint32_t pms_ld:1; + /** pms_st : R/SS/WTC; bitpos: [29]; default: 0; * 1: SPI1 read access error. 0: No read access error. It is cleared by when * spi_mem_c_C_PMS_REJECT_INT_CLR bit is set. */ - uint32_t mem_pms_st:1; - /** mem_pms_multi_hit : R/SS/WTC; bitpos: [30]; default: 0; + uint32_t pms_st:1; + /** pms_multi_hit : R/SS/WTC; bitpos: [30]; default: 0; * 1: SPI1 access is rejected because of address miss. 0: No address miss error. It is * cleared by when spi_mem_c_C_PMS_REJECT_INT_CLR bit is set. */ - uint32_t mem_pms_multi_hit:1; - /** mem_pms_ivd : R/SS/WTC; bitpos: [31]; default: 0; + uint32_t pms_multi_hit:1; + /** pms_ivd : R/SS/WTC; bitpos: [31]; default: 0; * 1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit * error. It is cleared by when spi_mem_c_C_PMS_REJECT_INT_CLR bit is set. */ - uint32_t mem_pms_ivd:1; + uint32_t pms_ivd:1; }; uint32_t val; } spi_mem_c_pms_reject_reg_t; /** Group: MSPI ECC registers */ -/** Type of mem_ecc_ctrl register +/** Type of ecc_ctrl register * MSPI ECC control register */ typedef union { struct { uint32_t reserved_0:5; - /** mem_ecc_err_cnt : HRO; bitpos: [10:5]; default: 0; + /** ecc_err_cnt : HRO; bitpos: [10:5]; default: 0; * This bits show the error times of MSPI ECC read. It is cleared by when * spi_mem_c_C_ECC_ERR_INT_CLR bit is set. */ - uint32_t mem_ecc_err_cnt:6; + uint32_t ecc_err_cnt:6; /** fmem_ecc_err_int_num : HRO; bitpos: [16:11]; default: 10; * Set the error times of MSPI ECC read to generate MSPI spi_mem_c_C_ECC_ERR_INT interrupt. */ @@ -1076,36 +1076,36 @@ typedef union { * should be 0. Otherwise, this bit should be 1. */ uint32_t fmem_ecc_addr_en:1; - /** mem_usr_ecc_addr_en : HRO; bitpos: [21]; default: 0; + /** usr_ecc_addr_en : HRO; bitpos: [21]; default: 0; * Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer. */ - uint32_t mem_usr_ecc_addr_en:1; + uint32_t usr_ecc_addr_en:1; uint32_t reserved_22:2; - /** mem_ecc_continue_record_err_en : HRO; bitpos: [24]; default: 1; + /** ecc_continue_record_err_en : HRO; bitpos: [24]; default: 1; * 1: The error information in spi_mem_c_C_ECC_ERR_BITS and spi_mem_c_C_ECC_ERR_ADDR is * updated when there is an ECC error. 0: spi_mem_c_C_ECC_ERR_BITS and * spi_mem_c_C_ECC_ERR_ADDR record the first ECC error information. */ - uint32_t mem_ecc_continue_record_err_en:1; - /** mem_ecc_err_bits : HRO; bitpos: [31:25]; default: 0; + uint32_t ecc_continue_record_err_en:1; + /** ecc_err_bits : HRO; bitpos: [31:25]; default: 0; * Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding to * byte 0 bit 0 to byte 15 bit 7) */ - uint32_t mem_ecc_err_bits:7; + uint32_t ecc_err_bits:7; }; uint32_t val; } spi_mem_c_ecc_ctrl_reg_t; -/** Type of mem_ecc_err_addr register +/** Type of ecc_err_addr register * MSPI ECC error address register */ typedef union { struct { - /** mem_ecc_err_addr : HRO; bitpos: [26:0]; default: 0; + /** ecc_err_addr : HRO; bitpos: [26:0]; default: 0; * This bits show the first MSPI ECC error address. It is cleared by when * spi_mem_c_C_ECC_ERR_INT_CLR bit is set. */ - uint32_t mem_ecc_err_addr:27; + uint32_t ecc_err_addr:27; uint32_t reserved_27:5; }; uint32_t val; @@ -1146,11 +1146,11 @@ typedef union { typedef union { struct { uint32_t reserved_0:26; - /** mem_all_fifo_empty : RO; bitpos: [26]; default: 1; + /** all_fifo_empty : RO; bitpos: [26]; default: 1; * The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers * and SPI0 transfers are done. 0: Others. */ - uint32_t mem_all_fifo_empty:1; + uint32_t all_fifo_empty:1; /** rdata_afifo_rempty : RO; bitpos: [27]; default: 1; * 1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending. */ @@ -1176,60 +1176,60 @@ typedef union { uint32_t val; } spi_mem_c_smem_axi_addr_ctrl_reg_t; -/** Type of mem_axi_err_resp_en register +/** Type of axi_err_resp_en register * SPI0 AXI error response enable register */ typedef union { struct { - /** mem_aw_resp_en_mmu_vld : HRO; bitpos: [0]; default: 0; + /** aw_resp_en_mmu_vld : HRO; bitpos: [0]; default: 0; * Set this bit to enable AXI response function for mmu valid err in axi write trans. */ - uint32_t mem_aw_resp_en_mmu_vld:1; - /** mem_aw_resp_en_mmu_gid : HRO; bitpos: [1]; default: 0; + uint32_t aw_resp_en_mmu_vld:1; + /** aw_resp_en_mmu_gid : HRO; bitpos: [1]; default: 0; * Set this bit to enable AXI response function for mmu gid err in axi write trans. */ - uint32_t mem_aw_resp_en_mmu_gid:1; - /** mem_aw_resp_en_axi_size : HRO; bitpos: [2]; default: 0; + uint32_t aw_resp_en_mmu_gid:1; + /** aw_resp_en_axi_size : HRO; bitpos: [2]; default: 0; * Set this bit to enable AXI response function for axi size err in axi write trans. */ - uint32_t mem_aw_resp_en_axi_size:1; - /** mem_aw_resp_en_axi_flash : HRO; bitpos: [3]; default: 0; + uint32_t aw_resp_en_axi_size:1; + /** aw_resp_en_axi_flash : HRO; bitpos: [3]; default: 0; * Set this bit to enable AXI response function for axi flash err in axi write trans. */ - uint32_t mem_aw_resp_en_axi_flash:1; - /** mem_aw_resp_en_mmu_ecc : HRO; bitpos: [4]; default: 0; + uint32_t aw_resp_en_axi_flash:1; + /** aw_resp_en_mmu_ecc : HRO; bitpos: [4]; default: 0; * Set this bit to enable AXI response function for mmu ecc err in axi write trans. */ - uint32_t mem_aw_resp_en_mmu_ecc:1; - /** mem_aw_resp_en_mmu_sens : HRO; bitpos: [5]; default: 0; + uint32_t aw_resp_en_mmu_ecc:1; + /** aw_resp_en_mmu_sens : HRO; bitpos: [5]; default: 0; * Set this bit to enable AXI response function for mmu sens in err axi write trans. */ - uint32_t mem_aw_resp_en_mmu_sens:1; - /** mem_aw_resp_en_axi_wstrb : HRO; bitpos: [6]; default: 0; + uint32_t aw_resp_en_mmu_sens:1; + /** aw_resp_en_axi_wstrb : HRO; bitpos: [6]; default: 0; * Set this bit to enable AXI response function for axi wstrb err in axi write trans. */ - uint32_t mem_aw_resp_en_axi_wstrb:1; - /** mem_ar_resp_en_mmu_vld : R/W; bitpos: [7]; default: 0; + uint32_t aw_resp_en_axi_wstrb:1; + /** ar_resp_en_mmu_vld : R/W; bitpos: [7]; default: 0; * Set this bit to enable AXI response function for mmu valid err in axi read trans. */ - uint32_t mem_ar_resp_en_mmu_vld:1; - /** mem_ar_resp_en_mmu_gid : R/W; bitpos: [8]; default: 0; + uint32_t ar_resp_en_mmu_vld:1; + /** ar_resp_en_mmu_gid : R/W; bitpos: [8]; default: 0; * Set this bit to enable AXI response function for mmu gid err in axi read trans. */ - uint32_t mem_ar_resp_en_mmu_gid:1; - /** mem_ar_resp_en_mmu_ecc : R/W; bitpos: [9]; default: 0; + uint32_t ar_resp_en_mmu_gid:1; + /** ar_resp_en_mmu_ecc : R/W; bitpos: [9]; default: 0; * Set this bit to enable AXI response function for mmu ecc err in axi read trans. */ - uint32_t mem_ar_resp_en_mmu_ecc:1; - /** mem_ar_resp_en_mmu_sens : R/W; bitpos: [10]; default: 0; + uint32_t ar_resp_en_mmu_ecc:1; + /** ar_resp_en_mmu_sens : R/W; bitpos: [10]; default: 0; * Set this bit to enable AXI response function for mmu sensitive err in axi read * trans. */ - uint32_t mem_ar_resp_en_mmu_sens:1; - /** mem_ar_resp_en_axi_size : R/W; bitpos: [11]; default: 0; + uint32_t ar_resp_en_mmu_sens:1; + /** ar_resp_en_axi_size : R/W; bitpos: [11]; default: 0; * Set this bit to enable AXI response function for axi size err in axi read trans. */ - uint32_t mem_ar_resp_en_axi_size:1; + uint32_t ar_resp_en_axi_size:1; uint32_t reserved_12:20; }; uint32_t val; @@ -1237,223 +1237,223 @@ typedef union { /** Group: Flash timing registers */ -/** Type of mem_timing_cali register +/** Type of timing_cali register * SPI0 flash timing calibration register */ typedef union { struct { - /** mem_timing_clk_ena : R/W; bitpos: [0]; default: 1; + /** timing_clk_ena : R/W; bitpos: [0]; default: 1; * The bit is used to enable timing adjust clock for all reading operations. */ - uint32_t mem_timing_clk_ena:1; - /** mem_timing_cali : R/W; bitpos: [1]; default: 0; + uint32_t timing_clk_ena:1; + /** timing_cali : R/W; bitpos: [1]; default: 0; * The bit is used to enable timing auto-calibration for all reading operations. */ - uint32_t mem_timing_cali:1; - /** mem_extra_dummy_cyclelen : R/W; bitpos: [4:2]; default: 0; + uint32_t timing_cali:1; + /** extra_dummy_cyclelen : R/W; bitpos: [4:2]; default: 0; * add extra dummy spi clock cycle length for spi clock calibration. */ - uint32_t mem_extra_dummy_cyclelen:3; - /** mem_dll_timing_cali : HRO; bitpos: [5]; default: 0; + uint32_t extra_dummy_cyclelen:3; + /** dll_timing_cali : HRO; bitpos: [5]; default: 0; * Set this bit to enable DLL for timing calibration in DDR mode when accessed to * flash. */ - uint32_t mem_dll_timing_cali:1; - /** mem_timing_cali_update : WT; bitpos: [6]; default: 0; + uint32_t dll_timing_cali:1; + /** timing_cali_update : WT; bitpos: [6]; default: 0; * Set this bit to update delay mode, delay num and extra dummy in MSPI. */ - uint32_t mem_timing_cali_update:1; + uint32_t timing_cali_update:1; uint32_t reserved_7:25; }; uint32_t val; } spi_mem_c_timing_cali_reg_t; -/** Type of mem_din_mode register +/** Type of din_mode register * MSPI flash input timing delay mode control register */ typedef union { struct { - /** mem_din0_mode : R/W; bitpos: [2:0]; default: 0; + /** din0_mode : R/W; bitpos: [2:0]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the * spi_clk high edge, 6: input with the spi_clk low edge */ - uint32_t mem_din0_mode:3; - /** mem_din1_mode : R/W; bitpos: [5:3]; default: 0; + uint32_t din0_mode:3; + /** din1_mode : R/W; bitpos: [5:3]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the * spi_clk high edge, 6: input with the spi_clk low edge */ - uint32_t mem_din1_mode:3; - /** mem_din2_mode : R/W; bitpos: [8:6]; default: 0; + uint32_t din1_mode:3; + /** din2_mode : R/W; bitpos: [8:6]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the * spi_clk high edge, 6: input with the spi_clk low edge */ - uint32_t mem_din2_mode:3; - /** mem_din3_mode : R/W; bitpos: [11:9]; default: 0; + uint32_t din2_mode:3; + /** din3_mode : R/W; bitpos: [11:9]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the * spi_clk high edge, 6: input with the spi_clk low edge */ - uint32_t mem_din3_mode:3; - /** mem_din4_mode : R/W; bitpos: [14:12]; default: 0; + uint32_t din3_mode:3; + /** din4_mode : R/W; bitpos: [14:12]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the spi_clk */ - uint32_t mem_din4_mode:3; - /** mem_din5_mode : R/W; bitpos: [17:15]; default: 0; + uint32_t din4_mode:3; + /** din5_mode : R/W; bitpos: [17:15]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the spi_clk */ - uint32_t mem_din5_mode:3; - /** mem_din6_mode : R/W; bitpos: [20:18]; default: 0; + uint32_t din5_mode:3; + /** din6_mode : R/W; bitpos: [20:18]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the spi_clk */ - uint32_t mem_din6_mode:3; - /** mem_din7_mode : R/W; bitpos: [23:21]; default: 0; + uint32_t din6_mode:3; + /** din7_mode : R/W; bitpos: [23:21]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the spi_clk */ - uint32_t mem_din7_mode:3; - /** mem_dins_mode : R/W; bitpos: [26:24]; default: 0; + uint32_t din7_mode:3; + /** dins_mode : R/W; bitpos: [26:24]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the spi_clk */ - uint32_t mem_dins_mode:3; + uint32_t dins_mode:3; uint32_t reserved_27:5; }; uint32_t val; } spi_mem_c_din_mode_reg_t; -/** Type of mem_din_num register +/** Type of din_num register * MSPI flash input timing delay number control register */ typedef union { struct { - /** mem_din0_num : R/W; bitpos: [1:0]; default: 0; + /** din0_num : R/W; bitpos: [1:0]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ - uint32_t mem_din0_num:2; - /** mem_din1_num : R/W; bitpos: [3:2]; default: 0; + uint32_t din0_num:2; + /** din1_num : R/W; bitpos: [3:2]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ - uint32_t mem_din1_num:2; - /** mem_din2_num : R/W; bitpos: [5:4]; default: 0; + uint32_t din1_num:2; + /** din2_num : R/W; bitpos: [5:4]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ - uint32_t mem_din2_num:2; - /** mem_din3_num : R/W; bitpos: [7:6]; default: 0; + uint32_t din2_num:2; + /** din3_num : R/W; bitpos: [7:6]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ - uint32_t mem_din3_num:2; - /** mem_din4_num : R/W; bitpos: [9:8]; default: 0; + uint32_t din3_num:2; + /** din4_num : R/W; bitpos: [9:8]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ - uint32_t mem_din4_num:2; - /** mem_din5_num : R/W; bitpos: [11:10]; default: 0; + uint32_t din4_num:2; + /** din5_num : R/W; bitpos: [11:10]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ - uint32_t mem_din5_num:2; - /** mem_din6_num : R/W; bitpos: [13:12]; default: 0; + uint32_t din5_num:2; + /** din6_num : R/W; bitpos: [13:12]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ - uint32_t mem_din6_num:2; - /** mem_din7_num : R/W; bitpos: [15:14]; default: 0; + uint32_t din6_num:2; + /** din7_num : R/W; bitpos: [15:14]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ - uint32_t mem_din7_num:2; - /** mem_dins_num : R/W; bitpos: [17:16]; default: 0; + uint32_t din7_num:2; + /** dins_num : R/W; bitpos: [17:16]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ - uint32_t mem_dins_num:2; + uint32_t dins_num:2; uint32_t reserved_18:14; }; uint32_t val; } spi_mem_c_din_num_reg_t; -/** Type of mem_dout_mode register +/** Type of dout_mode register * MSPI flash output timing adjustment control register */ typedef union { struct { - /** mem_dout0_mode : R/W; bitpos: [0]; default: 0; + /** dout0_mode : R/W; bitpos: [0]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output * with the spi_clk high edge ,6: output with the spi_clk low edge */ - uint32_t mem_dout0_mode:1; - /** mem_dout1_mode : R/W; bitpos: [1]; default: 0; + uint32_t dout0_mode:1; + /** dout1_mode : R/W; bitpos: [1]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output * with the spi_clk high edge ,6: output with the spi_clk low edge */ - uint32_t mem_dout1_mode:1; - /** mem_dout2_mode : R/W; bitpos: [2]; default: 0; + uint32_t dout1_mode:1; + /** dout2_mode : R/W; bitpos: [2]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output * with the spi_clk high edge ,6: output with the spi_clk low edge */ - uint32_t mem_dout2_mode:1; - /** mem_dout3_mode : R/W; bitpos: [3]; default: 0; + uint32_t dout2_mode:1; + /** dout3_mode : R/W; bitpos: [3]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output * with the spi_clk high edge ,6: output with the spi_clk low edge */ - uint32_t mem_dout3_mode:1; - /** mem_dout4_mode : R/W; bitpos: [4]; default: 0; + uint32_t dout3_mode:1; + /** dout4_mode : R/W; bitpos: [4]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the spi_clk */ - uint32_t mem_dout4_mode:1; - /** mem_dout5_mode : R/W; bitpos: [5]; default: 0; + uint32_t dout4_mode:1; + /** dout5_mode : R/W; bitpos: [5]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the spi_clk */ - uint32_t mem_dout5_mode:1; - /** mem_dout6_mode : R/W; bitpos: [6]; default: 0; + uint32_t dout5_mode:1; + /** dout6_mode : R/W; bitpos: [6]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the spi_clk */ - uint32_t mem_dout6_mode:1; - /** mem_dout7_mode : R/W; bitpos: [7]; default: 0; + uint32_t dout6_mode:1; + /** dout7_mode : R/W; bitpos: [7]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the spi_clk */ - uint32_t mem_dout7_mode:1; - /** mem_douts_mode : R/W; bitpos: [8]; default: 0; + uint32_t dout7_mode:1; + /** douts_mode : R/W; bitpos: [8]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the spi_clk */ - uint32_t mem_douts_mode:1; + uint32_t douts_mode:1; uint32_t reserved_9:23; }; uint32_t val; @@ -1692,7 +1692,7 @@ typedef union { /** Group: Manual Encryption plaintext Memory */ -/** Type of mem_xts_plain_base register +/** Type of xts_plain_base register * The base address of the memory that stores plaintext in Manual Encryption */ typedef union { @@ -1708,7 +1708,7 @@ typedef union { /** Group: Manual Encryption configuration registers */ -/** Type of mem_xts_linesize register +/** Type of xts_linesize register * Manual Encryption Line-Size register */ typedef union { @@ -1724,7 +1724,7 @@ typedef union { uint32_t val; } spi_mem_c_xts_linesize_reg_t; -/** Type of mem_xts_destination register +/** Type of xts_destination register * Manual Encryption destination register */ typedef union { @@ -1739,7 +1739,7 @@ typedef union { uint32_t val; } spi_mem_c_xts_destination_reg_t; -/** Type of mem_xts_physical_address register +/** Type of xts_physical_address register * Manual Encryption physical address register */ typedef union { @@ -1757,7 +1757,7 @@ typedef union { /** Group: Manual Encryption control and status registers */ -/** Type of mem_xts_trigger register +/** Type of xts_trigger register * Manual Encryption physical address register */ typedef union { @@ -1774,7 +1774,7 @@ typedef union { uint32_t val; } spi_mem_c_xts_trigger_reg_t; -/** Type of mem_xts_release register +/** Type of xts_release register * Manual Encryption physical address register */ typedef union { @@ -1790,7 +1790,7 @@ typedef union { uint32_t val; } spi_mem_c_xts_release_reg_t; -/** Type of mem_xts_destroy register +/** Type of xts_destroy register * Manual Encryption physical address register */ typedef union { @@ -1806,7 +1806,7 @@ typedef union { uint32_t val; } spi_mem_c_xts_destroy_reg_t; -/** Type of mem_xts_state register +/** Type of xts_state register * Manual Encryption physical address register */ typedef union { @@ -1824,7 +1824,7 @@ typedef union { /** Group: Manual Encryption version control register */ -/** Type of mem_xts_date register +/** Type of xts_date register * Manual Encryption version register */ typedef union { @@ -1840,7 +1840,7 @@ typedef union { /** Group: MMU access registers */ -/** Type of mem_mmu_item_content register +/** Type of mmu_item_content register * MSPI-MMU item content register */ typedef union { @@ -1853,7 +1853,7 @@ typedef union { uint32_t val; } spi_mem_c_mmu_item_content_reg_t; -/** Type of mem_mmu_item_index register +/** Type of mmu_item_index register * MSPI-MMU item index register */ typedef union { @@ -1868,7 +1868,7 @@ typedef union { /** Group: MMU power control and configuration registers */ -/** Type of mem_mmu_power_ctrl register +/** Type of mmu_power_ctrl register * MSPI MMU power control register */ typedef union { @@ -1891,10 +1891,10 @@ typedef union { */ uint32_t mmu_page_size:2; uint32_t reserved_5:11; - /** mem_aux_ctrl : HRO; bitpos: [29:16]; default: 4896; + /** aux_ctrl : HRO; bitpos: [29:16]; default: 4896; * MMU PSRAM aux control register */ - uint32_t mem_aux_ctrl:14; + uint32_t aux_ctrl:14; uint32_t reserved_30:2; }; uint32_t val; @@ -1902,7 +1902,7 @@ typedef union { /** Group: External mem cryption DPA registers */ -/** Type of mem_dpa_ctrl register +/** Type of dpa_ctrl register * SPI memory cryption DPA register */ typedef union { @@ -1931,15 +1931,15 @@ typedef union { /** Group: Version control register */ -/** Type of mem_date register +/** Type of date register * SPI0 version control register */ typedef union { struct { - /** mem_date : R/W; bitpos: [27:0]; default: 36712560; + /** date : R/W; bitpos: [27:0]; default: 36712560; * SPI0 register version. */ - uint32_t mem_date:28; + uint32_t date:28; uint32_t reserved_28:4; }; uint32_t val; @@ -1947,30 +1947,30 @@ typedef union { typedef struct spi_mem_c_dev_s { - volatile spi_mem_c_cmd_reg_t mem_cmd; + volatile spi_mem_c_cmd_reg_t cmd; uint32_t reserved_004; - volatile spi_mem_c_ctrl_reg_t mem_ctrl; - volatile spi_mem_c_ctrl1_reg_t mem_ctrl1; - volatile spi_mem_c_ctrl2_reg_t mem_ctrl2; - volatile spi_mem_c_clock_reg_t mem_clock; - volatile spi_mem_c_user_reg_t mem_user; - volatile spi_mem_c_user1_reg_t mem_user1; - volatile spi_mem_c_user2_reg_t mem_user2; + volatile spi_mem_c_ctrl_reg_t ctrl; + volatile spi_mem_c_ctrl1_reg_t ctrl1; + volatile spi_mem_c_ctrl2_reg_t ctrl2; + volatile spi_mem_c_clock_reg_t clock; + volatile spi_mem_c_user_reg_t user; + volatile spi_mem_c_user1_reg_t user1; + volatile spi_mem_c_user2_reg_t user2; uint32_t reserved_024[4]; - volatile spi_mem_c_misc_reg_t mem_misc; + volatile spi_mem_c_misc_reg_t misc; uint32_t reserved_038; - volatile spi_mem_c_cache_fctrl_reg_t mem_cache_fctrl; + volatile spi_mem_c_cache_fctrl_reg_t cache_fctrl; uint32_t reserved_040; - volatile spi_mem_c_sram_cmd_reg_t mem_sram_cmd; + volatile spi_mem_c_sram_cmd_reg_t sram_cmd; uint32_t reserved_048[3]; - volatile spi_mem_c_fsm_reg_t mem_fsm; + volatile spi_mem_c_fsm_reg_t fsm; uint32_t reserved_058[26]; - volatile spi_mem_c_int_ena_reg_t mem_int_ena; - volatile spi_mem_c_int_clr_reg_t mem_int_clr; - volatile spi_mem_c_int_raw_reg_t mem_int_raw; - volatile spi_mem_c_int_st_reg_t mem_int_st; + volatile spi_mem_c_int_ena_reg_t int_ena; + volatile spi_mem_c_int_clr_reg_t int_clr; + volatile spi_mem_c_int_raw_reg_t int_raw; + volatile spi_mem_c_int_st_reg_t int_st; uint32_t reserved_0d0; - volatile spi_mem_c_ddr_reg_t mem_ddr; + volatile spi_mem_c_ddr_reg_t ddr; volatile spi_mem_c_smem_ddr_reg_t smem_ddr; uint32_t reserved_0dc[9]; volatile spi_mem_c_fmem_pmsn_attr_reg_t fmem_pmsn_attr[4]; @@ -1980,42 +1980,42 @@ typedef struct spi_mem_c_dev_s { volatile spi_mem_c_smem_pmsn_addr_reg_t smem_pmsn_addr[4]; volatile spi_mem_c_smem_pmsn_size_reg_t smem_pmsn_size[4]; uint32_t reserved_160; - volatile spi_mem_c_pms_reject_reg_t mem_pms_reject; - volatile spi_mem_c_ecc_ctrl_reg_t mem_ecc_ctrl; - volatile spi_mem_c_ecc_err_addr_reg_t mem_ecc_err_addr; - volatile spi_mem_c_axi_err_addr_reg_t mem_axi_err_addr; + volatile spi_mem_c_pms_reject_reg_t pms_reject; + volatile spi_mem_c_ecc_ctrl_reg_t ecc_ctrl; + volatile spi_mem_c_ecc_err_addr_reg_t ecc_err_addr; + volatile spi_mem_c_axi_err_addr_reg_t axi_err_addr; volatile spi_mem_c_smem_ecc_ctrl_reg_t smem_ecc_ctrl; volatile spi_mem_c_smem_axi_addr_ctrl_reg_t smem_axi_addr_ctrl; - volatile spi_mem_c_axi_err_resp_en_reg_t mem_axi_err_resp_en; - volatile spi_mem_c_timing_cali_reg_t mem_timing_cali; - volatile spi_mem_c_din_mode_reg_t mem_din_mode; - volatile spi_mem_c_din_num_reg_t mem_din_num; - volatile spi_mem_c_dout_mode_reg_t mem_dout_mode; + volatile spi_mem_c_axi_err_resp_en_reg_t axi_err_resp_en; + volatile spi_mem_c_timing_cali_reg_t timing_cali; + volatile spi_mem_c_din_mode_reg_t din_mode; + volatile spi_mem_c_din_num_reg_t din_num; + volatile spi_mem_c_dout_mode_reg_t dout_mode; volatile spi_mem_c_smem_timing_cali_reg_t smem_timing_cali; volatile spi_mem_c_smem_din_mode_reg_t smem_din_mode; volatile spi_mem_c_smem_din_num_reg_t smem_din_num; volatile spi_mem_c_smem_dout_mode_reg_t smem_dout_mode; volatile spi_mem_c_smem_ac_reg_t smem_ac; uint32_t reserved_1a4[23]; - volatile spi_mem_c_clock_gate_reg_t mem_clock_gate; + volatile spi_mem_c_clock_gate_reg_t clock_gate; uint32_t reserved_204[63]; - volatile spi_mem_c_xts_plain_base_reg_t mem_xts_plain_base; + volatile spi_mem_c_xts_plain_base_reg_t xts_plain_base; uint32_t reserved_304[15]; - volatile spi_mem_c_xts_linesize_reg_t mem_xts_linesize; - volatile spi_mem_c_xts_destination_reg_t mem_xts_destination; - volatile spi_mem_c_xts_physical_address_reg_t mem_xts_physical_address; - volatile spi_mem_c_xts_trigger_reg_t mem_xts_trigger; - volatile spi_mem_c_xts_release_reg_t mem_xts_release; - volatile spi_mem_c_xts_destroy_reg_t mem_xts_destroy; - volatile spi_mem_c_xts_state_reg_t mem_xts_state; - volatile spi_mem_c_xts_date_reg_t mem_xts_date; + volatile spi_mem_c_xts_linesize_reg_t xts_linesize; + volatile spi_mem_c_xts_destination_reg_t xts_destination; + volatile spi_mem_c_xts_physical_address_reg_t xts_physical_address; + volatile spi_mem_c_xts_trigger_reg_t xts_trigger; + volatile spi_mem_c_xts_release_reg_t xts_release; + volatile spi_mem_c_xts_destroy_reg_t xts_destroy; + volatile spi_mem_c_xts_state_reg_t xts_state; + volatile spi_mem_c_xts_date_reg_t xts_date; uint32_t reserved_360[7]; - volatile spi_mem_c_mmu_item_content_reg_t mem_mmu_item_content; - volatile spi_mem_c_mmu_item_index_reg_t mem_mmu_item_index; - volatile spi_mem_c_mmu_power_ctrl_reg_t mem_mmu_power_ctrl; - volatile spi_mem_c_dpa_ctrl_reg_t mem_dpa_ctrl; + volatile spi_mem_c_mmu_item_content_reg_t mmu_item_content; + volatile spi_mem_c_mmu_item_index_reg_t mmu_item_index; + volatile spi_mem_c_mmu_power_ctrl_reg_t mmu_power_ctrl; + volatile spi_mem_c_dpa_ctrl_reg_t dpa_ctrl; uint32_t reserved_38c[28]; - volatile spi_mem_c_date_reg_t mem_date; + volatile spi_mem_c_date_reg_t date; } spi_mem_c_dev_t; diff --git a/components/soc/esp32p4/include/soc/spi_mem_reg.h b/components/soc/esp32p4/include/soc/spi_mem_reg.h index 1a559cf575..75a585fb6e 100644 --- a/components/soc/esp32p4/include/soc/spi_mem_reg.h +++ b/components/soc/esp32p4/include/soc/spi_mem_reg.h @@ -1,3444 +1,9 @@ -/* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD +/** + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ #pragma once -#include -#include "soc.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define SPI_MEM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x0) -/* SPI_MEM_FLASH_READ : R/W/SC ;bitpos:[31] ;default: 1'b0 ; */ -/*description: Read flash enable. Read flash operation will be triggered when the bit is set. T -he bit will be cleared once the operation done. 1: enable 0: disable..*/ -#define SPI_MEM_FLASH_READ (BIT(31)) -#define SPI_MEM_FLASH_READ_M (BIT(31)) -#define SPI_MEM_FLASH_READ_V 0x1 -#define SPI_MEM_FLASH_READ_S 31 -/* SPI_MEM_FLASH_WREN : R/W/SC ;bitpos:[30] ;default: 1'b0 ; */ -/*description: Write flash enable. Write enable command will be sent when the bit is set. The -bit will be cleared once the operation done. 1: enable 0: disable..*/ -#define SPI_MEM_FLASH_WREN (BIT(30)) -#define SPI_MEM_FLASH_WREN_M (BIT(30)) -#define SPI_MEM_FLASH_WREN_V 0x1 -#define SPI_MEM_FLASH_WREN_S 30 -/* SPI_MEM_FLASH_WRDI : R/W/SC ;bitpos:[29] ;default: 1'b0 ; */ -/*description: Write flash disable. Write disable command will be sent when the bit is set. The - bit will be cleared once the operation done. 1: enable 0: disable..*/ -#define SPI_MEM_FLASH_WRDI (BIT(29)) -#define SPI_MEM_FLASH_WRDI_M (BIT(29)) -#define SPI_MEM_FLASH_WRDI_V 0x1 -#define SPI_MEM_FLASH_WRDI_S 29 -/* SPI_MEM_FLASH_RDID : R/W/SC ;bitpos:[28] ;default: 1'b0 ; */ -/*description: Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will b -e cleared once the operation done. 1: enable 0: disable..*/ -#define SPI_MEM_FLASH_RDID (BIT(28)) -#define SPI_MEM_FLASH_RDID_M (BIT(28)) -#define SPI_MEM_FLASH_RDID_V 0x1 -#define SPI_MEM_FLASH_RDID_S 28 -/* SPI_MEM_FLASH_RDSR : R/W/SC ;bitpos:[27] ;default: 1'b0 ; */ -/*description: Read status register-1. Read status operation will be triggered when the bit is - set. The bit will be cleared once the operation done.1: enable 0: disable..*/ -#define SPI_MEM_FLASH_RDSR (BIT(27)) -#define SPI_MEM_FLASH_RDSR_M (BIT(27)) -#define SPI_MEM_FLASH_RDSR_V 0x1 -#define SPI_MEM_FLASH_RDSR_S 27 -/* SPI_MEM_FLASH_WRSR : R/W/SC ;bitpos:[26] ;default: 1'b0 ; */ -/*description: Write status register enable. Write status operation will be triggered when t -he bit is set. The bit will be cleared once the operation done.1: enable 0: disa -ble..*/ -#define SPI_MEM_FLASH_WRSR (BIT(26)) -#define SPI_MEM_FLASH_WRSR_M (BIT(26)) -#define SPI_MEM_FLASH_WRSR_V 0x1 -#define SPI_MEM_FLASH_WRSR_S 26 -/* SPI_MEM_FLASH_PP : R/W/SC ;bitpos:[25] ;default: 1'b0 ; */ -/*description: Page program enable(1 byte ~256 bytes data to be programmed). Page program opera -tion will be triggered when the bit is set. The bit will be cleared once the op -eration done .1: enable 0: disable..*/ -#define SPI_MEM_FLASH_PP (BIT(25)) -#define SPI_MEM_FLASH_PP_M (BIT(25)) -#define SPI_MEM_FLASH_PP_V 0x1 -#define SPI_MEM_FLASH_PP_S 25 -/* SPI_MEM_FLASH_SE : R/W/SC ;bitpos:[24] ;default: 1'b0 ; */ -/*description: Sector erase enable(4KB). Sector erase operation will be triggered when the bit -is set. The bit will be cleared once the operation done.1: enable 0: disable..*/ -#define SPI_MEM_FLASH_SE (BIT(24)) -#define SPI_MEM_FLASH_SE_M (BIT(24)) -#define SPI_MEM_FLASH_SE_V 0x1 -#define SPI_MEM_FLASH_SE_S 24 -/* SPI_MEM_FLASH_BE : R/W/SC ;bitpos:[23] ;default: 1'b0 ; */ -/*description: Block erase enable(32KB) . Block erase operation will be triggered when the bit - is set. The bit will be cleared once the operation done.1: enable 0: disable..*/ -#define SPI_MEM_FLASH_BE (BIT(23)) -#define SPI_MEM_FLASH_BE_M (BIT(23)) -#define SPI_MEM_FLASH_BE_V 0x1 -#define SPI_MEM_FLASH_BE_S 23 -/* SPI_MEM_FLASH_CE : R/W/SC ;bitpos:[22] ;default: 1'b0 ; */ -/*description: Chip erase enable. Chip erase operation will be triggered when the bit is set. T -he bit will be cleared once the operation done.1: enable 0: disable..*/ -#define SPI_MEM_FLASH_CE (BIT(22)) -#define SPI_MEM_FLASH_CE_M (BIT(22)) -#define SPI_MEM_FLASH_CE_V 0x1 -#define SPI_MEM_FLASH_CE_S 22 -/* SPI_MEM_FLASH_DP : R/W/SC ;bitpos:[21] ;default: 1'b0 ; */ -/*description: Drive Flash into power down. An operation will be triggered when the bit is set -. The bit will be cleared once the operation done.1: enable 0: disable..*/ -#define SPI_MEM_FLASH_DP (BIT(21)) -#define SPI_MEM_FLASH_DP_M (BIT(21)) -#define SPI_MEM_FLASH_DP_V 0x1 -#define SPI_MEM_FLASH_DP_S 21 -/* SPI_MEM_FLASH_RES : R/W/SC ;bitpos:[20] ;default: 1'b0 ; */ -/*description: This bit combined with reg_resandres bit releases Flash from the power-down stat -e or high performance mode and obtains the devices ID. The bit will be cleared o -nce the operation done.1: enable 0: disable..*/ -#define SPI_MEM_FLASH_RES (BIT(20)) -#define SPI_MEM_FLASH_RES_M (BIT(20)) -#define SPI_MEM_FLASH_RES_V 0x1 -#define SPI_MEM_FLASH_RES_S 20 -/* SPI_MEM_FLASH_HPM : R/W/SC ;bitpos:[19] ;default: 1'b0 ; */ -/*description: Drive Flash into high performance mode. The bit will be cleared once the operat -ion done.1: enable 0: disable..*/ -#define SPI_MEM_FLASH_HPM (BIT(19)) -#define SPI_MEM_FLASH_HPM_M (BIT(19)) -#define SPI_MEM_FLASH_HPM_V 0x1 -#define SPI_MEM_FLASH_HPM_S 19 -/* SPI_MEM_USR : HRO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared. An operat -ion will be triggered when the bit is set. The bit will be cleared once the oper -ation done.1: enable 0: disable..*/ -#define SPI_MEM_USR (BIT(18)) -#define SPI_MEM_USR_M (BIT(18)) -#define SPI_MEM_USR_V 0x1 -#define SPI_MEM_USR_S 18 -/* SPI_MEM_FLASH_PE : R/W/SC ;bitpos:[17] ;default: 1'b0 ; */ -/*description: In user mode, it is set to indicate that program/erase operation will be trigger -ed. The bit is combined with spi_mem_usr bit. The bit will be cleared once the o -peration done.1: enable 0: disable..*/ -#define SPI_MEM_FLASH_PE (BIT(17)) -#define SPI_MEM_FLASH_PE_M (BIT(17)) -#define SPI_MEM_FLASH_PE_V 0x1 -#define SPI_MEM_FLASH_PE_S 17 -/* SPI_MEM_SLV_ST : RO ;bitpos:[7:4] ;default: 4'b0 ; */ -/*description: The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation sta -te, 2: send command state, 3: send address state, 4: wait state, 5: read data st -ate, 6:write data state, 7: done state, 8: read data end state..*/ -#define SPI_MEM_SLV_ST 0x0000000F -#define SPI_MEM_SLV_ST_M ((SPI_MEM_SLV_ST_V)<<(SPI_MEM_SLV_ST_S)) -#define SPI_MEM_SLV_ST_V 0xF -#define SPI_MEM_SLV_ST_S 4 -/* SPI_MEM_MST_ST : RO ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT -, 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA se -nt data is stored in SPI0 TX FIFO, 5: SPI0 write data state..*/ -#define SPI_MEM_MST_ST 0x0000000F -#define SPI_MEM_MST_ST_M ((SPI_MEM_MST_ST_V)<<(SPI_MEM_MST_ST_S)) -#define SPI_MEM_MST_ST_V 0xF -#define SPI_MEM_MST_ST_S 0 - -#define SPI_MEM_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x4) -/* SPI_MEM_USR_ADDR_VALUE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: In user mode, it is the memory address. other then the bit0-bit23 is the memory -address, the bit24-bit31 are the byte length of a transfer..*/ -#define SPI_MEM_USR_ADDR_VALUE 0xFFFFFFFF -#define SPI_MEM_USR_ADDR_VALUE_M ((SPI_MEM_USR_ADDR_VALUE_V)<<(SPI_MEM_USR_ADDR_VALUE_S)) -#define SPI_MEM_USR_ADDR_VALUE_V 0xFFFFFFFF -#define SPI_MEM_USR_ADDR_VALUE_S 0 - -#define SPI_MEM_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x8) -/* SPI_MEM_DATA_IE_ALWAYS_ON : R/W ;bitpos:[31] ;default: 1'b1 ; */ -/*description: When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are a -lways 1. 0: Others..*/ -#define SPI_MEM_DATA_IE_ALWAYS_ON (BIT(31)) -#define SPI_MEM_DATA_IE_ALWAYS_ON_M (BIT(31)) -#define SPI_MEM_DATA_IE_ALWAYS_ON_V 0x1 -#define SPI_MEM_DATA_IE_ALWAYS_ON_S 31 -/* SPI_MEM_DQS_IE_ALWAYS_ON : HRO ;bitpos:[30] ;default: 1'b0 ; */ -/*description: When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are alway -s 1. 0: Others..*/ -#define SPI_MEM_DQS_IE_ALWAYS_ON (BIT(30)) -#define SPI_MEM_DQS_IE_ALWAYS_ON_M (BIT(30)) -#define SPI_MEM_DQS_IE_ALWAYS_ON_V 0x1 -#define SPI_MEM_DQS_IE_ALWAYS_ON_S 30 -/* SPI_MEM_FREAD_QIO : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: In the read operations address phase and read-data phase apply 4 signals. 1: ena -ble 0: disable..*/ -#define SPI_MEM_FREAD_QIO (BIT(24)) -#define SPI_MEM_FREAD_QIO_M (BIT(24)) -#define SPI_MEM_FREAD_QIO_V 0x1 -#define SPI_MEM_FREAD_QIO_S 24 -/* SPI_MEM_FREAD_DIO : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: In the read operations address phase and read-data phase apply 2 signals. 1: ena -ble 0: disable..*/ -#define SPI_MEM_FREAD_DIO (BIT(23)) -#define SPI_MEM_FREAD_DIO_M (BIT(23)) -#define SPI_MEM_FREAD_DIO_V 0x1 -#define SPI_MEM_FREAD_DIO_S 23 -/* SPI_MEM_WRSR_2B : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: two bytes data will be written to status register when it is set. 1: enable 0: d -isable..*/ -#define SPI_MEM_WRSR_2B (BIT(22)) -#define SPI_MEM_WRSR_2B_M (BIT(22)) -#define SPI_MEM_WRSR_2B_V 0x1 -#define SPI_MEM_WRSR_2B_S 22 -/* SPI_MEM_WP_REG : R/W ;bitpos:[21] ;default: 1'b1 ; */ -/*description: Write protect signal output when SPI is idle. 1: output high, 0: output low..*/ -#define SPI_MEM_WP_REG (BIT(21)) -#define SPI_MEM_WP_REG_M (BIT(21)) -#define SPI_MEM_WP_REG_V 0x1 -#define SPI_MEM_WP_REG_S 21 -/* SPI_MEM_FREAD_QUAD : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: In the read operations read-data phase apply 4 signals. 1: enable 0: disable..*/ -#define SPI_MEM_FREAD_QUAD (BIT(20)) -#define SPI_MEM_FREAD_QUAD_M (BIT(20)) -#define SPI_MEM_FREAD_QUAD_V 0x1 -#define SPI_MEM_FREAD_QUAD_S 20 -/* SPI_MEM_D_POL : R/W ;bitpos:[19] ;default: 1'b1 ; */ -/*description: The bit is used to set MOSI line polarity, 1: high 0, low.*/ -#define SPI_MEM_D_POL (BIT(19)) -#define SPI_MEM_D_POL_M (BIT(19)) -#define SPI_MEM_D_POL_V 0x1 -#define SPI_MEM_D_POL_S 19 -/* SPI_MEM_Q_POL : R/W ;bitpos:[18] ;default: 1'b1 ; */ -/*description: The bit is used to set MISO line polarity, 1: high 0, low.*/ -#define SPI_MEM_Q_POL (BIT(18)) -#define SPI_MEM_Q_POL_M (BIT(18)) -#define SPI_MEM_Q_POL_V 0x1 -#define SPI_MEM_Q_POL_S 18 -/* SPI_MEM_RESANDRES : R/W ;bitpos:[15] ;default: 1'b1 ; */ -/*description: The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with -spi_mem_flash_res bit. 1: enable 0: disable..*/ -#define SPI_MEM_RESANDRES (BIT(15)) -#define SPI_MEM_RESANDRES_M (BIT(15)) -#define SPI_MEM_RESANDRES_V 0x1 -#define SPI_MEM_RESANDRES_S 15 -/* SPI_MEM_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: In the read operations, read-data phase apply 2 signals. 1: enable 0: disable..*/ -#define SPI_MEM_FREAD_DUAL (BIT(14)) -#define SPI_MEM_FREAD_DUAL_M (BIT(14)) -#define SPI_MEM_FREAD_DUAL_V 0x1 -#define SPI_MEM_FREAD_DUAL_S 14 -/* SPI_MEM_FASTRD_MODE : R/W ;bitpos:[13] ;default: 1'b1 ; */ -/*description: This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QO -UT and SPI_MEM_FREAD_DOUT. 1: enable 0: disable..*/ -#define SPI_MEM_FASTRD_MODE (BIT(13)) -#define SPI_MEM_FASTRD_MODE_M (BIT(13)) -#define SPI_MEM_FASTRD_MODE_V 0x1 -#define SPI_MEM_FASTRD_MODE_S 13 -/* SPI_MEM_TX_CRC_EN : HRO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disabl -e.*/ -#define SPI_MEM_TX_CRC_EN (BIT(11)) -#define SPI_MEM_TX_CRC_EN_M (BIT(11)) -#define SPI_MEM_TX_CRC_EN_V 0x1 -#define SPI_MEM_TX_CRC_EN_S 11 -/* SPI_MEM_FCS_CRC_EN : HRO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: For SPI1, initialize crc32 module before writing encrypted data to flash. Activ -e low..*/ -#define SPI_MEM_FCS_CRC_EN (BIT(10)) -#define SPI_MEM_FCS_CRC_EN_M (BIT(10)) -#define SPI_MEM_FCS_CRC_EN_V 0x1 -#define SPI_MEM_FCS_CRC_EN_S 10 -/* SPI_MEM_FCMD_OCT : HRO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: Apply 8 signals during command phase 1:enable 0: disable.*/ -#define SPI_MEM_FCMD_OCT (BIT(9)) -#define SPI_MEM_FCMD_OCT_M (BIT(9)) -#define SPI_MEM_FCMD_OCT_V 0x1 -#define SPI_MEM_FCMD_OCT_S 9 -/* SPI_MEM_FCMD_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Apply 4 signals during command phase 1:enable 0: disable.*/ -#define SPI_MEM_FCMD_QUAD (BIT(8)) -#define SPI_MEM_FCMD_QUAD_M (BIT(8)) -#define SPI_MEM_FCMD_QUAD_V 0x1 -#define SPI_MEM_FCMD_QUAD_S 8 -/* SPI_MEM_FADDR_OCT : HRO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Apply 8 signals during address phase 1:enable 0: disable.*/ -#define SPI_MEM_FADDR_OCT (BIT(6)) -#define SPI_MEM_FADDR_OCT_M (BIT(6)) -#define SPI_MEM_FADDR_OCT_V 0x1 -#define SPI_MEM_FADDR_OCT_S 6 -/* SPI_MEM_FDIN_OCT : HRO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Apply 8 signals during read-data phase 1:enable 0: disable.*/ -#define SPI_MEM_FDIN_OCT (BIT(5)) -#define SPI_MEM_FDIN_OCT_M (BIT(5)) -#define SPI_MEM_FDIN_OCT_V 0x1 -#define SPI_MEM_FDIN_OCT_S 5 -/* SPI_MEM_FDOUT_OCT : HRO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Apply 8 signals during write-data phase 1:enable 0: disable.*/ -#define SPI_MEM_FDOUT_OCT (BIT(4)) -#define SPI_MEM_FDOUT_OCT_M (BIT(4)) -#define SPI_MEM_FDOUT_OCT_V 0x1 -#define SPI_MEM_FDOUT_OCT_S 4 -/* SPI_MEM_FDUMMY_WOUT : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] -is output by the MSPI controller in the second half part of dummy phase. It is u -sed to pre-drive flash..*/ -#define SPI_MEM_FDUMMY_WOUT (BIT(3)) -#define SPI_MEM_FDUMMY_WOUT_M (BIT(3)) -#define SPI_MEM_FDUMMY_WOUT_V 0x1 -#define SPI_MEM_FDUMMY_WOUT_S 3 -/* SPI_MEM_FDUMMY_RIN : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] i -s output by the MSPI controller in the first half part of dummy phase. It is use -d to mask invalid SPI_DQS in the half part of dummy phase..*/ -#define SPI_MEM_FDUMMY_RIN (BIT(2)) -#define SPI_MEM_FDUMMY_RIN_M (BIT(2)) -#define SPI_MEM_FDUMMY_RIN_V 0x1 -#define SPI_MEM_FDUMMY_RIN_S 2 -/* SPI_MEM_WDUMMY_ALWAYS_OUT : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: In the dummy phase of an MSPI write data transfer when accesses to flash, the le -vel of SPI_IO[7:0] is output by the MSPI controller..*/ -#define SPI_MEM_WDUMMY_ALWAYS_OUT (BIT(1)) -#define SPI_MEM_WDUMMY_ALWAYS_OUT_M (BIT(1)) -#define SPI_MEM_WDUMMY_ALWAYS_OUT_V 0x1 -#define SPI_MEM_WDUMMY_ALWAYS_OUT_S 1 -/* SPI_MEM_WDUMMY_DQS_ALWAYS_OUT : HRO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: In the dummy phase of an MSPI write data transfer when accesses to flash, the le -vel of SPI_DQS is output by the MSPI controller..*/ -#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT (BIT(0)) -#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_M (BIT(0)) -#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_V 0x1 -#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_S 0 - -#define SPI_MEM_CTRL1_REG(i) (REG_SPI_MEM_BASE(i) + 0xC) -/* SPI_MEM_TXFIFO_RST : WT ;bitpos:[31] ;default: 1'b0 ; */ -/*description: The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to - send signals to AXI. Set this bit to reset these FIFO..*/ -#define SPI_MEM_TXFIFO_RST (BIT(31)) -#define SPI_MEM_TXFIFO_RST_M (BIT(31)) -#define SPI_MEM_TXFIFO_RST_V 0x1 -#define SPI_MEM_TXFIFO_RST_S 31 -/* SPI_MEM_RXFIFO_RST : WT ;bitpos:[30] ;default: 1'b0 ; */ -/*description: The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to - receive signals from AXI. Set this bit to reset these FIFO..*/ -#define SPI_MEM_RXFIFO_RST (BIT(30)) -#define SPI_MEM_RXFIFO_RST_M (BIT(30)) -#define SPI_MEM_RXFIFO_RST_V 0x1 -#define SPI_MEM_RXFIFO_RST_S 30 -/* SPI_MEM_FAST_WRITE_EN : R/W ;bitpos:[29] ;default: 1'b1 ; */ -/*description: Set this bit to write data faster, do not wait write data has been stored in tx_ -bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored -in tx_bus_fifo_l2..*/ -#define SPI_MEM_FAST_WRITE_EN (BIT(29)) -#define SPI_MEM_FAST_WRITE_EN_M (BIT(29)) -#define SPI_MEM_FAST_WRITE_EN_V 0x1 -#define SPI_MEM_FAST_WRITE_EN_S 29 -/* SPI_MEM_DUAL_RAM_EN : HRO ;bitpos:[28] ;default: 1'b0 ; */ -/*description: Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at -the same time..*/ -#define SPI_MEM_DUAL_RAM_EN (BIT(28)) -#define SPI_MEM_DUAL_RAM_EN_M (BIT(28)) -#define SPI_MEM_DUAL_RAM_EN_V 0x1 -#define SPI_MEM_DUAL_RAM_EN_S 28 -/* SPI_MEM_RAM0_EN : HRO ;bitpos:[27] ;default: 1'b1 ; */ -/*description: When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be ac -cessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 wi -ll be accessed. When SPI_MEM_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be ac -cessed at the same time..*/ -#define SPI_MEM_RAM0_EN (BIT(27)) -#define SPI_MEM_RAM0_EN_M (BIT(27)) -#define SPI_MEM_RAM0_EN_V 0x1 -#define SPI_MEM_RAM0_EN_S 27 -/* SPI_MEM_AW_SPLICE_EN : HRO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: Set this bit to enable AXI Write Splice-transfer..*/ -#define SPI_MEM_AW_SPLICE_EN (BIT(26)) -#define SPI_MEM_AW_SPLICE_EN_M (BIT(26)) -#define SPI_MEM_AW_SPLICE_EN_V 0x1 -#define SPI_MEM_AW_SPLICE_EN_S 26 -/* SPI_MEM_AR_SPLICE_EN : HRO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: Set this bit to enable AXI Read Splice-transfer..*/ -#define SPI_MEM_AR_SPLICE_EN (BIT(25)) -#define SPI_MEM_AR_SPLICE_EN_M (BIT(25)) -#define SPI_MEM_AR_SPLICE_EN_V 0x1 -#define SPI_MEM_AR_SPLICE_EN_S 25 -/* SPI_MEM_RRESP_ECC_ERR_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY - when there is a ECC error in AXI read data. The ECC error information is record -ed in SPI_MEM_ECC_ERR_ADDR_REG..*/ -#define SPI_MEM_RRESP_ECC_ERR_EN (BIT(24)) -#define SPI_MEM_RRESP_ECC_ERR_EN_M (BIT(24)) -#define SPI_MEM_RRESP_ECC_ERR_EN_V 0x1 -#define SPI_MEM_RRESP_ECC_ERR_EN_S 24 -/* SPI_MEM_SPI_AXI_RDATA_BACK_FAST : HRO ;bitpos:[23] ;default: 1'b1 ; */ -/*description: 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: R -eply AXI read data to AXI bus when all the read data is available..*/ -#define SPI_MEM_SPI_AXI_RDATA_BACK_FAST (BIT(23)) -#define SPI_MEM_SPI_AXI_RDATA_BACK_FAST_M (BIT(23)) -#define SPI_MEM_SPI_AXI_RDATA_BACK_FAST_V 0x1 -#define SPI_MEM_SPI_AXI_RDATA_BACK_FAST_S 23 -/* SPI_MEM_SPI_AW_SIZE0_1_SUPPORT_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */ -/*description: 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR..*/ -#define SPI_MEM_SPI_AW_SIZE0_1_SUPPORT_EN (BIT(22)) -#define SPI_MEM_SPI_AW_SIZE0_1_SUPPORT_EN_M (BIT(22)) -#define SPI_MEM_SPI_AW_SIZE0_1_SUPPORT_EN_V 0x1 -#define SPI_MEM_SPI_AW_SIZE0_1_SUPPORT_EN_S 22 -/* SPI_MEM_SPI_AR_SIZE0_1_SUPPORT_EN : R/W ;bitpos:[21] ;default: 1'b1 ; */ -/*description: 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and repl -y the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR..*/ -#define SPI_MEM_SPI_AR_SIZE0_1_SUPPORT_EN (BIT(21)) -#define SPI_MEM_SPI_AR_SIZE0_1_SUPPORT_EN_M (BIT(21)) -#define SPI_MEM_SPI_AR_SIZE0_1_SUPPORT_EN_V 0x1 -#define SPI_MEM_SPI_AR_SIZE0_1_SUPPORT_EN_S 21 -/* SPI_MEM_CS_HOLD_DLY_RES : R/W ;bitpos:[11:2] ;default: 10'h3ff ; */ -/*description: After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 5 -12) SPI_CLK cycles..*/ -#define SPI_MEM_CS_HOLD_DLY_RES 0x000003FF -#define SPI_MEM_CS_HOLD_DLY_RES_M ((SPI_MEM_CS_HOLD_DLY_RES_V)<<(SPI_MEM_CS_HOLD_DLY_RES_S)) -#define SPI_MEM_CS_HOLD_DLY_RES_V 0x3FF -#define SPI_MEM_CS_HOLD_DLY_RES_S 2 -/* SPI_MEM_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delaye -d one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inacti -ve 3: SPI clock is alwasy on..*/ -#define SPI_MEM_CLK_MODE 0x00000003 -#define SPI_MEM_CLK_MODE_M ((SPI_MEM_CLK_MODE_V)<<(SPI_MEM_CLK_MODE_S)) -#define SPI_MEM_CLK_MODE_V 0x3 -#define SPI_MEM_CLK_MODE_S 0 - -#define SPI_MEM_CTRL2_REG(i) (REG_SPI_MEM_BASE(i) + 0x10) -/* SPI_MEM_SYNC_RESET : WT ;bitpos:[31] ;default: 1'b0 ; */ -/*description: The spi0_mst_st and spi0_slv_st will be reset..*/ -#define SPI_MEM_SYNC_RESET (BIT(31)) -#define SPI_MEM_SYNC_RESET_M (BIT(31)) -#define SPI_MEM_SYNC_RESET_V 0x1 -#define SPI_MEM_SYNC_RESET_S 31 -/* SPI_MEM_CS_HOLD_DELAY : R/W ;bitpos:[30:25] ;default: 6'd0 ; */ -/*description: These bits are used to set the minimum CS high time tSHSL between SPI burst tran -sfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core - clock cycles..*/ -#define SPI_MEM_CS_HOLD_DELAY 0x0000003F -#define SPI_MEM_CS_HOLD_DELAY_M ((SPI_MEM_CS_HOLD_DELAY_V)<<(SPI_MEM_CS_HOLD_DELAY_S)) -#define SPI_MEM_CS_HOLD_DELAY_V 0x3F -#define SPI_MEM_CS_HOLD_DELAY_S 25 -/* SPI_MEM_SPLIT_TRANS_EN : R/W ;bitpos:[24] ;default: 1'b1 ; */ -/*description: Set this bit to enable SPI0 split one AXI read flash transfer into two SPI trans -fers when one transfer will cross flash or EXT_RAM page corner, valid no matter -whether there is an ECC region or not..*/ -#define SPI_MEM_SPLIT_TRANS_EN (BIT(24)) -#define SPI_MEM_SPLIT_TRANS_EN_M (BIT(24)) -#define SPI_MEM_SPLIT_TRANS_EN_V 0x1 -#define SPI_MEM_SPLIT_TRANS_EN_S 24 -/* SPI_MEM_ECC_16TO18_BYTE_EN : HRO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode whe -n accesses flash..*/ -#define SPI_MEM_ECC_16TO18_BYTE_EN (BIT(14)) -#define SPI_MEM_ECC_16TO18_BYTE_EN_M (BIT(14)) -#define SPI_MEM_ECC_16TO18_BYTE_EN_V 0x1 -#define SPI_MEM_ECC_16TO18_BYTE_EN_S 14 -/* SPI_MEM_ECC_SKIP_PAGE_CORNER : HRO ;bitpos:[13] ;default: 1'b1 ; */ -/*description: 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner w -hen accesses flash..*/ -#define SPI_MEM_ECC_SKIP_PAGE_CORNER (BIT(13)) -#define SPI_MEM_ECC_SKIP_PAGE_CORNER_M (BIT(13)) -#define SPI_MEM_ECC_SKIP_PAGE_CORNER_V 0x1 -#define SPI_MEM_ECC_SKIP_PAGE_CORNER_S 13 -/* SPI_MEM_ECC_CS_HOLD_TIME : HRO ;bitpos:[12:10] ;default: 3'd3 ; */ -/*description: SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC - mode when accessed flash..*/ -#define SPI_MEM_ECC_CS_HOLD_TIME 0x00000007 -#define SPI_MEM_ECC_CS_HOLD_TIME_M ((SPI_MEM_ECC_CS_HOLD_TIME_V)<<(SPI_MEM_ECC_CS_HOLD_TIME_S)) -#define SPI_MEM_ECC_CS_HOLD_TIME_V 0x7 -#define SPI_MEM_ECC_CS_HOLD_TIME_S 10 -/* SPI_MEM_CS_HOLD_TIME : R/W ;bitpos:[9:5] ;default: 5'h1 ; */ -/*description: SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined wi -th SPI_MEM_CS_HOLD bit..*/ -#define SPI_MEM_CS_HOLD_TIME 0x0000001F -#define SPI_MEM_CS_HOLD_TIME_M ((SPI_MEM_CS_HOLD_TIME_V)<<(SPI_MEM_CS_HOLD_TIME_S)) -#define SPI_MEM_CS_HOLD_TIME_V 0x1F -#define SPI_MEM_CS_HOLD_TIME_S 5 -/* SPI_MEM_CS_SETUP_TIME : R/W ;bitpos:[4:0] ;default: 5'h1 ; */ -/*description: (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with SPI_ME -M_CS_SETUP bit..*/ -#define SPI_MEM_CS_SETUP_TIME 0x0000001F -#define SPI_MEM_CS_SETUP_TIME_M ((SPI_MEM_CS_SETUP_TIME_V)<<(SPI_MEM_CS_SETUP_TIME_S)) -#define SPI_MEM_CS_SETUP_TIME_V 0x1F -#define SPI_MEM_CS_SETUP_TIME_S 0 - -#define SPI_MEM_CLOCK_REG(i) (REG_SPI_MEM_BASE(i) + 0x14) -/* SPI_MEM_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: 1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module - clock..*/ -#define SPI_MEM_CLK_EQU_SYSCLK (BIT(31)) -#define SPI_MEM_CLK_EQU_SYSCLK_M (BIT(31)) -#define SPI_MEM_CLK_EQU_SYSCLK_V 0x1 -#define SPI_MEM_CLK_EQU_SYSCLK_S 31 -/* SPI_MEM_CLKCNT_N : R/W ;bitpos:[23:16] ;default: 8'h3 ; */ -/*description: In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is - system/(spi_mem_clkcnt_N+1).*/ -#define SPI_MEM_CLKCNT_N 0x000000FF -#define SPI_MEM_CLKCNT_N_M ((SPI_MEM_CLKCNT_N_V)<<(SPI_MEM_CLKCNT_N_S)) -#define SPI_MEM_CLKCNT_N_V 0xFF -#define SPI_MEM_CLKCNT_N_S 16 -/* SPI_MEM_CLKCNT_H : R/W ;bitpos:[15:8] ;default: 8'h1 ; */ -/*description: In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1)..*/ -#define SPI_MEM_CLKCNT_H 0x000000FF -#define SPI_MEM_CLKCNT_H_M ((SPI_MEM_CLKCNT_H_V)<<(SPI_MEM_CLKCNT_H_S)) -#define SPI_MEM_CLKCNT_H_V 0xFF -#define SPI_MEM_CLKCNT_H_S 8 -/* SPI_MEM_CLKCNT_L : R/W ;bitpos:[7:0] ;default: 8'h3 ; */ -/*description: In the master mode it must be equal to spi_mem_clkcnt_N..*/ -#define SPI_MEM_CLKCNT_L 0x000000FF -#define SPI_MEM_CLKCNT_L_M ((SPI_MEM_CLKCNT_L_V)<<(SPI_MEM_CLKCNT_L_S)) -#define SPI_MEM_CLKCNT_L_V 0xFF -#define SPI_MEM_CLKCNT_L_S 0 - -#define SPI_MEM_USER_REG(i) (REG_SPI_MEM_BASE(i) + 0x18) -/* SPI_MEM_USR_COMMAND : R/W ;bitpos:[31] ;default: 1'b1 ; */ -/*description: This bit enable the command phase of an operation..*/ -#define SPI_MEM_USR_COMMAND (BIT(31)) -#define SPI_MEM_USR_COMMAND_M (BIT(31)) -#define SPI_MEM_USR_COMMAND_V 0x1 -#define SPI_MEM_USR_COMMAND_S 31 -/* SPI_MEM_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: This bit enable the address phase of an operation..*/ -#define SPI_MEM_USR_ADDR (BIT(30)) -#define SPI_MEM_USR_ADDR_M (BIT(30)) -#define SPI_MEM_USR_ADDR_V 0x1 -#define SPI_MEM_USR_ADDR_S 30 -/* SPI_MEM_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: This bit enable the dummy phase of an operation..*/ -#define SPI_MEM_USR_DUMMY (BIT(29)) -#define SPI_MEM_USR_DUMMY_M (BIT(29)) -#define SPI_MEM_USR_DUMMY_V 0x1 -#define SPI_MEM_USR_DUMMY_S 29 -/* SPI_MEM_USR_MISO : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: This bit enable the read-data phase of an operation..*/ -#define SPI_MEM_USR_MISO (BIT(28)) -#define SPI_MEM_USR_MISO_M (BIT(28)) -#define SPI_MEM_USR_MISO_V 0x1 -#define SPI_MEM_USR_MISO_S 28 -/* SPI_MEM_USR_MOSI : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: This bit enable the write-data phase of an operation..*/ -#define SPI_MEM_USR_MOSI (BIT(27)) -#define SPI_MEM_USR_MOSI_M (BIT(27)) -#define SPI_MEM_USR_MOSI_V 0x1 -#define SPI_MEM_USR_MOSI_S 27 -/* SPI_MEM_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: spi clock is disable in dummy phase when the bit is enable..*/ -#define SPI_MEM_USR_DUMMY_IDLE (BIT(26)) -#define SPI_MEM_USR_DUMMY_IDLE_M (BIT(26)) -#define SPI_MEM_USR_DUMMY_IDLE_V 0x1 -#define SPI_MEM_USR_DUMMY_IDLE_S 26 -/* SPI_MEM_USR_MOSI_HIGHPART : HRO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. -1: enable 0: disable..*/ -#define SPI_MEM_USR_MOSI_HIGHPART (BIT(25)) -#define SPI_MEM_USR_MOSI_HIGHPART_M (BIT(25)) -#define SPI_MEM_USR_MOSI_HIGHPART_V 0x1 -#define SPI_MEM_USR_MOSI_HIGHPART_S 25 -/* SPI_MEM_USR_MISO_HIGHPART : HRO ;bitpos:[24] ;default: 1'b0 ; */ -/*description: read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1 -: enable 0: disable..*/ -#define SPI_MEM_USR_MISO_HIGHPART (BIT(24)) -#define SPI_MEM_USR_MISO_HIGHPART_M (BIT(24)) -#define SPI_MEM_USR_MISO_HIGHPART_V 0x1 -#define SPI_MEM_USR_MISO_HIGHPART_S 24 -/* SPI_MEM_FWRITE_QIO : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: In the write operations address phase and read-data phase apply 4 signals..*/ -#define SPI_MEM_FWRITE_QIO (BIT(15)) -#define SPI_MEM_FWRITE_QIO_M (BIT(15)) -#define SPI_MEM_FWRITE_QIO_V 0x1 -#define SPI_MEM_FWRITE_QIO_S 15 -/* SPI_MEM_FWRITE_DIO : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: In the write operations address phase and read-data phase apply 2 signals..*/ -#define SPI_MEM_FWRITE_DIO (BIT(14)) -#define SPI_MEM_FWRITE_DIO_M (BIT(14)) -#define SPI_MEM_FWRITE_DIO_V 0x1 -#define SPI_MEM_FWRITE_DIO_S 14 -/* SPI_MEM_FWRITE_QUAD : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: In the write operations read-data phase apply 4 signals.*/ -#define SPI_MEM_FWRITE_QUAD (BIT(13)) -#define SPI_MEM_FWRITE_QUAD_M (BIT(13)) -#define SPI_MEM_FWRITE_QUAD_V 0x1 -#define SPI_MEM_FWRITE_QUAD_S 13 -/* SPI_MEM_FWRITE_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: In the write operations read-data phase apply 2 signals.*/ -#define SPI_MEM_FWRITE_DUAL (BIT(12)) -#define SPI_MEM_FWRITE_DUAL_M (BIT(12)) -#define SPI_MEM_FWRITE_DUAL_V 0x1 -#define SPI_MEM_FWRITE_DUAL_S 12 -/* SPI_MEM_CK_OUT_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3..*/ -#define SPI_MEM_CK_OUT_EDGE (BIT(9)) -#define SPI_MEM_CK_OUT_EDGE_M (BIT(9)) -#define SPI_MEM_CK_OUT_EDGE_V 0x1 -#define SPI_MEM_CK_OUT_EDGE_S 9 -/* SPI_MEM_CS_SETUP : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: spi cs is enable when spi is in prepare phase. 1: enable 0: disable..*/ -#define SPI_MEM_CS_SETUP (BIT(7)) -#define SPI_MEM_CS_SETUP_M (BIT(7)) -#define SPI_MEM_CS_SETUP_V 0x1 -#define SPI_MEM_CS_SETUP_S 7 -/* SPI_MEM_CS_HOLD : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: spi cs keep low when spi is in done phase. 1: enable 0: disable..*/ -#define SPI_MEM_CS_HOLD (BIT(6)) -#define SPI_MEM_CS_HOLD_M (BIT(6)) -#define SPI_MEM_CS_HOLD_V 0x1 -#define SPI_MEM_CS_HOLD_S 6 - -#define SPI_MEM_USER1_REG(i) (REG_SPI_MEM_BASE(i) + 0x1C) -/* SPI_MEM_USR_ADDR_BITLEN : R/W ;bitpos:[31:26] ;default: 6'd23 ; */ -/*description: The length in bits of address phase. The register value shall be (bit_num-1)..*/ -#define SPI_MEM_USR_ADDR_BITLEN 0x0000003F -#define SPI_MEM_USR_ADDR_BITLEN_M ((SPI_MEM_USR_ADDR_BITLEN_V)<<(SPI_MEM_USR_ADDR_BITLEN_S)) -#define SPI_MEM_USR_ADDR_BITLEN_V 0x3F -#define SPI_MEM_USR_ADDR_BITLEN_S 26 -/* SPI_MEM_USR_DBYTELEN : HRO ;bitpos:[8:6] ;default: 3'd1 ; */ -/*description: SPI0 USR_CMD read or write data byte length -1.*/ -#define SPI_MEM_USR_DBYTELEN 0x00000007 -#define SPI_MEM_USR_DBYTELEN_M ((SPI_MEM_USR_DBYTELEN_V)<<(SPI_MEM_USR_DBYTELEN_S)) -#define SPI_MEM_USR_DBYTELEN_V 0x7 -#define SPI_MEM_USR_DBYTELEN_S 6 -/* SPI_MEM_USR_DUMMY_CYCLELEN : R/W ;bitpos:[5:0] ;default: 6'd7 ; */ -/*description: The length in spi_mem_clk cycles of dummy phase. The register value shall be (cy -cle_num-1)..*/ -#define SPI_MEM_USR_DUMMY_CYCLELEN 0x0000003F -#define SPI_MEM_USR_DUMMY_CYCLELEN_M ((SPI_MEM_USR_DUMMY_CYCLELEN_V)<<(SPI_MEM_USR_DUMMY_CYCLELEN_S)) -#define SPI_MEM_USR_DUMMY_CYCLELEN_V 0x3F -#define SPI_MEM_USR_DUMMY_CYCLELEN_S 0 - -#define SPI_MEM_USER2_REG(i) (REG_SPI_MEM_BASE(i) + 0x20) -/* SPI_MEM_USR_COMMAND_BITLEN : R/W ;bitpos:[31:28] ;default: 4'd7 ; */ -/*description: The length in bits of command phase. The register value shall be (bit_num-1).*/ -#define SPI_MEM_USR_COMMAND_BITLEN 0x0000000F -#define SPI_MEM_USR_COMMAND_BITLEN_M ((SPI_MEM_USR_COMMAND_BITLEN_V)<<(SPI_MEM_USR_COMMAND_BITLEN_S)) -#define SPI_MEM_USR_COMMAND_BITLEN_V 0xF -#define SPI_MEM_USR_COMMAND_BITLEN_S 28 -/* SPI_MEM_USR_COMMAND_VALUE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */ -/*description: The value of command..*/ -#define SPI_MEM_USR_COMMAND_VALUE 0x0000FFFF -#define SPI_MEM_USR_COMMAND_VALUE_M ((SPI_MEM_USR_COMMAND_VALUE_V)<<(SPI_MEM_USR_COMMAND_VALUE_S)) -#define SPI_MEM_USR_COMMAND_VALUE_V 0xFFFF -#define SPI_MEM_USR_COMMAND_VALUE_S 0 - -#define SPI_MEM_MOSI_DLEN_REG(i) (REG_SPI_MEM_BASE(i) + 0x24) -/* SPI_MEM_USR_MOSI_DBITLEN : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: The length in bits of write-data. The register value shall be (bit_num-1)..*/ -#define SPI_MEM_USR_MOSI_DBITLEN 0x000003FF -#define SPI_MEM_USR_MOSI_DBITLEN_M ((SPI_MEM_USR_MOSI_DBITLEN_V)<<(SPI_MEM_USR_MOSI_DBITLEN_S)) -#define SPI_MEM_USR_MOSI_DBITLEN_V 0x3FF -#define SPI_MEM_USR_MOSI_DBITLEN_S 0 - -#define SPI_MEM_MISO_DLEN_REG(i) (REG_SPI_MEM_BASE(i) + 0x28) -/* SPI_MEM_USR_MISO_DBITLEN : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ -/*description: The length in bits of read-data. The register value shall be (bit_num-1)..*/ -#define SPI_MEM_USR_MISO_DBITLEN 0x000003FF -#define SPI_MEM_USR_MISO_DBITLEN_M ((SPI_MEM_USR_MISO_DBITLEN_V)<<(SPI_MEM_USR_MISO_DBITLEN_S)) -#define SPI_MEM_USR_MISO_DBITLEN_V 0x3FF -#define SPI_MEM_USR_MISO_DBITLEN_S 0 - -#define SPI_MEM_RD_STATUS_REG(i) (REG_SPI_MEM_BASE(i) + 0x2C) -/* SPI_MEM_WB_MODE : R/W ;bitpos:[23:16] ;default: 8'h00 ; */ -/*description: Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode b -it..*/ -#define SPI_MEM_WB_MODE 0x000000FF -#define SPI_MEM_WB_MODE_M ((SPI_MEM_WB_MODE_V)<<(SPI_MEM_WB_MODE_S)) -#define SPI_MEM_WB_MODE_V 0xFF -#define SPI_MEM_WB_MODE_S 16 -/* SPI_MEM_STATUS : R/W/SS ;bitpos:[15:0] ;default: 16'b0 ; */ -/*description: The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit..*/ -#define SPI_MEM_STATUS 0x0000FFFF -#define SPI_MEM_STATUS_M ((SPI_MEM_STATUS_V)<<(SPI_MEM_STATUS_S)) -#define SPI_MEM_STATUS_V 0xFFFF -#define SPI_MEM_STATUS_S 0 - -#define SPI_MEM_MISC_REG(i) (REG_SPI_MEM_BASE(i) + 0x34) -/* SPI_MEM_CS_KEEP_ACTIVE : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: SPI_CS line keep low when the bit is set..*/ -#define SPI_MEM_CS_KEEP_ACTIVE (BIT(10)) -#define SPI_MEM_CS_KEEP_ACTIVE_M (BIT(10)) -#define SPI_MEM_CS_KEEP_ACTIVE_V 0x1 -#define SPI_MEM_CS_KEEP_ACTIVE_S 10 -/* SPI_MEM_CK_IDLE_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: 1: SPI_CLK line is high when idle 0: spi clk line is low when idle.*/ -#define SPI_MEM_CK_IDLE_EDGE (BIT(9)) -#define SPI_MEM_CK_IDLE_EDGE_M (BIT(9)) -#define SPI_MEM_CK_IDLE_EDGE_V 0x1 -#define SPI_MEM_CK_IDLE_EDGE_S 9 -/* SPI_MEM_SSUB_PIN : HRO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: For SPI0, sram is connected to SUBPINs..*/ -#define SPI_MEM_SSUB_PIN (BIT(8)) -#define SPI_MEM_SSUB_PIN_M (BIT(8)) -#define SPI_MEM_SSUB_PIN_V 0x1 -#define SPI_MEM_SSUB_PIN_S 8 -/* SPI_MEM_FSUB_PIN : HRO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: For SPI0, flash is connected to SUBPINs..*/ -#define SPI_MEM_FSUB_PIN (BIT(7)) -#define SPI_MEM_FSUB_PIN_M (BIT(7)) -#define SPI_MEM_FSUB_PIN_V 0x1 -#define SPI_MEM_FSUB_PIN_S 7 -/* SPI_MEM_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI d -evice, such as flash, external RAM and so on..*/ -#define SPI_MEM_CS1_DIS (BIT(1)) -#define SPI_MEM_CS1_DIS_M (BIT(1)) -#define SPI_MEM_CS1_DIS_V 0x1 -#define SPI_MEM_CS1_DIS_S 1 -/* SPI_MEM_CS0_DIS : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI d -evice, such as flash, external RAM and so on..*/ -#define SPI_MEM_CS0_DIS (BIT(0)) -#define SPI_MEM_CS0_DIS_M (BIT(0)) -#define SPI_MEM_CS0_DIS_V 0x1 -#define SPI_MEM_CS0_DIS_S 0 - -#define SPI_MEM_TX_CRC_REG(i) (REG_SPI_MEM_BASE(i) + 0x38) -/* SPI_MEM_TX_CRC_DATA : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */ -/*description: For SPI1, the value of crc32..*/ -#define SPI_MEM_TX_CRC_DATA 0xFFFFFFFF -#define SPI_MEM_TX_CRC_DATA_M ((SPI_MEM_TX_CRC_DATA_V)<<(SPI_MEM_TX_CRC_DATA_S)) -#define SPI_MEM_TX_CRC_DATA_V 0xFFFFFFFF -#define SPI_MEM_TX_CRC_DATA_S 0 - -#define SPI_MEM_CACHE_FCTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x3C) -/* SPI_MEM_SPI_CLOSE_AXI_INF_EN : R/W ;bitpos:[31] ;default: 1'b1 ; */ -/*description: Set this bit to close AXI read/write transfer to MSPI, which means that only SLV -_ERR will be replied to BRESP/RRESP..*/ -#define SPI_MEM_SPI_CLOSE_AXI_INF_EN (BIT(31)) -#define SPI_MEM_SPI_CLOSE_AXI_INF_EN_M (BIT(31)) -#define SPI_MEM_SPI_CLOSE_AXI_INF_EN_V 0x1 -#define SPI_MEM_SPI_CLOSE_AXI_INF_EN_S 31 -/* SPI_MEM_SPI_SAME_AW_AR_ADDR_CHK_EN : HRO ;bitpos:[30] ;default: 1'b1 ; */ -/*description: Set this bit to check AXI read/write the same address region..*/ -#define SPI_MEM_SPI_SAME_AW_AR_ADDR_CHK_EN (BIT(30)) -#define SPI_MEM_SPI_SAME_AW_AR_ADDR_CHK_EN_M (BIT(30)) -#define SPI_MEM_SPI_SAME_AW_AR_ADDR_CHK_EN_V 0x1 -#define SPI_MEM_SPI_SAME_AW_AR_ADDR_CHK_EN_S 30 -/* SPI_MEM_FADDR_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is - the same with spi_mem_fread_qio..*/ -#define SPI_MEM_FADDR_QUAD (BIT(8)) -#define SPI_MEM_FADDR_QUAD_M (BIT(8)) -#define SPI_MEM_FADDR_QUAD_V 0x1 -#define SPI_MEM_FADDR_QUAD_S 8 -/* SPI_MEM_FDOUT_QUAD : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is th -e same with spi_mem_fread_qio..*/ -#define SPI_MEM_FDOUT_QUAD (BIT(7)) -#define SPI_MEM_FDOUT_QUAD_M (BIT(7)) -#define SPI_MEM_FDOUT_QUAD_V 0x1 -#define SPI_MEM_FDOUT_QUAD_S 7 -/* SPI_MEM_FDIN_QUAD : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the - same with spi_mem_fread_qio..*/ -#define SPI_MEM_FDIN_QUAD (BIT(6)) -#define SPI_MEM_FDIN_QUAD_M (BIT(6)) -#define SPI_MEM_FDIN_QUAD_V 0x1 -#define SPI_MEM_FDIN_QUAD_S 6 -/* SPI_MEM_FADDR_DUAL : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is - the same with spi_mem_fread_dio..*/ -#define SPI_MEM_FADDR_DUAL (BIT(5)) -#define SPI_MEM_FADDR_DUAL_M (BIT(5)) -#define SPI_MEM_FADDR_DUAL_V 0x1 -#define SPI_MEM_FADDR_DUAL_S 5 -/* SPI_MEM_FDOUT_DUAL : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the - same with spi_mem_fread_dio..*/ -#define SPI_MEM_FDOUT_DUAL (BIT(4)) -#define SPI_MEM_FDOUT_DUAL_M (BIT(4)) -#define SPI_MEM_FDOUT_DUAL_V 0x1 -#define SPI_MEM_FDOUT_DUAL_S 4 -/* SPI_MEM_FDIN_DUAL : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the -same with spi_mem_fread_dio..*/ -#define SPI_MEM_FDIN_DUAL (BIT(3)) -#define SPI_MEM_FDIN_DUAL_M (BIT(3)) -#define SPI_MEM_FDIN_DUAL_V 0x1 -#define SPI_MEM_FDIN_DUAL_S 3 -/* SPI_MEM_CACHE_FLASH_USR_CMD : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: For SPI0, cache read flash for user define command, 1: enable, 0:disable..*/ -#define SPI_MEM_CACHE_FLASH_USR_CMD (BIT(2)) -#define SPI_MEM_CACHE_FLASH_USR_CMD_M (BIT(2)) -#define SPI_MEM_CACHE_FLASH_USR_CMD_V 0x1 -#define SPI_MEM_CACHE_FLASH_USR_CMD_S 2 -/* SPI_MEM_CACHE_USR_ADDR_4BYTE : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable..*/ -#define SPI_MEM_CACHE_USR_ADDR_4BYTE (BIT(1)) -#define SPI_MEM_CACHE_USR_ADDR_4BYTE_M (BIT(1)) -#define SPI_MEM_CACHE_USR_ADDR_4BYTE_V 0x1 -#define SPI_MEM_CACHE_USR_ADDR_4BYTE_S 1 -/* SPI_MEM_AXI_REQ_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: For SPI0, AXI master access enable, 1: enable, 0:disable..*/ -#define SPI_MEM_AXI_REQ_EN (BIT(0)) -#define SPI_MEM_AXI_REQ_EN_M (BIT(0)) -#define SPI_MEM_AXI_REQ_EN_V 0x1 -#define SPI_MEM_AXI_REQ_EN_S 0 - -#define SPI_MEM_CACHE_SCTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x40) -/* SPI_MEM_SRAM_WDUMMY_CYCLELEN : HRO ;bitpos:[27:22] ;default: 6'b1 ; */ -/*description: For SPI0, In the external RAM mode, it is the length in bits of write dummy phas -e. The register value shall be (bit_num-1)..*/ -#define SPI_MEM_SRAM_WDUMMY_CYCLELEN 0x0000003F -#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_M ((SPI_MEM_SRAM_WDUMMY_CYCLELEN_V)<<(SPI_MEM_SRAM_WDUMMY_CYCLELEN_S)) -#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_V 0x3F -#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_S 22 -/* SPI_MEM_SRAM_OCT : HRO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: reserved.*/ -#define SPI_MEM_SRAM_OCT (BIT(21)) -#define SPI_MEM_SRAM_OCT_M (BIT(21)) -#define SPI_MEM_SRAM_OCT_V 0x1 -#define SPI_MEM_SRAM_OCT_S 21 -/* SPI_MEM_CACHE_SRAM_USR_WCMD : HRO ;bitpos:[20] ;default: 1'b1 ; */ -/*description: For SPI0, In the external RAM mode cache write sram for user define command.*/ -#define SPI_MEM_CACHE_SRAM_USR_WCMD (BIT(20)) -#define SPI_MEM_CACHE_SRAM_USR_WCMD_M (BIT(20)) -#define SPI_MEM_CACHE_SRAM_USR_WCMD_V 0x1 -#define SPI_MEM_CACHE_SRAM_USR_WCMD_S 20 -/* SPI_MEM_SRAM_ADDR_BITLEN : HRO ;bitpos:[19:14] ;default: 6'd23 ; */ -/*description: For SPI0, In the external RAM mode, it is the length in bits of address phase. T -he register value shall be (bit_num-1)..*/ -#define SPI_MEM_SRAM_ADDR_BITLEN 0x0000003F -#define SPI_MEM_SRAM_ADDR_BITLEN_M ((SPI_MEM_SRAM_ADDR_BITLEN_V)<<(SPI_MEM_SRAM_ADDR_BITLEN_S)) -#define SPI_MEM_SRAM_ADDR_BITLEN_V 0x3F -#define SPI_MEM_SRAM_ADDR_BITLEN_S 14 -/* SPI_MEM_SRAM_RDUMMY_CYCLELEN : HRO ;bitpos:[11:6] ;default: 6'b1 ; */ -/*description: For SPI0, In the external RAM mode, it is the length in bits of read dummy phase -. The register value shall be (bit_num-1)..*/ -#define SPI_MEM_SRAM_RDUMMY_CYCLELEN 0x0000003F -#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_M ((SPI_MEM_SRAM_RDUMMY_CYCLELEN_V)<<(SPI_MEM_SRAM_RDUMMY_CYCLELEN_S)) -#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_V 0x3F -#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_S 6 -/* SPI_MEM_CACHE_SRAM_USR_RCMD : HRO ;bitpos:[5] ;default: 1'b1 ; */ -/*description: For SPI0, In the external RAM mode cache read external RAM for user define comma -nd..*/ -#define SPI_MEM_CACHE_SRAM_USR_RCMD (BIT(5)) -#define SPI_MEM_CACHE_SRAM_USR_RCMD_M (BIT(5)) -#define SPI_MEM_CACHE_SRAM_USR_RCMD_V 0x1 -#define SPI_MEM_CACHE_SRAM_USR_RCMD_S 5 -/* SPI_MEM_USR_RD_SRAM_DUMMY : HRO ;bitpos:[4] ;default: 1'b1 ; */ -/*description: For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read - operations..*/ -#define SPI_MEM_USR_RD_SRAM_DUMMY (BIT(4)) -#define SPI_MEM_USR_RD_SRAM_DUMMY_M (BIT(4)) -#define SPI_MEM_USR_RD_SRAM_DUMMY_V 0x1 -#define SPI_MEM_USR_RD_SRAM_DUMMY_S 4 -/* SPI_MEM_USR_WR_SRAM_DUMMY : HRO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: For SPI0, In the external RAM mode, it is the enable bit of dummy phase for writ -e operations..*/ -#define SPI_MEM_USR_WR_SRAM_DUMMY (BIT(3)) -#define SPI_MEM_USR_WR_SRAM_DUMMY_M (BIT(3)) -#define SPI_MEM_USR_WR_SRAM_DUMMY_V 0x1 -#define SPI_MEM_USR_WR_SRAM_DUMMY_S 3 -/* SPI_MEM_USR_SRAM_QIO : HRO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disab -le.*/ -#define SPI_MEM_USR_SRAM_QIO (BIT(2)) -#define SPI_MEM_USR_SRAM_QIO_M (BIT(2)) -#define SPI_MEM_USR_SRAM_QIO_V 0x1 -#define SPI_MEM_USR_SRAM_QIO_S 2 -/* SPI_MEM_USR_SRAM_DIO : HRO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disab -le.*/ -#define SPI_MEM_USR_SRAM_DIO (BIT(1)) -#define SPI_MEM_USR_SRAM_DIO_M (BIT(1)) -#define SPI_MEM_USR_SRAM_DIO_V 0x1 -#define SPI_MEM_USR_SRAM_DIO_S 1 -/* SPI_MEM_CACHE_USR_SADDR_4BYTE : HRO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: en -able, 0:disable..*/ -#define SPI_MEM_CACHE_USR_SADDR_4BYTE (BIT(0)) -#define SPI_MEM_CACHE_USR_SADDR_4BYTE_M (BIT(0)) -#define SPI_MEM_CACHE_USR_SADDR_4BYTE_V 0x1 -#define SPI_MEM_CACHE_USR_SADDR_4BYTE_S 0 - -#define SPI_MEM_SRAM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x44) -/* SPI_MEM_SPI_SMEM_DATA_IE_ALWAYS_ON : HRO ;bitpos:[31] ;default: 1'b1 ; */ -/*description: When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0 -] are always 1. 0: Others..*/ -#define SPI_MEM_SPI_SMEM_DATA_IE_ALWAYS_ON (BIT(31)) -#define SPI_MEM_SPI_SMEM_DATA_IE_ALWAYS_ON_M (BIT(31)) -#define SPI_MEM_SPI_SMEM_DATA_IE_ALWAYS_ON_V 0x1 -#define SPI_MEM_SPI_SMEM_DATA_IE_ALWAYS_ON_S 31 -/* SPI_MEM_SPI_SMEM_DQS_IE_ALWAYS_ON : HRO ;bitpos:[30] ;default: 1'b1 ; */ -/*description: When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS ar -e always 1. 0: Others..*/ -#define SPI_MEM_SPI_SMEM_DQS_IE_ALWAYS_ON (BIT(30)) -#define SPI_MEM_SPI_SMEM_DQS_IE_ALWAYS_ON_M (BIT(30)) -#define SPI_MEM_SPI_SMEM_DQS_IE_ALWAYS_ON_V 0x1 -#define SPI_MEM_SPI_SMEM_DQS_IE_ALWAYS_ON_S 30 -/* SPI_MEM_SDOUT_HEX : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: For SPI0 external RAM , dout phase apply 16 signals. 1: enable 0: disable..*/ -#define SPI_MEM_SDOUT_HEX (BIT(27)) -#define SPI_MEM_SDOUT_HEX_M (BIT(27)) -#define SPI_MEM_SDOUT_HEX_V 0x1 -#define SPI_MEM_SDOUT_HEX_S 27 -/* SPI_MEM_SDIN_HEX : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: For SPI0 external RAM , din phase apply 16 signals. 1: enable 0: disable..*/ -#define SPI_MEM_SDIN_HEX (BIT(26)) -#define SPI_MEM_SDIN_HEX_M (BIT(26)) -#define SPI_MEM_SDIN_HEX_V 0x1 -#define SPI_MEM_SDIN_HEX_S 26 -/* SPI_MEM_SPI_SMEM_WDUMMY_ALWAYS_OUT : HRO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: In the dummy phase of an MSPI write data transfer when accesses to external RAM, - the level of SPI_IO[7:0] is output by the MSPI controller..*/ -#define SPI_MEM_SPI_SMEM_WDUMMY_ALWAYS_OUT (BIT(25)) -#define SPI_MEM_SPI_SMEM_WDUMMY_ALWAYS_OUT_M (BIT(25)) -#define SPI_MEM_SPI_SMEM_WDUMMY_ALWAYS_OUT_V 0x1 -#define SPI_MEM_SPI_SMEM_WDUMMY_ALWAYS_OUT_S 25 -/* SPI_MEM_SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT : HRO ;bitpos:[24] ;default: 1'b0 ; */ -/*description: In the dummy phase of an MSPI write data transfer when accesses to external RAM, - the level of SPI_DQS is output by the MSPI controller..*/ -#define SPI_MEM_SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT (BIT(24)) -#define SPI_MEM_SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_M (BIT(24)) -#define SPI_MEM_SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_V 0x1 -#define SPI_MEM_SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_S 24 -/* SPI_MEM_SDUMMY_WOUT : HRO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: In the dummy phase of a MSPI write data transfer when accesses to external RAM, -the signal level of SPI bus is output by the MSPI controller..*/ -#define SPI_MEM_SDUMMY_WOUT (BIT(23)) -#define SPI_MEM_SDUMMY_WOUT_M (BIT(23)) -#define SPI_MEM_SDUMMY_WOUT_V 0x1 -#define SPI_MEM_SDUMMY_WOUT_S 23 -/* SPI_MEM_SDUMMY_RIN : R/W ;bitpos:[22] ;default: 1'b1 ; */ -/*description: In the dummy phase of a MSPI read data transfer when accesses to external RAM, t -he signal level of SPI bus is output by the MSPI controller..*/ -#define SPI_MEM_SDUMMY_RIN (BIT(22)) -#define SPI_MEM_SDUMMY_RIN_M (BIT(22)) -#define SPI_MEM_SDUMMY_RIN_V 0x1 -#define SPI_MEM_SDUMMY_RIN_S 22 -/* SPI_MEM_SCMD_OCT : HRO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable..*/ -#define SPI_MEM_SCMD_OCT (BIT(21)) -#define SPI_MEM_SCMD_OCT_M (BIT(21)) -#define SPI_MEM_SCMD_OCT_V 0x1 -#define SPI_MEM_SCMD_OCT_S 21 -/* SPI_MEM_SADDR_OCT : HRO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable..*/ -#define SPI_MEM_SADDR_OCT (BIT(20)) -#define SPI_MEM_SADDR_OCT_M (BIT(20)) -#define SPI_MEM_SADDR_OCT_V 0x1 -#define SPI_MEM_SADDR_OCT_S 20 -/* SPI_MEM_SDOUT_OCT : HRO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable..*/ -#define SPI_MEM_SDOUT_OCT (BIT(19)) -#define SPI_MEM_SDOUT_OCT_M (BIT(19)) -#define SPI_MEM_SDOUT_OCT_V 0x1 -#define SPI_MEM_SDOUT_OCT_S 19 -/* SPI_MEM_SDIN_OCT : HRO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable..*/ -#define SPI_MEM_SDIN_OCT (BIT(18)) -#define SPI_MEM_SDIN_OCT_M (BIT(18)) -#define SPI_MEM_SDIN_OCT_V 0x1 -#define SPI_MEM_SDIN_OCT_S 18 -/* SPI_MEM_SCMD_QUAD : HRO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit - is the same with spi_mem_usr_sram_qio..*/ -#define SPI_MEM_SCMD_QUAD (BIT(17)) -#define SPI_MEM_SCMD_QUAD_M (BIT(17)) -#define SPI_MEM_SCMD_QUAD_V 0x1 -#define SPI_MEM_SCMD_QUAD_S 17 -/* SPI_MEM_SADDR_QUAD : HRO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The - bit is the same with spi_mem_usr_sram_qio..*/ -#define SPI_MEM_SADDR_QUAD (BIT(16)) -#define SPI_MEM_SADDR_QUAD_M (BIT(16)) -#define SPI_MEM_SADDR_QUAD_V 0x1 -#define SPI_MEM_SADDR_QUAD_S 16 -/* SPI_MEM_SDOUT_QUAD : HRO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bi -t is the same with spi_mem_usr_sram_qio..*/ -#define SPI_MEM_SDOUT_QUAD (BIT(15)) -#define SPI_MEM_SDOUT_QUAD_M (BIT(15)) -#define SPI_MEM_SDOUT_QUAD_V 0x1 -#define SPI_MEM_SDOUT_QUAD_S 15 -/* SPI_MEM_SDIN_QUAD : HRO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit - is the same with spi_mem_usr_sram_qio..*/ -#define SPI_MEM_SDIN_QUAD (BIT(14)) -#define SPI_MEM_SDIN_QUAD_M (BIT(14)) -#define SPI_MEM_SDIN_QUAD_V 0x1 -#define SPI_MEM_SDIN_QUAD_S 14 -/* SPI_MEM_SADDR_DUAL : HRO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The - bit is the same with spi_mem_usr_sram_dio..*/ -#define SPI_MEM_SADDR_DUAL (BIT(12)) -#define SPI_MEM_SADDR_DUAL_M (BIT(12)) -#define SPI_MEM_SADDR_DUAL_V 0x1 -#define SPI_MEM_SADDR_DUAL_S 12 -/* SPI_MEM_SDOUT_DUAL : HRO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bi -t is the same with spi_mem_usr_sram_dio..*/ -#define SPI_MEM_SDOUT_DUAL (BIT(11)) -#define SPI_MEM_SDOUT_DUAL_M (BIT(11)) -#define SPI_MEM_SDOUT_DUAL_V 0x1 -#define SPI_MEM_SDOUT_DUAL_S 11 -/* SPI_MEM_SDIN_DUAL : HRO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit - is the same with spi_mem_usr_sram_dio..*/ -#define SPI_MEM_SDIN_DUAL (BIT(10)) -#define SPI_MEM_SDIN_DUAL_M (BIT(10)) -#define SPI_MEM_SDIN_DUAL_V 0x1 -#define SPI_MEM_SDIN_DUAL_S 10 -/* SPI_MEM_SWB_MODE : HRO ;bitpos:[9:2] ;default: 8'b0 ; */ -/*description: Mode bits in the external RAM fast read mode it is combined with spi_mem_fastrd -_mode bit..*/ -#define SPI_MEM_SWB_MODE 0x000000FF -#define SPI_MEM_SWB_MODE_M ((SPI_MEM_SWB_MODE_V)<<(SPI_MEM_SWB_MODE_S)) -#define SPI_MEM_SWB_MODE_V 0xFF -#define SPI_MEM_SWB_MODE_S 2 -/* SPI_MEM_SCLK_MODE : HRO ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delaye -d one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inacti -ve 3: SPI clock is always on..*/ -#define SPI_MEM_SCLK_MODE 0x00000003 -#define SPI_MEM_SCLK_MODE_M ((SPI_MEM_SCLK_MODE_V)<<(SPI_MEM_SCLK_MODE_S)) -#define SPI_MEM_SCLK_MODE_V 0x3 -#define SPI_MEM_SCLK_MODE_S 0 - -#define SPI_MEM_SRAM_DRD_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x48) -/* SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN : HRO ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: For SPI0,When cache mode is enable it is the length in bits of command phase for - sram. The register value shall be (bit_num-1)..*/ -#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN 0x0000000F -#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_M ((SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V)<<(SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S)) -#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V 0xF -#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S 28 -/* SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE : HRO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: For SPI0,When cache mode is enable it is the read command value of command phase - for sram..*/ -#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE 0x0000FFFF -#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_M ((SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V)<<(SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S)) -#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V 0xFFFF -#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S 0 - -#define SPI_MEM_SRAM_DWR_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x4C) -/* SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN : HRO ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: For SPI0,When cache mode is enable it is the in bits of command phase for sram. - The register value shall be (bit_num-1)..*/ -#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN 0x0000000F -#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_M ((SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V)<<(SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S)) -#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V 0xF -#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S 28 -/* SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE : HRO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: For SPI0,When cache mode is enable it is the write command value of command phas -e for sram..*/ -#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE 0x0000FFFF -#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_M ((SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V)<<(SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S)) -#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V 0xFFFF -#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S 0 - -#define SPI_MEM_SRAM_CLK_REG(i) (REG_SPI_MEM_BASE(i) + 0x50) -/* SPI_MEM_SCLK_EQU_SYSCLK : HRO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: For SPI0 external RAM interface, 1: spi_mem_clk is eqaul to system 0: spi_mem_c -lk is divided from system clock..*/ -#define SPI_MEM_SCLK_EQU_SYSCLK (BIT(31)) -#define SPI_MEM_SCLK_EQU_SYSCLK_M (BIT(31)) -#define SPI_MEM_SCLK_EQU_SYSCLK_V 0x1 -#define SPI_MEM_SCLK_EQU_SYSCLK_S 31 -/* SPI_MEM_SCLKCNT_N : HRO ;bitpos:[23:16] ;default: 8'h3 ; */ -/*description: For SPI0 external RAM interface, it is the divider of spi_mem_clk. So spi_mem_c -lk frequency is system/(spi_mem_clkcnt_N+1).*/ -#define SPI_MEM_SCLKCNT_N 0x000000FF -#define SPI_MEM_SCLKCNT_N_M ((SPI_MEM_SCLKCNT_N_V)<<(SPI_MEM_SCLKCNT_N_S)) -#define SPI_MEM_SCLKCNT_N_V 0xFF -#define SPI_MEM_SCLKCNT_N_S 16 -/* SPI_MEM_SCLKCNT_H : HRO ;bitpos:[15:8] ;default: 8'h1 ; */ -/*description: For SPI0 external RAM interface, it must be floor((spi_mem_clkcnt_N+1)/2-1)..*/ -#define SPI_MEM_SCLKCNT_H 0x000000FF -#define SPI_MEM_SCLKCNT_H_M ((SPI_MEM_SCLKCNT_H_V)<<(SPI_MEM_SCLKCNT_H_S)) -#define SPI_MEM_SCLKCNT_H_V 0xFF -#define SPI_MEM_SCLKCNT_H_S 8 -/* SPI_MEM_SCLKCNT_L : HRO ;bitpos:[7:0] ;default: 8'h3 ; */ -/*description: For SPI0 external RAM interface, it must be equal to spi_mem_clkcnt_N..*/ -#define SPI_MEM_SCLKCNT_L 0x000000FF -#define SPI_MEM_SCLKCNT_L_M ((SPI_MEM_SCLKCNT_L_V)<<(SPI_MEM_SCLKCNT_L_S)) -#define SPI_MEM_SCLKCNT_L_V 0xFF -#define SPI_MEM_SCLKCNT_L_S 0 - -#define SPI_MEM_FSM_REG(i) (REG_SPI_MEM_BASE(i) + 0x54) -/* SPI_MEM_LOCK_DELAY_TIME : R/W ;bitpos:[11:7] ;default: 5'd4 ; */ -/*description: The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1..*/ -#define SPI_MEM_LOCK_DELAY_TIME 0x0000001F -#define SPI_MEM_LOCK_DELAY_TIME_M ((SPI_MEM_LOCK_DELAY_TIME_V)<<(SPI_MEM_LOCK_DELAY_TIME_S)) -#define SPI_MEM_LOCK_DELAY_TIME_V 0x1F -#define SPI_MEM_LOCK_DELAY_TIME_S 7 - -#define SPI_MEM_W0_REG(i) (REG_SPI_MEM_BASE(i) + 0x58) -/* SPI_MEM_BUF0 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer.*/ -#define SPI_MEM_BUF0 0xFFFFFFFF -#define SPI_MEM_BUF0_M ((SPI_MEM_BUF0_V)<<(SPI_MEM_BUF0_S)) -#define SPI_MEM_BUF0_V 0xFFFFFFFF -#define SPI_MEM_BUF0_S 0 - -#define SPI_MEM_W1_REG(i) (REG_SPI_MEM_BASE(i) + 0x5C) -/* SPI_MEM_BUF1 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer.*/ -#define SPI_MEM_BUF1 0xFFFFFFFF -#define SPI_MEM_BUF1_M ((SPI_MEM_BUF1_V)<<(SPI_MEM_BUF1_S)) -#define SPI_MEM_BUF1_V 0xFFFFFFFF -#define SPI_MEM_BUF1_S 0 - -#define SPI_MEM_W2_REG(i) (REG_SPI_MEM_BASE(i) + 0x60) -/* SPI_MEM_BUF2 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer.*/ -#define SPI_MEM_BUF2 0xFFFFFFFF -#define SPI_MEM_BUF2_M ((SPI_MEM_BUF2_V)<<(SPI_MEM_BUF2_S)) -#define SPI_MEM_BUF2_V 0xFFFFFFFF -#define SPI_MEM_BUF2_S 0 - -#define SPI_MEM_W3_REG(i) (REG_SPI_MEM_BASE(i) + 0x64) -/* SPI_MEM_BUF3 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer.*/ -#define SPI_MEM_BUF3 0xFFFFFFFF -#define SPI_MEM_BUF3_M ((SPI_MEM_BUF3_V)<<(SPI_MEM_BUF3_S)) -#define SPI_MEM_BUF3_V 0xFFFFFFFF -#define SPI_MEM_BUF3_S 0 - -#define SPI_MEM_W4_REG(i) (REG_SPI_MEM_BASE(i) + 0x68) -/* SPI_MEM_BUF4 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer.*/ -#define SPI_MEM_BUF4 0xFFFFFFFF -#define SPI_MEM_BUF4_M ((SPI_MEM_BUF4_V)<<(SPI_MEM_BUF4_S)) -#define SPI_MEM_BUF4_V 0xFFFFFFFF -#define SPI_MEM_BUF4_S 0 - -#define SPI_MEM_W5_REG(i) (REG_SPI_MEM_BASE(i) + 0x6C) -/* SPI_MEM_BUF5 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer.*/ -#define SPI_MEM_BUF5 0xFFFFFFFF -#define SPI_MEM_BUF5_M ((SPI_MEM_BUF5_V)<<(SPI_MEM_BUF5_S)) -#define SPI_MEM_BUF5_V 0xFFFFFFFF -#define SPI_MEM_BUF5_S 0 - -#define SPI_MEM_W6_REG(i) (REG_SPI_MEM_BASE(i) + 0x70) -/* SPI_MEM_BUF6 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer.*/ -#define SPI_MEM_BUF6 0xFFFFFFFF -#define SPI_MEM_BUF6_M ((SPI_MEM_BUF6_V)<<(SPI_MEM_BUF6_S)) -#define SPI_MEM_BUF6_V 0xFFFFFFFF -#define SPI_MEM_BUF6_S 0 - -#define SPI_MEM_W7_REG(i) (REG_SPI_MEM_BASE(i) + 0x74) -/* SPI_MEM_BUF7 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer.*/ -#define SPI_MEM_BUF7 0xFFFFFFFF -#define SPI_MEM_BUF7_M ((SPI_MEM_BUF7_V)<<(SPI_MEM_BUF7_S)) -#define SPI_MEM_BUF7_V 0xFFFFFFFF -#define SPI_MEM_BUF7_S 0 - -#define SPI_MEM_W8_REG(i) (REG_SPI_MEM_BASE(i) + 0x78) -/* SPI_MEM_BUF8 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer.*/ -#define SPI_MEM_BUF8 0xFFFFFFFF -#define SPI_MEM_BUF8_M ((SPI_MEM_BUF8_V)<<(SPI_MEM_BUF8_S)) -#define SPI_MEM_BUF8_V 0xFFFFFFFF -#define SPI_MEM_BUF8_S 0 - -#define SPI_MEM_W9_REG(i) (REG_SPI_MEM_BASE(i) + 0x7C) -/* SPI_MEM_BUF9 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer.*/ -#define SPI_MEM_BUF9 0xFFFFFFFF -#define SPI_MEM_BUF9_M ((SPI_MEM_BUF9_V)<<(SPI_MEM_BUF9_S)) -#define SPI_MEM_BUF9_V 0xFFFFFFFF -#define SPI_MEM_BUF9_S 0 - -#define SPI_MEM_W10_REG(i) (REG_SPI_MEM_BASE(i) + 0x80) -/* SPI_MEM_BUF10 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer.*/ -#define SPI_MEM_BUF10 0xFFFFFFFF -#define SPI_MEM_BUF10_M ((SPI_MEM_BUF10_V)<<(SPI_MEM_BUF10_S)) -#define SPI_MEM_BUF10_V 0xFFFFFFFF -#define SPI_MEM_BUF10_S 0 - -#define SPI_MEM_W11_REG(i) (REG_SPI_MEM_BASE(i) + 0x84) -/* SPI_MEM_BUF11 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer.*/ -#define SPI_MEM_BUF11 0xFFFFFFFF -#define SPI_MEM_BUF11_M ((SPI_MEM_BUF11_V)<<(SPI_MEM_BUF11_S)) -#define SPI_MEM_BUF11_V 0xFFFFFFFF -#define SPI_MEM_BUF11_S 0 - -#define SPI_MEM_W12_REG(i) (REG_SPI_MEM_BASE(i) + 0x88) -/* SPI_MEM_BUF12 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer.*/ -#define SPI_MEM_BUF12 0xFFFFFFFF -#define SPI_MEM_BUF12_M ((SPI_MEM_BUF12_V)<<(SPI_MEM_BUF12_S)) -#define SPI_MEM_BUF12_V 0xFFFFFFFF -#define SPI_MEM_BUF12_S 0 - -#define SPI_MEM_W13_REG(i) (REG_SPI_MEM_BASE(i) + 0x8C) -/* SPI_MEM_BUF13 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer.*/ -#define SPI_MEM_BUF13 0xFFFFFFFF -#define SPI_MEM_BUF13_M ((SPI_MEM_BUF13_V)<<(SPI_MEM_BUF13_S)) -#define SPI_MEM_BUF13_V 0xFFFFFFFF -#define SPI_MEM_BUF13_S 0 - -#define SPI_MEM_W14_REG(i) (REG_SPI_MEM_BASE(i) + 0x90) -/* SPI_MEM_BUF14 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer.*/ -#define SPI_MEM_BUF14 0xFFFFFFFF -#define SPI_MEM_BUF14_M ((SPI_MEM_BUF14_V)<<(SPI_MEM_BUF14_S)) -#define SPI_MEM_BUF14_V 0xFFFFFFFF -#define SPI_MEM_BUF14_S 0 - -#define SPI_MEM_W15_REG(i) (REG_SPI_MEM_BASE(i) + 0x94) -/* SPI_MEM_BUF15 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: data buffer.*/ -#define SPI_MEM_BUF15 0xFFFFFFFF -#define SPI_MEM_BUF15_M ((SPI_MEM_BUF15_V)<<(SPI_MEM_BUF15_S)) -#define SPI_MEM_BUF15_V 0xFFFFFFFF -#define SPI_MEM_BUF15_S 0 - -#define SPI_MEM_FLASH_WAITI_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x98) -/* SPI_MEM_WAITI_CMD : R/W ;bitpos:[31:16] ;default: 16'h05 ; */ -/*description: The command value to wait flash idle(RDSR)..*/ -#define SPI_MEM_WAITI_CMD 0x0000FFFF -#define SPI_MEM_WAITI_CMD_M ((SPI_MEM_WAITI_CMD_V)<<(SPI_MEM_WAITI_CMD_S)) -#define SPI_MEM_WAITI_CMD_V 0xFFFF -#define SPI_MEM_WAITI_CMD_S 16 -/* SPI_MEM_WAITI_DUMMY_CYCLELEN : R/W ;bitpos:[15:10] ;default: 6'h0 ; */ -/*description: The dummy cycle length when wait flash idle(RDSR)..*/ -#define SPI_MEM_WAITI_DUMMY_CYCLELEN 0x0000003F -#define SPI_MEM_WAITI_DUMMY_CYCLELEN_M ((SPI_MEM_WAITI_DUMMY_CYCLELEN_V)<<(SPI_MEM_WAITI_DUMMY_CYCLELEN_S)) -#define SPI_MEM_WAITI_DUMMY_CYCLELEN_V 0x3F -#define SPI_MEM_WAITI_DUMMY_CYCLELEN_S 10 -/* SPI_MEM_WAITI_CMD_2B : R/W ;bitpos:[9] ;default: 1'h0 ; */ -/*description: 1:The wait idle command bit length is 16. 0: The wait idle command bit length is - 8..*/ -#define SPI_MEM_WAITI_CMD_2B (BIT(9)) -#define SPI_MEM_WAITI_CMD_2B_M (BIT(9)) -#define SPI_MEM_WAITI_CMD_2B_V 0x1 -#define SPI_MEM_WAITI_CMD_2B_S 9 -/* SPI_MEM_WAITI_ADDR_CYCLELEN : R/W ;bitpos:[4:3] ;default: 2'b0 ; */ -/*description: When SPI_MEM_WAITI_ADDR_EN is set, the cycle length of sent out address is (SPI -_MEM_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI bus clock cycles. It is not active when -SPI_MEM_WAITI_ADDR_EN is cleared..*/ -#define SPI_MEM_WAITI_ADDR_CYCLELEN 0x00000003 -#define SPI_MEM_WAITI_ADDR_CYCLELEN_M ((SPI_MEM_WAITI_ADDR_CYCLELEN_V)<<(SPI_MEM_WAITI_ADDR_CYCLELEN_S)) -#define SPI_MEM_WAITI_ADDR_CYCLELEN_V 0x3 -#define SPI_MEM_WAITI_ADDR_CYCLELEN_S 3 -/* SPI_MEM_WAITI_ADDR_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: 1: Output address 0 in RDSR or read SUS command transfer. 0: Do not send out ad -dress in RDSR or read SUS command transfer..*/ -#define SPI_MEM_WAITI_ADDR_EN (BIT(2)) -#define SPI_MEM_WAITI_ADDR_EN_M (BIT(2)) -#define SPI_MEM_WAITI_ADDR_EN_V 0x1 -#define SPI_MEM_WAITI_ADDR_EN_S 2 -/* SPI_MEM_WAITI_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The dummy phase enable when wait flash idle (RDSR).*/ -#define SPI_MEM_WAITI_DUMMY (BIT(1)) -#define SPI_MEM_WAITI_DUMMY_M (BIT(1)) -#define SPI_MEM_WAITI_DUMMY_V 0x1 -#define SPI_MEM_WAITI_DUMMY_S 1 -/* SPI_MEM_WAITI_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: 1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto - Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto -Suspend/Resume are not supported..*/ -#define SPI_MEM_WAITI_EN (BIT(0)) -#define SPI_MEM_WAITI_EN_M (BIT(0)) -#define SPI_MEM_WAITI_EN_V 0x1 -#define SPI_MEM_WAITI_EN_S 0 - -#define SPI_MEM_FLASH_SUS_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x9C) -/* SPI_MEM_SUS_TIMEOUT_CNT : R/W ;bitpos:[31:25] ;default: 7'h4 ; */ -/*description: When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, - it will be treated as check pass..*/ -#define SPI_MEM_SUS_TIMEOUT_CNT 0x0000007F -#define SPI_MEM_SUS_TIMEOUT_CNT_M ((SPI_MEM_SUS_TIMEOUT_CNT_V)<<(SPI_MEM_SUS_TIMEOUT_CNT_S)) -#define SPI_MEM_SUS_TIMEOUT_CNT_V 0x7F -#define SPI_MEM_SUS_TIMEOUT_CNT_S 25 -/* SPI_MEM_PES_END_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend statu -s of flash. 0: Only need to check WIP is 0..*/ -#define SPI_MEM_PES_END_EN (BIT(24)) -#define SPI_MEM_PES_END_EN_M (BIT(24)) -#define SPI_MEM_PES_END_EN_V 0x1 -#define SPI_MEM_PES_END_EN_S 24 -/* SPI_MEM_PER_END_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status - of flash. 0: Only need to check WIP is 0..*/ -#define SPI_MEM_PER_END_EN (BIT(23)) -#define SPI_MEM_PER_END_EN_M (BIT(23)) -#define SPI_MEM_PER_END_EN_V 0x1 -#define SPI_MEM_PER_END_EN_S 23 -/* SPI_MEM_SPI_FMEM_RD_SUS_2B : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte w -hen check flash SUS/SUS1/SUS2 status bit.*/ -#define SPI_MEM_SPI_FMEM_RD_SUS_2B (BIT(22)) -#define SPI_MEM_SPI_FMEM_RD_SUS_2B_M (BIT(22)) -#define SPI_MEM_SPI_FMEM_RD_SUS_2B_V 0x1 -#define SPI_MEM_SPI_FMEM_RD_SUS_2B_S 22 -/* SPI_MEM_PESR_END_MSK : R/W ;bitpos:[21:6] ;default: 16'h80 ; */ -/*description: The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is -status_in[15:0](only status_in[7:0] is valid when only one byte of data is read -out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS -2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0]..*/ -#define SPI_MEM_PESR_END_MSK 0x0000FFFF -#define SPI_MEM_PESR_END_MSK_M ((SPI_MEM_PESR_END_MSK_V)<<(SPI_MEM_PESR_END_MSK_S)) -#define SPI_MEM_PESR_END_MSK_V 0xFFFF -#define SPI_MEM_PESR_END_MSK_S 6 -/* SPI_MEM_FLASH_PES_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to enable Auto-suspending function..*/ -#define SPI_MEM_FLASH_PES_EN (BIT(5)) -#define SPI_MEM_FLASH_PES_EN_M (BIT(5)) -#define SPI_MEM_FLASH_PES_EN_V 0x1 -#define SPI_MEM_FLASH_PES_EN_S 5 -/* SPI_MEM_PES_PER_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to enable PES end triggers PER transfer option. If this bit is 0, a -pplication should send PER after PES is done..*/ -#define SPI_MEM_PES_PER_EN (BIT(4)) -#define SPI_MEM_PES_PER_EN_M (BIT(4)) -#define SPI_MEM_PES_PER_EN_V 0x1 -#define SPI_MEM_PES_PER_EN_S 4 -/* SPI_MEM_FLASH_PES_WAIT_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after -program erase suspend command is sent. 0: SPI1 does not wait after program erase - suspend command is sent..*/ -#define SPI_MEM_FLASH_PES_WAIT_EN (BIT(3)) -#define SPI_MEM_FLASH_PES_WAIT_EN_M (BIT(3)) -#define SPI_MEM_FLASH_PES_WAIT_EN_V 0x1 -#define SPI_MEM_FLASH_PES_WAIT_EN_S 3 -/* SPI_MEM_FLASH_PER_WAIT_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after -program erase resume command is sent. 0: SPI1 does not wait after program erase -resume command is sent..*/ -#define SPI_MEM_FLASH_PER_WAIT_EN (BIT(2)) -#define SPI_MEM_FLASH_PER_WAIT_EN_M (BIT(2)) -#define SPI_MEM_FLASH_PER_WAIT_EN_V 0x1 -#define SPI_MEM_FLASH_PER_WAIT_EN_S 2 -/* SPI_MEM_FLASH_PES : R/W/SC ;bitpos:[1] ;default: 1'b0 ; */ -/*description: program erase suspend bit, program erase suspend operation will be triggered whe -n the bit is set. The bit will be cleared once the operation done.1: enable 0: d -isable..*/ -#define SPI_MEM_FLASH_PES (BIT(1)) -#define SPI_MEM_FLASH_PES_M (BIT(1)) -#define SPI_MEM_FLASH_PES_V 0x1 -#define SPI_MEM_FLASH_PES_S 1 -/* SPI_MEM_FLASH_PER : R/W/SC ;bitpos:[0] ;default: 1'b0 ; */ -/*description: program erase resume bit, program erase suspend operation will be triggered when - the bit is set. The bit will be cleared once the operation done.1: enable 0: di -sable..*/ -#define SPI_MEM_FLASH_PER (BIT(0)) -#define SPI_MEM_FLASH_PER_M (BIT(0)) -#define SPI_MEM_FLASH_PER_V 0x1 -#define SPI_MEM_FLASH_PER_S 0 - -#define SPI_MEM_FLASH_SUS_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0xA0) -/* SPI_MEM_WAIT_PESR_COMMAND : R/W ;bitpos:[31:16] ;default: 16'h05 ; */ -/*description: Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS -/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash -..*/ -#define SPI_MEM_WAIT_PESR_COMMAND 0x0000FFFF -#define SPI_MEM_WAIT_PESR_COMMAND_M ((SPI_MEM_WAIT_PESR_COMMAND_V)<<(SPI_MEM_WAIT_PESR_COMMAND_S)) -#define SPI_MEM_WAIT_PESR_COMMAND_V 0xFFFF -#define SPI_MEM_WAIT_PESR_COMMAND_S 16 -/* SPI_MEM_FLASH_PES_COMMAND : R/W ;bitpos:[15:0] ;default: 16'h7575 ; */ -/*description: Program/Erase suspend command..*/ -#define SPI_MEM_FLASH_PES_COMMAND 0x0000FFFF -#define SPI_MEM_FLASH_PES_COMMAND_M ((SPI_MEM_FLASH_PES_COMMAND_V)<<(SPI_MEM_FLASH_PES_COMMAND_S)) -#define SPI_MEM_FLASH_PES_COMMAND_V 0xFFFF -#define SPI_MEM_FLASH_PES_COMMAND_S 0 - -#define SPI_MEM_SUS_STATUS_REG(i) (REG_SPI_MEM_BASE(i) + 0xA4) -/* SPI_MEM_FLASH_PER_COMMAND : R/W ;bitpos:[31:16] ;default: 16'h7a7a ; */ -/*description: Program/Erase resume command..*/ -#define SPI_MEM_FLASH_PER_COMMAND 0x0000FFFF -#define SPI_MEM_FLASH_PER_COMMAND_M ((SPI_MEM_FLASH_PER_COMMAND_V)<<(SPI_MEM_FLASH_PER_COMMAND_S)) -#define SPI_MEM_FLASH_PER_COMMAND_V 0xFFFF -#define SPI_MEM_FLASH_PER_COMMAND_S 16 -/* SPI_MEM_FLASH_PESR_CMD_2B : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: 1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit leng -th of Program/Erase Suspend/Resume command is 8..*/ -#define SPI_MEM_FLASH_PESR_CMD_2B (BIT(15)) -#define SPI_MEM_FLASH_PESR_CMD_2B_M (BIT(15)) -#define SPI_MEM_FLASH_PESR_CMD_2B_V 0x1 -#define SPI_MEM_FLASH_PESR_CMD_2B_S 15 -/* SPI_MEM_SPI0_LOCK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it..*/ -#define SPI_MEM_SPI0_LOCK_EN (BIT(7)) -#define SPI_MEM_SPI0_LOCK_EN_M (BIT(7)) -#define SPI_MEM_SPI0_LOCK_EN_V 0x1 -#define SPI_MEM_SPI0_LOCK_EN_S 7 -/* SPI_MEM_FLASH_PES_DLY_128 : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_ -RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM -_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent..*/ -#define SPI_MEM_FLASH_PES_DLY_128 (BIT(6)) -#define SPI_MEM_FLASH_PES_DLY_128_M (BIT(6)) -#define SPI_MEM_FLASH_PES_DLY_128_V 0x1 -#define SPI_MEM_FLASH_PES_DLY_128_S 6 -/* SPI_MEM_FLASH_PER_DLY_128 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_ -RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM -_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent..*/ -#define SPI_MEM_FLASH_PER_DLY_128 (BIT(5)) -#define SPI_MEM_FLASH_PER_DLY_128_M (BIT(5)) -#define SPI_MEM_FLASH_PER_DLY_128_V 0x1 -#define SPI_MEM_FLASH_PER_DLY_128_S 5 -/* SPI_MEM_FLASH_DP_DLY_128 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP com -mand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles -after DP command is sent..*/ -#define SPI_MEM_FLASH_DP_DLY_128 (BIT(4)) -#define SPI_MEM_FLASH_DP_DLY_128_M (BIT(4)) -#define SPI_MEM_FLASH_DP_DLY_128_V 0x1 -#define SPI_MEM_FLASH_DP_DLY_128_S 4 -/* SPI_MEM_FLASH_RES_DLY_128 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES co -mmand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles - after RES command is sent..*/ -#define SPI_MEM_FLASH_RES_DLY_128 (BIT(3)) -#define SPI_MEM_FLASH_RES_DLY_128_M (BIT(3)) -#define SPI_MEM_FLASH_RES_DLY_128_V 0x1 -#define SPI_MEM_FLASH_RES_DLY_128_S 3 -/* SPI_MEM_FLASH_HPM_DLY_128 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM co -mmand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles - after HPM command is sent..*/ -#define SPI_MEM_FLASH_HPM_DLY_128 (BIT(2)) -#define SPI_MEM_FLASH_HPM_DLY_128_M (BIT(2)) -#define SPI_MEM_FLASH_HPM_DLY_128_V 0x1 -#define SPI_MEM_FLASH_HPM_DLY_128_S 2 -/* SPI_MEM_WAIT_PESR_CMD_2B : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: 1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: - SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit..*/ -#define SPI_MEM_WAIT_PESR_CMD_2B (BIT(1)) -#define SPI_MEM_WAIT_PESR_CMD_2B_M (BIT(1)) -#define SPI_MEM_WAIT_PESR_CMD_2B_V 0x1 -#define SPI_MEM_WAIT_PESR_CMD_2B_S 1 -/* SPI_MEM_FLASH_SUS : R/W/SS/SC ;bitpos:[0] ;default: 1'h0 ; */ -/*description: The status of flash suspend, only used in SPI1..*/ -#define SPI_MEM_FLASH_SUS (BIT(0)) -#define SPI_MEM_FLASH_SUS_M (BIT(0)) -#define SPI_MEM_FLASH_SUS_V 0x1 -#define SPI_MEM_FLASH_SUS_S 0 - -#define SPI_MEM_INT_ENA_REG(i) (REG_SPI_MEM_BASE(i) + 0xC0) -/* SPI_MEM_BROWN_OUT_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The enable bit for SPI_MEM_BROWN_OUT_INT interrupt..*/ -#define SPI_MEM_BROWN_OUT_INT_ENA (BIT(10)) -#define SPI_MEM_BROWN_OUT_INT_ENA_M (BIT(10)) -#define SPI_MEM_BROWN_OUT_INT_ENA_V 0x1 -#define SPI_MEM_BROWN_OUT_INT_ENA_S 10 -/* SPI_MEM_AXI_WADDR_ERR_INT_ENA : HRO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt..*/ -#define SPI_MEM_AXI_WADDR_ERR_INT_ENA (BIT(9)) -#define SPI_MEM_AXI_WADDR_ERR_INT_ENA_M (BIT(9)) -#define SPI_MEM_AXI_WADDR_ERR_INT_ENA_V 0x1 -#define SPI_MEM_AXI_WADDR_ERR_INT_ENA_S 9 -/* SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA : HRO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt..*/ -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA (BIT(8)) -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_M (BIT(8)) -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_V 0x1 -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_S 8 -/* SPI_MEM_AXI_RADDR_ERR_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt..*/ -#define SPI_MEM_AXI_RADDR_ERR_INT_ENA (BIT(7)) -#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_M (BIT(7)) -#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_V 0x1 -#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_S 7 -/* SPI_MEM_PMS_REJECT_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The enable bit for SPI_MEM_PMS_REJECT_INT interrupt..*/ -#define SPI_MEM_PMS_REJECT_INT_ENA (BIT(6)) -#define SPI_MEM_PMS_REJECT_INT_ENA_M (BIT(6)) -#define SPI_MEM_PMS_REJECT_INT_ENA_V 0x1 -#define SPI_MEM_PMS_REJECT_INT_ENA_S 6 -/* SPI_MEM_ECC_ERR_INT_ENA : HRO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The enable bit for SPI_MEM_ECC_ERR_INT interrupt..*/ -#define SPI_MEM_ECC_ERR_INT_ENA (BIT(5)) -#define SPI_MEM_ECC_ERR_INT_ENA_M (BIT(5)) -#define SPI_MEM_ECC_ERR_INT_ENA_V 0x1 -#define SPI_MEM_ECC_ERR_INT_ENA_S 5 -/* SPI_MEM_MST_ST_END_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The enable bit for SPI_MEM_MST_ST_END_INT interrupt..*/ -#define SPI_MEM_MST_ST_END_INT_ENA (BIT(4)) -#define SPI_MEM_MST_ST_END_INT_ENA_M (BIT(4)) -#define SPI_MEM_MST_ST_END_INT_ENA_V 0x1 -#define SPI_MEM_MST_ST_END_INT_ENA_S 4 -/* SPI_MEM_SLV_ST_END_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The enable bit for SPI_MEM_SLV_ST_END_INT interrupt..*/ -#define SPI_MEM_SLV_ST_END_INT_ENA (BIT(3)) -#define SPI_MEM_SLV_ST_END_INT_ENA_M (BIT(3)) -#define SPI_MEM_SLV_ST_END_INT_ENA_V 0x1 -#define SPI_MEM_SLV_ST_END_INT_ENA_S 3 -/* SPI_MEM_WPE_END_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The enable bit for SPI_MEM_WPE_END_INT interrupt..*/ -#define SPI_MEM_WPE_END_INT_ENA (BIT(2)) -#define SPI_MEM_WPE_END_INT_ENA_M (BIT(2)) -#define SPI_MEM_WPE_END_INT_ENA_V 0x1 -#define SPI_MEM_WPE_END_INT_ENA_S 2 -/* SPI_MEM_PES_END_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The enable bit for SPI_MEM_PES_END_INT interrupt..*/ -#define SPI_MEM_PES_END_INT_ENA (BIT(1)) -#define SPI_MEM_PES_END_INT_ENA_M (BIT(1)) -#define SPI_MEM_PES_END_INT_ENA_V 0x1 -#define SPI_MEM_PES_END_INT_ENA_S 1 -/* SPI_MEM_PER_END_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The enable bit for SPI_MEM_PER_END_INT interrupt..*/ -#define SPI_MEM_PER_END_INT_ENA (BIT(0)) -#define SPI_MEM_PER_END_INT_ENA_M (BIT(0)) -#define SPI_MEM_PER_END_INT_ENA_V 0x1 -#define SPI_MEM_PER_END_INT_ENA_S 0 - -#define SPI_MEM_INT_CLR_REG(i) (REG_SPI_MEM_BASE(i) + 0xC4) -/* SPI_MEM_BROWN_OUT_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The status bit for SPI_MEM_BROWN_OUT_INT interrupt..*/ -#define SPI_MEM_BROWN_OUT_INT_CLR (BIT(10)) -#define SPI_MEM_BROWN_OUT_INT_CLR_M (BIT(10)) -#define SPI_MEM_BROWN_OUT_INT_CLR_V 0x1 -#define SPI_MEM_BROWN_OUT_INT_CLR_S 10 -/* SPI_MEM_AXI_WADDR_ERR_INT_CLR : HRO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt..*/ -#define SPI_MEM_AXI_WADDR_ERR_INT_CLR (BIT(9)) -#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_M (BIT(9)) -#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_V 0x1 -#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_S 9 -/* SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR : HRO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt..*/ -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR (BIT(8)) -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_M (BIT(8)) -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_V 0x1 -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_S 8 -/* SPI_MEM_AXI_RADDR_ERR_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt..*/ -#define SPI_MEM_AXI_RADDR_ERR_INT_CLR (BIT(7)) -#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_M (BIT(7)) -#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_V 0x1 -#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_S 7 -/* SPI_MEM_PMS_REJECT_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The clear bit for SPI_MEM_PMS_REJECT_INT interrupt..*/ -#define SPI_MEM_PMS_REJECT_INT_CLR (BIT(6)) -#define SPI_MEM_PMS_REJECT_INT_CLR_M (BIT(6)) -#define SPI_MEM_PMS_REJECT_INT_CLR_V 0x1 -#define SPI_MEM_PMS_REJECT_INT_CLR_S 6 -/* SPI_MEM_ECC_ERR_INT_CLR : HRO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The clear bit for SPI_MEM_ECC_ERR_INT interrupt..*/ -#define SPI_MEM_ECC_ERR_INT_CLR (BIT(5)) -#define SPI_MEM_ECC_ERR_INT_CLR_M (BIT(5)) -#define SPI_MEM_ECC_ERR_INT_CLR_V 0x1 -#define SPI_MEM_ECC_ERR_INT_CLR_S 5 -/* SPI_MEM_MST_ST_END_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The clear bit for SPI_MEM_MST_ST_END_INT interrupt..*/ -#define SPI_MEM_MST_ST_END_INT_CLR (BIT(4)) -#define SPI_MEM_MST_ST_END_INT_CLR_M (BIT(4)) -#define SPI_MEM_MST_ST_END_INT_CLR_V 0x1 -#define SPI_MEM_MST_ST_END_INT_CLR_S 4 -/* SPI_MEM_SLV_ST_END_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The clear bit for SPI_MEM_SLV_ST_END_INT interrupt..*/ -#define SPI_MEM_SLV_ST_END_INT_CLR (BIT(3)) -#define SPI_MEM_SLV_ST_END_INT_CLR_M (BIT(3)) -#define SPI_MEM_SLV_ST_END_INT_CLR_V 0x1 -#define SPI_MEM_SLV_ST_END_INT_CLR_S 3 -/* SPI_MEM_WPE_END_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The clear bit for SPI_MEM_WPE_END_INT interrupt..*/ -#define SPI_MEM_WPE_END_INT_CLR (BIT(2)) -#define SPI_MEM_WPE_END_INT_CLR_M (BIT(2)) -#define SPI_MEM_WPE_END_INT_CLR_V 0x1 -#define SPI_MEM_WPE_END_INT_CLR_S 2 -/* SPI_MEM_PES_END_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The clear bit for SPI_MEM_PES_END_INT interrupt..*/ -#define SPI_MEM_PES_END_INT_CLR (BIT(1)) -#define SPI_MEM_PES_END_INT_CLR_M (BIT(1)) -#define SPI_MEM_PES_END_INT_CLR_V 0x1 -#define SPI_MEM_PES_END_INT_CLR_S 1 -/* SPI_MEM_PER_END_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The clear bit for SPI_MEM_PER_END_INT interrupt..*/ -#define SPI_MEM_PER_END_INT_CLR (BIT(0)) -#define SPI_MEM_PER_END_INT_CLR_M (BIT(0)) -#define SPI_MEM_PER_END_INT_CLR_V 0x1 -#define SPI_MEM_PER_END_INT_CLR_S 0 - -#define SPI_MEM_INT_RAW_REG(i) (REG_SPI_MEM_BASE(i) + 0xC8) -/* SPI_MEM_BROWN_OUT_INT_RAW : R/WTC/SS ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that -chip is loosing power and RTC module sends out brown out close flash request to -SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered - and MSPI returns to idle state. 0: Others..*/ -#define SPI_MEM_BROWN_OUT_INT_RAW (BIT(10)) -#define SPI_MEM_BROWN_OUT_INT_RAW_M (BIT(10)) -#define SPI_MEM_BROWN_OUT_INT_RAW_V 0x1 -#define SPI_MEM_BROWN_OUT_INT_RAW_S 10 -/* SPI_MEM_AXI_WADDR_ERR_INT_RAW : HRO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write - address is invalid by compared to MMU configuration. 0: Others..*/ -#define SPI_MEM_AXI_WADDR_ERR_INT_RAW (BIT(9)) -#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_M (BIT(9)) -#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_V 0x1 -#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_S 9 -/* SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW : HRO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI wr -ite flash request is received. 0: Others..*/ -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW (BIT(8)) -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_M (BIT(8)) -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_V 0x1 -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_S 8 -/* SPI_MEM_AXI_RADDR_ERR_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read -address is invalid by compared to MMU configuration. 0: Others..*/ -#define SPI_MEM_AXI_RADDR_ERR_INT_RAW (BIT(7)) -#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_M (BIT(7)) -#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_V 0x1 -#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_S 7 -/* SPI_MEM_PMS_REJECT_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access -is rejected. 0: Others..*/ -#define SPI_MEM_PMS_REJECT_INT_RAW (BIT(6)) -#define SPI_MEM_PMS_REJECT_INT_RAW_M (BIT(6)) -#define SPI_MEM_PMS_REJECT_INT_RAW_V 0x1 -#define SPI_MEM_PMS_REJECT_INT_RAW_S 6 -/* SPI_MEM_ECC_ERR_INT_RAW : HRO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is s -et and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error - times of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM -. When SPI_FMEM_ECC_ERR_INT_EN is cleared and SPI_SMEM_ECC_ERR_INT_EN is set, t -his bit is triggered when the error times of SPI0/1 ECC read external RAM are eq -ual or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SP -I_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times -of SPI0/1 ECC read external RAM and flash are equal or bigger than SPI_MEM_ECC_E -RR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are cleare -d, this bit will not be triggered..*/ -#define SPI_MEM_ECC_ERR_INT_RAW (BIT(5)) -#define SPI_MEM_ECC_ERR_INT_RAW_M (BIT(5)) -#define SPI_MEM_ECC_ERR_INT_RAW_V 0x1 -#define SPI_MEM_ECC_ERR_INT_RAW_S 5 -/* SPI_MEM_MST_ST_END_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st -is changed from non idle state to idle state. 0: Others..*/ -#define SPI_MEM_MST_ST_END_INT_RAW (BIT(4)) -#define SPI_MEM_MST_ST_END_INT_RAW_M (BIT(4)) -#define SPI_MEM_MST_ST_END_INT_RAW_V 0x1 -#define SPI_MEM_MST_ST_END_INT_RAW_S 4 -/* SPI_MEM_SLV_ST_END_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st -is changed from non idle state to idle state. It means that SPI_CS raises high. -0: Others.*/ -#define SPI_MEM_SLV_ST_END_INT_RAW (BIT(3)) -#define SPI_MEM_SLV_ST_END_INT_RAW_M (BIT(3)) -#define SPI_MEM_SLV_ST_END_INT_RAW_V 0x1 -#define SPI_MEM_SLV_ST_END_INT_RAW_S 3 -/* SPI_MEM_WPE_END_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/C -E is sent and flash is already idle. 0: Others..*/ -#define SPI_MEM_WPE_END_INT_RAW (BIT(2)) -#define SPI_MEM_WPE_END_INT_RAW_M (BIT(2)) -#define SPI_MEM_WPE_END_INT_RAW_V 0x1 -#define SPI_MEM_WPE_END_INT_RAW_S 2 -/* SPI_MEM_PES_END_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend com -mand (0x75) is sent and flash is suspended successfully. 0: Others..*/ -#define SPI_MEM_PES_END_INT_RAW (BIT(1)) -#define SPI_MEM_PES_END_INT_RAW_M (BIT(1)) -#define SPI_MEM_PES_END_INT_RAW_V 0x1 -#define SPI_MEM_PES_END_INT_RAW_S 1 -/* SPI_MEM_PER_END_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume com -mand (0x7A) is sent and flash is resumed successfully. 0: Others..*/ -#define SPI_MEM_PER_END_INT_RAW (BIT(0)) -#define SPI_MEM_PER_END_INT_RAW_M (BIT(0)) -#define SPI_MEM_PER_END_INT_RAW_V 0x1 -#define SPI_MEM_PER_END_INT_RAW_S 0 - -#define SPI_MEM_INT_ST_REG(i) (REG_SPI_MEM_BASE(i) + 0xCC) -/* SPI_MEM_BROWN_OUT_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The status bit for SPI_MEM_BROWN_OUT_INT interrupt..*/ -#define SPI_MEM_BROWN_OUT_INT_ST (BIT(10)) -#define SPI_MEM_BROWN_OUT_INT_ST_M (BIT(10)) -#define SPI_MEM_BROWN_OUT_INT_ST_V 0x1 -#define SPI_MEM_BROWN_OUT_INT_ST_S 10 -/* SPI_MEM_AXI_WADDR_ERR_INT_ST : HRO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt..*/ -#define SPI_MEM_AXI_WADDR_ERR_INT_ST (BIT(9)) -#define SPI_MEM_AXI_WADDR_ERR_INT_ST_M (BIT(9)) -#define SPI_MEM_AXI_WADDR_ERR_INT_ST_V 0x1 -#define SPI_MEM_AXI_WADDR_ERR_INT_ST_S 9 -/* SPI_MEM_AXI_WR_FLASH_ERR_INT_ST : HRO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt..*/ -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST (BIT(8)) -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_M (BIT(8)) -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_V 0x1 -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_S 8 -/* SPI_MEM_AXI_RADDR_ERR_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt..*/ -#define SPI_MEM_AXI_RADDR_ERR_INT_ST (BIT(7)) -#define SPI_MEM_AXI_RADDR_ERR_INT_ST_M (BIT(7)) -#define SPI_MEM_AXI_RADDR_ERR_INT_ST_V 0x1 -#define SPI_MEM_AXI_RADDR_ERR_INT_ST_S 7 -/* SPI_MEM_PMS_REJECT_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The status bit for SPI_MEM_PMS_REJECT_INT interrupt..*/ -#define SPI_MEM_PMS_REJECT_INT_ST (BIT(6)) -#define SPI_MEM_PMS_REJECT_INT_ST_M (BIT(6)) -#define SPI_MEM_PMS_REJECT_INT_ST_V 0x1 -#define SPI_MEM_PMS_REJECT_INT_ST_S 6 -/* SPI_MEM_ECC_ERR_INT_ST : HRO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The status bit for SPI_MEM_ECC_ERR_INT interrupt..*/ -#define SPI_MEM_ECC_ERR_INT_ST (BIT(5)) -#define SPI_MEM_ECC_ERR_INT_ST_M (BIT(5)) -#define SPI_MEM_ECC_ERR_INT_ST_V 0x1 -#define SPI_MEM_ECC_ERR_INT_ST_S 5 -/* SPI_MEM_MST_ST_END_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The status bit for SPI_MEM_MST_ST_END_INT interrupt..*/ -#define SPI_MEM_MST_ST_END_INT_ST (BIT(4)) -#define SPI_MEM_MST_ST_END_INT_ST_M (BIT(4)) -#define SPI_MEM_MST_ST_END_INT_ST_V 0x1 -#define SPI_MEM_MST_ST_END_INT_ST_S 4 -/* SPI_MEM_SLV_ST_END_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The status bit for SPI_MEM_SLV_ST_END_INT interrupt..*/ -#define SPI_MEM_SLV_ST_END_INT_ST (BIT(3)) -#define SPI_MEM_SLV_ST_END_INT_ST_M (BIT(3)) -#define SPI_MEM_SLV_ST_END_INT_ST_V 0x1 -#define SPI_MEM_SLV_ST_END_INT_ST_S 3 -/* SPI_MEM_WPE_END_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The status bit for SPI_MEM_WPE_END_INT interrupt..*/ -#define SPI_MEM_WPE_END_INT_ST (BIT(2)) -#define SPI_MEM_WPE_END_INT_ST_M (BIT(2)) -#define SPI_MEM_WPE_END_INT_ST_V 0x1 -#define SPI_MEM_WPE_END_INT_ST_S 2 -/* SPI_MEM_PES_END_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The status bit for SPI_MEM_PES_END_INT interrupt..*/ -#define SPI_MEM_PES_END_INT_ST (BIT(1)) -#define SPI_MEM_PES_END_INT_ST_M (BIT(1)) -#define SPI_MEM_PES_END_INT_ST_V 0x1 -#define SPI_MEM_PES_END_INT_ST_S 1 -/* SPI_MEM_PER_END_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The status bit for SPI_MEM_PER_END_INT interrupt..*/ -#define SPI_MEM_PER_END_INT_ST (BIT(0)) -#define SPI_MEM_PER_END_INT_ST_M (BIT(0)) -#define SPI_MEM_PER_END_INT_ST_V 0x1 -#define SPI_MEM_PER_END_INT_ST_S 0 - -#define SPI_MEM_DDR_REG(i) (REG_SPI_MEM_BASE(i) + 0xD4) -/* SPI_MEM_SPI_FMEM_HYPERBUS_CA : HRO ;bitpos:[30] ;default: 1'b0 ; */ -/*description: Set this bit to enable HyperRAM address out when accesses to flash, which means -ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}..*/ -#define SPI_MEM_SPI_FMEM_HYPERBUS_CA (BIT(30)) -#define SPI_MEM_SPI_FMEM_HYPERBUS_CA_M (BIT(30)) -#define SPI_MEM_SPI_FMEM_HYPERBUS_CA_V 0x1 -#define SPI_MEM_SPI_FMEM_HYPERBUS_CA_S 30 -/* SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR : HRO ;bitpos:[29] ;default: 1'b0 ; */ -/*description: Set this bit to enable octa_ram address out when accesses to flash, which means -ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0} -..*/ -#define SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR (BIT(29)) -#define SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR_M (BIT(29)) -#define SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR_V 0x1 -#define SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR_S 29 -/* SPI_MEM_SPI_FMEM_CLK_DIFF_INV : HRO ;bitpos:[28] ;default: 1'b0 ; */ -/*description: Set this bit to invert SPI_DIFF when accesses to flash. ..*/ -#define SPI_MEM_SPI_FMEM_CLK_DIFF_INV (BIT(28)) -#define SPI_MEM_SPI_FMEM_CLK_DIFF_INV_M (BIT(28)) -#define SPI_MEM_SPI_FMEM_CLK_DIFF_INV_V 0x1 -#define SPI_MEM_SPI_FMEM_CLK_DIFF_INV_S 28 -/* SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X : HRO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 a -ccesses flash or SPI1 accesses flash or sram..*/ -#define SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X (BIT(27)) -#define SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X_M (BIT(27)) -#define SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X_V 0x1 -#define SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X_S 27 -/* SPI_MEM_SPI_FMEM_DQS_CA_IN : HRO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR -..*/ -#define SPI_MEM_SPI_FMEM_DQS_CA_IN (BIT(26)) -#define SPI_MEM_SPI_FMEM_DQS_CA_IN_M (BIT(26)) -#define SPI_MEM_SPI_FMEM_DQS_CA_IN_V 0x1 -#define SPI_MEM_SPI_FMEM_DQS_CA_IN_S 26 -/* SPI_MEM_SPI_FMEM_CLK_DIFF_EN : HRO ;bitpos:[24] ;default: 1'b0 ; */ -/*description: Set this bit to enable the differential SPI_CLK#..*/ -#define SPI_MEM_SPI_FMEM_CLK_DIFF_EN (BIT(24)) -#define SPI_MEM_SPI_FMEM_CLK_DIFF_EN_M (BIT(24)) -#define SPI_MEM_SPI_FMEM_CLK_DIFF_EN_V 0x1 -#define SPI_MEM_SPI_FMEM_CLK_DIFF_EN_S 24 -/* SPI_MEM_SPI_FMEM_DDR_DQS_LOOP : HRO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi -0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or -SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and n -egative edge of SPI_DQS..*/ -#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP (BIT(21)) -#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_M (BIT(21)) -#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_V 0x1 -#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_S 21 -/* SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD : HRO ;bitpos:[20:14] ;default: 7'b0 ; */ -/*description: The delay number of data strobe which from memory based on SPI clock..*/ -#define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD 0x0000007F -#define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_M ((SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_V)<<(SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_S)) -#define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_V 0x7F -#define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_S 14 -/* SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN : HRO ;bitpos:[13] ;default: 1'h1 ; */ -/*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when -accesses to flash..*/ -#define SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN (BIT(13)) -#define SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN_M (BIT(13)) -#define SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN_V 0x1 -#define SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN_S 13 -/* SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN : HRO ;bitpos:[12] ;default: 1'h1 ; */ -/*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when - accesses to flash..*/ -#define SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN (BIT(12)) -#define SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN_M (BIT(12)) -#define SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN_V 0x1 -#define SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN_S 12 -/* SPI_MEM_SPI_FMEM_OUTMINBYTELEN : HRO ;bitpos:[11:5] ;default: 7'b1 ; */ -/*description: It is the minimum output data length in the panda device..*/ -#define SPI_MEM_SPI_FMEM_OUTMINBYTELEN 0x0000007F -#define SPI_MEM_SPI_FMEM_OUTMINBYTELEN_M ((SPI_MEM_SPI_FMEM_OUTMINBYTELEN_V)<<(SPI_MEM_SPI_FMEM_OUTMINBYTELEN_S)) -#define SPI_MEM_SPI_FMEM_OUTMINBYTELEN_V 0x7F -#define SPI_MEM_SPI_FMEM_OUTMINBYTELEN_S 5 -/* SPI_MEM_SPI_FMEM_DDR_CMD_DIS : HRO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: the bit is used to disable dual edge in command phase when DDR mode..*/ -#define SPI_MEM_SPI_FMEM_DDR_CMD_DIS (BIT(4)) -#define SPI_MEM_SPI_FMEM_DDR_CMD_DIS_M (BIT(4)) -#define SPI_MEM_SPI_FMEM_DDR_CMD_DIS_V 0x1 -#define SPI_MEM_SPI_FMEM_DDR_CMD_DIS_S 4 -/* SPI_MEM_SPI_FMEM_DDR_WDAT_SWP : HRO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set the bit to reorder tx data of the word in spi DDR mode..*/ -#define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP (BIT(3)) -#define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP_M (BIT(3)) -#define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP_V 0x1 -#define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP_S 3 -/* SPI_MEM_SPI_FMEM_DDR_RDAT_SWP : HRO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set the bit to reorder rx data of the word in spi DDR mode..*/ -#define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP (BIT(2)) -#define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP_M (BIT(2)) -#define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP_V 0x1 -#define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP_S 2 -/* SPI_MEM_SPI_FMEM_VAR_DUMMY : HRO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set the bit to enable variable dummy cycle in spi DDR mode..*/ -#define SPI_MEM_SPI_FMEM_VAR_DUMMY (BIT(1)) -#define SPI_MEM_SPI_FMEM_VAR_DUMMY_M (BIT(1)) -#define SPI_MEM_SPI_FMEM_VAR_DUMMY_V 0x1 -#define SPI_MEM_SPI_FMEM_VAR_DUMMY_S 1 -/* SPI_MEM_SPI_FMEM_DDR_EN : HRO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: 1: in DDR mode, 0 in SDR mode.*/ -#define SPI_MEM_SPI_FMEM_DDR_EN (BIT(0)) -#define SPI_MEM_SPI_FMEM_DDR_EN_M (BIT(0)) -#define SPI_MEM_SPI_FMEM_DDR_EN_V 0x1 -#define SPI_MEM_SPI_FMEM_DDR_EN_S 0 - -#define SPI_MEM_SPI_SMEM_DDR_REG(i) (REG_SPI_MEM_BASE(i) + 0xD8) -/* SPI_MEM_SPI_SMEM_HYPERBUS_CA : HRO ;bitpos:[30] ;default: 1'b0 ; */ -/*description: Set this bit to enable HyperRAM address out when accesses to external RAM, which - means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1 -]}..*/ -#define SPI_MEM_SPI_SMEM_HYPERBUS_CA (BIT(30)) -#define SPI_MEM_SPI_SMEM_HYPERBUS_CA_M (BIT(30)) -#define SPI_MEM_SPI_SMEM_HYPERBUS_CA_V 0x1 -#define SPI_MEM_SPI_SMEM_HYPERBUS_CA_S 30 -/* SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR : HRO ;bitpos:[29] ;default: 1'b0 ; */ -/*description: Set this bit to enable octa_ram address out when accesses to external RAM, which - means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1] -, 1'b0}..*/ -#define SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR (BIT(29)) -#define SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR_M (BIT(29)) -#define SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR_V 0x1 -#define SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR_S 29 -/* SPI_MEM_SPI_SMEM_CLK_DIFF_INV : HRO ;bitpos:[28] ;default: 1'b0 ; */ -/*description: Set this bit to invert SPI_DIFF when accesses to external RAM. ..*/ -#define SPI_MEM_SPI_SMEM_CLK_DIFF_INV (BIT(28)) -#define SPI_MEM_SPI_SMEM_CLK_DIFF_INV_M (BIT(28)) -#define SPI_MEM_SPI_SMEM_CLK_DIFF_INV_V 0x1 -#define SPI_MEM_SPI_SMEM_CLK_DIFF_INV_S 28 -/* SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X : HRO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 a -ccesses flash or SPI1 accesses flash or sram..*/ -#define SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X (BIT(27)) -#define SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X_M (BIT(27)) -#define SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X_V 0x1 -#define SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X_S 27 -/* SPI_MEM_SPI_SMEM_DQS_CA_IN : HRO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR -..*/ -#define SPI_MEM_SPI_SMEM_DQS_CA_IN (BIT(26)) -#define SPI_MEM_SPI_SMEM_DQS_CA_IN_M (BIT(26)) -#define SPI_MEM_SPI_SMEM_DQS_CA_IN_V 0x1 -#define SPI_MEM_SPI_SMEM_DQS_CA_IN_S 26 -/* SPI_MEM_SPI_SMEM_CLK_DIFF_EN : HRO ;bitpos:[24] ;default: 1'b0 ; */ -/*description: Set this bit to enable the differential SPI_CLK#..*/ -#define SPI_MEM_SPI_SMEM_CLK_DIFF_EN (BIT(24)) -#define SPI_MEM_SPI_SMEM_CLK_DIFF_EN_M (BIT(24)) -#define SPI_MEM_SPI_SMEM_CLK_DIFF_EN_V 0x1 -#define SPI_MEM_SPI_SMEM_CLK_DIFF_EN_S 24 -/* SPI_MEM_SPI_SMEM_DDR_DQS_LOOP : HRO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi -0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or -SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and n -egative edge of SPI_DQS..*/ -#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP (BIT(21)) -#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_M (BIT(21)) -#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_V 0x1 -#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_S 21 -/* SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD : HRO ;bitpos:[20:14] ;default: 7'b0 ; */ -/*description: The delay number of data strobe which from memory based on SPI clock..*/ -#define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD 0x0000007F -#define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_M ((SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_V)<<(SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_S)) -#define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_V 0x7F -#define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_S 14 -/* SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN : HRO ;bitpos:[13] ;default: 1'h1 ; */ -/*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when -accesses to external RAM..*/ -#define SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN (BIT(13)) -#define SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN_M (BIT(13)) -#define SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN_V 0x1 -#define SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN_S 13 -/* SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN : HRO ;bitpos:[12] ;default: 1'h1 ; */ -/*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when - accesses to external RAM..*/ -#define SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN (BIT(12)) -#define SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN_M (BIT(12)) -#define SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN_V 0x1 -#define SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN_S 12 -/* SPI_MEM_SPI_SMEM_OUTMINBYTELEN : HRO ;bitpos:[11:5] ;default: 7'b1 ; */ -/*description: It is the minimum output data length in the DDR psram..*/ -#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN 0x0000007F -#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN_M ((SPI_MEM_SPI_SMEM_OUTMINBYTELEN_V)<<(SPI_MEM_SPI_SMEM_OUTMINBYTELEN_S)) -#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN_V 0x7F -#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN_S 5 -/* SPI_MEM_SPI_SMEM_DDR_CMD_DIS : HRO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: the bit is used to disable dual edge in command phase when DDR mode..*/ -#define SPI_MEM_SPI_SMEM_DDR_CMD_DIS (BIT(4)) -#define SPI_MEM_SPI_SMEM_DDR_CMD_DIS_M (BIT(4)) -#define SPI_MEM_SPI_SMEM_DDR_CMD_DIS_V 0x1 -#define SPI_MEM_SPI_SMEM_DDR_CMD_DIS_S 4 -/* SPI_MEM_SPI_SMEM_DDR_WDAT_SWP : HRO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set the bit to reorder tx data of the word in spi DDR mode..*/ -#define SPI_MEM_SPI_SMEM_DDR_WDAT_SWP (BIT(3)) -#define SPI_MEM_SPI_SMEM_DDR_WDAT_SWP_M (BIT(3)) -#define SPI_MEM_SPI_SMEM_DDR_WDAT_SWP_V 0x1 -#define SPI_MEM_SPI_SMEM_DDR_WDAT_SWP_S 3 -/* SPI_MEM_SPI_SMEM_DDR_RDAT_SWP : HRO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set the bit to reorder rx data of the word in spi DDR mode..*/ -#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP (BIT(2)) -#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP_M (BIT(2)) -#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP_V 0x1 -#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP_S 2 -/* SPI_MEM_SPI_SMEM_VAR_DUMMY : HRO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set the bit to enable variable dummy cycle in spi DDR mode..*/ -#define SPI_MEM_SPI_SMEM_VAR_DUMMY (BIT(1)) -#define SPI_MEM_SPI_SMEM_VAR_DUMMY_M (BIT(1)) -#define SPI_MEM_SPI_SMEM_VAR_DUMMY_V 0x1 -#define SPI_MEM_SPI_SMEM_VAR_DUMMY_S 1 -/* SPI_MEM_SPI_SMEM_DDR_EN : HRO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: 1: in DDR mode, 0 in SDR mode.*/ -#define SPI_MEM_SPI_SMEM_DDR_EN (BIT(0)) -#define SPI_MEM_SPI_SMEM_DDR_EN_M (BIT(0)) -#define SPI_MEM_SPI_SMEM_DDR_EN_V 0x1 -#define SPI_MEM_SPI_SMEM_DDR_EN_S 0 - -#define SPI_MEM_SPI_FMEM_PMS0_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x100) -/* SPI_MEM_SPI_FMEM_PMS0_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash - PMS section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_ -PMS$n_SIZE_REG..*/ -#define SPI_MEM_SPI_FMEM_PMS0_ECC (BIT(2)) -#define SPI_MEM_SPI_FMEM_PMS0_ECC_M (BIT(2)) -#define SPI_MEM_SPI_FMEM_PMS0_ECC_V 0x1 -#define SPI_MEM_SPI_FMEM_PMS0_ECC_S 2 -/* SPI_MEM_SPI_FMEM_PMS0_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */ -/*description: 1: SPI1 flash PMS section $n write accessible. 0: Not allowed..*/ -#define SPI_MEM_SPI_FMEM_PMS0_WR_ATTR (BIT(1)) -#define SPI_MEM_SPI_FMEM_PMS0_WR_ATTR_M (BIT(1)) -#define SPI_MEM_SPI_FMEM_PMS0_WR_ATTR_V 0x1 -#define SPI_MEM_SPI_FMEM_PMS0_WR_ATTR_S 1 -/* SPI_MEM_SPI_FMEM_PMS0_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */ -/*description: 1: SPI1 flash PMS section $n read accessible. 0: Not allowed..*/ -#define SPI_MEM_SPI_FMEM_PMS0_RD_ATTR (BIT(0)) -#define SPI_MEM_SPI_FMEM_PMS0_RD_ATTR_M (BIT(0)) -#define SPI_MEM_SPI_FMEM_PMS0_RD_ATTR_V 0x1 -#define SPI_MEM_SPI_FMEM_PMS0_RD_ATTR_S 0 - -#define SPI_MEM_SPI_FMEM_PMS1_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x104) -/* SPI_MEM_SPI_FMEM_PMS1_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash - PMS section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_ -PMS$n_SIZE_REG..*/ -#define SPI_MEM_SPI_FMEM_PMS1_ECC (BIT(2)) -#define SPI_MEM_SPI_FMEM_PMS1_ECC_M (BIT(2)) -#define SPI_MEM_SPI_FMEM_PMS1_ECC_V 0x1 -#define SPI_MEM_SPI_FMEM_PMS1_ECC_S 2 -/* SPI_MEM_SPI_FMEM_PMS1_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */ -/*description: 1: SPI1 flash PMS section $n write accessible. 0: Not allowed..*/ -#define SPI_MEM_SPI_FMEM_PMS1_WR_ATTR (BIT(1)) -#define SPI_MEM_SPI_FMEM_PMS1_WR_ATTR_M (BIT(1)) -#define SPI_MEM_SPI_FMEM_PMS1_WR_ATTR_V 0x1 -#define SPI_MEM_SPI_FMEM_PMS1_WR_ATTR_S 1 -/* SPI_MEM_SPI_FMEM_PMS1_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */ -/*description: 1: SPI1 flash PMS section $n read accessible. 0: Not allowed..*/ -#define SPI_MEM_SPI_FMEM_PMS1_RD_ATTR (BIT(0)) -#define SPI_MEM_SPI_FMEM_PMS1_RD_ATTR_M (BIT(0)) -#define SPI_MEM_SPI_FMEM_PMS1_RD_ATTR_V 0x1 -#define SPI_MEM_SPI_FMEM_PMS1_RD_ATTR_S 0 - -#define SPI_MEM_SPI_FMEM_PMS2_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x108) -/* SPI_MEM_SPI_FMEM_PMS2_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash - PMS section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_ -PMS$n_SIZE_REG..*/ -#define SPI_MEM_SPI_FMEM_PMS2_ECC (BIT(2)) -#define SPI_MEM_SPI_FMEM_PMS2_ECC_M (BIT(2)) -#define SPI_MEM_SPI_FMEM_PMS2_ECC_V 0x1 -#define SPI_MEM_SPI_FMEM_PMS2_ECC_S 2 -/* SPI_MEM_SPI_FMEM_PMS2_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */ -/*description: 1: SPI1 flash PMS section $n write accessible. 0: Not allowed..*/ -#define SPI_MEM_SPI_FMEM_PMS2_WR_ATTR (BIT(1)) -#define SPI_MEM_SPI_FMEM_PMS2_WR_ATTR_M (BIT(1)) -#define SPI_MEM_SPI_FMEM_PMS2_WR_ATTR_V 0x1 -#define SPI_MEM_SPI_FMEM_PMS2_WR_ATTR_S 1 -/* SPI_MEM_SPI_FMEM_PMS2_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */ -/*description: 1: SPI1 flash PMS section $n read accessible. 0: Not allowed..*/ -#define SPI_MEM_SPI_FMEM_PMS2_RD_ATTR (BIT(0)) -#define SPI_MEM_SPI_FMEM_PMS2_RD_ATTR_M (BIT(0)) -#define SPI_MEM_SPI_FMEM_PMS2_RD_ATTR_V 0x1 -#define SPI_MEM_SPI_FMEM_PMS2_RD_ATTR_S 0 - -#define SPI_MEM_SPI_FMEM_PMS3_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x10C) -/* SPI_MEM_SPI_FMEM_PMS3_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash - PMS section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_ -PMS$n_SIZE_REG..*/ -#define SPI_MEM_SPI_FMEM_PMS3_ECC (BIT(2)) -#define SPI_MEM_SPI_FMEM_PMS3_ECC_M (BIT(2)) -#define SPI_MEM_SPI_FMEM_PMS3_ECC_V 0x1 -#define SPI_MEM_SPI_FMEM_PMS3_ECC_S 2 -/* SPI_MEM_SPI_FMEM_PMS3_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */ -/*description: 1: SPI1 flash PMS section $n write accessible. 0: Not allowed..*/ -#define SPI_MEM_SPI_FMEM_PMS3_WR_ATTR (BIT(1)) -#define SPI_MEM_SPI_FMEM_PMS3_WR_ATTR_M (BIT(1)) -#define SPI_MEM_SPI_FMEM_PMS3_WR_ATTR_V 0x1 -#define SPI_MEM_SPI_FMEM_PMS3_WR_ATTR_S 1 -/* SPI_MEM_SPI_FMEM_PMS3_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */ -/*description: 1: SPI1 flash PMS section $n read accessible. 0: Not allowed..*/ -#define SPI_MEM_SPI_FMEM_PMS3_RD_ATTR (BIT(0)) -#define SPI_MEM_SPI_FMEM_PMS3_RD_ATTR_M (BIT(0)) -#define SPI_MEM_SPI_FMEM_PMS3_RD_ATTR_V 0x1 -#define SPI_MEM_SPI_FMEM_PMS3_RD_ATTR_S 0 - -#define SPI_MEM_SPI_FMEM_PMS0_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x110) -/* SPI_MEM_SPI_FMEM_PMS0_ADDR_S : R/W ;bitpos:[26:0] ;default: 27'h0 ; */ -/*description: SPI1 flash PMS section $n start address value.*/ -#define SPI_MEM_SPI_FMEM_PMS0_ADDR_S 0x07FFFFFF -#define SPI_MEM_SPI_FMEM_PMS0_ADDR_S_M ((SPI_MEM_SPI_FMEM_PMS0_ADDR_S_V)<<(SPI_MEM_SPI_FMEM_PMS0_ADDR_S_S)) -#define SPI_MEM_SPI_FMEM_PMS0_ADDR_S_V 0x7FFFFFF -#define SPI_MEM_SPI_FMEM_PMS0_ADDR_S_S 0 - -#define SPI_MEM_SPI_FMEM_PMS1_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x114) -/* SPI_MEM_SPI_FMEM_PMS1_ADDR_S : R/W ;bitpos:[26:0] ;default: 27'hffffff ; */ -/*description: SPI1 flash PMS section $n start address value.*/ -#define SPI_MEM_SPI_FMEM_PMS1_ADDR_S 0x07FFFFFF -#define SPI_MEM_SPI_FMEM_PMS1_ADDR_S_M ((SPI_MEM_SPI_FMEM_PMS1_ADDR_S_V)<<(SPI_MEM_SPI_FMEM_PMS1_ADDR_S_S)) -#define SPI_MEM_SPI_FMEM_PMS1_ADDR_S_V 0x7FFFFFF -#define SPI_MEM_SPI_FMEM_PMS1_ADDR_S_S 0 - -#define SPI_MEM_SPI_FMEM_PMS2_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x118) -/* SPI_MEM_SPI_FMEM_PMS2_ADDR_S : R/W ;bitpos:[26:0] ;default: 27'h1ffffff ; */ -/*description: SPI1 flash PMS section $n start address value.*/ -#define SPI_MEM_SPI_FMEM_PMS2_ADDR_S 0x07FFFFFF -#define SPI_MEM_SPI_FMEM_PMS2_ADDR_S_M ((SPI_MEM_SPI_FMEM_PMS2_ADDR_S_V)<<(SPI_MEM_SPI_FMEM_PMS2_ADDR_S_S)) -#define SPI_MEM_SPI_FMEM_PMS2_ADDR_S_V 0x7FFFFFF -#define SPI_MEM_SPI_FMEM_PMS2_ADDR_S_S 0 - -#define SPI_MEM_SPI_FMEM_PMS3_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x11C) -/* SPI_MEM_SPI_FMEM_PMS3_ADDR_S : R/W ;bitpos:[26:0] ;default: 27'h2ffffff ; */ -/*description: SPI1 flash PMS section $n start address value.*/ -#define SPI_MEM_SPI_FMEM_PMS3_ADDR_S 0x07FFFFFF -#define SPI_MEM_SPI_FMEM_PMS3_ADDR_S_M ((SPI_MEM_SPI_FMEM_PMS3_ADDR_S_V)<<(SPI_MEM_SPI_FMEM_PMS3_ADDR_S_S)) -#define SPI_MEM_SPI_FMEM_PMS3_ADDR_S_V 0x7FFFFFF -#define SPI_MEM_SPI_FMEM_PMS3_ADDR_S_S 0 - -#define SPI_MEM_SPI_FMEM_PMS0_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x120) -/* SPI_MEM_SPI_FMEM_PMS0_SIZE : R/W ;bitpos:[14:0] ;default: 15'h1000 ; */ -/*description: SPI1 flash PMS section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS -$n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/ -#define SPI_MEM_SPI_FMEM_PMS0_SIZE 0x00007FFF -#define SPI_MEM_SPI_FMEM_PMS0_SIZE_M ((SPI_MEM_SPI_FMEM_PMS0_SIZE_V)<<(SPI_MEM_SPI_FMEM_PMS0_SIZE_S)) -#define SPI_MEM_SPI_FMEM_PMS0_SIZE_V 0x7FFF -#define SPI_MEM_SPI_FMEM_PMS0_SIZE_S 0 - -#define SPI_MEM_SPI_FMEM_PMS1_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x124) -/* SPI_MEM_SPI_FMEM_PMS1_SIZE : R/W ;bitpos:[14:0] ;default: 15'h1000 ; */ -/*description: SPI1 flash PMS section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS -$n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/ -#define SPI_MEM_SPI_FMEM_PMS1_SIZE 0x00007FFF -#define SPI_MEM_SPI_FMEM_PMS1_SIZE_M ((SPI_MEM_SPI_FMEM_PMS1_SIZE_V)<<(SPI_MEM_SPI_FMEM_PMS1_SIZE_S)) -#define SPI_MEM_SPI_FMEM_PMS1_SIZE_V 0x7FFF -#define SPI_MEM_SPI_FMEM_PMS1_SIZE_S 0 - -#define SPI_MEM_SPI_FMEM_PMS2_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x128) -/* SPI_MEM_SPI_FMEM_PMS2_SIZE : R/W ;bitpos:[14:0] ;default: 15'h1000 ; */ -/*description: SPI1 flash PMS section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS -$n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/ -#define SPI_MEM_SPI_FMEM_PMS2_SIZE 0x00007FFF -#define SPI_MEM_SPI_FMEM_PMS2_SIZE_M ((SPI_MEM_SPI_FMEM_PMS2_SIZE_V)<<(SPI_MEM_SPI_FMEM_PMS2_SIZE_S)) -#define SPI_MEM_SPI_FMEM_PMS2_SIZE_V 0x7FFF -#define SPI_MEM_SPI_FMEM_PMS2_SIZE_S 0 - -#define SPI_MEM_SPI_FMEM_PMS3_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x12C) -/* SPI_MEM_SPI_FMEM_PMS3_SIZE : R/W ;bitpos:[14:0] ;default: 15'h1000 ; */ -/*description: SPI1 flash PMS section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS -$n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/ -#define SPI_MEM_SPI_FMEM_PMS3_SIZE 0x00007FFF -#define SPI_MEM_SPI_FMEM_PMS3_SIZE_M ((SPI_MEM_SPI_FMEM_PMS3_SIZE_V)<<(SPI_MEM_SPI_FMEM_PMS3_SIZE_S)) -#define SPI_MEM_SPI_FMEM_PMS3_SIZE_V 0x7FFF -#define SPI_MEM_SPI_FMEM_PMS3_SIZE_S 0 - -#define SPI_MEM_SPI_SMEM_PMS0_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x130) -/* SPI_MEM_SPI_SMEM_PMS0_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th -e external RAM PMS section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG - and SPI_SMEM_PMS$n_SIZE_REG..*/ -#define SPI_MEM_SPI_SMEM_PMS0_ECC (BIT(2)) -#define SPI_MEM_SPI_SMEM_PMS0_ECC_M (BIT(2)) -#define SPI_MEM_SPI_SMEM_PMS0_ECC_V 0x1 -#define SPI_MEM_SPI_SMEM_PMS0_ECC_S 2 -/* SPI_MEM_SPI_SMEM_PMS0_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */ -/*description: 1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed..*/ -#define SPI_MEM_SPI_SMEM_PMS0_WR_ATTR (BIT(1)) -#define SPI_MEM_SPI_SMEM_PMS0_WR_ATTR_M (BIT(1)) -#define SPI_MEM_SPI_SMEM_PMS0_WR_ATTR_V 0x1 -#define SPI_MEM_SPI_SMEM_PMS0_WR_ATTR_S 1 -/* SPI_MEM_SPI_SMEM_PMS0_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */ -/*description: 1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed..*/ -#define SPI_MEM_SPI_SMEM_PMS0_RD_ATTR (BIT(0)) -#define SPI_MEM_SPI_SMEM_PMS0_RD_ATTR_M (BIT(0)) -#define SPI_MEM_SPI_SMEM_PMS0_RD_ATTR_V 0x1 -#define SPI_MEM_SPI_SMEM_PMS0_RD_ATTR_S 0 - -#define SPI_MEM_SPI_SMEM_PMS1_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x134) -/* SPI_MEM_SPI_SMEM_PMS1_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th -e external RAM PMS section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG - and SPI_SMEM_PMS$n_SIZE_REG..*/ -#define SPI_MEM_SPI_SMEM_PMS1_ECC (BIT(2)) -#define SPI_MEM_SPI_SMEM_PMS1_ECC_M (BIT(2)) -#define SPI_MEM_SPI_SMEM_PMS1_ECC_V 0x1 -#define SPI_MEM_SPI_SMEM_PMS1_ECC_S 2 -/* SPI_MEM_SPI_SMEM_PMS1_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */ -/*description: 1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed..*/ -#define SPI_MEM_SPI_SMEM_PMS1_WR_ATTR (BIT(1)) -#define SPI_MEM_SPI_SMEM_PMS1_WR_ATTR_M (BIT(1)) -#define SPI_MEM_SPI_SMEM_PMS1_WR_ATTR_V 0x1 -#define SPI_MEM_SPI_SMEM_PMS1_WR_ATTR_S 1 -/* SPI_MEM_SPI_SMEM_PMS1_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */ -/*description: 1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed..*/ -#define SPI_MEM_SPI_SMEM_PMS1_RD_ATTR (BIT(0)) -#define SPI_MEM_SPI_SMEM_PMS1_RD_ATTR_M (BIT(0)) -#define SPI_MEM_SPI_SMEM_PMS1_RD_ATTR_V 0x1 -#define SPI_MEM_SPI_SMEM_PMS1_RD_ATTR_S 0 - -#define SPI_MEM_SPI_SMEM_PMS2_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x138) -/* SPI_MEM_SPI_SMEM_PMS2_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th -e external RAM PMS section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG - and SPI_SMEM_PMS$n_SIZE_REG..*/ -#define SPI_MEM_SPI_SMEM_PMS2_ECC (BIT(2)) -#define SPI_MEM_SPI_SMEM_PMS2_ECC_M (BIT(2)) -#define SPI_MEM_SPI_SMEM_PMS2_ECC_V 0x1 -#define SPI_MEM_SPI_SMEM_PMS2_ECC_S 2 -/* SPI_MEM_SPI_SMEM_PMS2_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */ -/*description: 1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed..*/ -#define SPI_MEM_SPI_SMEM_PMS2_WR_ATTR (BIT(1)) -#define SPI_MEM_SPI_SMEM_PMS2_WR_ATTR_M (BIT(1)) -#define SPI_MEM_SPI_SMEM_PMS2_WR_ATTR_V 0x1 -#define SPI_MEM_SPI_SMEM_PMS2_WR_ATTR_S 1 -/* SPI_MEM_SPI_SMEM_PMS2_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */ -/*description: 1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed..*/ -#define SPI_MEM_SPI_SMEM_PMS2_RD_ATTR (BIT(0)) -#define SPI_MEM_SPI_SMEM_PMS2_RD_ATTR_M (BIT(0)) -#define SPI_MEM_SPI_SMEM_PMS2_RD_ATTR_V 0x1 -#define SPI_MEM_SPI_SMEM_PMS2_RD_ATTR_S 0 - -#define SPI_MEM_SPI_SMEM_PMS3_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x13C) -/* SPI_MEM_SPI_SMEM_PMS3_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th -e external RAM PMS section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG - and SPI_SMEM_PMS$n_SIZE_REG..*/ -#define SPI_MEM_SPI_SMEM_PMS3_ECC (BIT(2)) -#define SPI_MEM_SPI_SMEM_PMS3_ECC_M (BIT(2)) -#define SPI_MEM_SPI_SMEM_PMS3_ECC_V 0x1 -#define SPI_MEM_SPI_SMEM_PMS3_ECC_S 2 -/* SPI_MEM_SPI_SMEM_PMS3_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */ -/*description: 1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed..*/ -#define SPI_MEM_SPI_SMEM_PMS3_WR_ATTR (BIT(1)) -#define SPI_MEM_SPI_SMEM_PMS3_WR_ATTR_M (BIT(1)) -#define SPI_MEM_SPI_SMEM_PMS3_WR_ATTR_V 0x1 -#define SPI_MEM_SPI_SMEM_PMS3_WR_ATTR_S 1 -/* SPI_MEM_SPI_SMEM_PMS3_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */ -/*description: 1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed..*/ -#define SPI_MEM_SPI_SMEM_PMS3_RD_ATTR (BIT(0)) -#define SPI_MEM_SPI_SMEM_PMS3_RD_ATTR_M (BIT(0)) -#define SPI_MEM_SPI_SMEM_PMS3_RD_ATTR_V 0x1 -#define SPI_MEM_SPI_SMEM_PMS3_RD_ATTR_S 0 - -#define SPI_MEM_SPI_SMEM_PMS0_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x140) -/* SPI_MEM_SPI_SMEM_PMS0_ADDR_S : R/W ;bitpos:[26:0] ;default: 27'h0 ; */ -/*description: SPI1 external RAM PMS section $n start address value.*/ -#define SPI_MEM_SPI_SMEM_PMS0_ADDR_S 0x07FFFFFF -#define SPI_MEM_SPI_SMEM_PMS0_ADDR_S_M ((SPI_MEM_SPI_SMEM_PMS0_ADDR_S_V)<<(SPI_MEM_SPI_SMEM_PMS0_ADDR_S_S)) -#define SPI_MEM_SPI_SMEM_PMS0_ADDR_S_V 0x7FFFFFF -#define SPI_MEM_SPI_SMEM_PMS0_ADDR_S_S 0 - -#define SPI_MEM_SPI_SMEM_PMS1_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x144) -/* SPI_MEM_SPI_SMEM_PMS1_ADDR_S : R/W ;bitpos:[26:0] ;default: 27'hffffff ; */ -/*description: SPI1 external RAM PMS section $n start address value.*/ -#define SPI_MEM_SPI_SMEM_PMS1_ADDR_S 0x07FFFFFF -#define SPI_MEM_SPI_SMEM_PMS1_ADDR_S_M ((SPI_MEM_SPI_SMEM_PMS1_ADDR_S_V)<<(SPI_MEM_SPI_SMEM_PMS1_ADDR_S_S)) -#define SPI_MEM_SPI_SMEM_PMS1_ADDR_S_V 0x7FFFFFF -#define SPI_MEM_SPI_SMEM_PMS1_ADDR_S_S 0 - -#define SPI_MEM_SPI_SMEM_PMS2_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x148) -/* SPI_MEM_SPI_SMEM_PMS2_ADDR_S : R/W ;bitpos:[26:0] ;default: 27'h1ffffff ; */ -/*description: SPI1 external RAM PMS section $n start address value.*/ -#define SPI_MEM_SPI_SMEM_PMS2_ADDR_S 0x07FFFFFF -#define SPI_MEM_SPI_SMEM_PMS2_ADDR_S_M ((SPI_MEM_SPI_SMEM_PMS2_ADDR_S_V)<<(SPI_MEM_SPI_SMEM_PMS2_ADDR_S_S)) -#define SPI_MEM_SPI_SMEM_PMS2_ADDR_S_V 0x7FFFFFF -#define SPI_MEM_SPI_SMEM_PMS2_ADDR_S_S 0 - -#define SPI_MEM_SPI_SMEM_PMS3_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x14C) -/* SPI_MEM_SPI_SMEM_PMS3_ADDR_S : R/W ;bitpos:[26:0] ;default: 27'h2ffffff ; */ -/*description: SPI1 external RAM PMS section $n start address value.*/ -#define SPI_MEM_SPI_SMEM_PMS3_ADDR_S 0x07FFFFFF -#define SPI_MEM_SPI_SMEM_PMS3_ADDR_S_M ((SPI_MEM_SPI_SMEM_PMS3_ADDR_S_V)<<(SPI_MEM_SPI_SMEM_PMS3_ADDR_S_S)) -#define SPI_MEM_SPI_SMEM_PMS3_ADDR_S_V 0x7FFFFFF -#define SPI_MEM_SPI_SMEM_PMS3_ADDR_S_S 0 - -#define SPI_MEM_SPI_SMEM_PMS0_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x150) -/* SPI_MEM_SPI_SMEM_PMS0_SIZE : R/W ;bitpos:[14:0] ;default: 15'h1000 ; */ -/*description: SPI1 external RAM PMS section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S -MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/ -#define SPI_MEM_SPI_SMEM_PMS0_SIZE 0x00007FFF -#define SPI_MEM_SPI_SMEM_PMS0_SIZE_M ((SPI_MEM_SPI_SMEM_PMS0_SIZE_V)<<(SPI_MEM_SPI_SMEM_PMS0_SIZE_S)) -#define SPI_MEM_SPI_SMEM_PMS0_SIZE_V 0x7FFF -#define SPI_MEM_SPI_SMEM_PMS0_SIZE_S 0 - -#define SPI_MEM_SPI_SMEM_PMS1_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x154) -/* SPI_MEM_SPI_SMEM_PMS1_SIZE : R/W ;bitpos:[14:0] ;default: 15'h1000 ; */ -/*description: SPI1 external RAM PMS section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S -MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/ -#define SPI_MEM_SPI_SMEM_PMS1_SIZE 0x00007FFF -#define SPI_MEM_SPI_SMEM_PMS1_SIZE_M ((SPI_MEM_SPI_SMEM_PMS1_SIZE_V)<<(SPI_MEM_SPI_SMEM_PMS1_SIZE_S)) -#define SPI_MEM_SPI_SMEM_PMS1_SIZE_V 0x7FFF -#define SPI_MEM_SPI_SMEM_PMS1_SIZE_S 0 - -#define SPI_MEM_SPI_SMEM_PMS2_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x158) -/* SPI_MEM_SPI_SMEM_PMS2_SIZE : R/W ;bitpos:[14:0] ;default: 15'h1000 ; */ -/*description: SPI1 external RAM PMS section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S -MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/ -#define SPI_MEM_SPI_SMEM_PMS2_SIZE 0x00007FFF -#define SPI_MEM_SPI_SMEM_PMS2_SIZE_M ((SPI_MEM_SPI_SMEM_PMS2_SIZE_V)<<(SPI_MEM_SPI_SMEM_PMS2_SIZE_S)) -#define SPI_MEM_SPI_SMEM_PMS2_SIZE_V 0x7FFF -#define SPI_MEM_SPI_SMEM_PMS2_SIZE_S 0 - -#define SPI_MEM_SPI_SMEM_PMS3_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x15C) -/* SPI_MEM_SPI_SMEM_PMS3_SIZE : R/W ;bitpos:[14:0] ;default: 15'h1000 ; */ -/*description: SPI1 external RAM PMS section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S -MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/ -#define SPI_MEM_SPI_SMEM_PMS3_SIZE 0x00007FFF -#define SPI_MEM_SPI_SMEM_PMS3_SIZE_M ((SPI_MEM_SPI_SMEM_PMS3_SIZE_V)<<(SPI_MEM_SPI_SMEM_PMS3_SIZE_S)) -#define SPI_MEM_SPI_SMEM_PMS3_SIZE_V 0x7FFF -#define SPI_MEM_SPI_SMEM_PMS3_SIZE_S 0 - -#define SPI_MEM_PMS_REJECT_REG(i) (REG_SPI_MEM_BASE(i) + 0x164) -/* SPI_MEM_PMS_IVD : R/SS/WTC ;bitpos:[31] ;default: 1'h0 ; */ -/*description: 1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit - error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set..*/ -#define SPI_MEM_PMS_IVD (BIT(31)) -#define SPI_MEM_PMS_IVD_M (BIT(31)) -#define SPI_MEM_PMS_IVD_V 0x1 -#define SPI_MEM_PMS_IVD_S 31 -/* SPI_MEM_PMS_MULTI_HIT : R/SS/WTC ;bitpos:[30] ;default: 1'b0 ; */ -/*description: 1: SPI1 access is rejected because of address miss. 0: No address miss error. It - is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set..*/ -#define SPI_MEM_PMS_MULTI_HIT (BIT(30)) -#define SPI_MEM_PMS_MULTI_HIT_M (BIT(30)) -#define SPI_MEM_PMS_MULTI_HIT_V 0x1 -#define SPI_MEM_PMS_MULTI_HIT_S 30 -/* SPI_MEM_PMS_ST : R/SS/WTC ;bitpos:[29] ;default: 1'b0 ; */ -/*description: 1: SPI1 read access error. 0: No read access error. It is cleared by when SPI_M -EM_PMS_REJECT_INT_CLR bit is set..*/ -#define SPI_MEM_PMS_ST (BIT(29)) -#define SPI_MEM_PMS_ST_M (BIT(29)) -#define SPI_MEM_PMS_ST_V 0x1 -#define SPI_MEM_PMS_ST_S 29 -/* SPI_MEM_PMS_LD : R/SS/WTC ;bitpos:[28] ;default: 1'b0 ; */ -/*description: 1: SPI1 write access error. 0: No write access error. It is cleared by when SPI -_MEM_PMS_REJECT_INT_CLR bit is set..*/ -#define SPI_MEM_PMS_LD (BIT(28)) -#define SPI_MEM_PMS_LD_M (BIT(28)) -#define SPI_MEM_PMS_LD_V 0x1 -#define SPI_MEM_PMS_LD_S 28 -/* SPI_MEM_PM_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: Set this bit to enable SPI0/1 transfer permission control function..*/ -#define SPI_MEM_PM_EN (BIT(27)) -#define SPI_MEM_PM_EN_M (BIT(27)) -#define SPI_MEM_PM_EN_V 0x1 -#define SPI_MEM_PM_EN_S 27 -/* SPI_MEM_REJECT_ADDR : R/SS/WTC ;bitpos:[26:0] ;default: 27'h0 ; */ -/*description: This bits show the first SPI1 access error address. It is cleared by when SPI_M -EM_PMS_REJECT_INT_CLR bit is set..*/ -#define SPI_MEM_REJECT_ADDR 0x07FFFFFF -#define SPI_MEM_REJECT_ADDR_M ((SPI_MEM_REJECT_ADDR_V)<<(SPI_MEM_REJECT_ADDR_S)) -#define SPI_MEM_REJECT_ADDR_V 0x7FFFFFF -#define SPI_MEM_REJECT_ADDR_S 0 - -#define SPI_MEM_ECC_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x168) -/* SPI_MEM_ECC_ERR_BITS : HRO ;bitpos:[31:25] ;default: 7'd0 ; */ -/*description: Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding - to byte 0 bit 0 to byte 15 bit 7).*/ -#define SPI_MEM_ECC_ERR_BITS 0x0000007F -#define SPI_MEM_ECC_ERR_BITS_M ((SPI_MEM_ECC_ERR_BITS_V)<<(SPI_MEM_ECC_ERR_BITS_S)) -#define SPI_MEM_ECC_ERR_BITS_V 0x7F -#define SPI_MEM_ECC_ERR_BITS_S 25 -/* SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN : HRO ;bitpos:[24] ;default: 1'b1 ; */ -/*description: 1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is upd -ated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADD -R record the first ECC error information..*/ -#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN (BIT(24)) -#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_M (BIT(24)) -#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_V 0x1 -#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_S 24 -/* SPI_MEM_USR_ECC_ADDR_EN : HRO ;bitpos:[21] ;default: 1'd0 ; */ -/*description: Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer..*/ -#define SPI_MEM_USR_ECC_ADDR_EN (BIT(21)) -#define SPI_MEM_USR_ECC_ADDR_EN_M (BIT(21)) -#define SPI_MEM_USR_ECC_ADDR_EN_V 0x1 -#define SPI_MEM_USR_ECC_ADDR_EN_S 21 -/* SPI_MEM_SPI_FMEM_ECC_ADDR_EN : HRO ;bitpos:[20] ;default: 1'd0 ; */ -/*description: Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to t -he ECC region or non-ECC region of flash. If there is no ECC region in flash, th -is bit should be 0. Otherwise, this bit should be 1..*/ -#define SPI_MEM_SPI_FMEM_ECC_ADDR_EN (BIT(20)) -#define SPI_MEM_SPI_FMEM_ECC_ADDR_EN_M (BIT(20)) -#define SPI_MEM_SPI_FMEM_ECC_ADDR_EN_V 0x1 -#define SPI_MEM_SPI_FMEM_ECC_ADDR_EN_S 20 -/* SPI_MEM_SPI_FMEM_PAGE_SIZE : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ -/*description: Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: -1024 bytes. 3: 2048 bytes..*/ -#define SPI_MEM_SPI_FMEM_PAGE_SIZE 0x00000003 -#define SPI_MEM_SPI_FMEM_PAGE_SIZE_M ((SPI_MEM_SPI_FMEM_PAGE_SIZE_V)<<(SPI_MEM_SPI_FMEM_PAGE_SIZE_S)) -#define SPI_MEM_SPI_FMEM_PAGE_SIZE_V 0x3 -#define SPI_MEM_SPI_FMEM_PAGE_SIZE_S 18 -/* SPI_MEM_SPI_FMEM_ECC_ERR_INT_EN : HRO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: Set this bit to calculate the error times of MSPI ECC read when accesses to flas -h..*/ -#define SPI_MEM_SPI_FMEM_ECC_ERR_INT_EN (BIT(17)) -#define SPI_MEM_SPI_FMEM_ECC_ERR_INT_EN_M (BIT(17)) -#define SPI_MEM_SPI_FMEM_ECC_ERR_INT_EN_V 0x1 -#define SPI_MEM_SPI_FMEM_ECC_ERR_INT_EN_S 17 -/* SPI_MEM_SPI_FMEM_ECC_ERR_INT_NUM : HRO ;bitpos:[16:11] ;default: 6'd10 ; */ -/*description: Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interr -upt..*/ -#define SPI_MEM_SPI_FMEM_ECC_ERR_INT_NUM 0x0000003F -#define SPI_MEM_SPI_FMEM_ECC_ERR_INT_NUM_M ((SPI_MEM_SPI_FMEM_ECC_ERR_INT_NUM_V)<<(SPI_MEM_SPI_FMEM_ECC_ERR_INT_NUM_S)) -#define SPI_MEM_SPI_FMEM_ECC_ERR_INT_NUM_V 0x3F -#define SPI_MEM_SPI_FMEM_ECC_ERR_INT_NUM_S 11 -/* SPI_MEM_ECC_ERR_CNT : HRO ;bitpos:[10:5] ;default: 6'd0 ; */ -/*description: This bits show the error times of MSPI ECC read. It is cleared by when SPI_MEM_ -ECC_ERR_INT_CLR bit is set..*/ -#define SPI_MEM_ECC_ERR_CNT 0x0000003F -#define SPI_MEM_ECC_ERR_CNT_M ((SPI_MEM_ECC_ERR_CNT_V)<<(SPI_MEM_ECC_ERR_CNT_S)) -#define SPI_MEM_ECC_ERR_CNT_V 0x3F -#define SPI_MEM_ECC_ERR_CNT_S 5 - -#define SPI_MEM_ECC_ERR_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x16C) -/* SPI_MEM_ECC_ERR_ADDR : HRO ;bitpos:[26:0] ;default: 27'h0 ; */ -/*description: This bits show the first MSPI ECC error address. It is cleared by when SPI_MEM_ -ECC_ERR_INT_CLR bit is set..*/ -#define SPI_MEM_ECC_ERR_ADDR 0x07FFFFFF -#define SPI_MEM_ECC_ERR_ADDR_M ((SPI_MEM_ECC_ERR_ADDR_V)<<(SPI_MEM_ECC_ERR_ADDR_S)) -#define SPI_MEM_ECC_ERR_ADDR_V 0x7FFFFFF -#define SPI_MEM_ECC_ERR_ADDR_S 0 - -#define SPI_MEM_AXI_ERR_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x170) -/* SPI_MEM_AXI_ERR_ADDR : R/SS/WTC ;bitpos:[26:0] ;default: 27'h0 ; */ -/*description: This bits show the first AXI write/read invalid error or AXI write flash error a -ddress. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, SPI_MEM_AXI_WR_FLAS -H_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set..*/ -#define SPI_MEM_AXI_ERR_ADDR 0x07FFFFFF -#define SPI_MEM_AXI_ERR_ADDR_M ((SPI_MEM_AXI_ERR_ADDR_V)<<(SPI_MEM_AXI_ERR_ADDR_S)) -#define SPI_MEM_AXI_ERR_ADDR_V 0x7FFFFFF -#define SPI_MEM_AXI_ERR_ADDR_S 0 - -#define SPI_MEM_SPI_SMEM_ECC_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x174) -/* SPI_MEM_SPI_SMEM_ECC_ADDR_EN : HRO ;bitpos:[20] ;default: 1'd0 ; */ -/*description: Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to t -he ECC region or non-ECC region of external RAM. If there is no ECC region in ex -ternal RAM, this bit should be 0. Otherwise, this bit should be 1..*/ -#define SPI_MEM_SPI_SMEM_ECC_ADDR_EN (BIT(20)) -#define SPI_MEM_SPI_SMEM_ECC_ADDR_EN_M (BIT(20)) -#define SPI_MEM_SPI_SMEM_ECC_ADDR_EN_V 0x1 -#define SPI_MEM_SPI_SMEM_ECC_ADDR_EN_S 20 -/* SPI_MEM_SPI_SMEM_PAGE_SIZE : HRO ;bitpos:[19:18] ;default: 2'd2 ; */ -/*description: Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 byt -es. 2: 1024 bytes. 3: 2048 bytes..*/ -#define SPI_MEM_SPI_SMEM_PAGE_SIZE 0x00000003 -#define SPI_MEM_SPI_SMEM_PAGE_SIZE_M ((SPI_MEM_SPI_SMEM_PAGE_SIZE_V)<<(SPI_MEM_SPI_SMEM_PAGE_SIZE_S)) -#define SPI_MEM_SPI_SMEM_PAGE_SIZE_V 0x3 -#define SPI_MEM_SPI_SMEM_PAGE_SIZE_S 18 -/* SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN : HRO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: Set this bit to calculate the error times of MSPI ECC read when accesses to exte -rnal RAM..*/ -#define SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN (BIT(17)) -#define SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN_M (BIT(17)) -#define SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN_V 0x1 -#define SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN_S 17 - -#define SPI_MEM_SPI_SMEM_AXI_ADDR_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x178) -/* SPI_MEM_SPI_ALL_AXI_TRANS_AFIFO_EMPTY : RO ;bitpos:[31] ;default: 1'b1 ; */ -/*description: This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO -and RDATA_AFIFO are empty and spi0_mst_st is IDLE..*/ -#define SPI_MEM_SPI_ALL_AXI_TRANS_AFIFO_EMPTY (BIT(31)) -#define SPI_MEM_SPI_ALL_AXI_TRANS_AFIFO_EMPTY_M (BIT(31)) -#define SPI_MEM_SPI_ALL_AXI_TRANS_AFIFO_EMPTY_V 0x1 -#define SPI_MEM_SPI_ALL_AXI_TRANS_AFIFO_EMPTY_S 31 -/* SPI_MEM_SPI_WBLEN_AFIFO_REMPTY : RO ;bitpos:[30] ;default: 1'b1 ; */ -/*description: 1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending..*/ -#define SPI_MEM_SPI_WBLEN_AFIFO_REMPTY (BIT(30)) -#define SPI_MEM_SPI_WBLEN_AFIFO_REMPTY_M (BIT(30)) -#define SPI_MEM_SPI_WBLEN_AFIFO_REMPTY_V 0x1 -#define SPI_MEM_SPI_WBLEN_AFIFO_REMPTY_S 30 -/* SPI_MEM_SPI_WDATA_AFIFO_REMPTY : RO ;bitpos:[29] ;default: 1'b1 ; */ -/*description: 1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending..*/ -#define SPI_MEM_SPI_WDATA_AFIFO_REMPTY (BIT(29)) -#define SPI_MEM_SPI_WDATA_AFIFO_REMPTY_M (BIT(29)) -#define SPI_MEM_SPI_WDATA_AFIFO_REMPTY_V 0x1 -#define SPI_MEM_SPI_WDATA_AFIFO_REMPTY_S 29 -/* SPI_MEM_SPI_RADDR_AFIFO_REMPTY : RO ;bitpos:[28] ;default: 1'b1 ; */ -/*description: 1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending..*/ -#define SPI_MEM_SPI_RADDR_AFIFO_REMPTY (BIT(28)) -#define SPI_MEM_SPI_RADDR_AFIFO_REMPTY_M (BIT(28)) -#define SPI_MEM_SPI_RADDR_AFIFO_REMPTY_V 0x1 -#define SPI_MEM_SPI_RADDR_AFIFO_REMPTY_S 28 -/* SPI_MEM_SPI_RDATA_AFIFO_REMPTY : RO ;bitpos:[27] ;default: 1'b1 ; */ -/*description: 1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending..*/ -#define SPI_MEM_SPI_RDATA_AFIFO_REMPTY (BIT(27)) -#define SPI_MEM_SPI_RDATA_AFIFO_REMPTY_M (BIT(27)) -#define SPI_MEM_SPI_RDATA_AFIFO_REMPTY_V 0x1 -#define SPI_MEM_SPI_RDATA_AFIFO_REMPTY_S 27 -/* SPI_MEM_ALL_FIFO_EMPTY : RO ;bitpos:[26] ;default: 1'b1 ; */ -/*description: The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers - and SPI0 transfers are done. 0: Others..*/ -#define SPI_MEM_ALL_FIFO_EMPTY (BIT(26)) -#define SPI_MEM_ALL_FIFO_EMPTY_M (BIT(26)) -#define SPI_MEM_ALL_FIFO_EMPTY_V 0x1 -#define SPI_MEM_ALL_FIFO_EMPTY_S 26 - -#define SPI_MEM_TIMING_CALI_REG(i) (REG_SPI_MEM_BASE(i) + 0x180) -/* SPI_MEM_TIMING_CALI_UPDATE : WT ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Set this bit to update delay mode, delay num and extra dummy in MSPI..*/ -#define SPI_MEM_TIMING_CALI_UPDATE (BIT(6)) -#define SPI_MEM_TIMING_CALI_UPDATE_M (BIT(6)) -#define SPI_MEM_TIMING_CALI_UPDATE_V 0x1 -#define SPI_MEM_TIMING_CALI_UPDATE_S 6 -/* SPI_MEM_DLL_TIMING_CALI : HRO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to enable DLL for timing calibration in DDR mode when accessed to f -lash..*/ -#define SPI_MEM_DLL_TIMING_CALI (BIT(5)) -#define SPI_MEM_DLL_TIMING_CALI_M (BIT(5)) -#define SPI_MEM_DLL_TIMING_CALI_V 0x1 -#define SPI_MEM_DLL_TIMING_CALI_S 5 -/* SPI_MEM_EXTRA_DUMMY_CYCLELEN : R/W ;bitpos:[4:2] ;default: 3'd0 ; */ -/*description: add extra dummy spi clock cycle length for spi clock calibration..*/ -#define SPI_MEM_EXTRA_DUMMY_CYCLELEN 0x00000007 -#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_M ((SPI_MEM_EXTRA_DUMMY_CYCLELEN_V)<<(SPI_MEM_EXTRA_DUMMY_CYCLELEN_S)) -#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_V 0x7 -#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_S 2 -/* SPI_MEM_TIMING_CALI : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The bit is used to enable timing auto-calibration for all reading operations..*/ -#define SPI_MEM_TIMING_CALI (BIT(1)) -#define SPI_MEM_TIMING_CALI_M (BIT(1)) -#define SPI_MEM_TIMING_CALI_V 0x1 -#define SPI_MEM_TIMING_CALI_S 1 -/* SPI_MEM_TIMING_CLK_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: The bit is used to enable timing adjust clock for all reading operations..*/ -#define SPI_MEM_TIMING_CLK_ENA (BIT(0)) -#define SPI_MEM_TIMING_CLK_ENA_M (BIT(0)) -#define SPI_MEM_TIMING_CLK_ENA_V 0x1 -#define SPI_MEM_TIMING_CLK_ENA_S 0 - -#define SPI_MEM_DIN_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x184) -/* SPI_MEM_DINS_MODE : R/W ;bitpos:[26:24] ;default: 3'h0 ; */ -/*description: the input signals are delayed by system clock cycles, 0: input without delayed, -1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp -ut with the spi_clk.*/ -#define SPI_MEM_DINS_MODE 0x00000007 -#define SPI_MEM_DINS_MODE_M ((SPI_MEM_DINS_MODE_V)<<(SPI_MEM_DINS_MODE_S)) -#define SPI_MEM_DINS_MODE_V 0x7 -#define SPI_MEM_DINS_MODE_S 24 -/* SPI_MEM_DIN7_MODE : R/W ;bitpos:[23:21] ;default: 3'h0 ; */ -/*description: the input signals are delayed by system clock cycles, 0: input without delayed, -1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp -ut with the spi_clk.*/ -#define SPI_MEM_DIN7_MODE 0x00000007 -#define SPI_MEM_DIN7_MODE_M ((SPI_MEM_DIN7_MODE_V)<<(SPI_MEM_DIN7_MODE_S)) -#define SPI_MEM_DIN7_MODE_V 0x7 -#define SPI_MEM_DIN7_MODE_S 21 -/* SPI_MEM_DIN6_MODE : R/W ;bitpos:[20:18] ;default: 3'h0 ; */ -/*description: the input signals are delayed by system clock cycles, 0: input without delayed, -1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp -ut with the spi_clk.*/ -#define SPI_MEM_DIN6_MODE 0x00000007 -#define SPI_MEM_DIN6_MODE_M ((SPI_MEM_DIN6_MODE_V)<<(SPI_MEM_DIN6_MODE_S)) -#define SPI_MEM_DIN6_MODE_V 0x7 -#define SPI_MEM_DIN6_MODE_S 18 -/* SPI_MEM_DIN5_MODE : R/W ;bitpos:[17:15] ;default: 3'h0 ; */ -/*description: the input signals are delayed by system clock cycles, 0: input without delayed, -1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp -ut with the spi_clk.*/ -#define SPI_MEM_DIN5_MODE 0x00000007 -#define SPI_MEM_DIN5_MODE_M ((SPI_MEM_DIN5_MODE_V)<<(SPI_MEM_DIN5_MODE_S)) -#define SPI_MEM_DIN5_MODE_V 0x7 -#define SPI_MEM_DIN5_MODE_S 15 -/* SPI_MEM_DIN4_MODE : R/W ;bitpos:[14:12] ;default: 3'h0 ; */ -/*description: the input signals are delayed by system clock cycles, 0: input without delayed, -1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp -ut with the spi_clk.*/ -#define SPI_MEM_DIN4_MODE 0x00000007 -#define SPI_MEM_DIN4_MODE_M ((SPI_MEM_DIN4_MODE_V)<<(SPI_MEM_DIN4_MODE_S)) -#define SPI_MEM_DIN4_MODE_V 0x7 -#define SPI_MEM_DIN4_MODE_S 12 -/* SPI_MEM_DIN3_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */ -/*description: the input signals are delayed by system clock cycles, 0: input without delayed, -1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in -put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w -ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ -#define SPI_MEM_DIN3_MODE 0x00000007 -#define SPI_MEM_DIN3_MODE_M ((SPI_MEM_DIN3_MODE_V)<<(SPI_MEM_DIN3_MODE_S)) -#define SPI_MEM_DIN3_MODE_V 0x7 -#define SPI_MEM_DIN3_MODE_S 9 -/* SPI_MEM_DIN2_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */ -/*description: the input signals are delayed by system clock cycles, 0: input without delayed, -1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in -put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w -ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ -#define SPI_MEM_DIN2_MODE 0x00000007 -#define SPI_MEM_DIN2_MODE_M ((SPI_MEM_DIN2_MODE_V)<<(SPI_MEM_DIN2_MODE_S)) -#define SPI_MEM_DIN2_MODE_V 0x7 -#define SPI_MEM_DIN2_MODE_S 6 -/* SPI_MEM_DIN1_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */ -/*description: the input signals are delayed by system clock cycles, 0: input without delayed, -1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in -put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w -ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ -#define SPI_MEM_DIN1_MODE 0x00000007 -#define SPI_MEM_DIN1_MODE_M ((SPI_MEM_DIN1_MODE_V)<<(SPI_MEM_DIN1_MODE_S)) -#define SPI_MEM_DIN1_MODE_V 0x7 -#define SPI_MEM_DIN1_MODE_S 3 -/* SPI_MEM_DIN0_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ -/*description: the input signals are delayed by system clock cycles, 0: input without delayed, -1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in -put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w -ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ -#define SPI_MEM_DIN0_MODE 0x00000007 -#define SPI_MEM_DIN0_MODE_M ((SPI_MEM_DIN0_MODE_V)<<(SPI_MEM_DIN0_MODE_S)) -#define SPI_MEM_DIN0_MODE_V 0x7 -#define SPI_MEM_DIN0_MODE_S 0 - -#define SPI_MEM_DIN_NUM_REG(i) (REG_SPI_MEM_BASE(i) + 0x188) -/* SPI_MEM_DINS_NUM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: -delayed by 2 cycles,....*/ -#define SPI_MEM_DINS_NUM 0x00000003 -#define SPI_MEM_DINS_NUM_M ((SPI_MEM_DINS_NUM_V)<<(SPI_MEM_DINS_NUM_S)) -#define SPI_MEM_DINS_NUM_V 0x3 -#define SPI_MEM_DINS_NUM_S 16 -/* SPI_MEM_DIN7_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: -delayed by 2 cycles,....*/ -#define SPI_MEM_DIN7_NUM 0x00000003 -#define SPI_MEM_DIN7_NUM_M ((SPI_MEM_DIN7_NUM_V)<<(SPI_MEM_DIN7_NUM_S)) -#define SPI_MEM_DIN7_NUM_V 0x3 -#define SPI_MEM_DIN7_NUM_S 14 -/* SPI_MEM_DIN6_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: -delayed by 2 cycles,....*/ -#define SPI_MEM_DIN6_NUM 0x00000003 -#define SPI_MEM_DIN6_NUM_M ((SPI_MEM_DIN6_NUM_V)<<(SPI_MEM_DIN6_NUM_S)) -#define SPI_MEM_DIN6_NUM_V 0x3 -#define SPI_MEM_DIN6_NUM_S 12 -/* SPI_MEM_DIN5_NUM : R/W ;bitpos:[11:10] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: -delayed by 2 cycles,....*/ -#define SPI_MEM_DIN5_NUM 0x00000003 -#define SPI_MEM_DIN5_NUM_M ((SPI_MEM_DIN5_NUM_V)<<(SPI_MEM_DIN5_NUM_S)) -#define SPI_MEM_DIN5_NUM_V 0x3 -#define SPI_MEM_DIN5_NUM_S 10 -/* SPI_MEM_DIN4_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: -delayed by 2 cycles,....*/ -#define SPI_MEM_DIN4_NUM 0x00000003 -#define SPI_MEM_DIN4_NUM_M ((SPI_MEM_DIN4_NUM_V)<<(SPI_MEM_DIN4_NUM_S)) -#define SPI_MEM_DIN4_NUM_V 0x3 -#define SPI_MEM_DIN4_NUM_S 8 -/* SPI_MEM_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: -delayed by 2 cycles,....*/ -#define SPI_MEM_DIN3_NUM 0x00000003 -#define SPI_MEM_DIN3_NUM_M ((SPI_MEM_DIN3_NUM_V)<<(SPI_MEM_DIN3_NUM_S)) -#define SPI_MEM_DIN3_NUM_V 0x3 -#define SPI_MEM_DIN3_NUM_S 6 -/* SPI_MEM_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: -delayed by 2 cycles,....*/ -#define SPI_MEM_DIN2_NUM 0x00000003 -#define SPI_MEM_DIN2_NUM_M ((SPI_MEM_DIN2_NUM_V)<<(SPI_MEM_DIN2_NUM_S)) -#define SPI_MEM_DIN2_NUM_V 0x3 -#define SPI_MEM_DIN2_NUM_S 4 -/* SPI_MEM_DIN1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: -delayed by 2 cycles,....*/ -#define SPI_MEM_DIN1_NUM 0x00000003 -#define SPI_MEM_DIN1_NUM_M ((SPI_MEM_DIN1_NUM_V)<<(SPI_MEM_DIN1_NUM_S)) -#define SPI_MEM_DIN1_NUM_V 0x3 -#define SPI_MEM_DIN1_NUM_S 2 -/* SPI_MEM_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: -delayed by 2 cycles,....*/ -#define SPI_MEM_DIN0_NUM 0x00000003 -#define SPI_MEM_DIN0_NUM_M ((SPI_MEM_DIN0_NUM_V)<<(SPI_MEM_DIN0_NUM_S)) -#define SPI_MEM_DIN0_NUM_V 0x3 -#define SPI_MEM_DIN0_NUM_S 0 - -#define SPI_MEM_DOUT_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x18C) -/* SPI_MEM_DOUTS_MODE : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: the output signals are delayed by system clock cycles, 0: output without delayed -, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - output with the spi_clk.*/ -#define SPI_MEM_DOUTS_MODE (BIT(8)) -#define SPI_MEM_DOUTS_MODE_M (BIT(8)) -#define SPI_MEM_DOUTS_MODE_V 0x1 -#define SPI_MEM_DOUTS_MODE_S 8 -/* SPI_MEM_DOUT7_MODE : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: the output signals are delayed by system clock cycles, 0: output without delayed -, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - output with the spi_clk.*/ -#define SPI_MEM_DOUT7_MODE (BIT(7)) -#define SPI_MEM_DOUT7_MODE_M (BIT(7)) -#define SPI_MEM_DOUT7_MODE_V 0x1 -#define SPI_MEM_DOUT7_MODE_S 7 -/* SPI_MEM_DOUT6_MODE : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: the output signals are delayed by system clock cycles, 0: output without delayed -, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - output with the spi_clk.*/ -#define SPI_MEM_DOUT6_MODE (BIT(6)) -#define SPI_MEM_DOUT6_MODE_M (BIT(6)) -#define SPI_MEM_DOUT6_MODE_V 0x1 -#define SPI_MEM_DOUT6_MODE_S 6 -/* SPI_MEM_DOUT5_MODE : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: the output signals are delayed by system clock cycles, 0: output without delayed -, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - output with the spi_clk.*/ -#define SPI_MEM_DOUT5_MODE (BIT(5)) -#define SPI_MEM_DOUT5_MODE_M (BIT(5)) -#define SPI_MEM_DOUT5_MODE_V 0x1 -#define SPI_MEM_DOUT5_MODE_S 5 -/* SPI_MEM_DOUT4_MODE : R/W ;bitpos:[4] ;default: 1'h0 ; */ -/*description: the output signals are delayed by system clock cycles, 0: output without delayed -, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - output with the spi_clk.*/ -#define SPI_MEM_DOUT4_MODE (BIT(4)) -#define SPI_MEM_DOUT4_MODE_M (BIT(4)) -#define SPI_MEM_DOUT4_MODE_V 0x1 -#define SPI_MEM_DOUT4_MODE_S 4 -/* SPI_MEM_DOUT3_MODE : R/W ;bitpos:[3] ;default: 1'h0 ; */ -/*description: the output signals are delayed by system clock cycles, 0: output without delayed -, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp -ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ -#define SPI_MEM_DOUT3_MODE (BIT(3)) -#define SPI_MEM_DOUT3_MODE_M (BIT(3)) -#define SPI_MEM_DOUT3_MODE_V 0x1 -#define SPI_MEM_DOUT3_MODE_S 3 -/* SPI_MEM_DOUT2_MODE : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: the output signals are delayed by system clock cycles, 0: output without delayed -, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp -ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ -#define SPI_MEM_DOUT2_MODE (BIT(2)) -#define SPI_MEM_DOUT2_MODE_M (BIT(2)) -#define SPI_MEM_DOUT2_MODE_V 0x1 -#define SPI_MEM_DOUT2_MODE_S 2 -/* SPI_MEM_DOUT1_MODE : R/W ;bitpos:[1] ;default: 1'h0 ; */ -/*description: the output signals are delayed by system clock cycles, 0: output without delayed -, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp -ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ -#define SPI_MEM_DOUT1_MODE (BIT(1)) -#define SPI_MEM_DOUT1_MODE_M (BIT(1)) -#define SPI_MEM_DOUT1_MODE_V 0x1 -#define SPI_MEM_DOUT1_MODE_S 1 -/* SPI_MEM_DOUT0_MODE : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: the output signals are delayed by system clock cycles, 0: output without delayed -, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp -ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ -#define SPI_MEM_DOUT0_MODE (BIT(0)) -#define SPI_MEM_DOUT0_MODE_M (BIT(0)) -#define SPI_MEM_DOUT0_MODE_V 0x1 -#define SPI_MEM_DOUT0_MODE_S 0 - -#define SPI_MEM_SPI_SMEM_TIMING_CALI_REG(i) (REG_SPI_MEM_BASE(i) + 0x190) -/* SPI_MEM_SPI_SMEM_DLL_TIMING_CALI : HRO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to enable DLL for timing calibration in DDR mode when accessed to E -XT_RAM..*/ -#define SPI_MEM_SPI_SMEM_DLL_TIMING_CALI (BIT(5)) -#define SPI_MEM_SPI_SMEM_DLL_TIMING_CALI_M (BIT(5)) -#define SPI_MEM_SPI_SMEM_DLL_TIMING_CALI_V 0x1 -#define SPI_MEM_SPI_SMEM_DLL_TIMING_CALI_S 5 -/* SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN : HRO ;bitpos:[4:2] ;default: 3'd0 ; */ -/*description: For sram, add extra dummy spi clock cycle length for spi clock calibration..*/ -#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN 0x00000007 -#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_M ((SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V)<<(SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S)) -#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V 0x7 -#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S 2 -/* SPI_MEM_SPI_SMEM_TIMING_CALI : HRO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: For sram, the bit is used to enable timing auto-calibration for all reading oper -ations..*/ -#define SPI_MEM_SPI_SMEM_TIMING_CALI (BIT(1)) -#define SPI_MEM_SPI_SMEM_TIMING_CALI_M (BIT(1)) -#define SPI_MEM_SPI_SMEM_TIMING_CALI_V 0x1 -#define SPI_MEM_SPI_SMEM_TIMING_CALI_S 1 -/* SPI_MEM_SPI_SMEM_TIMING_CLK_ENA : HRO ;bitpos:[0] ;default: 1'b1 ; */ -/*description: For sram, the bit is used to enable timing adjust clock for all reading operatio -ns..*/ -#define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA (BIT(0)) -#define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA_M (BIT(0)) -#define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA_V 0x1 -#define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA_S 0 - -#define SPI_MEM_SPI_SMEM_DIN_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x194) -/* SPI_MEM_SPI_SMEM_DINS_MODE : HRO ;bitpos:[26:24] ;default: 3'h0 ; */ -/*description: the input signals are delayed by system clock cycles, 0: input without delayed, -1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in -put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w -ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ -#define SPI_MEM_SPI_SMEM_DINS_MODE 0x00000007 -#define SPI_MEM_SPI_SMEM_DINS_MODE_M ((SPI_MEM_SPI_SMEM_DINS_MODE_V)<<(SPI_MEM_SPI_SMEM_DINS_MODE_S)) -#define SPI_MEM_SPI_SMEM_DINS_MODE_V 0x7 -#define SPI_MEM_SPI_SMEM_DINS_MODE_S 24 -/* SPI_MEM_SPI_SMEM_DIN7_MODE : HRO ;bitpos:[23:21] ;default: 3'h0 ; */ -/*description: the input signals are delayed by system clock cycles, 0: input without delayed, -1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in -put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w -ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ -#define SPI_MEM_SPI_SMEM_DIN7_MODE 0x00000007 -#define SPI_MEM_SPI_SMEM_DIN7_MODE_M ((SPI_MEM_SPI_SMEM_DIN7_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN7_MODE_S)) -#define SPI_MEM_SPI_SMEM_DIN7_MODE_V 0x7 -#define SPI_MEM_SPI_SMEM_DIN7_MODE_S 21 -/* SPI_MEM_SPI_SMEM_DIN6_MODE : HRO ;bitpos:[20:18] ;default: 3'h0 ; */ -/*description: the input signals are delayed by system clock cycles, 0: input without delayed, -1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in -put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w -ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ -#define SPI_MEM_SPI_SMEM_DIN6_MODE 0x00000007 -#define SPI_MEM_SPI_SMEM_DIN6_MODE_M ((SPI_MEM_SPI_SMEM_DIN6_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN6_MODE_S)) -#define SPI_MEM_SPI_SMEM_DIN6_MODE_V 0x7 -#define SPI_MEM_SPI_SMEM_DIN6_MODE_S 18 -/* SPI_MEM_SPI_SMEM_DIN5_MODE : HRO ;bitpos:[17:15] ;default: 3'h0 ; */ -/*description: the input signals are delayed by system clock cycles, 0: input without delayed, -1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in -put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w -ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ -#define SPI_MEM_SPI_SMEM_DIN5_MODE 0x00000007 -#define SPI_MEM_SPI_SMEM_DIN5_MODE_M ((SPI_MEM_SPI_SMEM_DIN5_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN5_MODE_S)) -#define SPI_MEM_SPI_SMEM_DIN5_MODE_V 0x7 -#define SPI_MEM_SPI_SMEM_DIN5_MODE_S 15 -/* SPI_MEM_SPI_SMEM_DIN4_MODE : HRO ;bitpos:[14:12] ;default: 3'h0 ; */ -/*description: the input signals are delayed by system clock cycles, 0: input without delayed, -1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in -put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w -ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ -#define SPI_MEM_SPI_SMEM_DIN4_MODE 0x00000007 -#define SPI_MEM_SPI_SMEM_DIN4_MODE_M ((SPI_MEM_SPI_SMEM_DIN4_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN4_MODE_S)) -#define SPI_MEM_SPI_SMEM_DIN4_MODE_V 0x7 -#define SPI_MEM_SPI_SMEM_DIN4_MODE_S 12 -/* SPI_MEM_SPI_SMEM_DIN3_MODE : HRO ;bitpos:[11:9] ;default: 3'h0 ; */ -/*description: the input signals are delayed by system clock cycles, 0: input without delayed, -1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in -put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w -ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ -#define SPI_MEM_SPI_SMEM_DIN3_MODE 0x00000007 -#define SPI_MEM_SPI_SMEM_DIN3_MODE_M ((SPI_MEM_SPI_SMEM_DIN3_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN3_MODE_S)) -#define SPI_MEM_SPI_SMEM_DIN3_MODE_V 0x7 -#define SPI_MEM_SPI_SMEM_DIN3_MODE_S 9 -/* SPI_MEM_SPI_SMEM_DIN2_MODE : HRO ;bitpos:[8:6] ;default: 3'h0 ; */ -/*description: the input signals are delayed by system clock cycles, 0: input without delayed, -1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in -put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w -ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ -#define SPI_MEM_SPI_SMEM_DIN2_MODE 0x00000007 -#define SPI_MEM_SPI_SMEM_DIN2_MODE_M ((SPI_MEM_SPI_SMEM_DIN2_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN2_MODE_S)) -#define SPI_MEM_SPI_SMEM_DIN2_MODE_V 0x7 -#define SPI_MEM_SPI_SMEM_DIN2_MODE_S 6 -/* SPI_MEM_SPI_SMEM_DIN1_MODE : HRO ;bitpos:[5:3] ;default: 3'h0 ; */ -/*description: the input signals are delayed by system clock cycles, 0: input without delayed, -1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in -put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w -ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ -#define SPI_MEM_SPI_SMEM_DIN1_MODE 0x00000007 -#define SPI_MEM_SPI_SMEM_DIN1_MODE_M ((SPI_MEM_SPI_SMEM_DIN1_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN1_MODE_S)) -#define SPI_MEM_SPI_SMEM_DIN1_MODE_V 0x7 -#define SPI_MEM_SPI_SMEM_DIN1_MODE_S 3 -/* SPI_MEM_SPI_SMEM_DIN0_MODE : HRO ;bitpos:[2:0] ;default: 3'h0 ; */ -/*description: the input signals are delayed by system clock cycles, 0: input without delayed, -1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in -put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w -ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ -#define SPI_MEM_SPI_SMEM_DIN0_MODE 0x00000007 -#define SPI_MEM_SPI_SMEM_DIN0_MODE_M ((SPI_MEM_SPI_SMEM_DIN0_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN0_MODE_S)) -#define SPI_MEM_SPI_SMEM_DIN0_MODE_V 0x7 -#define SPI_MEM_SPI_SMEM_DIN0_MODE_S 0 - -#define SPI_MEM_SPI_SMEM_DIN_NUM_REG(i) (REG_SPI_MEM_BASE(i) + 0x198) -/* SPI_MEM_SPI_SMEM_DINS_NUM : HRO ;bitpos:[17:16] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles, 0: input without delayed, -1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in -put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w -ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ -#define SPI_MEM_SPI_SMEM_DINS_NUM 0x00000003 -#define SPI_MEM_SPI_SMEM_DINS_NUM_M ((SPI_MEM_SPI_SMEM_DINS_NUM_V)<<(SPI_MEM_SPI_SMEM_DINS_NUM_S)) -#define SPI_MEM_SPI_SMEM_DINS_NUM_V 0x3 -#define SPI_MEM_SPI_SMEM_DINS_NUM_S 16 -/* SPI_MEM_SPI_SMEM_DIN7_NUM : HRO ;bitpos:[15:14] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: -delayed by 2 cycles,....*/ -#define SPI_MEM_SPI_SMEM_DIN7_NUM 0x00000003 -#define SPI_MEM_SPI_SMEM_DIN7_NUM_M ((SPI_MEM_SPI_SMEM_DIN7_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN7_NUM_S)) -#define SPI_MEM_SPI_SMEM_DIN7_NUM_V 0x3 -#define SPI_MEM_SPI_SMEM_DIN7_NUM_S 14 -/* SPI_MEM_SPI_SMEM_DIN6_NUM : HRO ;bitpos:[13:12] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: -delayed by 2 cycles,....*/ -#define SPI_MEM_SPI_SMEM_DIN6_NUM 0x00000003 -#define SPI_MEM_SPI_SMEM_DIN6_NUM_M ((SPI_MEM_SPI_SMEM_DIN6_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN6_NUM_S)) -#define SPI_MEM_SPI_SMEM_DIN6_NUM_V 0x3 -#define SPI_MEM_SPI_SMEM_DIN6_NUM_S 12 -/* SPI_MEM_SPI_SMEM_DIN5_NUM : HRO ;bitpos:[11:10] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: -delayed by 2 cycles,....*/ -#define SPI_MEM_SPI_SMEM_DIN5_NUM 0x00000003 -#define SPI_MEM_SPI_SMEM_DIN5_NUM_M ((SPI_MEM_SPI_SMEM_DIN5_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN5_NUM_S)) -#define SPI_MEM_SPI_SMEM_DIN5_NUM_V 0x3 -#define SPI_MEM_SPI_SMEM_DIN5_NUM_S 10 -/* SPI_MEM_SPI_SMEM_DIN4_NUM : HRO ;bitpos:[9:8] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: -delayed by 2 cycles,....*/ -#define SPI_MEM_SPI_SMEM_DIN4_NUM 0x00000003 -#define SPI_MEM_SPI_SMEM_DIN4_NUM_M ((SPI_MEM_SPI_SMEM_DIN4_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN4_NUM_S)) -#define SPI_MEM_SPI_SMEM_DIN4_NUM_V 0x3 -#define SPI_MEM_SPI_SMEM_DIN4_NUM_S 8 -/* SPI_MEM_SPI_SMEM_DIN3_NUM : HRO ;bitpos:[7:6] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: -delayed by 2 cycles,....*/ -#define SPI_MEM_SPI_SMEM_DIN3_NUM 0x00000003 -#define SPI_MEM_SPI_SMEM_DIN3_NUM_M ((SPI_MEM_SPI_SMEM_DIN3_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN3_NUM_S)) -#define SPI_MEM_SPI_SMEM_DIN3_NUM_V 0x3 -#define SPI_MEM_SPI_SMEM_DIN3_NUM_S 6 -/* SPI_MEM_SPI_SMEM_DIN2_NUM : HRO ;bitpos:[5:4] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: -delayed by 2 cycles,....*/ -#define SPI_MEM_SPI_SMEM_DIN2_NUM 0x00000003 -#define SPI_MEM_SPI_SMEM_DIN2_NUM_M ((SPI_MEM_SPI_SMEM_DIN2_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN2_NUM_S)) -#define SPI_MEM_SPI_SMEM_DIN2_NUM_V 0x3 -#define SPI_MEM_SPI_SMEM_DIN2_NUM_S 4 -/* SPI_MEM_SPI_SMEM_DIN1_NUM : HRO ;bitpos:[3:2] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: -delayed by 2 cycles,....*/ -#define SPI_MEM_SPI_SMEM_DIN1_NUM 0x00000003 -#define SPI_MEM_SPI_SMEM_DIN1_NUM_M ((SPI_MEM_SPI_SMEM_DIN1_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN1_NUM_S)) -#define SPI_MEM_SPI_SMEM_DIN1_NUM_V 0x3 -#define SPI_MEM_SPI_SMEM_DIN1_NUM_S 2 -/* SPI_MEM_SPI_SMEM_DIN0_NUM : HRO ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: -delayed by 2 cycles,....*/ -#define SPI_MEM_SPI_SMEM_DIN0_NUM 0x00000003 -#define SPI_MEM_SPI_SMEM_DIN0_NUM_M ((SPI_MEM_SPI_SMEM_DIN0_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN0_NUM_S)) -#define SPI_MEM_SPI_SMEM_DIN0_NUM_V 0x3 -#define SPI_MEM_SPI_SMEM_DIN0_NUM_S 0 - -#define SPI_MEM_SPI_SMEM_DOUT_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x19C) -/* SPI_MEM_SPI_SMEM_DOUTS_MODE : HRO ;bitpos:[8] ;default: 1'h0 ; */ -/*description: the output signals are delayed by system clock cycles, 0: output without delayed -, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp -ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ -#define SPI_MEM_SPI_SMEM_DOUTS_MODE (BIT(8)) -#define SPI_MEM_SPI_SMEM_DOUTS_MODE_M (BIT(8)) -#define SPI_MEM_SPI_SMEM_DOUTS_MODE_V 0x1 -#define SPI_MEM_SPI_SMEM_DOUTS_MODE_S 8 -/* SPI_MEM_SPI_SMEM_DOUT7_MODE : HRO ;bitpos:[7] ;default: 1'h0 ; */ -/*description: the output signals are delayed by system clock cycles, 0: output without delayed -, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp -ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ -#define SPI_MEM_SPI_SMEM_DOUT7_MODE (BIT(7)) -#define SPI_MEM_SPI_SMEM_DOUT7_MODE_M (BIT(7)) -#define SPI_MEM_SPI_SMEM_DOUT7_MODE_V 0x1 -#define SPI_MEM_SPI_SMEM_DOUT7_MODE_S 7 -/* SPI_MEM_SPI_SMEM_DOUT6_MODE : HRO ;bitpos:[6] ;default: 1'h0 ; */ -/*description: the output signals are delayed by system clock cycles, 0: output without delayed -, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp -ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ -#define SPI_MEM_SPI_SMEM_DOUT6_MODE (BIT(6)) -#define SPI_MEM_SPI_SMEM_DOUT6_MODE_M (BIT(6)) -#define SPI_MEM_SPI_SMEM_DOUT6_MODE_V 0x1 -#define SPI_MEM_SPI_SMEM_DOUT6_MODE_S 6 -/* SPI_MEM_SPI_SMEM_DOUT5_MODE : HRO ;bitpos:[5] ;default: 1'h0 ; */ -/*description: the output signals are delayed by system clock cycles, 0: output without delayed -, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp -ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ -#define SPI_MEM_SPI_SMEM_DOUT5_MODE (BIT(5)) -#define SPI_MEM_SPI_SMEM_DOUT5_MODE_M (BIT(5)) -#define SPI_MEM_SPI_SMEM_DOUT5_MODE_V 0x1 -#define SPI_MEM_SPI_SMEM_DOUT5_MODE_S 5 -/* SPI_MEM_SPI_SMEM_DOUT4_MODE : HRO ;bitpos:[4] ;default: 1'h0 ; */ -/*description: the output signals are delayed by system clock cycles, 0: output without delayed -, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp -ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ -#define SPI_MEM_SPI_SMEM_DOUT4_MODE (BIT(4)) -#define SPI_MEM_SPI_SMEM_DOUT4_MODE_M (BIT(4)) -#define SPI_MEM_SPI_SMEM_DOUT4_MODE_V 0x1 -#define SPI_MEM_SPI_SMEM_DOUT4_MODE_S 4 -/* SPI_MEM_SPI_SMEM_DOUT3_MODE : HRO ;bitpos:[3] ;default: 1'h0 ; */ -/*description: the output signals are delayed by system clock cycles, 0: output without delayed -, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp -ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ -#define SPI_MEM_SPI_SMEM_DOUT3_MODE (BIT(3)) -#define SPI_MEM_SPI_SMEM_DOUT3_MODE_M (BIT(3)) -#define SPI_MEM_SPI_SMEM_DOUT3_MODE_V 0x1 -#define SPI_MEM_SPI_SMEM_DOUT3_MODE_S 3 -/* SPI_MEM_SPI_SMEM_DOUT2_MODE : HRO ;bitpos:[2] ;default: 1'h0 ; */ -/*description: the output signals are delayed by system clock cycles, 0: output without delayed -, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp -ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ -#define SPI_MEM_SPI_SMEM_DOUT2_MODE (BIT(2)) -#define SPI_MEM_SPI_SMEM_DOUT2_MODE_M (BIT(2)) -#define SPI_MEM_SPI_SMEM_DOUT2_MODE_V 0x1 -#define SPI_MEM_SPI_SMEM_DOUT2_MODE_S 2 -/* SPI_MEM_SPI_SMEM_DOUT1_MODE : HRO ;bitpos:[1] ;default: 1'h0 ; */ -/*description: the output signals are delayed by system clock cycles, 0: output without delayed -, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp -ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ -#define SPI_MEM_SPI_SMEM_DOUT1_MODE (BIT(1)) -#define SPI_MEM_SPI_SMEM_DOUT1_MODE_M (BIT(1)) -#define SPI_MEM_SPI_SMEM_DOUT1_MODE_V 0x1 -#define SPI_MEM_SPI_SMEM_DOUT1_MODE_S 1 -/* SPI_MEM_SPI_SMEM_DOUT0_MODE : HRO ;bitpos:[0] ;default: 1'h0 ; */ -/*description: the output signals are delayed by system clock cycles, 0: output without delayed -, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp -ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ -#define SPI_MEM_SPI_SMEM_DOUT0_MODE (BIT(0)) -#define SPI_MEM_SPI_SMEM_DOUT0_MODE_M (BIT(0)) -#define SPI_MEM_SPI_SMEM_DOUT0_MODE_V 0x1 -#define SPI_MEM_SPI_SMEM_DOUT0_MODE_S 0 - -#define SPI_MEM_SPI_SMEM_AC_REG(i) (REG_SPI_MEM_BASE(i) + 0x1A0) -/* SPI_MEM_SPI_SMEM_SPLIT_TRANS_EN : HRO ;bitpos:[31] ;default: 1'b1 ; */ -/*description: Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI - transfers when one transfer will cross flash/EXT_RAM page corner, valid no matt -er whether there is an ECC region or not..*/ -#define SPI_MEM_SPI_SMEM_SPLIT_TRANS_EN (BIT(31)) -#define SPI_MEM_SPI_SMEM_SPLIT_TRANS_EN_M (BIT(31)) -#define SPI_MEM_SPI_SMEM_SPLIT_TRANS_EN_V 0x1 -#define SPI_MEM_SPI_SMEM_SPLIT_TRANS_EN_S 31 -/* SPI_MEM_SPI_SMEM_CS_HOLD_DELAY : HRO ;bitpos:[30:25] ;default: 6'd0 ; */ -/*description: These bits are used to set the minimum CS high time tSHSL between SPI burst tran -sfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) M -SPI core clock cycles..*/ -#define SPI_MEM_SPI_SMEM_CS_HOLD_DELAY 0x0000003F -#define SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_M ((SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_V)<<(SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_S)) -#define SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_V 0x3F -#define SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_S 25 -/* SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN : HRO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode whe -n accesses external RAM..*/ -#define SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN (BIT(16)) -#define SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN_M (BIT(16)) -#define SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN_V 0x1 -#define SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN_S 16 -/* SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER : HRO ;bitpos:[15] ;default: 1'b1 ; */ -/*description: 1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner wh -en accesses external RAM..*/ -#define SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER (BIT(15)) -#define SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER_M (BIT(15)) -#define SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER_V 0x1 -#define SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER_S 15 -/* SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME : HRO ;bitpos:[14:12] ;default: 3'd3 ; */ -/*description: SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold c -ycles in ECC mode when accessed external RAM..*/ -#define SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME 0x00000007 -#define SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_M ((SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_V)<<(SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_S)) -#define SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_V 0x7 -#define SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_S 12 -/* SPI_MEM_SPI_SMEM_CS_HOLD_TIME : HRO ;bitpos:[11:7] ;default: 5'h1 ; */ -/*description: For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits a -re combined with spi_mem_cs_hold bit..*/ -#define SPI_MEM_SPI_SMEM_CS_HOLD_TIME 0x0000001F -#define SPI_MEM_SPI_SMEM_CS_HOLD_TIME_M ((SPI_MEM_SPI_SMEM_CS_HOLD_TIME_V)<<(SPI_MEM_SPI_SMEM_CS_HOLD_TIME_S)) -#define SPI_MEM_SPI_SMEM_CS_HOLD_TIME_V 0x1F -#define SPI_MEM_SPI_SMEM_CS_HOLD_TIME_S 7 -/* SPI_MEM_SPI_SMEM_CS_SETUP_TIME : HRO ;bitpos:[6:2] ;default: 5'h1 ; */ -/*description: For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with s -pi_mem_cs_setup bit..*/ -#define SPI_MEM_SPI_SMEM_CS_SETUP_TIME 0x0000001F -#define SPI_MEM_SPI_SMEM_CS_SETUP_TIME_M ((SPI_MEM_SPI_SMEM_CS_SETUP_TIME_V)<<(SPI_MEM_SPI_SMEM_CS_SETUP_TIME_S)) -#define SPI_MEM_SPI_SMEM_CS_SETUP_TIME_V 0x1F -#define SPI_MEM_SPI_SMEM_CS_SETUP_TIME_S 2 -/* SPI_MEM_SPI_SMEM_CS_HOLD : HRO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disab -le..*/ -#define SPI_MEM_SPI_SMEM_CS_HOLD (BIT(1)) -#define SPI_MEM_SPI_SMEM_CS_HOLD_M (BIT(1)) -#define SPI_MEM_SPI_SMEM_CS_HOLD_V 0x1 -#define SPI_MEM_SPI_SMEM_CS_HOLD_S 1 -/* SPI_MEM_SPI_SMEM_CS_SETUP : HRO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: d -isable..*/ -#define SPI_MEM_SPI_SMEM_CS_SETUP (BIT(0)) -#define SPI_MEM_SPI_SMEM_CS_SETUP_M (BIT(0)) -#define SPI_MEM_SPI_SMEM_CS_SETUP_V 0x1 -#define SPI_MEM_SPI_SMEM_CS_SETUP_S 0 - -#define SPI_MEM_SPI_SMEM_DIN_HEX_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x1A4) -/* SPI_MEM_SPI_SMEM_DINS_HEX_MODE : R/W ;bitpos:[26:24] ;default: 3'h0 ; */ -/*description: the input signals are delayed by system clock cycles, 0: input without delayed, -1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in -put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w -ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ -#define SPI_MEM_SPI_SMEM_DINS_HEX_MODE 0x00000007 -#define SPI_MEM_SPI_SMEM_DINS_HEX_MODE_M ((SPI_MEM_SPI_SMEM_DINS_HEX_MODE_V)<<(SPI_MEM_SPI_SMEM_DINS_HEX_MODE_S)) -#define SPI_MEM_SPI_SMEM_DINS_HEX_MODE_V 0x7 -#define SPI_MEM_SPI_SMEM_DINS_HEX_MODE_S 24 -/* SPI_MEM_SPI_SMEM_DIN15_MODE : R/W ;bitpos:[23:21] ;default: 3'h0 ; */ -/*description: the input signals are delayed by system clock cycles, 0: input without delayed, -1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in -put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w -ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ -#define SPI_MEM_SPI_SMEM_DIN15_MODE 0x00000007 -#define SPI_MEM_SPI_SMEM_DIN15_MODE_M ((SPI_MEM_SPI_SMEM_DIN15_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN15_MODE_S)) -#define SPI_MEM_SPI_SMEM_DIN15_MODE_V 0x7 -#define SPI_MEM_SPI_SMEM_DIN15_MODE_S 21 -/* SPI_MEM_SPI_SMEM_DIN14_MODE : R/W ;bitpos:[20:18] ;default: 3'h0 ; */ -/*description: the input signals are delayed by system clock cycles, 0: input without delayed, -1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in -put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w -ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ -#define SPI_MEM_SPI_SMEM_DIN14_MODE 0x00000007 -#define SPI_MEM_SPI_SMEM_DIN14_MODE_M ((SPI_MEM_SPI_SMEM_DIN14_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN14_MODE_S)) -#define SPI_MEM_SPI_SMEM_DIN14_MODE_V 0x7 -#define SPI_MEM_SPI_SMEM_DIN14_MODE_S 18 -/* SPI_MEM_SPI_SMEM_DIN13_MODE : R/W ;bitpos:[17:15] ;default: 3'h0 ; */ -/*description: the input signals are delayed by system clock cycles, 0: input without delayed, -1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in -put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w -ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ -#define SPI_MEM_SPI_SMEM_DIN13_MODE 0x00000007 -#define SPI_MEM_SPI_SMEM_DIN13_MODE_M ((SPI_MEM_SPI_SMEM_DIN13_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN13_MODE_S)) -#define SPI_MEM_SPI_SMEM_DIN13_MODE_V 0x7 -#define SPI_MEM_SPI_SMEM_DIN13_MODE_S 15 -/* SPI_MEM_SPI_SMEM_DIN12_MODE : R/W ;bitpos:[14:12] ;default: 3'h0 ; */ -/*description: the input signals are delayed by system clock cycles, 0: input without delayed, -1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in -put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w -ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ -#define SPI_MEM_SPI_SMEM_DIN12_MODE 0x00000007 -#define SPI_MEM_SPI_SMEM_DIN12_MODE_M ((SPI_MEM_SPI_SMEM_DIN12_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN12_MODE_S)) -#define SPI_MEM_SPI_SMEM_DIN12_MODE_V 0x7 -#define SPI_MEM_SPI_SMEM_DIN12_MODE_S 12 -/* SPI_MEM_SPI_SMEM_DIN11_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */ -/*description: the input signals are delayed by system clock cycles, 0: input without delayed, -1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in -put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w -ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ -#define SPI_MEM_SPI_SMEM_DIN11_MODE 0x00000007 -#define SPI_MEM_SPI_SMEM_DIN11_MODE_M ((SPI_MEM_SPI_SMEM_DIN11_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN11_MODE_S)) -#define SPI_MEM_SPI_SMEM_DIN11_MODE_V 0x7 -#define SPI_MEM_SPI_SMEM_DIN11_MODE_S 9 -/* SPI_MEM_SPI_SMEM_DIN10_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */ -/*description: the input signals are delayed by system clock cycles, 0: input without delayed, -1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in -put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w -ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ -#define SPI_MEM_SPI_SMEM_DIN10_MODE 0x00000007 -#define SPI_MEM_SPI_SMEM_DIN10_MODE_M ((SPI_MEM_SPI_SMEM_DIN10_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN10_MODE_S)) -#define SPI_MEM_SPI_SMEM_DIN10_MODE_V 0x7 -#define SPI_MEM_SPI_SMEM_DIN10_MODE_S 6 -/* SPI_MEM_SPI_SMEM_DIN09_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */ -/*description: the input signals are delayed by system clock cycles, 0: input without delayed, -1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in -put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w -ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ -#define SPI_MEM_SPI_SMEM_DIN09_MODE 0x00000007 -#define SPI_MEM_SPI_SMEM_DIN09_MODE_M ((SPI_MEM_SPI_SMEM_DIN09_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN09_MODE_S)) -#define SPI_MEM_SPI_SMEM_DIN09_MODE_V 0x7 -#define SPI_MEM_SPI_SMEM_DIN09_MODE_S 3 -/* SPI_MEM_SPI_SMEM_DIN08_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ -/*description: the input signals are delayed by system clock cycles, 0: input without delayed, -1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: in -put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w -ith the spi_clk high edge, 6: input with the spi_clk low edge.*/ -#define SPI_MEM_SPI_SMEM_DIN08_MODE 0x00000007 -#define SPI_MEM_SPI_SMEM_DIN08_MODE_M ((SPI_MEM_SPI_SMEM_DIN08_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN08_MODE_S)) -#define SPI_MEM_SPI_SMEM_DIN08_MODE_V 0x7 -#define SPI_MEM_SPI_SMEM_DIN08_MODE_S 0 - -#define SPI_MEM_SPI_SMEM_DIN_HEX_NUM_REG(i) (REG_SPI_MEM_BASE(i) + 0x1A8) -/* SPI_MEM_SPI_SMEM_DINS_HEX_NUM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: -delayed by 2 cycles,....*/ -#define SPI_MEM_SPI_SMEM_DINS_HEX_NUM 0x00000003 -#define SPI_MEM_SPI_SMEM_DINS_HEX_NUM_M ((SPI_MEM_SPI_SMEM_DINS_HEX_NUM_V)<<(SPI_MEM_SPI_SMEM_DINS_HEX_NUM_S)) -#define SPI_MEM_SPI_SMEM_DINS_HEX_NUM_V 0x3 -#define SPI_MEM_SPI_SMEM_DINS_HEX_NUM_S 16 -/* SPI_MEM_SPI_SMEM_DIN15_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: -delayed by 2 cycles,....*/ -#define SPI_MEM_SPI_SMEM_DIN15_NUM 0x00000003 -#define SPI_MEM_SPI_SMEM_DIN15_NUM_M ((SPI_MEM_SPI_SMEM_DIN15_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN15_NUM_S)) -#define SPI_MEM_SPI_SMEM_DIN15_NUM_V 0x3 -#define SPI_MEM_SPI_SMEM_DIN15_NUM_S 14 -/* SPI_MEM_SPI_SMEM_DIN14_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: -delayed by 2 cycles,....*/ -#define SPI_MEM_SPI_SMEM_DIN14_NUM 0x00000003 -#define SPI_MEM_SPI_SMEM_DIN14_NUM_M ((SPI_MEM_SPI_SMEM_DIN14_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN14_NUM_S)) -#define SPI_MEM_SPI_SMEM_DIN14_NUM_V 0x3 -#define SPI_MEM_SPI_SMEM_DIN14_NUM_S 12 -/* SPI_MEM_SPI_SMEM_DIN13_NUM : R/W ;bitpos:[11:10] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: -delayed by 2 cycles,....*/ -#define SPI_MEM_SPI_SMEM_DIN13_NUM 0x00000003 -#define SPI_MEM_SPI_SMEM_DIN13_NUM_M ((SPI_MEM_SPI_SMEM_DIN13_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN13_NUM_S)) -#define SPI_MEM_SPI_SMEM_DIN13_NUM_V 0x3 -#define SPI_MEM_SPI_SMEM_DIN13_NUM_S 10 -/* SPI_MEM_SPI_SMEM_DIN12_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: -delayed by 2 cycles,....*/ -#define SPI_MEM_SPI_SMEM_DIN12_NUM 0x00000003 -#define SPI_MEM_SPI_SMEM_DIN12_NUM_M ((SPI_MEM_SPI_SMEM_DIN12_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN12_NUM_S)) -#define SPI_MEM_SPI_SMEM_DIN12_NUM_V 0x3 -#define SPI_MEM_SPI_SMEM_DIN12_NUM_S 8 -/* SPI_MEM_SPI_SMEM_DIN11_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: -delayed by 2 cycles,....*/ -#define SPI_MEM_SPI_SMEM_DIN11_NUM 0x00000003 -#define SPI_MEM_SPI_SMEM_DIN11_NUM_M ((SPI_MEM_SPI_SMEM_DIN11_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN11_NUM_S)) -#define SPI_MEM_SPI_SMEM_DIN11_NUM_V 0x3 -#define SPI_MEM_SPI_SMEM_DIN11_NUM_S 6 -/* SPI_MEM_SPI_SMEM_DIN10_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: -delayed by 2 cycles,....*/ -#define SPI_MEM_SPI_SMEM_DIN10_NUM 0x00000003 -#define SPI_MEM_SPI_SMEM_DIN10_NUM_M ((SPI_MEM_SPI_SMEM_DIN10_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN10_NUM_S)) -#define SPI_MEM_SPI_SMEM_DIN10_NUM_V 0x3 -#define SPI_MEM_SPI_SMEM_DIN10_NUM_S 4 -/* SPI_MEM_SPI_SMEM_DIN09_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: -delayed by 2 cycles,....*/ -#define SPI_MEM_SPI_SMEM_DIN09_NUM 0x00000003 -#define SPI_MEM_SPI_SMEM_DIN09_NUM_M ((SPI_MEM_SPI_SMEM_DIN09_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN09_NUM_S)) -#define SPI_MEM_SPI_SMEM_DIN09_NUM_V 0x3 -#define SPI_MEM_SPI_SMEM_DIN09_NUM_S 2 -/* SPI_MEM_SPI_SMEM_DIN08_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: -delayed by 2 cycles,....*/ -#define SPI_MEM_SPI_SMEM_DIN08_NUM 0x00000003 -#define SPI_MEM_SPI_SMEM_DIN08_NUM_M ((SPI_MEM_SPI_SMEM_DIN08_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN08_NUM_S)) -#define SPI_MEM_SPI_SMEM_DIN08_NUM_V 0x3 -#define SPI_MEM_SPI_SMEM_DIN08_NUM_S 0 - -#define SPI_MEM_SPI_SMEM_DOUT_HEX_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x1AC) -/* SPI_MEM_SPI_SMEM_DOUTS_HEX_MODE : R/W ;bitpos:[8] ;default: 1'h0 ; */ -/*description: the output signals are delayed by system clock cycles, 0: output without delayed -, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp -ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ -#define SPI_MEM_SPI_SMEM_DOUTS_HEX_MODE (BIT(8)) -#define SPI_MEM_SPI_SMEM_DOUTS_HEX_MODE_M (BIT(8)) -#define SPI_MEM_SPI_SMEM_DOUTS_HEX_MODE_V 0x1 -#define SPI_MEM_SPI_SMEM_DOUTS_HEX_MODE_S 8 -/* SPI_MEM_SPI_SMEM_DOUT15_MODE : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: the output signals are delayed by system clock cycles, 0: output without delayed -, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp -ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ -#define SPI_MEM_SPI_SMEM_DOUT15_MODE (BIT(7)) -#define SPI_MEM_SPI_SMEM_DOUT15_MODE_M (BIT(7)) -#define SPI_MEM_SPI_SMEM_DOUT15_MODE_V 0x1 -#define SPI_MEM_SPI_SMEM_DOUT15_MODE_S 7 -/* SPI_MEM_SPI_SMEM_DOUT14_MODE : R/W ;bitpos:[6] ;default: 1'h0 ; */ -/*description: the output signals are delayed by system clock cycles, 0: output without delayed -, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp -ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ -#define SPI_MEM_SPI_SMEM_DOUT14_MODE (BIT(6)) -#define SPI_MEM_SPI_SMEM_DOUT14_MODE_M (BIT(6)) -#define SPI_MEM_SPI_SMEM_DOUT14_MODE_V 0x1 -#define SPI_MEM_SPI_SMEM_DOUT14_MODE_S 6 -/* SPI_MEM_SPI_SMEM_DOUT13_MODE : R/W ;bitpos:[5] ;default: 1'h0 ; */ -/*description: the output signals are delayed by system clock cycles, 0: output without delayed -, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp -ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ -#define SPI_MEM_SPI_SMEM_DOUT13_MODE (BIT(5)) -#define SPI_MEM_SPI_SMEM_DOUT13_MODE_M (BIT(5)) -#define SPI_MEM_SPI_SMEM_DOUT13_MODE_V 0x1 -#define SPI_MEM_SPI_SMEM_DOUT13_MODE_S 5 -/* SPI_MEM_SPI_SMEM_DOUT12_MODE : R/W ;bitpos:[4] ;default: 1'h0 ; */ -/*description: the output signals are delayed by system clock cycles, 0: output without delayed -, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp -ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ -#define SPI_MEM_SPI_SMEM_DOUT12_MODE (BIT(4)) -#define SPI_MEM_SPI_SMEM_DOUT12_MODE_M (BIT(4)) -#define SPI_MEM_SPI_SMEM_DOUT12_MODE_V 0x1 -#define SPI_MEM_SPI_SMEM_DOUT12_MODE_S 4 -/* SPI_MEM_SPI_SMEM_DOUT11_MODE : R/W ;bitpos:[3] ;default: 1'h0 ; */ -/*description: the output signals are delayed by system clock cycles, 0: output without delayed -, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp -ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ -#define SPI_MEM_SPI_SMEM_DOUT11_MODE (BIT(3)) -#define SPI_MEM_SPI_SMEM_DOUT11_MODE_M (BIT(3)) -#define SPI_MEM_SPI_SMEM_DOUT11_MODE_V 0x1 -#define SPI_MEM_SPI_SMEM_DOUT11_MODE_S 3 -/* SPI_MEM_SPI_SMEM_DOUT10_MODE : R/W ;bitpos:[2] ;default: 1'h0 ; */ -/*description: the output signals are delayed by system clock cycles, 0: output without delayed -, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp -ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ -#define SPI_MEM_SPI_SMEM_DOUT10_MODE (BIT(2)) -#define SPI_MEM_SPI_SMEM_DOUT10_MODE_M (BIT(2)) -#define SPI_MEM_SPI_SMEM_DOUT10_MODE_V 0x1 -#define SPI_MEM_SPI_SMEM_DOUT10_MODE_S 2 -/* SPI_MEM_SPI_SMEM_DOUT09_MODE : R/W ;bitpos:[1] ;default: 1'h0 ; */ -/*description: the output signals are delayed by system clock cycles, 0: output without delayed -, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp -ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ -#define SPI_MEM_SPI_SMEM_DOUT09_MODE (BIT(1)) -#define SPI_MEM_SPI_SMEM_DOUT09_MODE_M (BIT(1)) -#define SPI_MEM_SPI_SMEM_DOUT09_MODE_V 0x1 -#define SPI_MEM_SPI_SMEM_DOUT09_MODE_S 1 -/* SPI_MEM_SPI_SMEM_DOUT08_MODE : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: the output signals are delayed by system clock cycles, 0: output without delayed -, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp -ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/ -#define SPI_MEM_SPI_SMEM_DOUT08_MODE (BIT(0)) -#define SPI_MEM_SPI_SMEM_DOUT08_MODE_M (BIT(0)) -#define SPI_MEM_SPI_SMEM_DOUT08_MODE_V 0x1 -#define SPI_MEM_SPI_SMEM_DOUT08_MODE_S 0 - -#define SPI_MEM_CLOCK_GATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x200) -/* SPI_MEM_SPI_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: Register clock gate enable signal. 1: Enable. 0: Disable..*/ -#define SPI_MEM_SPI_CLK_EN (BIT(0)) -#define SPI_MEM_SPI_CLK_EN_M (BIT(0)) -#define SPI_MEM_SPI_CLK_EN_V 0x1 -#define SPI_MEM_SPI_CLK_EN_S 0 - -#define SPI_MEM_XTS_PLAIN_BASE_REG(i) (REG_SPI_MEM_BASE(i) + 0x300) -/* SPI_MEM_SPI_XTS_PLAIN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This field is only used to generate include file in c case. This field is useles -s. Please do not use this field..*/ -#define SPI_MEM_SPI_XTS_PLAIN 0xFFFFFFFF -#define SPI_MEM_SPI_XTS_PLAIN_M ((SPI_MEM_SPI_XTS_PLAIN_V)<<(SPI_MEM_SPI_XTS_PLAIN_S)) -#define SPI_MEM_SPI_XTS_PLAIN_V 0xFFFFFFFF -#define SPI_MEM_SPI_XTS_PLAIN_S 0 - -#define SPI_MEM_XTS_LINESIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x340) -/* SPI_MEM_SPI_XTS_LINESIZE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: This bits stores the line-size parameter which will be used in manual encryption - calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, - 1: 32-bytes, 2: 64-bytes, 3:reserved..*/ -#define SPI_MEM_SPI_XTS_LINESIZE 0x00000003 -#define SPI_MEM_SPI_XTS_LINESIZE_M ((SPI_MEM_SPI_XTS_LINESIZE_V)<<(SPI_MEM_SPI_XTS_LINESIZE_S)) -#define SPI_MEM_SPI_XTS_LINESIZE_V 0x3 -#define SPI_MEM_SPI_XTS_LINESIZE_S 0 - -#define SPI_MEM_XTS_DESTINATION_REG(i) (REG_SPI_MEM_BASE(i) + 0x344) -/* SPI_MEM_SPI_XTS_DESTINATION : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This bit stores the destination parameter which will be used in manual encryptio -n calculation. 0: flash(default), 1: psram(reserved). Only default value can be -used..*/ -#define SPI_MEM_SPI_XTS_DESTINATION (BIT(0)) -#define SPI_MEM_SPI_XTS_DESTINATION_M (BIT(0)) -#define SPI_MEM_SPI_XTS_DESTINATION_V 0x1 -#define SPI_MEM_SPI_XTS_DESTINATION_S 0 - -#define SPI_MEM_XTS_PHYSICAL_ADDRESS_REG(i) (REG_SPI_MEM_BASE(i) + 0x348) -/* SPI_MEM_SPI_XTS_PHYSICAL_ADDRESS : R/W ;bitpos:[25:0] ;default: 26'h0 ; */ -/*description: This bits stores the physical-address parameter which will be used in manual enc -ryption calculation. This value should aligned with byte number decided by line- -size parameter..*/ -#define SPI_MEM_SPI_XTS_PHYSICAL_ADDRESS 0x03FFFFFF -#define SPI_MEM_SPI_XTS_PHYSICAL_ADDRESS_M ((SPI_MEM_SPI_XTS_PHYSICAL_ADDRESS_V)<<(SPI_MEM_SPI_XTS_PHYSICAL_ADDRESS_S)) -#define SPI_MEM_SPI_XTS_PHYSICAL_ADDRESS_V 0x3FFFFFF -#define SPI_MEM_SPI_XTS_PHYSICAL_ADDRESS_S 0 - -#define SPI_MEM_XTS_TRIGGER_REG(i) (REG_SPI_MEM_BASE(i) + 0x34C) -/* SPI_MEM_SPI_XTS_TRIGGER : WT ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to trigger the process of manual encryption calculation. This actio -n should only be asserted when manual encryption status is 0. After this action, - manual encryption status becomes 1. After calculation is done, manual encryptio -n status becomes 2..*/ -#define SPI_MEM_SPI_XTS_TRIGGER (BIT(0)) -#define SPI_MEM_SPI_XTS_TRIGGER_M (BIT(0)) -#define SPI_MEM_SPI_XTS_TRIGGER_V 0x1 -#define SPI_MEM_SPI_XTS_TRIGGER_S 0 - -#define SPI_MEM_XTS_RELEASE_REG(i) (REG_SPI_MEM_BASE(i) + 0x350) -/* SPI_MEM_SPI_XTS_RELEASE : WT ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to release encrypted result to mspi. This action should only be ass -erted when manual encryption status is 2. After this action, manual encryption s -tatus will become 3..*/ -#define SPI_MEM_SPI_XTS_RELEASE (BIT(0)) -#define SPI_MEM_SPI_XTS_RELEASE_M (BIT(0)) -#define SPI_MEM_SPI_XTS_RELEASE_V 0x1 -#define SPI_MEM_SPI_XTS_RELEASE_S 0 - -#define SPI_MEM_XTS_DESTROY_REG(i) (REG_SPI_MEM_BASE(i) + 0x354) -/* SPI_MEM_SPI_XTS_DESTROY : WT ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to destroy encrypted result. This action should be asserted only wh -en manual encryption status is 3. After this action, manual encryption status wi -ll become 0..*/ -#define SPI_MEM_SPI_XTS_DESTROY (BIT(0)) -#define SPI_MEM_SPI_XTS_DESTROY_M (BIT(0)) -#define SPI_MEM_SPI_XTS_DESTROY_V 0x1 -#define SPI_MEM_SPI_XTS_DESTROY_S 0 - -#define SPI_MEM_XTS_STATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x358) -/* SPI_MEM_SPI_XTS_STATE : RO ;bitpos:[1:0] ;default: 2'h0 ; */ -/*description: This bits stores the status of manual encryption. 0: idle, 1: busy of encryption - calculation, 2: encryption calculation is done but the encrypted result is invi -sible to mspi, 3: the encrypted result is visible to mspi..*/ -#define SPI_MEM_SPI_XTS_STATE 0x00000003 -#define SPI_MEM_SPI_XTS_STATE_M ((SPI_MEM_SPI_XTS_STATE_V)<<(SPI_MEM_SPI_XTS_STATE_S)) -#define SPI_MEM_SPI_XTS_STATE_V 0x3 -#define SPI_MEM_SPI_XTS_STATE_S 0 - -#define SPI_MEM_XTS_DATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x35C) -/* SPI_MEM_SPI_XTS_DATE : R/W ;bitpos:[29:0] ;default: 30'h20201010 ; */ -/*description: This bits stores the last modified-time of manual encryption feature..*/ -#define SPI_MEM_SPI_XTS_DATE 0x3FFFFFFF -#define SPI_MEM_SPI_XTS_DATE_M ((SPI_MEM_SPI_XTS_DATE_V)<<(SPI_MEM_SPI_XTS_DATE_S)) -#define SPI_MEM_SPI_XTS_DATE_V 0x3FFFFFFF -#define SPI_MEM_SPI_XTS_DATE_S 0 - -#define SPI_MEM_MMU_ITEM_CONTENT_REG(i) (REG_SPI_MEM_BASE(i) + 0x37C) -/* SPI_MEM_SPI_MMU_ITEM_CONTENT : R/W ;bitpos:[31:0] ;default: 32'h037c ; */ -/*description: MSPI-MMU item content.*/ -#define SPI_MEM_SPI_MMU_ITEM_CONTENT 0xFFFFFFFF -#define SPI_MEM_SPI_MMU_ITEM_CONTENT_M ((SPI_MEM_SPI_MMU_ITEM_CONTENT_V)<<(SPI_MEM_SPI_MMU_ITEM_CONTENT_S)) -#define SPI_MEM_SPI_MMU_ITEM_CONTENT_V 0xFFFFFFFF -#define SPI_MEM_SPI_MMU_ITEM_CONTENT_S 0 - -#define SPI_MEM_MMU_ITEM_INDEX_REG(i) (REG_SPI_MEM_BASE(i) + 0x380) -/* SPI_MEM_SPI_MMU_ITEM_INDEX : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: MSPI-MMU item index.*/ -#define SPI_MEM_SPI_MMU_ITEM_INDEX 0xFFFFFFFF -#define SPI_MEM_SPI_MMU_ITEM_INDEX_M ((SPI_MEM_SPI_MMU_ITEM_INDEX_V)<<(SPI_MEM_SPI_MMU_ITEM_INDEX_S)) -#define SPI_MEM_SPI_MMU_ITEM_INDEX_V 0xFFFFFFFF -#define SPI_MEM_SPI_MMU_ITEM_INDEX_S 0 - -#define SPI_MEM_MMU_POWER_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x384) -/* SPI_MEM_RDN_RESULT : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: MSPI module clock domain and AXI clock domain ECO register result register.*/ -#define SPI_MEM_RDN_RESULT (BIT(31)) -#define SPI_MEM_RDN_RESULT_M (BIT(31)) -#define SPI_MEM_RDN_RESULT_V 0x1 -#define SPI_MEM_RDN_RESULT_S 31 -/* SPI_MEM_RDN_ENA : HRO ;bitpos:[30] ;default: 1'b0 ; */ -/*description: ECO register enable bit.*/ -#define SPI_MEM_RDN_ENA (BIT(30)) -#define SPI_MEM_RDN_ENA_M (BIT(30)) -#define SPI_MEM_RDN_ENA_V 0x1 -#define SPI_MEM_RDN_ENA_S 30 -/* SPI_MEM_AUX_CTRL : HRO ;bitpos:[29:16] ;default: 14'h1320 ; */ -/*description: MMU PSRAM aux control register.*/ -#define SPI_MEM_AUX_CTRL 0x00003FFF -#define SPI_MEM_AUX_CTRL_M ((SPI_MEM_AUX_CTRL_V)<<(SPI_MEM_AUX_CTRL_S)) -#define SPI_MEM_AUX_CTRL_V 0x3FFF -#define SPI_MEM_AUX_CTRL_S 16 -/* SPI_MEM_SPI_MMU_PAGE_SIZE : R/W ;bitpos:[4:3] ;default: 2'd0 ; */ -/*description: 0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8.*/ -#define SPI_MEM_SPI_MMU_PAGE_SIZE 0x00000003 -#define SPI_MEM_SPI_MMU_PAGE_SIZE_M ((SPI_MEM_SPI_MMU_PAGE_SIZE_V)<<(SPI_MEM_SPI_MMU_PAGE_SIZE_S)) -#define SPI_MEM_SPI_MMU_PAGE_SIZE_V 0x3 -#define SPI_MEM_SPI_MMU_PAGE_SIZE_S 3 -/* SPI_MEM_SPI_MMU_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: Set this bit to force mmu-memory powerup, in this case, the power should also be - controlled by rtc..*/ -#define SPI_MEM_SPI_MMU_MEM_FORCE_PU (BIT(2)) -#define SPI_MEM_SPI_MMU_MEM_FORCE_PU_M (BIT(2)) -#define SPI_MEM_SPI_MMU_MEM_FORCE_PU_V 0x1 -#define SPI_MEM_SPI_MMU_MEM_FORCE_PU_S 2 -/* SPI_MEM_SPI_MMU_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to force mmu-memory powerdown.*/ -#define SPI_MEM_SPI_MMU_MEM_FORCE_PD (BIT(1)) -#define SPI_MEM_SPI_MMU_MEM_FORCE_PD_M (BIT(1)) -#define SPI_MEM_SPI_MMU_MEM_FORCE_PD_V 0x1 -#define SPI_MEM_SPI_MMU_MEM_FORCE_PD_S 1 -/* SPI_MEM_SPI_MMU_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to enable mmu-memory clock force on.*/ -#define SPI_MEM_SPI_MMU_MEM_FORCE_ON (BIT(0)) -#define SPI_MEM_SPI_MMU_MEM_FORCE_ON_M (BIT(0)) -#define SPI_MEM_SPI_MMU_MEM_FORCE_ON_V 0x1 -#define SPI_MEM_SPI_MMU_MEM_FORCE_ON_S 0 - -#define SPI_MEM_DPA_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x388) -/* SPI_MEM_SPI_CRYPT_DPA_SELECT_REGISTER : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYP -T_SECURITY_LEVEL. 0: Controlled by efuse bits..*/ -#define SPI_MEM_SPI_CRYPT_DPA_SELECT_REGISTER (BIT(4)) -#define SPI_MEM_SPI_CRYPT_DPA_SELECT_REGISTER_M (BIT(4)) -#define SPI_MEM_SPI_CRYPT_DPA_SELECT_REGISTER_V 0x1 -#define SPI_MEM_SPI_CRYPT_DPA_SELECT_REGISTER_S 4 -/* SPI_MEM_SPI_CRYPT_CALC_D_DPA_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calc -ulation that using key 1 or key 2. 0: Enable DPA only in the calculation that us -ing key 1..*/ -#define SPI_MEM_SPI_CRYPT_CALC_D_DPA_EN (BIT(3)) -#define SPI_MEM_SPI_CRYPT_CALC_D_DPA_EN_M (BIT(3)) -#define SPI_MEM_SPI_CRYPT_CALC_D_DPA_EN_V 0x1 -#define SPI_MEM_SPI_CRYPT_CALC_D_DPA_EN_S 3 -/* SPI_MEM_SPI_CRYPT_SECURITY_LEVEL : R/W ;bitpos:[2:0] ;default: 3'd7 ; */ -/*description: Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1- -7: The bigger the number is, the more secure the cryption is. (Note that the per -formance of cryption will decrease together with this number increasing).*/ -#define SPI_MEM_SPI_CRYPT_SECURITY_LEVEL 0x00000007 -#define SPI_MEM_SPI_CRYPT_SECURITY_LEVEL_M ((SPI_MEM_SPI_CRYPT_SECURITY_LEVEL_V)<<(SPI_MEM_SPI_CRYPT_SECURITY_LEVEL_S)) -#define SPI_MEM_SPI_CRYPT_SECURITY_LEVEL_V 0x7 -#define SPI_MEM_SPI_CRYPT_SECURITY_LEVEL_S 0 - -#define SPI_MEM_REGISTERRND_ECO_HIGH_REG(i) (REG_SPI_MEM_BASE(i) + 0x3F0) -/* SPI_MEM_REGISTERRND_ECO_HIGH : RO ;bitpos:[31:0] ;default: 32'h037c ; */ -/*description: ECO high register.*/ -#define SPI_MEM_REGISTERRND_ECO_HIGH 0xFFFFFFFF -#define SPI_MEM_REGISTERRND_ECO_HIGH_M ((SPI_MEM_REGISTERRND_ECO_HIGH_V)<<(SPI_MEM_REGISTERRND_ECO_HIGH_S)) -#define SPI_MEM_REGISTERRND_ECO_HIGH_V 0xFFFFFFFF -#define SPI_MEM_REGISTERRND_ECO_HIGH_S 0 - -#define SPI_MEM_REGISTERRND_ECO_LOW_REG(i) (REG_SPI_MEM_BASE(i) + 0x3F4) -/* SPI_MEM_REGISTERRND_ECO_LOW : RO ;bitpos:[31:0] ;default: 32'h037c ; */ -/*description: ECO low register.*/ -#define SPI_MEM_REGISTERRND_ECO_LOW 0xFFFFFFFF -#define SPI_MEM_REGISTERRND_ECO_LOW_M ((SPI_MEM_REGISTERRND_ECO_LOW_V)<<(SPI_MEM_REGISTERRND_ECO_LOW_S)) -#define SPI_MEM_REGISTERRND_ECO_LOW_V 0xFFFFFFFF -#define SPI_MEM_REGISTERRND_ECO_LOW_S 0 - -#define SPI_MEM_DATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x3FC) -/* SPI_MEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2212091 ; */ -/*description: SPI0 register version..*/ -#define SPI_MEM_DATE 0x0FFFFFFF -#define SPI_MEM_DATE_M ((SPI_MEM_DATE_V)<<(SPI_MEM_DATE_S)) -#define SPI_MEM_DATE_V 0xFFFFFFF -#define SPI_MEM_DATE_S 0 - - -#ifdef __cplusplus -} -#endif +#include "soc/spi_mem_c_reg.h" +#include "soc/spi1_mem_c_reg.h" diff --git a/components/soc/esp32p4/include/soc/spi_mem_struct.h b/components/soc/esp32p4/include/soc/spi_mem_struct.h index 73af7d2536..13568f66a0 100644 --- a/components/soc/esp32p4/include/soc/spi_mem_struct.h +++ b/components/soc/esp32p4/include/soc/spi_mem_struct.h @@ -1,1138 +1,20 @@ -/* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD +/** + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ #pragma once -#include +#include "soc/spi_mem_c_struct.h" +#include "soc/spi1_mem_c_struct.h" + #ifdef __cplusplus extern "C" { #endif -typedef volatile struct spi_mem_dev_s { - union { - struct { - uint32_t mst_st : 4; /*The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state.*/ - uint32_t slv_st : 4; /*The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state.*/ - uint32_t reserved8 : 9; /*reserved*/ - uint32_t flash_pe : 1; /*In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable. */ - uint32_t usr : 1; /*SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */ - uint32_t flash_hpm : 1; /*Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable. */ - uint32_t flash_res : 1; /*This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable. */ - uint32_t flash_dp : 1; /*Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */ - uint32_t flash_ce : 1; /*Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */ - uint32_t flash_be : 1; /*Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */ - uint32_t flash_se : 1; /*Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */ - uint32_t flash_pp : 1; /*Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable. */ - uint32_t flash_wrsr : 1; /*Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */ - uint32_t flash_rdsr : 1; /*Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */ - uint32_t flash_rdid : 1; /*Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */ - uint32_t flash_wrdi : 1; /*Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */ - uint32_t flash_wren : 1; /*Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */ - uint32_t flash_read : 1; /*Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */ - }; - uint32_t val; - } cmd; - uint32_t addr; - union { - struct { - uint32_t wdummy_dqs_always_out : 1; /*In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_DQS is output by the MSPI controller.*/ - uint32_t wdummy_always_out : 1; /*In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller.*/ - uint32_t fdummy_rin : 1; /*In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller in the first half part of dummy phase. It is used to mask invalid SPI_DQS in the half part of dummy phase.*/ - uint32_t fdummy_wout : 1; /*In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller in the second half part of dummy phase. It is used to pre-drive flash.*/ - uint32_t fdout_oct : 1; /*Apply 8 signals during write-data phase 1:enable 0: disable*/ - uint32_t fdin_oct : 1; /*Apply 8 signals during read-data phase 1:enable 0: disable*/ - uint32_t faddr_oct : 1; /*Apply 8 signals during address phase 1:enable 0: disable*/ - uint32_t reserved7 : 1; /*reserved*/ - uint32_t fcmd_quad : 1; /*Apply 4 signals during command phase 1:enable 0: disable*/ - uint32_t fcmd_oct : 1; /*Apply 8 signals during command phase 1:enable 0: disable*/ - uint32_t fcs_crc_en : 1; /*For SPI1, initialize crc32 module before writing encrypted data to flash. Active low.*/ - uint32_t tx_crc_en : 1; /*For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable*/ - uint32_t reserved12 : 1; /*reserved*/ - uint32_t fastrd_mode : 1; /*This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT and SPI_MEM_FREAD_DOUT. 1: enable 0: disable. */ - uint32_t fread_dual : 1; /*In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. */ - uint32_t resandres : 1; /*The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable. */ - uint32_t reserved16 : 2; /*reserved*/ - uint32_t q_pol : 1; /*The bit is used to set MISO line polarity, 1: high 0, low*/ - uint32_t d_pol : 1; /*The bit is used to set MOSI line polarity, 1: high 0, low*/ - uint32_t fread_quad : 1; /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable. */ - uint32_t wp : 1; /*Write protect signal output when SPI is idle. 1: output high, 0: output low. */ - uint32_t wrsr_2b : 1; /*two bytes data will be written to status register when it is set. 1: enable 0: disable. */ - uint32_t fread_dio : 1; /*In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable. */ - uint32_t fread_qio : 1; /*In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable. */ - uint32_t reserved25 : 5; /*reserved*/ - uint32_t dqs_ie_always_on : 1; /*When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others.*/ - uint32_t data_ie_always_on : 1; /*When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are always 1. 0: Others.*/ - }; - uint32_t val; - } ctrl; - union { - struct { - uint32_t clk_mode : 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/ - uint32_t cs_hold_dly_res : 10; /*After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles.*/ - uint32_t reserved2 : 9; /*reserved*/ - uint32_t reg_ar_size0_1_support_en : 1; /*1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR.*/ - uint32_t reg_aw_size0_1_support_en : 1; /*1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR.*/ - uint32_t reg_axi_rdata_back_fast : 1; /*1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: Reply AXI read data to AXI bus when all the read data is available.*/ - uint32_t rresp_ecc_err_en : 1; /*1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY when there is a ECC error in AXI read data. The ECC error information is recorded in SPI_MEM_ECC_ERR_ADDR_REG.*/ - uint32_t ar_splice_en : 1; /*Set this bit to enable AXI Read Splice-transfer.*/ - uint32_t aw_splice_en : 1; /*Set this bit to enable AXI Write Splice-transfer.*/ - uint32_t ram0_en : 1; /*When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be accessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 will be accessed. When SPI_MEM_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be accessed at the same time.*/ - uint32_t dual_ram_en : 1; /*Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at the same time.*/ - uint32_t fast_write_en : 1; /*Set this bit to write data faster, do not wait write data has been stored in tx_bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored in tx_bus_fifo_l2.*/ - uint32_t rxfifo_rst : 1; /*The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to receive signals from AXI. Set this bit to reset these FIFO.*/ - uint32_t txfifo_rst : 1; /*The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to send signals to AXI. Set this bit to reset these FIFO.*/ - }; - uint32_t val; - } ctrl1; - union { - struct { - uint32_t cs_setup_time : 5; /*(cycles-1) of prepare phase by SPI Bus clock, this bits are combined with SPI_MEM_CS_SETUP bit.*/ - uint32_t cs_hold_time : 5; /*SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with SPI_MEM_CS_HOLD bit.*/ - uint32_t ecc_cs_hold_time : 3; /*SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC mode when accessed flash.*/ - uint32_t ecc_skip_page_corner : 1; /*1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when accesses flash.*/ - uint32_t ecc_16to18_byte_en : 1; /*Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses flash.*/ - uint32_t reserved15 : 9; /*reserved*/ - uint32_t split_trans_en : 1; /*Set this bit to enable SPI0 split one AXI read flash transfer into two SPI transfers when one transfer will cross flash or EXT_RAM page corner, valid no matter whether there is an ECC region or not.*/ - uint32_t cs_hold_delay : 6; /*These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/ - uint32_t sync_reset : 1; /*The spi0_mst_st and spi0_slv_st will be reset.*/ - }; - uint32_t val; - } ctrl2; - union { - struct { - uint32_t clkcnt_l : 8; /*In the master mode it must be equal to spi_mem_clkcnt_N. */ - uint32_t clkcnt_h : 8; /*In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).*/ - uint32_t clkcnt_n : 8; /*In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/ - uint32_t reserved24 : 7; /*In the master mode it is pre-divider of spi_mem_clk. */ - uint32_t clk_equ_sysclk : 1; /*1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module clock.*/ - }; - uint32_t val; - } clock; - union { - struct { - uint32_t reserved0 : 6; /*reserved*/ - uint32_t cs_hold : 1; /*spi cs keep low when spi is in done phase. 1: enable 0: disable. */ - uint32_t cs_setup : 1; /*spi cs is enable when spi is in prepare phase. 1: enable 0: disable. */ - uint32_t reserved8 : 1; /*reserved*/ - uint32_t ck_out_edge : 1; /*The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3.*/ - uint32_t reserved10 : 2; /*reserved*/ - uint32_t fwrite_dual : 1; /*In the write operations read-data phase apply 2 signals*/ - uint32_t fwrite_quad : 1; /*In the write operations read-data phase apply 4 signals*/ - uint32_t fwrite_dio : 1; /*In the write operations address phase and read-data phase apply 2 signals.*/ - uint32_t fwrite_qio : 1; /*In the write operations address phase and read-data phase apply 4 signals.*/ - uint32_t reserved16 : 8; /*reserved*/ - uint32_t usr_miso_highpart : 1; /*read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. */ - uint32_t usr_mosi_highpart : 1; /*write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. */ - uint32_t usr_dummy_idle : 1; /*spi clock is disable in dummy phase when the bit is enable.*/ - uint32_t usr_mosi : 1; /*This bit enable the write-data phase of an operation.*/ - uint32_t usr_miso : 1; /*This bit enable the read-data phase of an operation.*/ - uint32_t usr_dummy : 1; /*This bit enable the dummy phase of an operation.*/ - uint32_t usr_addr : 1; /*This bit enable the address phase of an operation.*/ - uint32_t usr_command : 1; /*This bit enable the command phase of an operation.*/ - }; - uint32_t val; - } user; - union { - struct { - uint32_t usr_dummy_cyclelen : 6; /*The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).*/ - uint32_t usr_dbytelen : 3; /*SPI0 USR_CMD read or write data byte length -1*/ - uint32_t reserved9 : 17; /*reserved*/ - uint32_t usr_addr_bitlen : 6; /*The length in bits of address phase. The register value shall be (bit_num-1).*/ - }; - uint32_t val; - } user1; - union { - struct { - uint32_t usr_command_value : 16; /*The value of command.*/ - uint32_t reserved16 : 12; /*reserved*/ - uint32_t usr_command_bitlen : 4; /*The length in bits of command phase. The register value shall be (bit_num-1)*/ - }; - uint32_t val; - } user2; - union { - struct { - uint32_t usr_mosi_bit_len : 10; /*The length in bits of write-data. The register value shall be (bit_num-1).*/ - uint32_t reserved10 : 22; /*reserved*/ - }; - uint32_t val; - } mosi_dlen; - union { - struct { - uint32_t usr_miso_bit_len : 10; /*The length in bits of read-data. The register value shall be (bit_num-1).*/ - uint32_t reserved10 : 22; /*reserved*/ - }; - uint32_t val; - } miso_dlen; - union { - struct { - uint32_t status : 16; /*The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.*/ - uint32_t wb_mode : 8; /*Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit.*/ - uint32_t reserved24 : 8; /*reserved*/ - }; - uint32_t val; - } rd_status; - uint32_t reserved_30; - union { - struct { - uint32_t cs0_dis : 1; /*SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI device, such as flash, external RAM and so on.*/ - uint32_t cs1_dis : 1; /*SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI device, such as flash, external RAM and so on.*/ - uint32_t reserved0 : 5; /*reserved*/ - uint32_t fsub_pin : 1; /*For SPI0, flash is connected to SUBPINs.*/ - uint32_t ssub_pin : 1; /*For SPI0, sram is connected to SUBPINs.*/ - uint32_t ck_idle_edge : 1; /*1: SPI_CLK line is high when idle 0: spi clk line is low when idle */ - uint32_t cs_keep_active : 1; /*SPI_CS line keep low when the bit is set.*/ - uint32_t reserved11 : 21; /*reserved*/ - }; - uint32_t val; - } misc; - uint32_t tx_crc; - union { - struct { - uint32_t axi_req_en : 1; /*For SPI0, AXI master access enable, 1: enable, 0:disable.*/ - uint32_t usr_addr_4byte : 1; /*For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable.*/ - uint32_t flash_usr_cmd : 1; /*For SPI0, cache read flash for user define command, 1: enable, 0:disable.*/ - uint32_t fdin_dual : 1; /*For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/ - uint32_t fdout_dual : 1; /*For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/ - uint32_t faddr_dual : 1; /*For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/ - uint32_t fdin_quad : 1; /*For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.*/ - uint32_t fdout_quad : 1; /*For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.*/ - uint32_t faddr_quad : 1; /*For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.*/ - uint32_t reserved9 : 21; /*reserved*/ - uint32_t reg_same_aw_ar_addr_chk_en : 1; /*Set this bit to check AXI read/write the same address region.*/ - uint32_t reg_close_axi_inf_en : 1; /*Set this bit to close AXI read/write transfer to MSPI, which means that only SLV_ERR will be replied to BRESP/RRESP.*/ - }; - uint32_t val; - } cache_fctrl; - union { - struct { - uint32_t usr_saddr_4byte : 1; /*For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: enable, 0:disable.*/ - uint32_t usr_sram_dio : 1; /*For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable*/ - uint32_t usr_sram_qio : 1; /*For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable*/ - uint32_t usr_wr_sram_dummy : 1; /*For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write operations.*/ - uint32_t usr_rd_sram_dummy : 1; /*For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read operations.*/ - uint32_t sram_usr_rcmd : 1; /*For SPI0, In the external RAM mode cache read external RAM for user define command.*/ - uint32_t sram_rdummy_cyclelen : 6; /*For SPI0, In the external RAM mode, it is the length in bits of read dummy phase. The register value shall be (bit_num-1).*/ - uint32_t reserved12 : 2; /*reserved*/ - uint32_t sram_addr_bitlen : 6; /*For SPI0, In the external RAM mode, it is the length in bits of address phase. The register value shall be (bit_num-1).*/ - uint32_t sram_usr_wcmd : 1; /*For SPI0, In the external RAM mode cache write sram for user define command*/ - uint32_t sram_oct : 1; /*reserved*/ - uint32_t sram_wdummy_cyclelen : 6; /*For SPI0, In the external RAM mode, it is the length in bits of write dummy phase. The register value shall be (bit_num-1).*/ - uint32_t reserved28 : 4; /*reserved*/ - }; - uint32_t val; - } cache_sctrl; - union { - struct { - uint32_t sclk_mode : 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on.*/ - uint32_t swb_mode : 8; /*Mode bits in the external RAM fast read mode it is combined with spi_mem_fastrd_mode bit.*/ - uint32_t sdin_dual : 1; /*For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/ - uint32_t sdout_dual : 1; /*For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/ - uint32_t saddr_dual : 1; /*For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/ - uint32_t reserved13 : 1; /*reserved*/ - uint32_t sdin_quad : 1; /*For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/ - uint32_t sdout_quad : 1; /*For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/ - uint32_t saddr_quad : 1; /*For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/ - uint32_t scmd_quad : 1; /*For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/ - uint32_t sdin_oct : 1; /*For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable. */ - uint32_t sdout_oct : 1; /*For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable. */ - uint32_t saddr_oct : 1; /*For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. */ - uint32_t scmd_oct : 1; /*For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable. */ - uint32_t sdummy_rin : 1; /*In the dummy phase of a MSPI read data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller.*/ - uint32_t sdummy_wout : 1; /*In the dummy phase of a MSPI write data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller.*/ - uint32_t wdummy_dqs_always_out : 1; /*In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_DQS is output by the MSPI controller.*/ - uint32_t wdummy_always_out : 1; /*In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_IO[7:0] is output by the MSPI controller.*/ - uint32_t sdin_hex : 1; /*For SPI0 external RAM , din phase apply 16 signals. 1: enable 0: disable. */ - uint32_t sdout_hex : 1; /*For SPI0 external RAM , dout phase apply 16 signals. 1: enable 0: disable. */ - uint32_t reserved28 : 2; /*reserved*/ - uint32_t dqs_ie_always_on : 1; /*When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others.*/ - uint32_t data_ie_always_on : 1; /*When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0] are always 1. 0: Others.*/ - }; - uint32_t val; - } sram_cmd; - union { - struct { - uint32_t sram_usr_rd_cmd_value : 16; /*For SPI0,When cache mode is enable it is the read command value of command phase for sram.*/ - uint32_t reserved16 : 12; /*reserved*/ - uint32_t sram_usr_rd_cmd_bitlen : 4; /*For SPI0,When cache mode is enable it is the length in bits of command phase for sram. The register value shall be (bit_num-1).*/ - }; - uint32_t val; - } sram_drd_cmd; - union { - struct { - uint32_t usr_wr_cmd_value : 16; /*For SPI0,When cache mode is enable it is the write command value of command phase for sram.*/ - uint32_t reserved16 : 12; /*reserved*/ - uint32_t usr_wr_cmd_bitlen : 4; /*For SPI0,When cache mode is enable it is the in bits of command phase for sram. The register value shall be (bit_num-1).*/ - }; - uint32_t val; - } sram_dwr_cmd; - union { - struct { - uint32_t cnt_l : 8; /*For SPI0 external RAM interface, it must be equal to spi_mem_clkcnt_N.*/ - uint32_t cnt_h : 8; /*For SPI0 external RAM interface, it must be floor((spi_mem_clkcnt_N+1)/2-1).*/ - uint32_t cnt_n : 8; /*For SPI0 external RAM interface, it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/ - uint32_t reserved24 : 7; /*reserved*/ - uint32_t equ_sysclk : 1; /*For SPI0 external RAM interface, 1: spi_mem_clk is eqaul to system 0: spi_mem_clk is divided from system clock.*/ - }; - uint32_t val; - } sram_clk; - union { - struct { - uint32_t reserved0 : 7; /*reserved*/ - uint32_t lock_delay_time : 5; /*The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1.*/ - uint32_t reserved12 : 20; /*reserved*/ - }; - uint32_t val; - } fsm; - uint32_t data_buf[16]; - union { - struct { - uint32_t waiti_en : 1; /*1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto Suspend/Resume are not supported.*/ - uint32_t waiti_dummy : 1; /*The dummy phase enable when wait flash idle (RDSR)*/ - uint32_t waiti_addr_en : 1; /*1: Output address 0 in RDSR or read SUS command transfer. 0: Do not send out address in RDSR or read SUS command transfer.*/ - uint32_t waiti_addr_cyclelen : 2; /*When SPI_MEM_WAITI_ADDR_EN is set, the cycle length of sent out address is (SPI_MEM_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI bus clock cycles. It is not active when SPI_MEM_WAITI_ADDR_EN is cleared.*/ - uint32_t reserved5 : 4; /*reserved*/ - uint32_t waiti_cmd_2b : 1; /*1:The wait idle command bit length is 16. 0: The wait idle command bit length is 8.*/ - uint32_t waiti_dummy_cyclelen : 6; /*The dummy cycle length when wait flash idle(RDSR).*/ - uint32_t waiti_cmd : 16; /*The command value to wait flash idle(RDSR).*/ - }; - uint32_t val; - } flash_waiti_ctrl; - union { - struct { - uint32_t flash_per : 1; /*program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */ - uint32_t flash_pes : 1; /*program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */ - uint32_t flash_per_wait_en : 1; /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent. */ - uint32_t flash_pes_wait_en : 1; /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent. */ - uint32_t pes_per_en : 1; /*Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done.*/ - uint32_t flash_pes_en : 1; /*Set this bit to enable Auto-suspending function.*/ - uint32_t pesr_end_msk : 16; /*The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0].*/ - uint32_t frd_sus_2b : 1; /*1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte when check flash SUS/SUS1/SUS2 status bit*/ - uint32_t per_end_en : 1; /*1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0.*/ - uint32_t pes_end_en : 1; /*1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0.*/ - uint32_t sus_timeout_cnt : 7; /*When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it will be treated as check pass.*/ - }; - uint32_t val; - } flash_sus_ctrl; - union { - struct { - uint32_t flash_pes_command : 16; /*Program/Erase suspend command.*/ - uint32_t wait_pesr_command : 16; /*Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash.*/ - }; - uint32_t val; - } flash_sus_cmd; - union { - struct { - uint32_t flash_sus : 1; /*The status of flash suspend, only used in SPI1.*/ - uint32_t wait_pesr_cmd_2b : 1; /*1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.*/ - uint32_t flash_hpm_dly_128 : 1; /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent.*/ - uint32_t flash_res_dly_128 : 1; /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent.*/ - uint32_t flash_dp_dly_128 : 1; /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent.*/ - uint32_t flash_per_dly_128 : 1; /*Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent.*/ - uint32_t flash_pes_dly_128 : 1; /*Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent.*/ - uint32_t spi0_lock_en : 1; /*1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it.*/ - uint32_t reserved8 : 7; /*reserved*/ - uint32_t flash_pesr_cmd_2b : 1; /*1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit length of Program/Erase Suspend/Resume command is 8.*/ - uint32_t flash_per_command : 16; /*Program/Erase resume command.*/ - }; - uint32_t val; - } sus_status; - uint32_t reserved_a8; - uint32_t reserved_ac; - uint32_t reserved_b0; - uint32_t reserved_b4; - uint32_t reserved_b8; - uint32_t reserved_bc; - union { - struct { - uint32_t per_end_en : 1; /*The enable bit for SPI_MEM_PER_END_INT interrupt.*/ - uint32_t pes_end_en : 1; /*The enable bit for SPI_MEM_PES_END_INT interrupt.*/ - uint32_t wpe_end_en : 1; /*The enable bit for SPI_MEM_WPE_END_INT interrupt.*/ - uint32_t slv_st_end_en : 1; /*The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.*/ - uint32_t mst_st_end_en : 1; /*The enable bit for SPI_MEM_MST_ST_END_INT interrupt.*/ - uint32_t ecc_err_en : 1; /*The enable bit for SPI_MEM_ECC_ERR_INT interrupt.*/ - uint32_t pms_reject_en : 1; /*The enable bit for SPI_MEM_PMS_REJECT_INT interrupt.*/ - uint32_t axi_raddr_err_en : 1; /*The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.*/ - uint32_t axi_wr_flash_err_en : 1; /*The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.*/ - uint32_t axi_waddr_err_en : 1; /*The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.*/ - uint32_t brown_out_en : 1; /*The enable bit for SPI_MEM_BROWN_OUT_INT interrupt.*/ - uint32_t reserved10 : 17; /*reserved*/ - uint32_t dqs0_afifo_ovf_en : 1; /*The enable bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt.*/ - uint32_t dqs1_afifo_ovf_en : 1; /*The enable bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt.*/ - uint32_t bus_fifo1_udf_en : 1; /*The enable bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt.*/ - uint32_t bus_fifo0_udf_en : 1; /*The enable bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt.*/ - }; - uint32_t val; - } int_ena; - union { - struct { - uint32_t per_end : 1; /*The clear bit for SPI_MEM_PER_END_INT interrupt.*/ - uint32_t pes_end : 1; /*The clear bit for SPI_MEM_PES_END_INT interrupt.*/ - uint32_t wpe_end : 1; /*The clear bit for SPI_MEM_WPE_END_INT interrupt.*/ - uint32_t slv_st_end : 1; /*The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.*/ - uint32_t mst_st_end : 1; /*The clear bit for SPI_MEM_MST_ST_END_INT interrupt.*/ - uint32_t ecc_err : 1; /*The clear bit for SPI_MEM_ECC_ERR_INT interrupt.*/ - uint32_t pms_reject : 1; /*The clear bit for SPI_MEM_PMS_REJECT_INT interrupt.*/ - uint32_t axi_raddr_err : 1; /*The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.*/ - uint32_t axi_wr_flash_err : 1; /*The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.*/ - uint32_t axi_waddr_err : 1; /*The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.*/ - uint32_t brown_out : 1; /*The status bit for SPI_MEM_BROWN_OUT_INT interrupt.*/ - uint32_t reserved10 : 17; /*reserved*/ - uint32_t dqs0_afifo_ovf : 1; /*The clear bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt.*/ - uint32_t dqs1_afifo_ovf : 1; /*The clear bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt.*/ - uint32_t bus_fifo1_udf : 1; /*The clear bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt.*/ - uint32_t bus_fifo0_udf : 1; /*The clear bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt.*/ - }; - uint32_t val; - } int_clr; - union { - struct { - uint32_t per_end : 1; /*The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed successfully. 0: Others.*/ - uint32_t pes_end : 1; /*The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended successfully. 0: Others.*/ - uint32_t wpe_end : 1; /*The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others.*/ - uint32_t slv_st_end : 1; /*The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others*/ - uint32_t mst_st_end : 1; /*The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is changed from non idle state to idle state. 0: Others.*/ - uint32_t ecc_err : 1; /*The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN is cleared and SPI_SMEM_ECC_ERR_INT_EN is set, this bit is triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times of SPI0/1 ECC read external RAM and flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are cleared, this bit will not be triggered.*/ - uint32_t pms_reject : 1; /*The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is rejected. 0: Others.*/ - uint32_t axi_raddr_err : 1; /*The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read address is invalid by compared to MMU configuration. 0: Others.*/ - uint32_t axi_wr_flash_err : 1; /*The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write flash request is received. 0: Others.*/ - uint32_t axi_waddr_err : 1; /*The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write address is invalid by compared to MMU configuration. 0: Others.*/ - uint32_t brown_out : 1; /*The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others.*/ - uint32_t reserved10 : 17; /*reserved*/ - uint32_t dqs0_afifo_ovf : 1; /*The raw bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO connected to SPI_DQS1 is overflow.*/ - uint32_t dqs1_afifo_ovf : 1; /*The raw bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO connected to SPI_DQS is overflow.*/ - uint32_t bus_fifo1_udf : 1; /*The raw bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. 1: Triggered when BUS1 FIFO is underflow.*/ - uint32_t bus_fifo0_udf : 1; /*The raw bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. 1: Triggered when BUS0 FIFO is underflow.*/ - }; - uint32_t val; - } int_raw; - union { - struct { - uint32_t per_end : 1; /*The status bit for SPI_MEM_PER_END_INT interrupt.*/ - uint32_t pes_end : 1; /*The status bit for SPI_MEM_PES_END_INT interrupt.*/ - uint32_t wpe_end : 1; /*The status bit for SPI_MEM_WPE_END_INT interrupt.*/ - uint32_t slv_st_end : 1; /*The status bit for SPI_MEM_SLV_ST_END_INT interrupt.*/ - uint32_t mst_st_end : 1; /*The status bit for SPI_MEM_MST_ST_END_INT interrupt.*/ - uint32_t ecc_err : 1; /*The status bit for SPI_MEM_ECC_ERR_INT interrupt.*/ - uint32_t pms_reject : 1; /*The status bit for SPI_MEM_PMS_REJECT_INT interrupt.*/ - uint32_t axi_raddr_err : 1; /*The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.*/ - uint32_t axi_wr_flash_err : 1; /*The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.*/ - uint32_t axi_waddr_err : 1; /*The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.*/ - uint32_t brown_out : 1; /*The status bit for SPI_MEM_BROWN_OUT_INT interrupt.*/ - uint32_t reserved10 : 17; /*reserved*/ - uint32_t dqs0_afifo_ovf : 1; /*The status bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt.*/ - uint32_t dqs1_afifo_ovf : 1; /*The status bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt.*/ - uint32_t bus_fifo1_udf : 1; /*The status bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt.*/ - uint32_t bus_fifo0_udf : 1; /*The status bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt.*/ - }; - uint32_t val; - } int_st; - uint32_t reserved_d0; - union { - struct { - uint32_t fmem_ddr_en : 1; /*1: in DDR mode, 0 in SDR mode*/ - uint32_t fmem_var_dummy : 1; /*Set the bit to enable variable dummy cycle in spi DDR mode.*/ - uint32_t fmem_ddr_rdat_swp : 1; /*Set the bit to reorder rx data of the word in spi DDR mode.*/ - uint32_t fmem_ddr_wdat_swp : 1; /*Set the bit to reorder tx data of the word in spi DDR mode.*/ - uint32_t fmem_ddr_cmd_dis : 1; /*the bit is used to disable dual edge in command phase when DDR mode.*/ - uint32_t fmem_outminbytelen : 7; /*It is the minimum output data length in the panda device.*/ - uint32_t fmem_tx_ddr_msk_en : 1; /*Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to flash.*/ - uint32_t fmem_rx_ddr_msk_en : 1; /*Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to flash.*/ - uint32_t fmem_usr_ddr_dqs_thd : 7; /*The delay number of data strobe which from memory based on SPI clock.*/ - uint32_t fmem_ddr_dqs_loop : 1; /*1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS.*/ - uint32_t reserved22 : 2; /*reserved*/ - uint32_t fmem_clk_diff_en : 1; /*Set this bit to enable the differential SPI_CLK#.*/ - uint32_t reserved25 : 1; /*reserved*/ - uint32_t fmem_dqs_ca_in : 1; /*Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.*/ - uint32_t fmem_hyperbus_dummy_2x : 1; /*Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram.*/ - uint32_t fmem_clk_diff_inv : 1; /*Set this bit to invert SPI_DIFF when accesses to flash. .*/ - uint32_t fmem_octa_ram_addr : 1; /*Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.*/ - uint32_t fmem_hyperbus_ca : 1; /*Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.*/ - uint32_t reserved31 : 1; /*reserved*/ - }; - uint32_t val; - } ddr; - union { - struct { - uint32_t ddr_en : 1; /*1: in DDR mode, 0 in SDR mode*/ - uint32_t var_dummy : 1; /*Set the bit to enable variable dummy cycle in spi DDR mode.*/ - uint32_t ddr_rdat_swp : 1; /*Set the bit to reorder rx data of the word in spi DDR mode.*/ - uint32_t ddr_wdat_swp : 1; /*Set the bit to reorder tx data of the word in spi DDR mode.*/ - uint32_t ddr_cmd_dis : 1; /*the bit is used to disable dual edge in command phase when DDR mode.*/ - uint32_t outminbytelen : 7; /*It is the minimum output data length in the DDR psram.*/ - uint32_t tx_ddr_msk_en : 1; /*Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to external RAM.*/ - uint32_t rx_ddr_msk_en : 1; /*Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to external RAM.*/ - uint32_t usr_ddr_dqs_thd : 7; /*The delay number of data strobe which from memory based on SPI clock.*/ - uint32_t ddr_dqs_loop : 1; /*1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS.*/ - uint32_t reserved22 : 2; /*reserved*/ - uint32_t clk_diff_en : 1; /*Set this bit to enable the differential SPI_CLK#.*/ - uint32_t reserved25 : 1; /*reserved*/ - uint32_t dqs_ca_in : 1; /*Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.*/ - uint32_t hyperbus_dummy_2x : 1; /*Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram.*/ - uint32_t clk_diff_inv : 1; /*Set this bit to invert SPI_DIFF when accesses to external RAM. .*/ - uint32_t octa_ram_addr : 1; /*Set this bit to enable octa_ram address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.*/ - uint32_t hyperbus_ca : 1; /*Set this bit to enable HyperRAM address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.*/ - uint32_t reserved31 : 1; /*reserved*/ - }; - uint32_t val; - } spi_smem_ddr; - uint32_t reserved_dc; - uint32_t reserved_e0; - uint32_t reserved_e4; - uint32_t reserved_e8; - uint32_t reserved_ec; - uint32_t reserved_f0; - uint32_t reserved_f4; - uint32_t reserved_f8; - uint32_t reserved_fc; - union { - struct { - uint32_t fmem_pms0_rd_attr : 1; /*1: SPI1 flash PMS section $n read accessible. 0: Not allowed.*/ - uint32_t fmem_pms0_wr_attr : 1; /*1: SPI1 flash PMS section $n write accessible. 0: Not allowed.*/ - uint32_t fmem_pms0_ecc : 1; /*SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_PMS$n_SIZE_REG.*/ - uint32_t reserved3 : 29; /*reserved*/ - }; - uint32_t val; - } spi_fmem_pms0_attr; - union { - struct { - uint32_t fmem_pms1_rd_attr : 1; /*1: SPI1 flash PMS section $n read accessible. 0: Not allowed.*/ - uint32_t fmem_pms1_wr_attr : 1; /*1: SPI1 flash PMS section $n write accessible. 0: Not allowed.*/ - uint32_t fmem_pms1_ecc : 1; /*SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_PMS$n_SIZE_REG.*/ - uint32_t reserved3 : 29; /*reserved*/ - }; - uint32_t val; - } spi_fmem_pms1_attr; - union { - struct { - uint32_t fmem_pms2_rd_attr : 1; /*1: SPI1 flash PMS section $n read accessible. 0: Not allowed.*/ - uint32_t fmem_pms2_wr_attr : 1; /*1: SPI1 flash PMS section $n write accessible. 0: Not allowed.*/ - uint32_t fmem_pms2_ecc : 1; /*SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_PMS$n_SIZE_REG.*/ - uint32_t reserved3 : 29; /*reserved*/ - }; - uint32_t val; - } spi_fmem_pms2_attr; - union { - struct { - uint32_t fmem_pms3_rd_attr : 1; /*1: SPI1 flash PMS section $n read accessible. 0: Not allowed.*/ - uint32_t fmem_pms3_wr_attr : 1; /*1: SPI1 flash PMS section $n write accessible. 0: Not allowed.*/ - uint32_t fmem_pms3_ecc : 1; /*SPI1 flash PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_PMS$n_SIZE_REG.*/ - uint32_t reserved3 : 29; /*reserved*/ - }; - uint32_t val; - } spi_fmem_pms3_attr; - union { - struct { - uint32_t fmem_pms0_addr_s : 26; /*SPI1 flash PMS section $n start address value*/ - uint32_t reserved26 : 6; /*reserved*/ - }; - uint32_t val; - } spi_fmem_pms0_addr; - union { - struct { - uint32_t fmem_pms1_addr_s : 26; /*SPI1 flash PMS section $n start address value*/ - uint32_t reserved26 : 6; /*reserved*/ - }; - uint32_t val; - } spi_fmem_pms1_addr; - union { - struct { - uint32_t fmem_pms2_addr_s : 26; /*SPI1 flash PMS section $n start address value*/ - uint32_t reserved26 : 6; /*reserved*/ - }; - uint32_t val; - } spi_fmem_pms2_addr; - union { - struct { - uint32_t fmem_pms3_addr_s : 26; /*SPI1 flash PMS section $n start address value*/ - uint32_t reserved26 : 6; /*reserved*/ - }; - uint32_t val; - } spi_fmem_pms3_addr; - union { - struct { - uint32_t fmem_pms0_size : 14; /*SPI1 flash PMS section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS$n_ADDR_S + SPI_FMEM_PMS$n_SIZE)*/ - uint32_t reserved14 : 18; /*reserved*/ - }; - uint32_t val; - } spi_fmem_pms0_size; - union { - struct { - uint32_t fmem_pms1_size : 14; /*SPI1 flash PMS section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS$n_ADDR_S + SPI_FMEM_PMS$n_SIZE)*/ - uint32_t reserved14 : 18; /*reserved*/ - }; - uint32_t val; - } spi_fmem_pms1_size; - union { - struct { - uint32_t fmem_pms2_size : 14; /*SPI1 flash PMS section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS$n_ADDR_S + SPI_FMEM_PMS$n_SIZE)*/ - uint32_t reserved14 : 18; /*reserved*/ - }; - uint32_t val; - } spi_fmem_pms2_size; - union { - struct { - uint32_t fmem_pms3_size : 14; /*SPI1 flash PMS section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS$n_ADDR_S + SPI_FMEM_PMS$n_SIZE)*/ - uint32_t reserved14 : 18; /*reserved*/ - }; - uint32_t val; - } spi_fmem_pms3_size; - union { - struct { - uint32_t pms0_rd_attr : 1; /*1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed.*/ - uint32_t pms0_wr_attr : 1; /*1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed.*/ - uint32_t pms0_ecc : 1; /*SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM PMS section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG and SPI_SMEM_PMS$n_SIZE_REG.*/ - uint32_t reserved3 : 29; /*reserved*/ - }; - uint32_t val; - } spi_smem_pms0_attr; - union { - struct { - uint32_t pms1_rd_attr : 1; /*1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed.*/ - uint32_t pms1_wr_attr : 1; /*1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed.*/ - uint32_t pms1_ecc : 1; /*SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM PMS section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG and SPI_SMEM_PMS$n_SIZE_REG.*/ - uint32_t reserved3 : 29; /*reserved*/ - }; - uint32_t val; - } spi_smem_pms1_attr; - union { - struct { - uint32_t pms2_rd_attr : 1; /*1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed.*/ - uint32_t pms2_wr_attr : 1; /*1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed.*/ - uint32_t pms2_ecc : 1; /*SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM PMS section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG and SPI_SMEM_PMS$n_SIZE_REG.*/ - uint32_t reserved3 : 29; /*reserved*/ - }; - uint32_t val; - } spi_smem_pms2_attr; - union { - struct { - uint32_t pms3_rd_attr : 1; /*1: SPI1 external RAM PMS section $n read accessible. 0: Not allowed.*/ - uint32_t pms3_wr_attr : 1; /*1: SPI1 external RAM PMS section $n write accessible. 0: Not allowed.*/ - uint32_t pms3_ecc : 1; /*SPI1 external RAM PMS section $n ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM PMS section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG and SPI_SMEM_PMS$n_SIZE_REG.*/ - uint32_t reserved3 : 29; /*reserved*/ - }; - uint32_t val; - } spi_smem_pms3_attr; - union { - struct { - uint32_t pms0_addr_s : 26; /*SPI1 external RAM PMS section $n start address value*/ - uint32_t reserved26 : 6; /*reserved*/ - }; - uint32_t val; - } spi_smem_pms0_addr; - union { - struct { - uint32_t pms1_addr_s : 26; /*SPI1 external RAM PMS section $n start address value*/ - uint32_t reserved26 : 6; /*reserved*/ - }; - uint32_t val; - } spi_smem_pms1_addr; - union { - struct { - uint32_t pms2_addr_s : 26; /*SPI1 external RAM PMS section $n start address value*/ - uint32_t reserved26 : 6; /*reserved*/ - }; - uint32_t val; - } spi_smem_pms2_addr; - union { - struct { - uint32_t pms3_addr_s : 26; /*SPI1 external RAM PMS section $n start address value*/ - uint32_t reserved26 : 6; /*reserved*/ - }; - uint32_t val; - } spi_smem_pms3_addr; - union { - struct { - uint32_t pms0_size : 14; /*SPI1 external RAM PMS section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_SMEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE)*/ - uint32_t reserved14 : 18; /*reserved*/ - }; - uint32_t val; - } spi_smem_pms0_size; - union { - struct { - uint32_t pms1_size : 14; /*SPI1 external RAM PMS section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_SMEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE)*/ - uint32_t reserved14 : 18; /*reserved*/ - }; - uint32_t val; - } spi_smem_pms1_size; - union { - struct { - uint32_t pms2_size : 14; /*SPI1 external RAM PMS section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_SMEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE)*/ - uint32_t reserved14 : 18; /*reserved*/ - }; - uint32_t val; - } spi_smem_pms2_size; - union { - struct { - uint32_t pms3_size : 14; /*SPI1 external RAM PMS section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_SMEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE)*/ - uint32_t reserved14 : 18; /*reserved*/ - }; - uint32_t val; - } spi_smem_pms3_size; - uint32_t reserved_160; - union { - struct { - uint32_t reject_addr : 26; /*This bits show the first SPI1 access error address. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. */ - uint32_t pm_en : 1; /*Set this bit to enable SPI0/1 transfer permission control function.*/ - uint32_t reserved27 : 1; /*reserved*/ - uint32_t pms_ld : 1; /*1: SPI1 write access error. 0: No write access error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. */ - uint32_t pms_st : 1; /*1: SPI1 read access error. 0: No read access error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. */ - uint32_t pms_multi_hit : 1; /*1: SPI1 access is rejected because of address miss. 0: No address miss error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. */ - uint32_t pms_ivd : 1; /*1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. */ - }; - uint32_t val; - } pms_reject; - union { - struct { - uint32_t reserved0 : 11; /*reserved*/ - uint32_t ecc_err_int_num : 6; /*Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt.*/ - uint32_t fmem_ecc_err_int_en : 1; /*Set this bit to calculate the error times of MSPI ECC read when accesses to flash.*/ - uint32_t fmem_page_size : 2; /*Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/ - uint32_t fmem_ecc_addr_en : 1; /*Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the ECC region or non-ECC region of flash. If there is no ECC region in flash, this bit should be 0. Otherwise, this bit should be 1.*/ - uint32_t usr_ecc_addr_en : 1; /*Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer.*/ - uint32_t reserved22 : 2; /*reserved*/ - uint32_t ecc_continue_record_err_en : 1; /*1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR record the first ECC error information.*/ - uint32_t ecc_err_bits : 7; /*Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding to byte 0 bit 0 to byte 15 bit 7)*/ - }; - uint32_t val; - } ecc_ctrl; - union { - struct { - uint32_t ecc_err_addr : 26; /*This bits show the first MSPI ECC error address. It is cleared by when SPI_MEM_ECC_ERR_INT_CLR bit is set. */ - uint32_t ecc_err_cnt : 6; /*This bits show the error times of MSPI ECC read. It is cleared by when SPI_MEM_ECC_ERR_INT_CLR bit is set. */ - }; - uint32_t val; - } ecc_err_addr; - union { - struct { - uint32_t axi_err_addr : 26; /*This bits show the first AXI write/read invalid error or AXI write flash error address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set. */ - uint32_t all_fifo_empty : 1; /*The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers and SPI0 transfers are done. 0: Others.*/ - uint32_t reg_rdata_afifo_rempty : 1; /*1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending.*/ - uint32_t reg_raddr_afifo_rempty : 1; /*1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending.*/ - uint32_t reg_wdata_afifo_rempty : 1; /*1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending.*/ - uint32_t reg_wblen_afifo_rempty : 1; /*1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending.*/ - uint32_t reg_all_axi_trans_afifo_empty : 1; /*This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO and RDATA_AFIFO are empty and spi0_mst_st is IDLE.*/ - }; - uint32_t val; - } axi_err_addr; - union { - struct { - uint32_t reserved0 : 17; /*reserved*/ - uint32_t ecc_err_int_en : 1; /*Set this bit to calculate the error times of MSPI ECC read when accesses to external RAM.*/ - uint32_t page_size : 2; /*Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/ - uint32_t ecc_addr_en : 1; /*Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the ECC region or non-ECC region of external RAM. If there is no ECC region in external RAM, this bit should be 0. Otherwise, this bit should be 1.*/ - uint32_t reserved21 : 11; /*reserved*/ - }; - uint32_t val; - } spi_smem_ecc_ctrl; - uint32_t reserved_178; - uint32_t reserved_17c; - union { - struct { - uint32_t timing_clk_ena : 1; /*The bit is used to enable timing adjust clock for all reading operations.*/ - uint32_t timing_cali : 1; /*The bit is used to enable timing auto-calibration for all reading operations.*/ - uint32_t extra_dummy_cyclelen : 3; /*add extra dummy spi clock cycle length for spi clock calibration.*/ - uint32_t dll_timing_cali : 1; /*Set this bit to enable DLL for timing calibration in DDR mode when accessed to flash.*/ - uint32_t timing_cali_update : 1; /*Set this bit to update delay mode, delay num and extra dummy in MSPI.*/ - uint32_t reserved7 : 25; /*reserved*/ - }; - uint32_t val; - } timing_cali; - union { - struct { - uint32_t din0_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ - uint32_t din1_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ - uint32_t din2_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ - uint32_t din3_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ - uint32_t din4_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk*/ - uint32_t din5_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk*/ - uint32_t din6_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk*/ - uint32_t din7_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk*/ - uint32_t dins_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk*/ - uint32_t reserved27 : 5; /*reserved*/ - }; - uint32_t val; - } din_mode; - union { - struct { - uint32_t din0_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ - uint32_t din1_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ - uint32_t din2_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ - uint32_t din3_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ - uint32_t din4_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ - uint32_t din5_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ - uint32_t din6_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ - uint32_t din7_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ - uint32_t dins_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ - uint32_t reserved18 : 14; /*reserved*/ - }; - uint32_t val; - } din_num; - union { - struct { - uint32_t dout0_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ - uint32_t dout1_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ - uint32_t dout2_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ - uint32_t dout3_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ - uint32_t dout4_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk*/ - uint32_t dout5_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk*/ - uint32_t dout6_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk*/ - uint32_t dout7_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk*/ - uint32_t douts_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk*/ - uint32_t reserved9 : 23; /*reserved*/ - }; - uint32_t val; - } dout_mode; - union { - struct { - uint32_t timing_clk_ena : 1; /*For sram, the bit is used to enable timing adjust clock for all reading operations.*/ - uint32_t timing_cali : 1; /*For sram, the bit is used to enable timing auto-calibration for all reading operations.*/ - uint32_t extra_dummy_cyclelen : 3; /*For sram, add extra dummy spi clock cycle length for spi clock calibration.*/ - uint32_t dll_timing_cali : 1; /*Set this bit to enable DLL for timing calibration in DDR mode when accessed to EXT_RAM.*/ - uint32_t reserved6 : 26; /*reserved*/ - }; - uint32_t val; - } spi_smem_timing_cali; - union { - struct { - uint32_t din0_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ - uint32_t din1_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ - uint32_t din2_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ - uint32_t din3_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ - uint32_t din4_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ - uint32_t din5_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ - uint32_t din6_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ - uint32_t din7_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ - uint32_t dins_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ - uint32_t reserved27 : 5; /*reserved*/ - }; - uint32_t val; - } spi_smem_din_mode; - union { - struct { - uint32_t din0_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ - uint32_t din1_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ - uint32_t din2_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ - uint32_t din3_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ - uint32_t din4_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ - uint32_t din5_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ - uint32_t din6_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ - uint32_t din7_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ - uint32_t dins_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ - uint32_t reserved18 : 14; /*reserved*/ - }; - uint32_t val; - } spi_smem_din_num; - union { - struct { - uint32_t dout0_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ - uint32_t dout1_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ - uint32_t dout2_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ - uint32_t dout3_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ - uint32_t dout4_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ - uint32_t dout5_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ - uint32_t dout6_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ - uint32_t dout7_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ - uint32_t douts_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ - uint32_t reserved9 : 23; /*reserved*/ - }; - uint32_t val; - } spi_smem_dout_mode; - union { - struct { - uint32_t cs_setup : 1; /*For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: disable. */ - uint32_t cs_hold : 1; /*For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable. */ - uint32_t cs_setup_time : 5; /*For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.*/ - uint32_t cs_hold_time : 5; /*For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.*/ - uint32_t ecc_cs_hold_time : 3; /*SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold cycles in ECC mode when accessed external RAM.*/ - uint32_t ecc_skip_page_corner : 1; /*1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner when accesses external RAM.*/ - uint32_t ecc_16to18_byte_en : 1; /*Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses external RAM.*/ - uint32_t reserved17 : 8; /*reserved*/ - uint32_t cs_hold_delay : 6; /*These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/ - uint32_t split_trans_en : 1; /*Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI transfers when one transfer will cross flash/EXT_RAM page corner, valid no matter whether there is an ECC region or not.*/ - }; - uint32_t val; - } spi_smem_ac; - union { - struct { - uint32_t din08_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ - uint32_t din09_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ - uint32_t din10_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ - uint32_t din11_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ - uint32_t din12_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ - uint32_t din13_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ - uint32_t din14_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ - uint32_t din15_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ - uint32_t dins_hex_mode : 3; /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge*/ - uint32_t reserved27 : 5; /*reserved*/ - }; - uint32_t val; - } spi_smem_din_hex_mode; - union { - struct { - uint32_t din08_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ - uint32_t din09_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ - uint32_t din10_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ - uint32_t din11_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ - uint32_t din12_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ - uint32_t din13_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ - uint32_t din14_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ - uint32_t din15_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ - uint32_t dins_hex_num : 2; /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/ - uint32_t reserved18 : 14; /*reserved*/ - }; - uint32_t val; - } spi_smem_din_hex_num; - union { - struct { - uint32_t dout08_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ - uint32_t dout09_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ - uint32_t dout10_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ - uint32_t dout11_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ - uint32_t dout12_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ - uint32_t dout13_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ - uint32_t dout14_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ - uint32_t dout15_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ - uint32_t douts_hex_mode : 1; /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/ - uint32_t reserved9 : 23; /*reserved*/ - }; - uint32_t val; - } spi_smem_dout_hex_mode; - uint32_t reserved_1b0; - uint32_t reserved_1b4; - uint32_t reserved_1b8; - uint32_t reserved_1bc; - uint32_t reserved_1c0; - uint32_t reserved_1c4; - uint32_t reserved_1c8; - uint32_t reserved_1cc; - uint32_t reserved_1d0; - uint32_t reserved_1d4; - uint32_t reserved_1d8; - uint32_t reserved_1dc; - uint32_t reserved_1e0; - uint32_t reserved_1e4; - uint32_t reserved_1e8; - uint32_t reserved_1ec; - uint32_t reserved_1f0; - uint32_t reserved_1f4; - uint32_t reserved_1f8; - uint32_t reserved_1fc; - union { - struct { - uint32_t reg_clk_en : 1; /*Register clock gate enable signal. 1: Enable. 0: Disable.*/ - uint32_t reserved1 : 31; /*reserved*/ - }; - uint32_t val; - } clock_gate; - uint32_t reserved_204; - uint32_t reserved_208; - uint32_t reserved_20c; - uint32_t reserved_210; - uint32_t reserved_214; - uint32_t reserved_218; - uint32_t reserved_21c; - uint32_t reserved_220; - uint32_t reserved_224; - uint32_t reserved_228; - uint32_t reserved_22c; - uint32_t reserved_230; - uint32_t reserved_234; - uint32_t reserved_238; - uint32_t reserved_23c; - uint32_t reserved_240; - uint32_t reserved_244; - uint32_t reserved_248; - uint32_t reserved_24c; - uint32_t reserved_250; - uint32_t reserved_254; - uint32_t reserved_258; - uint32_t reserved_25c; - uint32_t reserved_260; - uint32_t reserved_264; - uint32_t reserved_268; - uint32_t reserved_26c; - uint32_t reserved_270; - uint32_t reserved_274; - uint32_t reserved_278; - uint32_t reserved_27c; - uint32_t reserved_280; - uint32_t reserved_284; - uint32_t reserved_288; - uint32_t reserved_28c; - uint32_t reserved_290; - uint32_t reserved_294; - uint32_t reserved_298; - uint32_t reserved_29c; - uint32_t reserved_2a0; - uint32_t reserved_2a4; - uint32_t reserved_2a8; - uint32_t reserved_2ac; - uint32_t reserved_2b0; - uint32_t reserved_2b4; - uint32_t reserved_2b8; - uint32_t reserved_2bc; - uint32_t reserved_2c0; - uint32_t reserved_2c4; - uint32_t reserved_2c8; - uint32_t reserved_2cc; - uint32_t reserved_2d0; - uint32_t reserved_2d4; - uint32_t reserved_2d8; - uint32_t reserved_2dc; - uint32_t reserved_2e0; - uint32_t reserved_2e4; - uint32_t reserved_2e8; - uint32_t reserved_2ec; - uint32_t reserved_2f0; - uint32_t reserved_2f4; - uint32_t reserved_2f8; - uint32_t reserved_2fc; - uint32_t xts_plain_base; - uint32_t reserved_304; - uint32_t reserved_308; - uint32_t reserved_30c; - uint32_t reserved_310; - uint32_t reserved_314; - uint32_t reserved_318; - uint32_t reserved_31c; - uint32_t reserved_320; - uint32_t reserved_324; - uint32_t reserved_328; - uint32_t reserved_32c; - uint32_t reserved_330; - uint32_t reserved_334; - uint32_t reserved_338; - uint32_t reserved_33c; - union { - struct { - uint32_t reg_xts_linesize : 2; /*This bits stores the line-size parameter which will be used in manual encryption calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1: 32-bytes, 2: 64-bytes, 3:reserved.*/ - uint32_t reserved2 : 30; /*reserved*/ - }; - uint32_t val; - } xts_linesize; - union { - struct { - uint32_t reg_xts_destination : 1; /*This bit stores the destination parameter which will be used in manual encryption calculation. 0: flash(default), 1: psram(reserved). Only default value can be used.*/ - uint32_t reserved1 : 31; /*reserved*/ - }; - uint32_t val; - } xts_destination; - union { - struct { - uint32_t reg_xts_physical_address : 26; /*This bits stores the physical-address parameter which will be used in manual encryption calculation. This value should aligned with byte number decided by line-size parameter.*/ - uint32_t reserved26 : 6; /*reserved*/ - }; - uint32_t val; - } xts_physical_address; - union { - struct { - uint32_t reg_xts_trigger : 1; /*Set this bit to trigger the process of manual encryption calculation. This action should only be asserted when manual encryption status is 0. After this action, manual encryption status becomes 1. After calculation is done, manual encryption status becomes 2.*/ - uint32_t reserved1 : 31; /*reserved*/ - }; - uint32_t val; - } xts_trigger; - union { - struct { - uint32_t reg_xts_release : 1; /*Set this bit to release encrypted result to mspi. This action should only be asserted when manual encryption status is 2. After this action, manual encryption status will become 3.*/ - uint32_t reserved1 : 31; /*reserved*/ - }; - uint32_t val; - } xts_release; - union { - struct { - uint32_t reg_xts_destroy : 1; /*Set this bit to destroy encrypted result. This action should be asserted only when manual encryption status is 3. After this action, manual encryption status will become 0.*/ - uint32_t reserved1 : 31; /*reserved*/ - }; - uint32_t val; - } xts_destroy; - union { - struct { - uint32_t reg_xts_state : 2; /*This bits stores the status of manual encryption. 0: idle, 1: busy of encryption calculation, 2: encryption calculation is done but the encrypted result is invisible to mspi, 3: the encrypted result is visible to mspi.*/ - uint32_t reserved2 : 30; /*reserved*/ - }; - uint32_t val; - } xts_state; - union { - struct { - uint32_t reg_xts_date : 30; /*This bits stores the last modified-time of manual encryption feature.*/ - uint32_t reserved30 : 2; /*reserved*/ - }; - uint32_t val; - } xts_date; - uint32_t reserved_360; - uint32_t reserved_364; - uint32_t reserved_368; - uint32_t reserved_36c; - uint32_t reserved_370; - uint32_t reserved_374; - uint32_t reserved_378; - uint32_t mmu_item_content; - uint32_t mmu_item_index; - union { - struct { - uint32_t mem_force_on : 1; /*Set this bit to enable mmu-memory clock force on*/ - uint32_t mem_force_pd : 1; /*Set this bit to force mmu-memory powerdown*/ - uint32_t mem_force_pu : 1; /*Set this bit to force mmu-memory powerup, in this case, the power should also be controlled by rtc.*/ - uint32_t reserved3 : 13; /*reserved*/ - uint32_t aux_ctrl : 14; /*MMU PSRAM aux control register*/ - uint32_t rdn_ena : 1; /*ECO register enable bit*/ - uint32_t rdn_result : 1; /*MSPI module clock domain and AXI clock domain ECO register result register*/ - }; - uint32_t val; - } mmu_power_ctrl; - union { - struct { - uint32_t crtyp_security_level : 3; /*Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-7: The bigger the number is, the more secure the cryption is. (Note that the performance of cryption will decrease together with this number increasing)*/ - uint32_t crtyp_calc_d_dpa_en : 1; /*Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that using key 1.*/ - uint32_t crtyp_dpa_selectister : 1; /*1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits.*/ - uint32_t reserved5 : 27; /*reserved*/ - }; - uint32_t val; - } dpa_ctrl; - uint32_t reserved_38c; - uint32_t reserved_390; - uint32_t reserved_394; - uint32_t reserved_398; - uint32_t reserved_39c; - uint32_t reserved_3a0; - uint32_t reserved_3a4; - uint32_t reserved_3a8; - uint32_t reserved_3ac; - uint32_t reserved_3b0; - uint32_t reserved_3b4; - uint32_t reserved_3b8; - uint32_t reserved_3bc; - uint32_t reserved_3c0; - uint32_t reserved_3c4; - uint32_t reserved_3c8; - uint32_t reserved_3cc; - uint32_t reserved_3d0; - uint32_t reserved_3d4; - uint32_t reserved_3d8; - uint32_t reserved_3dc; - uint32_t reserved_3e0; - uint32_t reserved_3e4; - uint32_t reserved_3e8; - uint32_t reserved_3ec; - uint32_t registeredrnd_eco_high; - uint32_t registeredrnd_eco_low; - uint32_t reserved_3f8; - union { - struct { - uint32_t date : 28; /*SPI0 register version.*/ - uint32_t reserved28 : 4; /*reserved*/ - }; - uint32_t val; - } date; -} spi_mem_dev_t; -extern spi_mem_dev_t SPIMEM0; +typedef struct spi1_mem_c_dev_s spi_mem_dev_t; extern spi_mem_dev_t SPIMEM1; - -#ifndef __cplusplus -_Static_assert(sizeof(spi_mem_dev_t) == 0x400, "Invalid size of spi_mem_dev_t structure"); -#endif +extern spi_mem_c_dev_t SPIMEM0; #ifdef __cplusplus } diff --git a/components/soc/include/soc/spi_periph.h b/components/soc/include/soc/spi_periph.h index f127fa2687..28a4f049e5 100644 --- a/components/soc/include/soc/spi_periph.h +++ b/components/soc/include/soc/spi_periph.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/components/spi_flash/spi_flash_wrap.c b/components/spi_flash/spi_flash_wrap.c index 3a514d435f..e43f8d31b7 100644 --- a/components/spi_flash/spi_flash_wrap.c +++ b/components/spi_flash/spi_flash_wrap.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -12,6 +12,7 @@ #include "spi_flash_defs.h" #include "esp_rom_sys.h" #include "esp_rom_spiflash.h" +#include "rom/spi_flash.h" #include "spi_flash_override.h" #include "esp_private/spi_flash_os.h" @@ -87,9 +88,9 @@ esp_err_t spi_flash_wrap_enable_77(spi_flash_wrap_size_t wrap_size) { uint8_t wrap_code = (uint8_t) (((__builtin_ctz(wrap_size) - 3) * 2) << 4); // According to the special format, we need enable QIO_FWRITE for command 77h and clear it after this command is done. - REG_SET_BIT(SPI_MEM_USER_REG(1), SPI_MEM_FWRITE_QIO); + REG_SET_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_MEM_FWRITE_QIO); bootloader_flash_execute_command_common(CMD_WRAP, 0, 0, 6, 8, wrap_code, 0); - REG_CLR_BIT(SPI_MEM_USER_REG(1), SPI_MEM_FWRITE_QIO); + REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_MEM_FWRITE_QIO); return ESP_OK; } @@ -110,9 +111,9 @@ esp_err_t spi_flash_wrap_clear_c0(void) esp_err_t spi_flash_wrap_clear_77(void) { // According to the special format, we need enable QIO_FWRITE for command 77h and clear it after this command is done. - REG_SET_BIT(SPI_MEM_USER_REG(1), SPI_MEM_FWRITE_QIO); + REG_SET_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_MEM_FWRITE_QIO); bootloader_flash_execute_command_common(CMD_WRAP, 0, 0, 6, 8, 0x10, 0); - REG_CLR_BIT(SPI_MEM_USER_REG(1), SPI_MEM_FWRITE_QIO); + REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_MEM_FWRITE_QIO); return ESP_OK; } @@ -153,7 +154,7 @@ esp_err_t spi_flash_wrap_disable(void) bool spi_flash_support_wrap_size(uint32_t wrap_size) { // Only QIO mode supports wrap. - if (!REG_GET_BIT(SPI_MEM_CTRL_REG(0), SPI_MEM_FREAD_QIO)) { + if (!REG_GET_BIT(PERIPHS_SPI_FLASH_CTRL, SPI_MEM_FREAD_QIO)) { ESP_EARLY_LOGE(FLASH_WRAP_TAG, "flash wrap is only supported in QIO mode"); abort(); }