From 2c59c4fbf2b0a8de002e8efe60b70ee73b9a3ae3 Mon Sep 17 00:00:00 2001 From: Lou Tianhao Date: Sun, 7 Apr 2024 17:17:24 +0800 Subject: [PATCH] fix(ci): bypass c5mp ci check --- components/esp_hw_support/CMakeLists.txt | 10 +- .../port/esp32c5/CMakeLists.txt | 26 +++-- .../esp_hw_support/port/esp32c5/rtc_time.c | 5 + .../include/esp32c5/mp/esp32c5/rom/rtc.h | 4 +- .../hal/esp32c5/include/hal/lp_timer_ll.h | 40 +++++++ components/hal/esp32c5/include/hal/pau_ll.h | 110 ++++++++++++++++++ components/hal/esp32c5/pau_hal.c | 2 - components/hal/esp32c6/pau_hal.c | 2 - components/hal/esp32p4/pau_hal.c | 2 - 9 files changed, 184 insertions(+), 17 deletions(-) diff --git a/components/esp_hw_support/CMakeLists.txt b/components/esp_hw_support/CMakeLists.txt index f09acaf796..498f346959 100644 --- a/components/esp_hw_support/CMakeLists.txt +++ b/components/esp_hw_support/CMakeLists.txt @@ -150,12 +150,20 @@ if(NOT BOOTLOADER_BUILD) list(APPEND srcs "esp_clock_output.c") endif() - if(CONFIG_IDF_TARGET_ESP32C5) + if(CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION) list(REMOVE_ITEM srcs "sleep_gpio.c" # TODO: [ESP32C5] IDF-8638, IDF-8640 "port/esp_clk_tree_common.c" # TODO: [ESP32C5] IDF-8638, IDF-8640 ) endif() + if(CONFIG_IDF_TARGET_ESP32C5_MP_VERSION) + list(REMOVE_ITEM srcs + "sleep_modes.c" # TODO: [ESP32C5] IDF-8638, IDF-8640 + "sleep_wake_stub.c" # TODO: [ESP32C5] IDF-8638, IDF-8640 + "sleep_gpio.c" # TODO: [ESP32C5] IDF-8638, IDF-8640 + "port/esp_clk_tree_common.c" # TODO: [ESP32C5] IDF-8638, IDF-8640 + ) + endif() if(CONFIG_IDF_TARGET_ESP32C61) # TODO: [ESP32C61] IDF-9245, IDF-9247, IDF-9248 list(REMOVE_ITEM srcs "sleep_cpu.c" diff --git a/components/esp_hw_support/port/esp32c5/CMakeLists.txt b/components/esp_hw_support/port/esp32c5/CMakeLists.txt index e6ffeeefef..d14b5b2cf6 100644 --- a/components/esp_hw_support/port/esp32c5/CMakeLists.txt +++ b/components/esp_hw_support/port/esp32c5/CMakeLists.txt @@ -1,11 +1,21 @@ -set(srcs "rtc_clk_init.c" - "rtc_clk.c" - "rtc_time.c" - "pmu_init.c" - "pmu_sleep.c" - "pmu_param.c" - "chip_info.c" - ) +if(CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION) + set(srcs "rtc_clk_init.c" + "rtc_clk.c" + "rtc_time.c" + "pmu_init.c" + "pmu_sleep.c" + "pmu_param.c" + "chip_info.c" + ) +endif() +if(CONFIG_IDF_TARGET_ESP32C5_MP_VERSION) + set(srcs "rtc_clk_init.c" + "rtc_time.c" + "rtc_clk.c" + "chip_info.c" + ) +endif() + if(NOT BOOTLOADER_BUILD) list(APPEND srcs "sar_periph_ctrl.c" diff --git a/components/esp_hw_support/port/esp32c5/rtc_time.c b/components/esp_hw_support/port/esp32c5/rtc_time.c index 4ddbb751d7..65b2c3cb7f 100644 --- a/components/esp_hw_support/port/esp32c5/rtc_time.c +++ b/components/esp_hw_support/port/esp32c5/rtc_time.c @@ -245,7 +245,12 @@ uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period) uint64_t rtc_time_get(void) { +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION return lp_timer_hal_get_cycle_count(); +#else + ESP_EARLY_LOGW(TAG, "rtc_timer has not been implemented yet"); + return 0; +#endif } void rtc_clk_wait_for_slow_cycle(void) //This function may not by useful any more diff --git a/components/esp_rom/include/esp32c5/mp/esp32c5/rom/rtc.h b/components/esp_rom/include/esp32c5/mp/esp32c5/rom/rtc.h index 42559d7524..eb98a8ebc4 100644 --- a/components/esp_rom/include/esp32c5/mp/esp32c5/rom/rtc.h +++ b/components/esp_rom/include/esp32c5/mp/esp32c5/rom/rtc.h @@ -63,8 +63,8 @@ extern "C" { #define RTC_ENTRY_ADDR_REG LP_AON_STORE6_REG #define RTC_RESET_CAUSE_REG LP_AON_STORE6_REG #define RTC_MEMORY_CRC_REG LP_AON_STORE7_REG -#define LIGHT_SLEEP_WAKE_STUB_ADDR_REG LP_AON_STORE8_REG -#define SLEEP_MODE_REG LP_AON_STORE9_REG +#define RTC_SLEEP_WAKE_STUB_ADDR_REG LP_AON_STORE8_REG +#define RTC_SLEEP_MODE_REG LP_AON_STORE8_REG #define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) //!< Disable logging from the ROM code. diff --git a/components/hal/esp32c5/include/hal/lp_timer_ll.h b/components/hal/esp32c5/include/hal/lp_timer_ll.h index 0e643b0adc..357a89b8a1 100644 --- a/components/hal/esp32c5/include/hal/lp_timer_ll.h +++ b/components/hal/esp32c5/include/hal/lp_timer_ll.h @@ -13,6 +13,7 @@ #include "soc/rtc.h" #include "soc/lp_timer_struct.h" #include "soc/lp_aon_reg.h" +#include "hal/assert.h" #include "hal/lp_timer_types.h" #include "esp_attr.h" @@ -31,8 +32,12 @@ extern "C" { */ FORCE_INLINE_ATTR void lp_timer_ll_set_alarm_target(lp_timer_dev_t *dev, uint8_t timer_id, uint64_t value) { +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION dev->target[timer_id].hi.main_timer_tar_high = (value >> 32) & 0xFFFF; dev->target[timer_id].lo.main_timer_tar_low = value & 0xFFFFFFFF; +#else + HAL_ASSERT(false && "lp_timer not supported yet"); +#endif } /** @@ -46,7 +51,11 @@ FORCE_INLINE_ATTR void lp_timer_ll_set_alarm_target(lp_timer_dev_t *dev, uint8_t */ FORCE_INLINE_ATTR void lp_timer_ll_set_target_enable(lp_timer_dev_t *dev, uint8_t timer_id, bool en) { +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION dev->target[timer_id].hi.main_timer_tar_en = en; +#else + HAL_ASSERT(false && "lp_timer not supported yet"); +#endif } /** @@ -59,7 +68,12 @@ FORCE_INLINE_ATTR void lp_timer_ll_set_target_enable(lp_timer_dev_t *dev, uint8_ */ FORCE_INLINE_ATTR uint32_t lp_timer_ll_get_counter_value_low(lp_timer_dev_t *dev, uint8_t buffer_id) { +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION return dev->counter[buffer_id].lo.main_timer_buf_low; +#else + HAL_ASSERT(false && "lp_timer not supported yet"); + return 0; +#endif } /** @@ -72,7 +86,12 @@ FORCE_INLINE_ATTR uint32_t lp_timer_ll_get_counter_value_low(lp_timer_dev_t *dev */ FORCE_INLINE_ATTR uint32_t lp_timer_ll_get_counter_value_high(lp_timer_dev_t *dev, uint8_t buffer_id) { +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION return dev->counter[buffer_id].hi.main_timer_buf_high; +#else + HAL_ASSERT(false && "lp_timer not supported yet"); + return 0; +#endif } /** @@ -84,7 +103,11 @@ FORCE_INLINE_ATTR uint32_t lp_timer_ll_get_counter_value_high(lp_timer_dev_t *de */ FORCE_INLINE_ATTR void lp_timer_ll_counter_snapshot(lp_timer_dev_t *dev) { +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION dev->update.main_timer_update = 1; +#else + HAL_ASSERT(false && "lp_timer not supported yet"); +#endif } /** @@ -96,7 +119,11 @@ FORCE_INLINE_ATTR void lp_timer_ll_counter_snapshot(lp_timer_dev_t *dev) */ FORCE_INLINE_ATTR void lp_timer_ll_clear_alarm_intr_status(lp_timer_dev_t *dev) { +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION dev->int_clr.soc_wakeup_int_clr = 1; +#else + HAL_ASSERT(false && "lp_timer not supported yet"); +#endif } /** @@ -108,7 +135,11 @@ FORCE_INLINE_ATTR void lp_timer_ll_clear_alarm_intr_status(lp_timer_dev_t *dev) */ FORCE_INLINE_ATTR void lp_timer_ll_clear_overflow_intr_status(lp_timer_dev_t *dev) { +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION dev->int_clr.overflow_clr = 1; +#else + HAL_ASSERT(false && "lp_timer not supported yet"); +#endif } /** @@ -120,7 +151,11 @@ FORCE_INLINE_ATTR void lp_timer_ll_clear_overflow_intr_status(lp_timer_dev_t *de */ FORCE_INLINE_ATTR void lp_timer_ll_clear_lp_alarm_intr_status(lp_timer_dev_t *dev) { +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION dev->lp_int_clr.main_timer_lp_int_clr = 1; +#else + HAL_ASSERT(false && "lp_timer not supported yet"); +#endif } /** @@ -132,8 +167,13 @@ FORCE_INLINE_ATTR void lp_timer_ll_clear_lp_alarm_intr_status(lp_timer_dev_t *de */ FORCE_INLINE_ATTR uint64_t lp_timer_ll_time_to_count(uint64_t time_in_us) { +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION uint32_t slow_clk_value = REG_READ(LP_AON_STORE1_REG); return ((time_in_us * (1 << RTC_CLK_CAL_FRACT)) / slow_clk_value); +#else + HAL_ASSERT(false && "lp_timer not supported yet"); + return 0; +#endif } #ifdef __cplusplus diff --git a/components/hal/esp32c5/include/hal/pau_ll.h b/components/hal/esp32c5/include/hal/pau_ll.h index 0bd9593294..7294cfdefd 100644 --- a/components/hal/esp32c5/include/hal/pau_ll.h +++ b/components/hal/esp32c5/include/hal/pau_ll.h @@ -22,132 +22,242 @@ extern "C" { static inline uint32_t pau_ll_get_regdma_backup_flow_error(pau_dev_t *dev) { +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION return dev->regdma_conf.flow_err; +#else + HAL_ASSERT(false && "pau not supported yet"); + return 0; +#endif } static inline void pau_ll_select_regdma_entry_link(pau_dev_t *dev, int link) { +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION dev->regdma_conf.link_sel = link; +#else + HAL_ASSERT(false && "pau not supported yet"); +#endif } static inline void pau_ll_set_regdma_entry_link_backup_direction(pau_dev_t *dev, bool to_mem) { +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION dev->regdma_conf.to_mem = to_mem ? 1 : 0; +#else + HAL_ASSERT(false && "pau not supported yet"); +#endif } static inline void pau_ll_set_regdma_entry_link_backup_start_enable(pau_dev_t *dev) { +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION dev->regdma_conf.start = 1; +#else + HAL_ASSERT(false && "pau not supported yet"); +#endif } static inline void pau_ll_set_regdma_entry_link_backup_start_disable(pau_dev_t *dev) { +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION dev->regdma_conf.start = 0; +#else + HAL_ASSERT(false && "pau not supported yet"); +#endif } static inline void pau_ll_set_regdma_select_wifimac_link(pau_dev_t *dev) { +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION dev->regdma_conf.sel_mac = 1; +#else + HAL_ASSERT(false && "pau not supported yet"); +#endif } static inline void pau_ll_set_regdma_deselect_wifimac_link(pau_dev_t *dev) { +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION dev->regdma_conf.sel_mac = 0; +#else + HAL_ASSERT(false && "pau not supported yet"); +#endif } static inline void pau_ll_set_regdma_wifimac_link_backup_direction(pau_dev_t *dev, bool to_mem) { +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION dev->regdma_conf.to_mem_mac = to_mem ? 1 : 0; +#else + HAL_ASSERT(false && "pau not supported yet"); +#endif } static inline void pau_ll_set_regdma_wifimac_link_backup_start_enable(pau_dev_t *dev) { +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION dev->regdma_conf.start_mac = 1; +#else + HAL_ASSERT(false && "pau not supported yet"); +#endif } static inline void pau_ll_set_regdma_wifimac_link_backup_start_disable(pau_dev_t *dev) { +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION dev->regdma_conf.start_mac = 0; +#else + HAL_ASSERT(false && "pau not supported yet"); +#endif } static inline void pau_ll_set_regdma_link0_addr(pau_dev_t *dev, void *link_addr) { +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION dev->regdma_link_0_addr.val = (uint32_t)link_addr; +#else + HAL_ASSERT(false && "pau not supported yet"); +#endif } static inline void pau_ll_set_regdma_link1_addr(pau_dev_t *dev, void *link_addr) { +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION dev->regdma_link_1_addr.val = (uint32_t)link_addr; +#else + HAL_ASSERT(false && "pau not supported yet"); +#endif } static inline void pau_ll_set_regdma_link2_addr(pau_dev_t *dev, void *link_addr) { +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION dev->regdma_link_2_addr.val = (uint32_t)link_addr; +#else + HAL_ASSERT(false && "pau not supported yet"); +#endif } static inline void pau_ll_set_regdma_link3_addr(pau_dev_t *dev, void *link_addr) { +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION dev->regdma_link_3_addr.val = (uint32_t)link_addr; +#else + HAL_ASSERT(false && "pau not supported yet"); +#endif } static inline void pau_ll_set_regdma_wifimac_link_addr(pau_dev_t *dev, void *link_addr) { +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION dev->regdma_link_mac_addr.val = (uint32_t)link_addr; +#else + HAL_ASSERT(false && "pau not supported yet"); +#endif } static inline uint32_t pau_ll_get_regdma_current_link_addr(pau_dev_t *dev) { +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION return dev->regdma_current_link_addr.val; +#else + HAL_ASSERT(false && "pau not supported yet"); + return 0; +#endif } static inline uint32_t pau_ll_get_regdma_backup_addr(pau_dev_t *dev) { +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION return dev->regdma_backup_addr.val; +#else + HAL_ASSERT(false && "pau not supported yet"); + return 0; +#endif } static inline uint32_t pau_ll_get_regdma_memory_addr(pau_dev_t *dev) { +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION return dev->regdma_mem_addr.val; +#else + HAL_ASSERT(false && "pau not supported yet"); + return 0; +#endif } static inline uint32_t pau_ll_get_regdma_intr_raw_signal(pau_dev_t *dev) { +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION return dev->int_raw.val; +#else + HAL_ASSERT(false && "pau not supported yet"); + return 0; +#endif } static inline uint32_t pau_ll_get_regdma_intr_status(pau_dev_t *dev) { +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION return dev->int_st.val; +#else + HAL_ASSERT(false && "pau not supported yet"); + return 0; +#endif } static inline void pau_ll_set_regdma_backup_done_intr_enable(pau_dev_t *dev) { +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION dev->int_ena.done_int_ena = 1; +#else + HAL_ASSERT(false && "pau not supported yet"); +#endif } static inline void pau_ll_set_regdma_backup_done_intr_disable(pau_dev_t *dev) { +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION dev->int_ena.done_int_ena = 0; +#else + HAL_ASSERT(false && "pau not supported yet"); +#endif } static inline void pau_ll_set_regdma_backup_error_intr_enable(pau_dev_t *dev) { +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION dev->int_ena.error_int_ena = 1; +#else + HAL_ASSERT(false && "pau not supported yet"); +#endif } static inline void pau_ll_set_regdma_backup_error_intr_disable(pau_dev_t *dev) { +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION dev->int_ena.error_int_ena = 0; +#else + HAL_ASSERT(false && "pau not supported yet"); +#endif } static inline void pau_ll_clear_regdma_backup_done_intr_state(pau_dev_t *dev) { +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION dev->int_clr.done_int_clr = 1; +#else + HAL_ASSERT(false && "pau not supported yet"); +#endif } static inline void pau_ll_clear_regdma_backup_error_intr_state(pau_dev_t *dev) { +#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION dev->int_clr.error_int_clr = 1; +#else + HAL_ASSERT(false && "pau not supported yet"); +#endif } #ifdef __cplusplus diff --git a/components/hal/esp32c5/pau_hal.c b/components/hal/esp32c5/pau_hal.c index 80cf785b33..000a958b32 100644 --- a/components/hal/esp32c5/pau_hal.c +++ b/components/hal/esp32c5/pau_hal.c @@ -4,8 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ -// The HAL layer for PAU (ESP32-C6 specific part) - #include "soc/soc.h" #include "esp_attr.h" #include "hal/pau_hal.h" diff --git a/components/hal/esp32c6/pau_hal.c b/components/hal/esp32c6/pau_hal.c index 53be6120c3..cc39004bae 100644 --- a/components/hal/esp32c6/pau_hal.c +++ b/components/hal/esp32c6/pau_hal.c @@ -4,8 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ -// The HAL layer for PAU (ESP32-C6 specific part) - #include "soc/soc.h" #include "esp_attr.h" #include "hal/pau_hal.h" diff --git a/components/hal/esp32p4/pau_hal.c b/components/hal/esp32p4/pau_hal.c index 958210f0c1..38b98ba4e1 100644 --- a/components/hal/esp32p4/pau_hal.c +++ b/components/hal/esp32p4/pau_hal.c @@ -4,8 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ -// The HAL layer for PAU (ESP32-C6 specific part) - #include "soc/soc.h" #include "soc/soc_caps.h" #include "esp_attr.h"