kopia lustrzana https://github.com/espressif/esp-idf
driver/adc: support adc single sample on s3
laokaiyao
rodzic
6bb6f3ebc4
commit
27d9657b6c
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@ -61,8 +61,7 @@ if(${target} STREQUAL "esp32s3")
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"sdmmc_transaction.c"
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"mcpwm.c"
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"spi_slave_hd.c"
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"touch_sensor_common.c"
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)
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"touch_sensor_common.c")
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endif()
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if(IDF_TARGET STREQUAL "esp32c3")
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@ -117,7 +117,7 @@ static _lock_t adc2_wifi_lock;
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#endif // CONFIG_IDF_TARGET_*
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#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
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#if CONFIG_IDF_TARGET_ESP32S2
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#ifdef CONFIG_PM_ENABLE
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static esp_pm_lock_handle_t s_adc2_arbiter_lock;
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#endif //CONFIG_PM_ENABLE
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@ -127,7 +127,7 @@ static esp_pm_lock_handle_t s_adc2_arbiter_lock;
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ADC Common
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---------------------------------------------------------------*/
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#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
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#if CONFIG_IDF_TARGET_ESP32S2
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static uint32_t get_calibration_offset(adc_ll_num_t adc_n, adc_channel_t chan)
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{
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adc_atten_t atten = adc_hal_get_atten(adc_n, chan);
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@ -299,10 +299,10 @@ esp_err_t adc_set_data_inv(adc_unit_t adc_unit, bool inv_en)
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esp_err_t adc_set_data_width(adc_unit_t adc_unit, adc_bits_width_t bits)
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{
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#ifdef CONFIG_IDF_TARGET_ESP32
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#if CONFIG_IDF_TARGET_ESP32
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ADC_CHECK(bits < ADC_WIDTH_MAX, "WIDTH ERR: ESP32 support 9 ~ 12 bit width", ESP_ERR_INVALID_ARG);
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#else
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ADC_CHECK(bits == ADC_WIDTH_BIT_13, "WIDTH ERR: " CONFIG_IDF_TARGET " support 13 bit width", ESP_ERR_INVALID_ARG);
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ADC_CHECK(bits == ADC_WIDTH_MAX - 1, "WIDTH ERR: see `adc_bits_width_t` for supported bit width", ESP_ERR_INVALID_ARG);
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#endif
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if (adc_unit & ADC_UNIT_1) {
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@ -329,7 +329,7 @@ esp_err_t adc_set_data_width(adc_unit_t adc_unit, adc_bits_width_t bits)
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esp_err_t adc_rtc_reset(void)
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{
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FSM_ENTER();
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adc_hal_rtc_reset();
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adc_ll_rtc_reset();
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FSM_EXIT();
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return ESP_OK;
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}
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@ -358,10 +358,10 @@ esp_err_t adc1_config_channel_atten(adc1_channel_t channel, adc_atten_t atten)
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esp_err_t adc1_config_width(adc_bits_width_t width_bit)
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{
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#ifdef CONFIG_IDF_TARGET_ESP32
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#if CONFIG_IDF_TARGET_ESP32
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ADC_CHECK(width_bit < ADC_WIDTH_MAX, "WIDTH ERR: ESP32 support 9 ~ 12 bit width", ESP_ERR_INVALID_ARG);
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#elif !defined(CONFIG_IDF_TARGET_ESP32)
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ADC_CHECK(width_bit == ADC_WIDTH_BIT_13, "WIDTH ERR: " CONFIG_IDF_TARGET " support 13 bit width", ESP_ERR_INVALID_ARG);
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#else
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ADC_CHECK(width_bit == ADC_WIDTH_MAX - 1, "WIDTH ERR: see `adc_bits_width_t` for supported bit width", ESP_ERR_INVALID_ARG);
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#endif
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SARADC1_ENTER();
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@ -382,7 +382,11 @@ esp_err_t adc1_dma_mode_acquire(void)
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SARADC1_ENTER();
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/* switch SARADC into DIG channel */
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#if CONFIG_IDF_TARGET_ESP32S3 // remove this macro. TODO: IDF-1776
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adc_hal_set_controller(ADC_NUM_1, ADC_LL_CTRL_DIG);
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#else
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adc_hal_set_controller(ADC_NUM_1, ADC_CTRL_DIG);
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#endif
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SARADC1_EXIT();
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return ESP_OK;
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@ -397,7 +401,11 @@ esp_err_t adc1_rtc_mode_acquire(void)
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SARADC1_ENTER();
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/* switch SARADC into RTC channel. */
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#if CONFIG_IDF_TARGET_ESP32S3 // remove this macro. TODO: IDF-1776
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adc_hal_set_controller(ADC_NUM_1, ADC_LL_CTRL_RTC);
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#else
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adc_hal_set_controller(ADC_NUM_1, ADC_CTRL_RTC);
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#endif
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SARADC1_EXIT();
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return ESP_OK;
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@ -419,7 +427,7 @@ int adc1_get_raw(adc1_channel_t channel)
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ADC_CHANNEL_CHECK(ADC_NUM_1, channel);
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adc1_rtc_mode_acquire();
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#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
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#if CONFIG_IDF_TARGET_ESP32S2
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// Get calibration value before going into critical section
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uint32_t cal_val = get_calibration_offset(ADC_NUM_1, channel);
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adc_hal_set_calibration_param(ADC_NUM_1, cal_val);
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@ -430,10 +438,14 @@ int adc1_get_raw(adc1_channel_t channel)
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adc_hal_hall_disable(); //Disable other peripherals.
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adc_hal_amp_disable(); //Currently the LNA is not open, close it by default.
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#endif
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#if CONFIG_IDF_TARGET_ESP32S3 // remove this macro. TODO: IDF-1776
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adc_hal_set_controller(ADC_NUM_1, ADC_LL_CTRL_RTC); //Set controller
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#else
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adc_hal_set_controller(ADC_NUM_1, ADC_CTRL_RTC); //Set controller
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#endif
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adc_hal_convert(ADC_NUM_1, channel, &adc_value); //Start conversion, For ADC1, the data always valid.
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#if !CONFIG_IDF_TARGET_ESP32
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adc_hal_rtc_reset(); //Reset FSM of rtc controller
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adc_ll_rtc_reset(); //Reset FSM of rtc controller
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#endif
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SARADC1_EXIT();
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@ -452,7 +464,11 @@ void adc1_ulp_enable(void)
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adc_power_acquire();
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SARADC1_ENTER();
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adc_hal_set_controller(ADC_NUM_1, ADC_CTRL_ULP);
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#if CONFIG_IDF_TARGET_ESP32S3 // remove this macro. TODO: IDF-1776
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adc_hal_set_controller(ADC_NUM_1, ADC_LL_CTRL_ULP);
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#else
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adc_hal_set_controller(ADC_NUM_1, ADC_CTRL_ULP); //Set controller
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#endif
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/* since most users do not need LNA and HALL with uLP, we disable them here
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open them in the uLP if needed. */
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#ifdef CONFIG_IDF_TARGET_ESP32
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@ -556,13 +572,13 @@ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int *
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ADC_CHECK(raw_out != NULL, "ADC out value err", ESP_ERR_INVALID_ARG);
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ADC_CHECK(channel < ADC2_CHANNEL_MAX, "ADC Channel Err", ESP_ERR_INVALID_ARG);
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#ifdef CONFIG_IDF_TARGET_ESP32
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#if CONFIG_IDF_TARGET_ESP32
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ADC_CHECK(width_bit < ADC_WIDTH_MAX, "WIDTH ERR: ESP32 support 9 ~ 12 bit width", ESP_ERR_INVALID_ARG);
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#else
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ADC_CHECK(width_bit == ADC_WIDTH_BIT_13, "WIDTH ERR: ESP32S2 support 13 bit width", ESP_ERR_INVALID_ARG);
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ADC_CHECK(width_bit == ADC_WIDTH_MAX - 1, "WIDTH ERR: see `adc_bits_width_t` for supported bit width", ESP_ERR_INVALID_ARG);
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#endif
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#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
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#if CONFIG_IDF_TARGET_ESP32S2
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// Get calibration value before going into critical section
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uint32_t cal_val = get_calibration_offset(ADC_NUM_2, channel);
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adc_hal_set_calibration_param(ADC_NUM_2, cal_val);
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@ -581,7 +597,11 @@ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int *
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adc2_dac_disable(channel); //disable other peripherals
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#endif
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adc_hal_rtc_set_output_format(ADC_NUM_2, width_bit);
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adc_hal_set_controller(ADC_NUM_2, ADC_CTRL_RTC);// set controller
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#if CONFIG_IDF_TARGET_ESP32S3 // remove this macro. TODO: IDF-1776
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adc_hal_set_controller(ADC_NUM_2, ADC_LL_CTRL_ARB);// set controller
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#else
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adc_hal_set_controller(ADC_NUM_2, ADC_CTRL_RTC);
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#endif
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#if !CONFIG_IDF_TARGET_ESP32
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#ifdef CONFIG_PM_ENABLE
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@ -596,7 +616,7 @@ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int *
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adc_value = -1;
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}
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#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
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#if CONFIG_IDF_TARGET_ESP32S2
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#ifdef CONFIG_PM_ENABLE
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/* Release APB clock. */
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if (s_adc2_arbiter_lock) {
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@ -7,231 +7,4 @@
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#pragma once
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#include "driver/adc_common.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*---------------------------------------------------------------
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Common setting
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---------------------------------------------------------------*/
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/**
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* @brief Config ADC module arbiter.
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* The arbiter is to improve the use efficiency of ADC2. After the control right is robbed by the high priority,
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* the low priority controller will read the invalid ADC2 data, and the validity of the data can be judged by the flag bit in the data.
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*
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* @note Only ADC2 support arbiter.
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* @note Default priority: Wi-Fi > RTC > Digital;
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* @note In normal use, there is no need to call this interface to config arbiter.
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*
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* @param adc_unit ADC unit.
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* @param config Refer to `adc_arbiter_t`.
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*
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* @return
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* - ESP_OK Success
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* - ESP_ERR_NOT_SUPPORTED ADC unit not support arbiter.
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*/
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esp_err_t adc_arbiter_config(adc_unit_t adc_unit, adc_arbiter_t *config);
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/*---------------------------------------------------------------
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Digital controller setting
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---------------------------------------------------------------*/
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/**
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* @brief ADC digital controller initialization.
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* @return
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* - ESP_OK Success
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*/
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esp_err_t adc_digi_init(void);
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/**
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* @brief ADC digital controller deinitialization.
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* @return
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* - ESP_OK Success
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*/
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esp_err_t adc_digi_deinit(void);
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/**
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* @brief Setting the digital controller.
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*
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* @param config Pointer to digital controller paramter. Refer to `adc_digi_config_t`.
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*
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* @return
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* - ESP_OK Success
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*/
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esp_err_t adc_digi_controller_config(const adc_digi_config_t *config);
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/**
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* @brief Enable digital controller to trigger the measurement.
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*
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* @return
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* - ESP_OK Success
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*/
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esp_err_t adc_digi_start(void);
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/**
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* @brief Disable digital controller to trigger the measurement.
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*
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* @return
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* - ESP_OK Success
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*/
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esp_err_t adc_digi_stop(void);
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/*************************************/
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/* Digital controller filter setting */
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/*************************************/
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/**
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* @brief Reset adc digital controller filter.
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*
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* @param idx Filter index.
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*
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* @return
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* - ESP_OK Success
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*/
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esp_err_t adc_digi_filter_reset(adc_digi_filter_idx_t idx);
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/**
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* @brief Set adc digital controller filter configuration.
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*
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* @note For ESP32S2, Filter IDX0/IDX1 can only be used to filter all enabled channels of ADC1/ADC2 unit at the same time.
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*
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* @param idx Filter index.
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* @param config See ``adc_digi_filter_t``.
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*
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* @return
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* - ESP_OK Success
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*/
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esp_err_t adc_digi_filter_set_config(adc_digi_filter_idx_t idx, adc_digi_filter_t *config);
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/**
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* @brief Get adc digital controller filter configuration.
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*
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* @note For ESP32S2, Filter IDX0/IDX1 can only be used to filter all enabled channels of ADC1/ADC2 unit at the same time.
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*
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* @param idx Filter index.
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* @param config See ``adc_digi_filter_t``.
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*
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* @return
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* - ESP_OK Success
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*/
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esp_err_t adc_digi_filter_get_config(adc_digi_filter_idx_t idx, adc_digi_filter_t *config);
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/**
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* @brief Enable/disable adc digital controller filter.
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* Filtering the ADC data to obtain smooth data at higher sampling rates.
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*
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* @note For ESP32S2, Filter IDX0/IDX1 can only be used to filter all enabled channels of ADC1/ADC2 unit at the same time.
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*
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* @param idx Filter index.
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* @param enable Enable/Disable filter.
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*
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* @return
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* - ESP_OK Success
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*/
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esp_err_t adc_digi_filter_enable(adc_digi_filter_idx_t idx, bool enable);
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/**************************************/
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/* Digital controller monitor setting */
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/**************************************/
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/**
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* @brief Config monitor of adc digital controller.
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*
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* @note For ESP32S2, The monitor will monitor all the enabled channel data of the each ADC unit at the same time.
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*
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* @param idx Monitor index.
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* @param config See ``adc_digi_monitor_t``.
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*
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* @return
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* - ESP_OK Success
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*/
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esp_err_t adc_digi_monitor_set_config(adc_digi_monitor_idx_t idx, adc_digi_monitor_t *config);
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/**
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* @brief Enable/disable monitor of adc digital controller.
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*
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* @note For ESP32S2, The monitor will monitor all the enabled channel data of the each ADC unit at the same time.
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*
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* @param idx Monitor index.
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* @param enable True or false enable monitor.
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*
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* @return
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* - ESP_OK Success
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*/
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esp_err_t adc_digi_monitor_enable(adc_digi_monitor_idx_t idx, bool enable);
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/**************************************/
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/* Digital controller intr setting */
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/**************************************/
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/**
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* @brief Enable interrupt of adc digital controller by bitmask.
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*
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* @param adc_unit ADC unit.
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* @param intr_mask Interrupt bitmask. See ``adc_digi_intr_t``.
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*
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* @return
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* - ESP_OK Success
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*/
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esp_err_t adc_digi_intr_enable(adc_unit_t adc_unit, adc_digi_intr_t intr_mask);
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/**
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* @brief Disable interrupt of adc digital controller by bitmask.
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*
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* @param adc_unit ADC unit.
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* @param intr_mask Interrupt bitmask. See ``adc_digi_intr_t``.
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*
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* @return
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* - ESP_OK Success
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*/
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esp_err_t adc_digi_intr_disable(adc_unit_t adc_unit, adc_digi_intr_t intr_mask);
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/**
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* @brief Clear interrupt of adc digital controller by bitmask.
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*
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* @param adc_unit ADC unit.
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* @param intr_mask Interrupt bitmask. See ``adc_digi_intr_t``.
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*
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* @return
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* - ESP_OK Success
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*/
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esp_err_t adc_digi_intr_clear(adc_unit_t adc_unit, adc_digi_intr_t intr_mask);
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/**
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* @brief Get interrupt status mask of adc digital controller.
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*
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* @param adc_unit ADC unit.
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* @return
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* - intr Interrupt bitmask, See ``adc_digi_intr_t``.
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*/
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uint32_t adc_digi_intr_get_status(adc_unit_t adc_unit);
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/**
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* @brief Register ADC interrupt handler, the handler is an ISR.
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* The handler will be attached to the same CPU core that this function is running on.
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*
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* @param fn Interrupt handler function.
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* @param arg Parameter for handler function
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* @param intr_alloc_flags Flags used to allocate the interrupt. One or multiple (ORred)
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* ESP_INTR_FLAG_* values. See esp_intr_alloc.h for more info.
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*
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* @return
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* - ESP_OK Success
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* - ESP_ERR_NOT_FOUND Can not find the interrupt that matches the flags.
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* - ESP_ERR_INVALID_ARG Function pointer error.
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*/
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esp_err_t adc_digi_isr_register(void (*fn)(void *), void *arg, int intr_alloc_flags);
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/**
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* @brief Deregister ADC interrupt handler, the handler is an ISR.
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*
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* @return
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* - ESP_OK Success
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* - ESP_ERR_INVALID_ARG hander error.
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* - ESP_FAIL ISR not be registered.
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*/
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esp_err_t adc_digi_isr_deregister(void);
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#ifdef __cplusplus
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}
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#endif
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// This file will be removed. TODO: IDF-1776
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@ -48,8 +48,6 @@ void adc_hal_init(void)
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ADC calibration setting
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---------------------------------------------------------------*/
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#if SOC_ADC_HW_CALIBRATION_V1
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// ESP32-S2 and C3 support HW offset calibration.
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void adc_hal_calibration_init(adc_ll_num_t adc_n)
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{
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adc_ll_calibration_init(adc_n);
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@ -94,7 +92,7 @@ static void cal_setup(adc_ll_num_t adc_n, adc_channel_t channel, adc_atten_t att
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adc_ll_onetime_sample_enable(ADC_NUM_2, false);
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/* Enable/disable internal connect GND (for calibration). */
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if (internal_gnd) {
|
||||
const int esp32c3_invalid_chan = (adc_n == ADC_NUM_1)? 0xF: 0x1;
|
||||
const int esp32c3_invalid_chan = (adc_n == ADC_NUM_1) ? 0xF : 0x1;
|
||||
adc_ll_onetime_set_channel(adc_n, esp32c3_invalid_chan);
|
||||
} else {
|
||||
adc_ll_onetime_set_channel(adc_n, channel);
|
||||
|
|
@ -110,7 +108,7 @@ static uint32_t read_cal_channel(adc_ll_num_t adc_n, int channel)
|
|||
esp_rom_delay_us(5);
|
||||
adc_ll_onetime_start(true);
|
||||
|
||||
while(!adc_ll_intr_get_raw(ADC_LL_INTR_ADC1_DONE | ADC_LL_INTR_ADC2_DONE));
|
||||
while (!adc_ll_intr_get_raw(ADC_LL_INTR_ADC1_DONE | ADC_LL_INTR_ADC2_DONE));
|
||||
|
||||
uint32_t read_val = -1;
|
||||
if (adc_n == ADC_NUM_1) {
|
||||
|
|
@ -179,8 +177,8 @@ uint32_t adc_hal_self_calibration(adc_ll_num_t adc_n, adc_channel_t channel, adc
|
|||
|
||||
chk_code = code_h + code_l;
|
||||
uint32_t ret = ((code_sum - chk_code) % (ADC_HAL_CAL_TIMES - 2) < 4)
|
||||
? (code_sum - chk_code) / (ADC_HAL_CAL_TIMES - 2)
|
||||
: (code_sum - chk_code) / (ADC_HAL_CAL_TIMES - 2) + 1;
|
||||
? (code_sum - chk_code) / (ADC_HAL_CAL_TIMES - 2)
|
||||
: (code_sum - chk_code) / (ADC_HAL_CAL_TIMES - 2) + 1;
|
||||
|
||||
adc_ll_calibration_finish(adc_n);
|
||||
return ret;
|
||||
|
|
@ -227,11 +225,11 @@ static void adc_hal_digi_dma_link_descriptors(dma_descriptor_t *desc, uint8_t *d
|
|||
desc[n].dw0.suc_eof = 0;
|
||||
desc[n].dw0.owner = 1;
|
||||
desc[n].buffer = data_buf;
|
||||
desc[n].next = &desc[n+1];
|
||||
desc[n].next = &desc[n + 1];
|
||||
data_buf += size;
|
||||
n++;
|
||||
}
|
||||
desc[n-1].next = NULL;
|
||||
desc[n - 1].next = NULL;
|
||||
}
|
||||
|
||||
void adc_hal_digi_rxdma_start(adc_hal_context_t *hal, uint8_t *data_buf)
|
||||
|
|
@ -334,7 +332,7 @@ static void adc_hal_onetime_start(void)
|
|||
//3 ADC digital controller clock cycle
|
||||
delay = delay * 3;
|
||||
//This coefficient (8) is got from test. When digi_clk is not smaller than ``APB_CLK_FREQ/8``, no delay is needed.
|
||||
if (digi_clk >= APB_CLK_FREQ/8) {
|
||||
if (digi_clk >= APB_CLK_FREQ / 8) {
|
||||
delay = 0;
|
||||
}
|
||||
|
||||
|
|
@ -352,7 +350,7 @@ static esp_err_t adc_hal_single_read(adc_ll_num_t adc_n, int *out_raw)
|
|||
*out_raw = adc_ll_adc2_read();
|
||||
if (adc_ll_analysis_raw_data(adc_n, *out_raw)) {
|
||||
return ESP_ERR_INVALID_STATE;
|
||||
}
|
||||
}
|
||||
}
|
||||
return ESP_OK;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,256 +0,0 @@
|
|||
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
/*******************************************************************************
|
||||
* NOTICE
|
||||
* The hal is not public api, don't use in application code.
|
||||
* See readme.md in hal/include/hal/readme.md
|
||||
******************************************************************************/
|
||||
|
||||
// The HAL layer for ADC (esp32s3 specific part)
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "hal/adc_ll.h"
|
||||
#include "hal/adc_types.h"
|
||||
|
||||
#include_next "hal/adc_hal.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
Digital controller setting
|
||||
---------------------------------------------------------------*/
|
||||
/**
|
||||
* Digital controller deinitialization.
|
||||
*/
|
||||
void adc_hal_digi_deinit(void);
|
||||
|
||||
/**
|
||||
* Setting the digital controller.
|
||||
*
|
||||
* @param cfg Pointer to digital controller paramter.
|
||||
*/
|
||||
void adc_hal_digi_controller_config(const adc_digi_config_t *cfg);
|
||||
|
||||
/**
|
||||
* ADC Digital controller output data invert or not.
|
||||
*
|
||||
* @param adc_n ADC unit.
|
||||
* @param inv_en data invert or not.
|
||||
*/
|
||||
#define adc_hal_digi_output_invert(adc_n, inv_en) adc_ll_digi_output_invert(adc_n, inv_en)
|
||||
|
||||
/**
|
||||
* Sets the number of interval clock cycles for the digital controller to trigger the measurement.
|
||||
*
|
||||
* @note The trigger interval should not be less than the sampling time of the SAR ADC.
|
||||
* @param cycle The number of clock cycles for the trigger interval. The unit is the divided clock. Range: 40 ~ 4095.
|
||||
*/
|
||||
#define adc_hal_digi_set_trigger_interval(cycle) adc_ll_digi_set_trigger_interval(cycle)
|
||||
|
||||
/**
|
||||
* Enable digital controller to trigger the measurement.
|
||||
*/
|
||||
void adc_hal_digi_enable(void);
|
||||
|
||||
/**
|
||||
* Disable digital controller to trigger the measurement.
|
||||
*/
|
||||
void adc_hal_digi_disable(void);
|
||||
|
||||
/**
|
||||
* Set ADC digital controller clock division factor. The clock divided from `APLL` or `APB` clock.
|
||||
* Enable clock and select clock source for ADC digital controller.
|
||||
* Expression: controller_clk = APLL/APB * (div_num + div_b / div_a).
|
||||
*
|
||||
* @param clk Refer to `adc_digi_clk_t`.
|
||||
*/
|
||||
void adc_hal_digi_clk_config(const adc_digi_clk_t *clk);
|
||||
|
||||
/**
|
||||
* Reset adc digital controller filter.
|
||||
*
|
||||
* @param adc_n ADC unit.
|
||||
*/
|
||||
#define adc_hal_digi_filter_reset(adc_n) adc_ll_digi_filter_reset(adc_n)
|
||||
|
||||
/**
|
||||
* Set adc digital controller filter factor.
|
||||
*
|
||||
* @param adc_n ADC unit.
|
||||
* @param factor Expression: filter_data = (k-1)/k * last_data + new_data / k. Set values: (2, 4, 8, 16, 64).
|
||||
*/
|
||||
#define adc_hal_digi_filter_set_factor(adc_n, factor) adc_ll_digi_filter_set_factor(adc_n, factor)
|
||||
|
||||
/**
|
||||
* Get adc digital controller filter factor.
|
||||
*
|
||||
* @param adc_n ADC unit.
|
||||
* @param factor Expression: filter_data = (k-1)/k * last_data + new_data / k. Set values: (2, 4, 8, 16, 64).
|
||||
*/
|
||||
#define adc_hal_digi_filter_get_factor(adc_n, factor) adc_ll_digi_filter_get_factor(adc_n, factor)
|
||||
|
||||
/**
|
||||
* Enable/disable adc digital controller filter.
|
||||
* Filtering the ADC data to obtain smooth data at higher sampling rates.
|
||||
*
|
||||
* @note The filter will filter all the enabled channel data of the each ADC unit at the same time.
|
||||
* @param adc_n ADC unit.
|
||||
*/
|
||||
#define adc_hal_digi_filter_enable(adc_n, enable) adc_ll_digi_filter_enable(adc_n, enable)
|
||||
|
||||
/**
|
||||
* Get the filtered data of adc digital controller filter.
|
||||
* The data after each measurement and filtering is updated to the DMA by the digital controller. But it can also be obtained manually through this API.
|
||||
*
|
||||
* @note The filter will filter all the enabled channel data of the each ADC unit at the same time.
|
||||
* @param adc_n ADC unit.
|
||||
* @return Filtered data.
|
||||
*/
|
||||
#define adc_hal_digi_filter_read_data(adc_n) adc_ll_digi_filter_read_data(adc_n)
|
||||
|
||||
/**
|
||||
* Config monitor of adc digital controller.
|
||||
*
|
||||
* @note The monitor will monitor all the enabled channel data of the each ADC unit at the same time.
|
||||
* @param adc_n ADC unit.
|
||||
* @param config Refer to `adc_digi_monitor_t`.
|
||||
*/
|
||||
void adc_hal_digi_monitor_config(adc_ll_num_t adc_n, adc_digi_monitor_t *config);
|
||||
|
||||
/**
|
||||
* Enable/disable monitor of adc digital controller.
|
||||
*
|
||||
* @note The monitor will monitor all the enabled channel data of the each ADC unit at the same time.
|
||||
* @param adc_n ADC unit.
|
||||
*/
|
||||
#define adc_hal_digi_monitor_enable(adc_n, enable) adc_ll_digi_monitor_enable(adc_n, enable)
|
||||
|
||||
/**
|
||||
* Enable interrupt of adc digital controller by bitmask.
|
||||
*
|
||||
* @param adc_n ADC unit.
|
||||
* @param intr Interrupt bitmask.
|
||||
*/
|
||||
#define adc_hal_digi_intr_enable(adc_n, intr) adc_ll_digi_intr_enable(adc_n, intr)
|
||||
|
||||
/**
|
||||
* Disable interrupt of adc digital controller by bitmask.
|
||||
*
|
||||
* @param adc_n ADC unit.
|
||||
* @param intr Interrupt bitmask.
|
||||
*/
|
||||
#define adc_hal_digi_intr_disable(adc_n, intr) adc_ll_digi_intr_disable(adc_n, intr)
|
||||
|
||||
/**
|
||||
* Clear interrupt of adc digital controller by bitmask.
|
||||
*
|
||||
* @param adc_n ADC unit.
|
||||
* @param intr Interrupt bitmask.
|
||||
*/
|
||||
#define adc_hal_digi_intr_clear(adc_n, intr) adc_ll_digi_intr_clear(adc_n, intr)
|
||||
|
||||
/**
|
||||
* Get interrupt status mask of adc digital controller.
|
||||
*
|
||||
* @param adc_n ADC unit.
|
||||
* @return
|
||||
* - intr Interrupt bitmask.
|
||||
*/
|
||||
#define adc_hal_digi_get_intr_status(adc_n) adc_ll_digi_get_intr_status(adc_n)
|
||||
|
||||
|
||||
/**
|
||||
* Set DMA eof num of adc digital controller.
|
||||
* If the number of measurements reaches `dma_eof_num`, then `dma_in_suc_eof` signal is generated.
|
||||
*
|
||||
* @param num eof num of DMA.
|
||||
*/
|
||||
#define adc_hal_digi_dma_set_eof_num(num) adc_ll_digi_dma_set_eof_num(num)
|
||||
|
||||
/**
|
||||
* Enable output data to DMA from adc digital controller.
|
||||
*/
|
||||
#define adc_hal_digi_dma_enable() adc_ll_digi_dma_enable()
|
||||
|
||||
/**
|
||||
* Disable output data to DMA from adc digital controller.
|
||||
*/
|
||||
#define adc_hal_digi_dma_disable() adc_ll_digi_dma_disable()
|
||||
|
||||
/**
|
||||
* Reset adc digital controller.
|
||||
*/
|
||||
#define adc_hal_digi_reset() adc_ll_digi_reset()
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
RTC controller setting
|
||||
---------------------------------------------------------------*/
|
||||
/**
|
||||
* Reset RTC controller FSM.
|
||||
*/
|
||||
#define adc_hal_rtc_reset() adc_ll_rtc_reset()
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
Common setting
|
||||
---------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* Config ADC2 module arbiter.
|
||||
* The arbiter is to improve the use efficiency of ADC2. After the control right is robbed by the high priority,
|
||||
* the low priority controller will read the invalid ADC2 data, and the validity of the data can be judged by the flag bit in the data.
|
||||
*
|
||||
* @note Only ADC2 support arbiter.
|
||||
* @note The arbiter's working clock is APB_CLK. When the APB_CLK clock drops below 8 MHz, the arbiter must be in shield mode.
|
||||
* @note Default priority: Wi-Fi > RTC > Digital;
|
||||
*
|
||||
* @param config Refer to `adc_arbiter_t`.
|
||||
*/
|
||||
void adc_hal_arbiter_config(adc_arbiter_t *config);
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
ADC calibration setting
|
||||
---------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* Calibrate the ADC using internal connections.
|
||||
*
|
||||
* @note Different ADC units and different attenuation options use different calibration data (initial data).
|
||||
*
|
||||
* @param adc_n ADC index number.
|
||||
* @param channel adc channel number.
|
||||
* @param atten The attenuation for the channel
|
||||
* @param internal_gnd true: Disconnect from the IO port and use the internal GND as the calibration voltage.
|
||||
* false: Use IO external voltage as calibration voltage.
|
||||
*
|
||||
* @return
|
||||
* - The calibration result (initial data) to ADC, use `adc_hal_set_calibration_param` to set.
|
||||
*/
|
||||
uint32_t adc_hal_self_calibration(adc_ll_num_t adc_n, adc_channel_t channel, adc_atten_t atten, bool internal_gnd);
|
||||
|
||||
/**
|
||||
* Set the calibration result (initial data) to ADC.
|
||||
*
|
||||
* @note Different ADC units and different attenuation options use different calibration data (initial data).
|
||||
*
|
||||
* @param adc_n ADC index number.
|
||||
*/
|
||||
#define adc_hal_set_calibration_param(adc_n, param) adc_ll_set_calibration_param(adc_n, param);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -57,22 +57,6 @@ typedef enum {
|
|||
ADC_LL_CTRL_ARB = 4, ///< For ADC2. The controller is selected by the arbiter.
|
||||
} adc_ll_controller_t;
|
||||
|
||||
/**
|
||||
* @brief ADC digital controller (DMA mode) work mode.
|
||||
*
|
||||
* @note The conversion mode affects the sampling frequency:
|
||||
* SINGLE_UNIT_1: When the measurement is triggered, only ADC1 is sampled once.
|
||||
* SINGLE_UNIT_2: When the measurement is triggered, only ADC2 is sampled once.
|
||||
* BOTH_UNIT : When the measurement is triggered, ADC1 and ADC2 are sampled at the same time.
|
||||
* ALTER_UNIT : When the measurement is triggered, ADC1 or ADC2 samples alternately.
|
||||
*/
|
||||
typedef enum {
|
||||
ADC_LL_DIGI_CONV_ONLY_ADC1 = 0, // Only use ADC1 for conversion
|
||||
ADC_LL_DIGI_CONV_ONLY_ADC2 = 1, // Only use ADC2 for conversion
|
||||
ADC_LL_DIGI_CONV_BOTH_UNIT = 2, // Use Both ADC1 and ADC2 for conversion simultaneously
|
||||
ADC_LL_DIGI_CONV_ALTER_UNIT = 3 // Use both ADC1 and ADC2 for conversion by turn. e.g. ADC1 -> ADC2 -> ADC1 -> ADC2 .....
|
||||
} adc_ll_digi_convert_mode_t;
|
||||
|
||||
typedef struct {
|
||||
union {
|
||||
struct {
|
||||
|
|
@ -96,8 +80,8 @@ typedef struct {
|
|||
typedef struct {
|
||||
union {
|
||||
struct {
|
||||
uint16_t data: 13; /*!<ADC real output data info. Resolution: 13 bit. */
|
||||
uint16_t reserved: 1; /*!<reserved */
|
||||
uint16_t data: 12; /*!<ADC real output data info. Resolution: 13 bit. */
|
||||
uint16_t reserved: 2; /*!<reserved */
|
||||
uint16_t flag: 2; /*!<ADC data flag info.
|
||||
If (flag == 0), The data is valid.
|
||||
If (flag > 0), The data is invalid. */
|
||||
|
|
@ -142,6 +126,7 @@ static inline void adc_ll_digi_set_fsm_time(uint32_t rst_wait, uint32_t start_wa
|
|||
static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle)
|
||||
{
|
||||
//To be added including RTC_CNTR reg and functions
|
||||
abort();
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -192,17 +177,17 @@ static inline void adc_ll_digi_convert_limit_disable(void)
|
|||
*
|
||||
* @param mode Conversion mode select.
|
||||
*/
|
||||
static inline void adc_ll_digi_set_convert_mode(adc_ll_digi_convert_mode_t mode)
|
||||
static inline void adc_ll_digi_set_convert_mode(adc_digi_convert_mode_t mode)
|
||||
{
|
||||
if (mode == ADC_LL_DIGI_CONV_ONLY_ADC1) {
|
||||
if (mode == ADC_CONV_SINGLE_UNIT_1) {
|
||||
APB_SARADC.ctrl.work_mode = 0;
|
||||
APB_SARADC.ctrl.sar_sel = 0;
|
||||
} else if (mode == ADC_LL_DIGI_CONV_ONLY_ADC2) {
|
||||
} else if (mode == ADC_CONV_SINGLE_UNIT_2) {
|
||||
APB_SARADC.ctrl.work_mode = 0;
|
||||
APB_SARADC.ctrl.sar_sel = 1;
|
||||
} else if (mode == ADC_LL_DIGI_CONV_BOTH_UNIT) {
|
||||
} else if (mode == ADC_CONV_BOTH_UNIT) {
|
||||
APB_SARADC.ctrl.work_mode = 1;
|
||||
} else if (mode == ADC_LL_DIGI_CONV_ALTER_UNIT) {
|
||||
} else if (mode == ADC_CONV_ALTER_UNIT) {
|
||||
APB_SARADC.ctrl.work_mode = 2;
|
||||
}
|
||||
APB_SARADC.ctrl.data_sar_sel = 1;
|
||||
|
|
@ -238,23 +223,7 @@ static inline void adc_ll_digi_set_pattern_table_len(adc_ll_num_t adc_n, uint32_
|
|||
*/
|
||||
static inline void adc_ll_digi_set_pattern_table(adc_ll_num_t adc_n, uint32_t pattern_index, adc_digi_pattern_table_t table)
|
||||
{
|
||||
uint32_t tab;
|
||||
uint8_t index = pattern_index / 4;
|
||||
uint8_t offset = (pattern_index % 4) * 6;
|
||||
adc_ll_digi_pattern_table_t pattern = {0};
|
||||
|
||||
pattern.val = (table.atten & 0x3) | ((table.channel & 0xF) << 2);
|
||||
if (table.unit == ADC_NUM_1){
|
||||
tab = APB_SARADC.sar1_patt_tab[index].sar1_patt_tab; //Read old register value
|
||||
tab &= (~(0xFC0000 >> offset)); //Clear old data
|
||||
tab |= ((uint32_t)(pattern.val & 0x3F) << 18) >> offset; //Fill in the new data
|
||||
APB_SARADC.sar1_patt_tab[index].sar1_patt_tab = tab; //Write back
|
||||
} else {
|
||||
tab = APB_SARADC.sar2_patt_tab[index].sar2_patt_tab; //Read old register value
|
||||
tab &= (~(0xFC0000 >> offset)); //clear old data
|
||||
tab |= ((uint32_t)(pattern.val & 0x3F) << 18) >> offset; //Fill in the new data
|
||||
APB_SARADC.sar2_patt_tab[index].sar2_patt_tab = tab; //Write back
|
||||
}
|
||||
abort();
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -377,13 +346,26 @@ static inline void adc_ll_digi_filter_reset(adc_ll_num_t adc_n)
|
|||
abort();
|
||||
}
|
||||
|
||||
/**
|
||||
* Disable adc digital controller filter.
|
||||
* Filtering the ADC data to obtain smooth data at higher sampling rates.
|
||||
*
|
||||
* @note If the channel info is not supported, the filter function will not be enabled.
|
||||
* @param adc_n ADC unit.
|
||||
*/
|
||||
static inline void adc_ll_digi_filter_disable(adc_digi_filter_idx_t idx)
|
||||
{
|
||||
abort();
|
||||
}
|
||||
|
||||
/**
|
||||
* Set adc digital controller filter factor.
|
||||
*
|
||||
* @param adc_n ADC unit.
|
||||
* @param factor Expression: filter_data = (k-1)/k * last_data + new_data / k. Set values: (2, 4, 8, 16, 64).
|
||||
* @note If the channel info is not supported, the filter function will not be enabled.
|
||||
* @param idx ADC filter unit.
|
||||
* @param filter Filter config. Expression: filter_data = (k-1)/k * last_data + new_data / k. Set values: (2, 4, 8, 16, 64).
|
||||
*/
|
||||
static inline void adc_ll_digi_filter_set_factor(adc_ll_num_t adc_n, adc_digi_filter_mode_t factor)
|
||||
static inline void adc_ll_digi_filter_set_factor(adc_digi_filter_idx_t idx, adc_digi_filter_t *filter)
|
||||
{
|
||||
abort();
|
||||
}
|
||||
|
|
@ -394,19 +376,7 @@ static inline void adc_ll_digi_filter_set_factor(adc_ll_num_t adc_n, adc_digi_fi
|
|||
* @param adc_n ADC unit.
|
||||
* @param factor Expression: filter_data = (k-1)/k * last_data + new_data / k. Set values: (2, 4, 8, 16, 64).
|
||||
*/
|
||||
static inline void adc_ll_digi_filter_get_factor(adc_ll_num_t adc_n, adc_digi_filter_mode_t *factor)
|
||||
{
|
||||
abort();
|
||||
}
|
||||
|
||||
/**
|
||||
* Enable/disable adc digital controller filter.
|
||||
* Filtering the ADC data to obtain smooth data at higher sampling rates.
|
||||
*
|
||||
* @note The filter will filter all the enabled channel data of the each ADC unit at the same time.
|
||||
* @param adc_n ADC unit.
|
||||
*/
|
||||
static inline void adc_ll_digi_filter_enable(adc_ll_num_t adc_n, bool enable)
|
||||
static inline void adc_ll_digi_filter_get_factor(adc_digi_filter_idx_t idx, adc_digi_filter_t *filter)
|
||||
{
|
||||
abort();
|
||||
}
|
||||
|
|
@ -432,11 +402,23 @@ static inline uint32_t adc_ll_digi_filter_read_data(adc_ll_num_t adc_n)
|
|||
* @param is_larger true: If ADC_OUT > threshold, Generates monitor interrupt.
|
||||
* false: If ADC_OUT < threshold, Generates monitor interrupt.
|
||||
*/
|
||||
static inline void adc_ll_digi_monitor_set_mode(adc_ll_num_t adc_n, bool is_larger)
|
||||
static inline void adc_ll_digi_monitor_set_mode(adc_digi_monitor_idx_t idx, adc_digi_monitor_t *cfg)
|
||||
{
|
||||
abort();
|
||||
}
|
||||
|
||||
/**
|
||||
* Enable/disable monitor of adc digital controller.
|
||||
*
|
||||
* @note If the channel info is not supported, the monitor function will not be enabled.
|
||||
* @param adc_n ADC unit.
|
||||
*/
|
||||
static inline void adc_ll_digi_monitor_disable(adc_digi_monitor_idx_t idx)
|
||||
{
|
||||
abort();
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* Set monitor threshold of adc digital controller.
|
||||
*
|
||||
|
|
@ -523,6 +505,30 @@ static inline uint32_t adc_ll_pwdet_get_cct(void)
|
|||
return SENS.sar_meas2_mux.sar2_pwdet_cct;
|
||||
}
|
||||
|
||||
/**
|
||||
* Analyze whether the obtained raw data is correct.
|
||||
* ADC2 can use arbiter. The arbitration result is stored in the channel information of the returned data.
|
||||
*
|
||||
* @param adc_n ADC unit.
|
||||
* @param raw_data ADC raw data input (convert value).
|
||||
* @return
|
||||
* - 0: The data is correct to use.
|
||||
* - -1: The data is invalid.
|
||||
*/
|
||||
static inline adc_ll_rtc_raw_data_t adc_ll_analysis_raw_data(adc_ll_num_t adc_n, int raw_data)
|
||||
{
|
||||
if (adc_n == ADC_NUM_1) {
|
||||
return ADC_RTC_DATA_OK;
|
||||
}
|
||||
|
||||
//The raw data API returns value without channel information. Read value directly from the register
|
||||
if (((APB_SARADC.apb_saradc2_data_status.adc2_data >> 12) & 0xF) > 9) {
|
||||
return ADC_RTC_DATA_FAIL;
|
||||
}
|
||||
|
||||
return ADC_RTC_DATA_OK;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
Common setting
|
||||
---------------------------------------------------------------*/
|
||||
|
|
@ -534,12 +540,18 @@ static inline uint32_t adc_ll_pwdet_get_cct(void)
|
|||
static inline void adc_ll_set_power_manage(adc_ll_power_t manage)
|
||||
{
|
||||
if (manage == ADC_POWER_SW_ON) {
|
||||
SENS.sar_peri_clk_gate_conf.saradc_clk_en = 1;
|
||||
SENS.sar_power_xpd_sar.force_xpd_sar = 3; //SENS_FORCE_XPD_SAR_PU;
|
||||
APB_SARADC.ctrl.sar_clk_gated = 1;
|
||||
APB_SARADC.ctrl.xpd_sar_force = 3;
|
||||
} else if (manage == ADC_POWER_BY_FSM) {
|
||||
SENS.sar_peri_clk_gate_conf.saradc_clk_en = 1;
|
||||
SENS.sar_power_xpd_sar.force_xpd_sar = 0; //SENS_FORCE_XPD_SAR_FSM;
|
||||
APB_SARADC.ctrl.sar_clk_gated = 1;
|
||||
APB_SARADC.ctrl.xpd_sar_force = 0;
|
||||
} else if (manage == ADC_POWER_SW_OFF) {
|
||||
SENS.sar_power_xpd_sar.force_xpd_sar = 2; //SENS_FORCE_XPD_SAR_PD;
|
||||
SENS.sar_peri_clk_gate_conf.saradc_clk_en = 0;
|
||||
APB_SARADC.ctrl.sar_clk_gated = 0;
|
||||
APB_SARADC.ctrl.xpd_sar_force = 2;
|
||||
}
|
||||
|
|
@ -559,37 +571,37 @@ static inline void adc_ll_set_controller(adc_ll_num_t adc_n, adc_ll_controller_t
|
|||
{
|
||||
if (adc_n == ADC_NUM_1) {
|
||||
switch (ctrl) {
|
||||
case ADC_LL_CTRL_RTC:
|
||||
SENS.sar_meas1_mux.sar1_dig_force = 0; // 1: Select digital control; 0: Select RTC control.
|
||||
SENS.sar_meas1_ctrl2.meas1_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
|
||||
SENS.sar_meas1_ctrl2.sar1_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
|
||||
break;
|
||||
case ADC_LL_CTRL_ULP:
|
||||
SENS.sar_meas1_mux.sar1_dig_force = 0; // 1: Select digital control; 0: Select RTC control.
|
||||
SENS.sar_meas1_ctrl2.meas1_start_force = 0; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
|
||||
SENS.sar_meas1_ctrl2.sar1_en_pad_force = 0; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
|
||||
break;
|
||||
case ADC_LL_CTRL_DIG:
|
||||
SENS.sar_meas1_mux.sar1_dig_force = 1; // 1: Select digital control; 0: Select RTC control.
|
||||
SENS.sar_meas1_ctrl2.meas1_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
|
||||
SENS.sar_meas1_ctrl2.sar1_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
case ADC_LL_CTRL_RTC:
|
||||
SENS.sar_meas1_mux.sar1_dig_force = 0; // 1: Select digital control; 0: Select RTC control.
|
||||
SENS.sar_meas1_ctrl2.meas1_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
|
||||
SENS.sar_meas1_ctrl2.sar1_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
|
||||
break;
|
||||
case ADC_LL_CTRL_ULP:
|
||||
SENS.sar_meas1_mux.sar1_dig_force = 0; // 1: Select digital control; 0: Select RTC control.
|
||||
SENS.sar_meas1_ctrl2.meas1_start_force = 0; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
|
||||
SENS.sar_meas1_ctrl2.sar1_en_pad_force = 0; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
|
||||
break;
|
||||
case ADC_LL_CTRL_DIG:
|
||||
SENS.sar_meas1_mux.sar1_dig_force = 1; // 1: Select digital control; 0: Select RTC control.
|
||||
SENS.sar_meas1_ctrl2.meas1_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
|
||||
SENS.sar_meas1_ctrl2.sar1_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
} else { // adc_n == ADC_NUM_2
|
||||
//If ADC2 is not controlled by ULP, the arbiter will decide which controller to use ADC2.
|
||||
switch (ctrl) {
|
||||
case ADC_LL_CTRL_ARB:
|
||||
SENS.sar_meas2_ctrl2.meas2_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
|
||||
SENS.sar_meas2_ctrl2.sar2_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
|
||||
break;
|
||||
case ADC_LL_CTRL_ULP:
|
||||
SENS.sar_meas2_ctrl2.meas2_start_force = 0; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
|
||||
SENS.sar_meas2_ctrl2.sar2_en_pad_force = 0; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
case ADC_LL_CTRL_ARB:
|
||||
SENS.sar_meas2_ctrl2.meas2_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
|
||||
SENS.sar_meas2_ctrl2.sar2_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
|
||||
break;
|
||||
case ADC_LL_CTRL_ULP:
|
||||
SENS.sar_meas2_ctrl2.meas2_start_force = 0; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
|
||||
SENS.sar_meas2_ctrl2.sar2_en_pad_force = 0; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -752,19 +764,23 @@ static inline void adc_ll_vref_output(adc_ll_num_t adc, adc_channel_t channel, b
|
|||
*/
|
||||
static inline void adc_ll_set_sar_clk_div(adc_ll_num_t adc_n, uint32_t div)
|
||||
{
|
||||
abort();
|
||||
if (adc_n == ADC_NUM_1) {
|
||||
SENS.sar_reader1_ctrl.sar1_clk_div = div;
|
||||
} else { // adc_n == ADC_NUM_2
|
||||
SENS.sar_reader2_ctrl.sar2_clk_div = div;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Set adc output data format for RTC controller.
|
||||
*
|
||||
* @note ESP32S2 RTC controller only support 13bit.
|
||||
* @note ESP32S3 RTC controller only support 13bit.
|
||||
* @prarm adc_n ADC unit.
|
||||
* @prarm bits Output data bits width option.
|
||||
*/
|
||||
static inline void adc_ll_rtc_set_output_format(adc_ll_num_t adc_n, adc_bits_width_t bits)
|
||||
{
|
||||
abort();
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -777,7 +793,11 @@ static inline void adc_ll_rtc_set_output_format(adc_ll_num_t adc_n, adc_bits_wid
|
|||
*/
|
||||
static inline void adc_ll_rtc_enable_channel(adc_ll_num_t adc_n, int channel)
|
||||
{
|
||||
abort();
|
||||
if (adc_n == ADC_NUM_1) {
|
||||
SENS.sar_meas1_ctrl2.sar1_en_pad = (1 << channel); //only one channel is selected.
|
||||
} else { // adc_n == ADC_NUM_2
|
||||
SENS.sar_meas2_ctrl2.sar2_en_pad = (1 << channel); //only one channel is selected.
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -790,7 +810,11 @@ static inline void adc_ll_rtc_enable_channel(adc_ll_num_t adc_n, int channel)
|
|||
*/
|
||||
static inline void adc_ll_rtc_disable_channel(adc_ll_num_t adc_n)
|
||||
{
|
||||
abort();
|
||||
if (adc_n == ADC_NUM_1) {
|
||||
SENS.sar_meas1_ctrl2.sar1_en_pad = 0; //only one channel is selected.
|
||||
} else { // adc_n == ADC_NUM_2
|
||||
SENS.sar_meas2_ctrl2.sar2_en_pad = 0; //only one channel is selected.
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -803,7 +827,14 @@ static inline void adc_ll_rtc_disable_channel(adc_ll_num_t adc_n)
|
|||
*/
|
||||
static inline void adc_ll_rtc_start_convert(adc_ll_num_t adc_n, int channel)
|
||||
{
|
||||
abort();
|
||||
if (adc_n == ADC_NUM_1) {
|
||||
while (SENS.sar_slave_addr1.meas_status != 0);
|
||||
SENS.sar_meas1_ctrl2.meas1_start_sar = 0;
|
||||
SENS.sar_meas1_ctrl2.meas1_start_sar = 1;
|
||||
} else { // adc_n == ADC_NUM_2
|
||||
SENS.sar_meas2_ctrl2.meas2_start_sar = 0; //start force 0
|
||||
SENS.sar_meas2_ctrl2.meas2_start_sar = 1; //start force 1
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -816,7 +847,13 @@ static inline void adc_ll_rtc_start_convert(adc_ll_num_t adc_n, int channel)
|
|||
*/
|
||||
static inline bool adc_ll_rtc_convert_is_done(adc_ll_num_t adc_n)
|
||||
{
|
||||
abort();
|
||||
bool ret = true;
|
||||
if (adc_n == ADC_NUM_1) {
|
||||
ret = (bool)SENS.sar_meas1_ctrl2.meas1_done_sar;
|
||||
} else { // adc_n == ADC_NUM_2
|
||||
ret = (bool)SENS.sar_meas2_ctrl2.meas2_done_sar;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -828,7 +865,13 @@ static inline bool adc_ll_rtc_convert_is_done(adc_ll_num_t adc_n)
|
|||
*/
|
||||
static inline int adc_ll_rtc_get_convert_value(adc_ll_num_t adc_n)
|
||||
{
|
||||
abort();
|
||||
int ret_val = 0;
|
||||
if (adc_n == ADC_NUM_1) {
|
||||
ret_val = SENS.sar_meas1_ctrl2.meas1_data_sar;
|
||||
} else { // adc_n == ADC_NUM_2
|
||||
ret_val = SENS.sar_meas2_ctrl2.meas2_data_sar;
|
||||
}
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -839,7 +882,11 @@ static inline int adc_ll_rtc_get_convert_value(adc_ll_num_t adc_n)
|
|||
*/
|
||||
static inline void adc_ll_rtc_output_invert(adc_ll_num_t adc_n, bool inv_en)
|
||||
{
|
||||
abort();
|
||||
if (adc_n == ADC_NUM_1) {
|
||||
SENS.sar_reader1_ctrl.sar1_data_inv = inv_en; // Enable / Disable ADC data invert
|
||||
} else { // adc_n == ADC_NUM_2
|
||||
SENS.sar_reader2_ctrl.sar2_data_inv = inv_en; // Enable / Disable ADC data invert
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -849,7 +896,13 @@ static inline void adc_ll_rtc_output_invert(adc_ll_num_t adc_n, bool inv_en)
|
|||
*/
|
||||
static inline void adc_ll_rtc_intr_enable(adc_ll_num_t adc_n)
|
||||
{
|
||||
abort();
|
||||
if (adc_n == ADC_NUM_1) {
|
||||
SENS.sar_reader1_ctrl.sar1_int_en = 1;
|
||||
RTCCNTL.int_ena.rtc_saradc1 = 1;
|
||||
} else { // adc_n == ADC_NUM_2
|
||||
SENS.sar_reader2_ctrl.sar2_int_en = 1;
|
||||
RTCCNTL.int_ena.rtc_saradc2 = 1;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -859,7 +912,13 @@ static inline void adc_ll_rtc_intr_enable(adc_ll_num_t adc_n)
|
|||
*/
|
||||
static inline void adc_ll_rtc_intr_disable(adc_ll_num_t adc_n)
|
||||
{
|
||||
abort();
|
||||
if (adc_n == ADC_NUM_1) {
|
||||
SENS.sar_reader1_ctrl.sar1_int_en = 0;
|
||||
RTCCNTL.int_ena.rtc_saradc1 = 0;
|
||||
} else { // adc_n == ADC_NUM_2
|
||||
SENS.sar_reader2_ctrl.sar2_int_en = 0;
|
||||
RTCCNTL.int_ena.rtc_saradc2 = 0;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -867,7 +926,8 @@ static inline void adc_ll_rtc_intr_disable(adc_ll_num_t adc_n)
|
|||
*/
|
||||
static inline void adc_ll_rtc_reset(void)
|
||||
{
|
||||
abort();
|
||||
SENS.sar_peri_reset_conf.saradc_reset = 1;
|
||||
SENS.sar_peri_reset_conf.saradc_reset = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -878,7 +938,7 @@ static inline void adc_ll_rtc_reset(void)
|
|||
*/
|
||||
static inline void adc_ll_rtc_set_arbiter_stable_cycle(uint32_t cycle)
|
||||
{
|
||||
abort();
|
||||
SENS.sar_reader2_ctrl.sar2_wait_arb_cycle = cycle;
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -895,7 +955,20 @@ static inline void adc_ll_rtc_set_arbiter_stable_cycle(uint32_t cycle)
|
|||
*/
|
||||
static inline adc_ll_rtc_raw_data_t adc_ll_rtc_analysis_raw_data(adc_ll_num_t adc_n, uint16_t raw_data)
|
||||
{
|
||||
abort();
|
||||
/* ADC1 don't need check data */
|
||||
if (adc_n == ADC_NUM_1) {
|
||||
return ADC_RTC_DATA_OK;
|
||||
}
|
||||
adc_ll_rtc_output_data_t *temp = (adc_ll_rtc_output_data_t *)&raw_data;
|
||||
if (temp->flag == 0) {
|
||||
return ADC_RTC_DATA_OK;
|
||||
} else if (temp->flag == 1) {
|
||||
return ADC_RTC_CTRL_UNSELECTED;
|
||||
} else if (temp->flag == 2) {
|
||||
return ADC_RTC_CTRL_BREAK;
|
||||
} else {
|
||||
return ADC_RTC_DATA_FAIL;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -933,9 +1006,24 @@ static inline adc_ll_rtc_raw_data_t adc_ll_rtc_analysis_raw_data(adc_ll_num_t ad
|
|||
*/
|
||||
static inline void adc_ll_set_atten(adc_ll_num_t adc_n, adc_channel_t channel, adc_atten_t atten)
|
||||
{
|
||||
abort();
|
||||
if (adc_n == ADC_NUM_1) {
|
||||
SENS.sar_atten1 = ( SENS.sar_atten1 & ~(0x3 << (channel * 2)) ) | ((atten & 0x3) << (channel * 2));
|
||||
} else { // adc_n == ADC_NUM_2
|
||||
SENS.sar_atten2 = ( SENS.sar_atten2 & ~(0x3 << (channel * 2)) ) | ((atten & 0x3) << (channel * 2));
|
||||
}
|
||||
}
|
||||
|
||||
static inline uint32_t adc_ll_adc1_read(void)
|
||||
{
|
||||
//On ESP32S3, valid data width is 12-bit
|
||||
return (APB_SARADC.apb_saradc1_data_status.adc1_data & 0xfff);
|
||||
}
|
||||
|
||||
static inline uint32_t adc_ll_adc2_read(void)
|
||||
{
|
||||
//On ESP32S3, valid data width is 12-bit
|
||||
return (APB_SARADC.apb_saradc2_data_status.adc2_data & 0xfff);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
|
|
|||
|
|
@ -133,7 +133,7 @@ typedef struct {
|
|||
- 2: 11 bit;
|
||||
- 3: 12 bit. */
|
||||
int8_t channel: 4; /*!< ADC channel index. */
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
uint8_t reserved: 2; /*!< reserved0 */
|
||||
uint8_t channel: 4; /*!< ADC channel index. */
|
||||
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
|
||||
|
|
@ -295,7 +295,7 @@ typedef struct {
|
|||
#endif
|
||||
} adc_digi_config_t;
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
|
||||
#if CONFIG_IDF_TARGET_ESP32S2
|
||||
/**
|
||||
* @brief ADC digital controller (DMA mode) interrupt type options.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -1,30 +0,0 @@
|
|||
// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#pragma once
|
||||
|
||||
#define SOC_ADC_PERIPH_NUM (2)
|
||||
#define SOC_ADC_PATT_LEN_MAX (16)
|
||||
#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (10)
|
||||
#define SOC_ADC_MAX_CHANNEL_NUM (10)
|
||||
#define SOC_ADC_MAX_BITWIDTH (13)
|
||||
|
||||
|
||||
/**
|
||||
* Check if adc support digital controller (DMA) mode.
|
||||
* @value
|
||||
* - 1 : support;
|
||||
* - 0 : not support;
|
||||
*/
|
||||
#define SOC_ADC_SUPPORT_DMA_MODE(PERIPH_NUM) ((PERIPH_NUM==0)? 1: 1)
|
||||
#define SOC_ADC_SUPPORT_RTC_CTRL 1
|
||||
|
|
@ -28,7 +28,12 @@
|
|||
|
||||
|
||||
/*-------------------------- ADC CAPS ----------------------------------------*/
|
||||
#include "adc_caps.h"
|
||||
#define SOC_ADC_PERIPH_NUM (2)
|
||||
#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (10)
|
||||
#define SOC_ADC_MAX_CHANNEL_NUM (10)
|
||||
#define SOC_ADC_MAX_BITWIDTH (12)
|
||||
#define SOC_ADC_SUPPORT_RTC_CTRL (1)
|
||||
|
||||
|
||||
/*-------------------------- BROWNOUT CAPS -----------------------------------*/
|
||||
#include "brownout_caps.h"
|
||||
|
|
|
|||
Ładowanie…
Reference in New Issue