refactor(esp_psram): reformat code with astyle_py

components/esp_psram/esp_psram.c

@@ -4,7 +4,6 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-
 /*----------------------------------------------------------------------------------------------------
  * Abstraction layer for PSRAM. PSRAM device related registers and MMU/Cache related code shouls be
  * abstracted to lower layers.
@@ -35,7 +34,6 @@
 #include "esp_private/esp_cache_esp32_private.h"
 #endif
 
-
 /**
  * Two types of PSRAM memory regions for now:
  * - 8bit aligned
@@ -84,12 +82,12 @@ typedef struct {
 static psram_ctx_t s_psram_ctx;
 static const char* TAG = "esp_psram";
 
-
 #if CONFIG_IDF_TARGET_ESP32
 //If no function in esp_himem.c is used, this function will be linked into the
 //binary instead of the one in esp_himem.c, automatically making sure no memory
 //is reserved if no himem function is used.
-size_t __attribute__((weak)) esp_himem_reserved_area_size(void) {
+size_t __attribute__((weak)) esp_himem_reserved_area_size(void)
+{
     return 0;
 }
 
@@ -105,7 +103,6 @@ static void IRAM_ATTR s_mapping(int v_start, int size)
 }
 #endif  //CONFIG_IDF_TARGET_ESP32
 
-
 esp_err_t esp_psram_init(void)
 {
     if (s_psram_ctx.is_initialised) {
@@ -301,12 +298,11 @@ esp_err_t esp_psram_init(void)
     return ESP_OK;
 }
 
-
 esp_err_t esp_psram_extram_add_to_heap_allocator(void)
 {
     esp_err_t ret = ESP_FAIL;
 
-    uint32_t byte_aligned_caps[] = {MALLOC_CAP_SPIRAM|MALLOC_CAP_DEFAULT, 0, MALLOC_CAP_8BIT|MALLOC_CAP_32BIT};
+    uint32_t byte_aligned_caps[] = {MALLOC_CAP_SPIRAM | MALLOC_CAP_DEFAULT, 0, MALLOC_CAP_8BIT | MALLOC_CAP_32BIT};
     ret = heap_caps_add_region_with_caps(byte_aligned_caps,
                                          s_psram_ctx.regions_to_heap[PSRAM_MEM_8BIT_ALIGNED].vaddr_start,
                                          s_psram_ctx.regions_to_heap[PSRAM_MEM_8BIT_ALIGNED].vaddr_end);
@@ -316,7 +312,7 @@ esp_err_t esp_psram_extram_add_to_heap_allocator(void)
 
     if (s_psram_ctx.regions_to_heap[PSRAM_MEM_32BIT_ALIGNED].size) {
         assert(s_psram_ctx.regions_to_heap[PSRAM_MEM_32BIT_ALIGNED].vaddr_start);
-        uint32_t word_aligned_caps[] = {MALLOC_CAP_SPIRAM|MALLOC_CAP_DEFAULT, 0, MALLOC_CAP_32BIT};
+        uint32_t word_aligned_caps[] = {MALLOC_CAP_SPIRAM | MALLOC_CAP_DEFAULT, 0, MALLOC_CAP_32BIT};
         ret = heap_caps_add_region_with_caps(word_aligned_caps,
                                              s_psram_ctx.regions_to_heap[PSRAM_MEM_32BIT_ALIGNED].vaddr_start,
                                              s_psram_ctx.regions_to_heap[PSRAM_MEM_32BIT_ALIGNED].vaddr_end);
@@ -331,7 +327,6 @@ esp_err_t esp_psram_extram_add_to_heap_allocator(void)
     return ESP_OK;
 }
 
-
 bool IRAM_ATTR esp_psram_check_ptr_addr(const void *p)
 {
     if (!s_psram_ctx.is_initialised) {
@@ -342,7 +337,6 @@ bool IRAM_ATTR esp_psram_check_ptr_addr(const void *p)
            ((intptr_t)p >= s_psram_ctx.mapped_regions[PSRAM_MEM_32BIT_ALIGNED].vaddr_start && (intptr_t)p < s_psram_ctx.mapped_regions[PSRAM_MEM_32BIT_ALIGNED].vaddr_end);
 }
 
-
 esp_err_t esp_psram_extram_reserve_dma_pool(size_t size)
 {
     if (size == 0) {
@@ -423,7 +417,7 @@ static bool s_test_psram(intptr_t v_start, size_t size, intptr_t reserved_start,
         }
     }
     if (errct) {
-        ESP_EARLY_LOGE(TAG, "SPI SRAM memory test fail. %d/%d writes failed, first @ %X\n", errct, size/32, initial_err + v_start);
+        ESP_EARLY_LOGE(TAG, "SPI SRAM memory test fail. %d/%d writes failed, first @ %X\n", errct, size / 32, initial_err + v_start);
         return false;
     } else {
         ESP_EARLY_LOGI(TAG, "SPI SRAM memory test OK");

components/esp_psram/mmu_psram_flash.c

@@ -43,7 +43,6 @@ static uint32_t page0_mapped = 0;
 static uint32_t page0_page = INVALID_PHY_PAGE;
 #endif  //#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS || CONFIG_SPIRAM_RODATA
 
-
 #if CONFIG_SPIRAM_FETCH_INSTRUCTIONS
 esp_err_t mmu_config_psram_text_segment(uint32_t start_page, uint32_t psram_size, uint32_t *out_page)
 {
@@ -87,7 +86,6 @@ esp_err_t mmu_config_psram_text_segment(uint32_t start_page, uint32_t psram_size
 }
 #endif  //#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS
 
-
 #if CONFIG_SPIRAM_RODATA
 esp_err_t mmu_config_psram_rodata_segment(uint32_t start_page, uint32_t psram_size, uint32_t *out_page)
 {
@@ -135,7 +133,6 @@ esp_err_t mmu_config_psram_rodata_segment(uint32_t start_page, uint32_t psram_si
 }
 #endif  //#if CONFIG_SPIRAM_RODATA
 
-
 /*----------------------------------------------------------------------------
                     Part 2 APIs (See @Backgrounds on top of this file)
 -------------------------------------------------------------------------------*/
@@ -196,7 +193,6 @@ uint32_t instruction_flash_end_page_get(void)
 }
 #endif  //CONFIG_SPIRAM_FETCH_INSTRUCTIONS
 
-
 #if CONFIG_SPIRAM_RODATA
 //------------------------------------Copy Flash .rodata to PSRAM-------------------------------------//
 static uint32_t rodata_in_spiram;
@@ -218,7 +214,7 @@ void rodata_flash_page_info_init(uint32_t psram_start_physical_page)
     uint32_t rodata_mmu_offset = ((uint32_t)&_rodata_reserved_start & SOC_MMU_VADDR_MASK) / MMU_PAGE_SIZE;
     rodata_start_page = ((volatile uint32_t *)(DR_REG_MMU_TABLE + PRO_CACHE_IBUS2_MMU_START))[rodata_mmu_offset];
 #elif CONFIG_IDF_TARGET_ESP32S3
-    uint32_t rodata_page_cnt = ((uint32_t)&_rodata_reserved_end - ((uint32_t)&_rodata_reserved_start & ~ (MMU_PAGE_SIZE - 1)) + MMU_PAGE_SIZE - 1) / MMU_PAGE_SIZE;
+    uint32_t rodata_page_cnt = ((uint32_t)&_rodata_reserved_end - ((uint32_t)&_rodata_reserved_start & ~(MMU_PAGE_SIZE - 1)) + MMU_PAGE_SIZE - 1) / MMU_PAGE_SIZE;
     rodata_start_page = *(volatile uint32_t *)(DR_REG_MMU_TABLE + CACHE_DROM_MMU_START);
 #endif
     rodata_start_page &= SOC_MMU_VALID_VAL_MASK;

tools/ci/astyle-rules.yml

@@ -71,7 +71,6 @@ components_not_formatted_temporary:
     - "/components/esp_partition/"
     - "/components/esp_phy/"
     - "/components/esp_pm/"
-    - "/components/esp_psram/"
     - "/components/esp_ringbuf/"
     - "/components/esp_rom/"
     - "/components/esp_system/"