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xtensa: update header file

pull/4494/head
morris 2019-11-28 21:07:47 +08:00
rodzic 3224f24ef6
commit 13cb9f8718
18 zmienionych plików z 1280 dodań i 310 usunięć
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6
components/perfmon/xtensa_perfmon_masks.c
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@ -42,8 +42,10 @@ const xtensa_perfmon_select_t xtensa_perfmon_select_table[] = {
{XTPERF_CNT_OUTBOUND_PIF, "Outbound PIF"},
{XTPERF_CNT_INBOUND_PIF, "Inbound PIF"},
{XTPERF_CNT_PREFETCH, "Prefetch"},
#if XCHAL_HW_VERSION >= 270004
{XTPERF_CNT_IDMA, "iDMA"},
{XTPERF_CNT_INSN_LENGTH, "Length of Instructions"},
#endif
{-1, ""},
};
@ -157,6 +159,7 @@ const xtensa_perfmon_masks_t xtensa_perfmon_masks_table[] = {
{XTPERF_CNT_PREFETCH, XTPERF_MASK_PREFETCH_I_MISS, "I prefetch-buffer-lookup miss"},
{XTPERF_CNT_PREFETCH, XTPERF_MASK_PREFETCH_D_MISS, "D prefetch-buffer-lookup miss"},
{XTPERF_CNT_PREFETCH, XTPERF_MASK_PREFETCH_D_L1_FILL, "Direct fill to (L1) Data Cache (unused)"},
#if XCHAL_HW_VERSION >= 270004
{XTPERF_CNT_IDMA, XTPERF_MASK_IDMA_ACTIVE_CYCLES, "active cycles"},
{XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_16, "16-bit"},
{XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_24, "24-bit"},
@ -173,6 +176,7 @@ const xtensa_perfmon_masks_t xtensa_perfmon_masks_table[] = {
{XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_112, "112-bit"},
{XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_120, "120-bit"},
{XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_128, "128-bit"},
#endif
{-1, 0, ""},
};
@ -281,6 +285,7 @@ const uint32_t xtensa_perfmon_select_mask_all[MAX_PERFMON_EVENTS * 2] = {
XTPERF_CNT_PREFETCH, XTPERF_MASK_PREFETCH_I_MISS,
XTPERF_CNT_PREFETCH, XTPERF_MASK_PREFETCH_D_MISS,
XTPERF_CNT_PREFETCH, XTPERF_MASK_PREFETCH_D_L1_FILL,
#if XCHAL_HW_VERSION >= 270004
XTPERF_CNT_IDMA, XTPERF_MASK_IDMA_ALL,
XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_16,
XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_24,
@ -297,4 +302,5 @@ const uint32_t xtensa_perfmon_select_mask_all[MAX_PERFMON_EVENTS * 2] = {
XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_112,
XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_120,
XTPERF_CNT_INSN_LENGTH, XTPERF_MASK_INSN_LENGTH_128
#endif
};

20
components/xtensa/include/xtensa/cacheasm.h
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@ -148,7 +148,7 @@
* if all sets affected by cainst,
* or 1 if only one set (or not all sets) of the cache
* is affected by cainst (eg. DIWB or DIWBI [not yet ISA defined]).
* aa, ab unique address registers (temporaries).
* aa, ab unique address registers (temporaries).
* awb set to other than a0 if wb type of instruction
* loopokay 1 allows use of zero-overhead loops, 0 does not
* immrange range (max value) of cainst's immediate offset parameter, in bytes
@ -841,7 +841,7 @@
#if XCHAL_ICACHE_SIZE > 0
#if XCHAL_HAVE_ICACHE_DYN_WAYS
// Read from MEMCTL and shift/mask
rsr \aa, MEMCTL
rsr.memctl \aa
extui \aa, \aa, MEMCTL_ICWU_SHIFT, MEMCTL_ICWU_BITS
blti \aa, XCHAL_ICACHE_WAYS, .Licgw
movi \aa, XCHAL_ICACHE_WAYS
@ -869,13 +869,13 @@
#if XCHAL_ICACHE_SIZE > 0
#if XCHAL_HAVE_ICACHE_DYN_WAYS
movi \ac, MEMCTL_ICWU_CLR_MASK // set up to clear bits 18-22
rsr \ab, MEMCTL
rsr.memctl \ab
and \ab, \ab, \ac
movi \ac, MEMCTL_INV_EN // set bit 23
slli \aa, \aa, MEMCTL_ICWU_SHIFT // move to right spot
or \ab, \ab, \aa
or \ab, \ab, \ac
wsr \ab, MEMCTL
wsr.memctl \ab
isync
#else
// All ways are always enabled
@ -898,13 +898,13 @@
#if XCHAL_DCACHE_SIZE > 0
#if XCHAL_HAVE_DCACHE_DYN_WAYS
// Read from MEMCTL and shift/mask
rsr \aa, MEMCTL
rsr.memctl \aa
extui \aa, \aa, MEMCTL_DCWU_SHIFT, MEMCTL_DCWU_BITS
blti \aa, XCHAL_DCACHE_WAYS, .Ldcgw
movi \aa, XCHAL_DCACHE_WAYS
.Ldcgw:
#else
// All ways are always enabled
// All ways are always enabled
movi \aa, XCHAL_DCACHE_WAYS
#endif
#else
@ -925,11 +925,11 @@
.macro dcache_set_ways aa, ab, ac
#if (XCHAL_DCACHE_SIZE > 0) && XCHAL_HAVE_DCACHE_DYN_WAYS
movi \ac, MEMCTL_DCWA_CLR_MASK // set up to clear bits 13-17
rsr \ab, MEMCTL
rsr.memctl \ab
and \ab, \ab, \ac // clear ways allocatable
slli \ac, \aa, MEMCTL_DCWA_SHIFT
or \ab, \ab, \ac // set ways allocatable
wsr \ab, MEMCTL
wsr.memctl \ab
#if XCHAL_DCACHE_IS_WRITEBACK
// Check if the way count is increasing or decreasing
extui \ac, \ab, MEMCTL_DCWU_SHIFT, MEMCTL_DCWU_BITS // bits 8-12 - ways in use
@ -942,7 +942,7 @@
beqz \ab, .Ldsw2
j .Ldsw1
.Ldsw2:
rsr \ab, MEMCTL
rsr.memctl \ab
#endif
.Ldsw3:
// No dirty data to write back, just set the new number of ways
@ -952,7 +952,7 @@
or \ab, \ab, \ac // set bit 23
slli \aa, \aa, MEMCTL_DCWU_SHIFT
or \ab, \ab, \aa // set ways in use
wsr \ab, MEMCTL
wsr.memctl \ab
#else
// No dcache or no way disable support
#endif

10
components/xtensa/include/xtensa/cacheattrasm.h
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@ -94,7 +94,7 @@
*
* (Internal macro.)
* Returns value of CACHEATTR register (or closest equivalent) in a2.
*
*
* Entry:
* (none)
* Exit:
@ -103,7 +103,7 @@
*/
.macro _cacheattr_get tlb
#if XCHAL_HAVE_CACHEATTR
rsr a2, CACHEATTR
rsr.cacheattr a2
#elif XCHAL_CA_8X512
// We have a config that "mimics" CACHEATTR using a simplified
// "MMU" composed of a single statically-mapped way.
@ -253,7 +253,7 @@
*/
.macro cacheattr_is_enabled label
#if XCHAL_HAVE_CACHEATTR
rsr a2, CACHEATTR
rsr.cacheattr a2
movi a3, XCHAL_ALLCA_ENAMASK
#elif XCHAL_CA_8X512
icacheattr_get
@ -400,7 +400,7 @@
#if XCHAL_HAVE_CACHEATTR
# if XCHAL_ICACHE_LINESIZE < 4
// No i-cache, so can always safely write to CACHEATTR:
wsr a2, CACHEATTR
wsr.cacheattr a2
# else
// The Athens micro-architecture, when using the old
// exception architecture option (ie. with the CACHEATTR register)
@ -414,7 +414,7 @@
j 1f
.begin no-transform
.align 16 /*XCHAL_ICACHE_LINESIZE*/ // align to within an I-cache line
1: wsr a2, CACHEATTR
1: wsr.cacheattr a2
isync
.end no-transform
nop

66
components/xtensa/include/xtensa/core-macros.h
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@ -38,13 +38,13 @@
/*************************** CACHE ***************************/
/* All the macros are in the lower case now and some of them
/* All the macros are in the lower case now and some of them
* share the name with the existing functions from hal.h.
* Including this header file will define XTHAL_USE_CACHE_MACROS
* Including this header file will define XTHAL_USE_CACHE_MACROS
* which directs hal.h not to use the functions.
*/
*
/*
*
* Single-cache-line operations in C-callable inline assembly.
* Essentially macro versions (uppercase) of:
*
@ -72,7 +72,7 @@
*
* NOTE: All the block block cache ops and line prefetches are implemented
* using intrinsics so they are better optimized regarding memory barriers etc.
*
*
* All block downgrade functions exist in two forms: with and without
* the 'max' parameter: This parameter allows compiler to optimize
* the functions whenever the parameter is smaller than the cache size.
@ -199,7 +199,7 @@
# define _XTHAL_DCACHE_BLOCK_DOWNGRADE(addr, size, type) \
unsigned _s = size; \
unsigned _a = addr; \
unsigned _a = (unsigned) addr; \
do { \
unsigned __s = (_s > XCHAL_DCACHE_SIZE) ? \
XCHAL_DCACHE_SIZE : _s; \
@ -211,7 +211,7 @@
# define _XTHAL_DCACHE_BLOCK_DOWNGRADE_MAX(addr, size, type, max) \
if (max <= XCHAL_DCACHE_SIZE) { \
unsigned _s = size; \
unsigned _a = addr; \
unsigned _a = (unsigned) addr; \
type((const int*)_a, _s); \
} \
else { \
@ -369,6 +369,33 @@
# define XTHAL_SET_CCOMPARE(n,v) do {/*nothing*/} while(0)
#endif
/* New functions added to accomodate XEA3 and allow deprecation of older
functions. For this release they just map to the older ones. */
/* Enables the specified interrupt. */
static inline void xthal_interrupt_enable(unsigned intnum)
{
xthal_int_enable(1 << intnum);
}
/* Disables the specified interrupt. */
static inline void xthal_interrupt_disable(unsigned intnum)
{
xthal_int_disable(1 << intnum);
}
/* Triggers the specified interrupt. */
static inline void xthal_interrupt_trigger(unsigned intnum)
{
xthal_set_intset(1 << intnum);
}
/* Clears the specified interrupt. */
static inline void xthal_interrupt_clear(unsigned intnum)
{
xthal_set_intclear(1 << intnum);
}
/*************************** MISC ***************************/
@ -413,7 +440,7 @@ static inline unsigned XTHAL_COMPARE_AND_SET( int *addr, int testval, int setva
" bne %2, %0, 9f \n" // test
" s32i %1, %3, 0 \n" // write the new value
"9: wsr.ps %4 ; rsync \n" // restore the PS
: "=a"(result)
: "=a"(result)
: "0" (setval), "a" (testval), "a" (addr), "a" (tmp)
: "memory");
#else
@ -450,6 +477,29 @@ static inline void XTHAL_WER (unsigned reg, unsigned value)
#endif /* XCHAL_HAVE_EXTERN_REGS */
/*
* Sets a single entry at 'index' within the MPU
*
* The caller must ensure that the resulting MPU map is ordered.
*/
static inline void xthal_mpu_set_entry (xthal_MPU_entry entry)
{
#if XCHAL_HAVE_MPU
__asm__ __volatile__("j 1f\n\t.align 8\n\t1: memw\n\twptlb %0, %1\n\t" : : "a" (entry.at), "a"(entry.as));
#endif
}
/* Same as xthal_mpu_set_entry except that this function must not be used to change the MPU entry
* for the currently executing instruction ... use xthal_mpu_set_entry instead. */
static inline void xthal_mpu_set_entry_ (xthal_MPU_entry entry)
{
#if XCHAL_HAVE_MPU
__asm__ __volatile__("wptlb %0, %1\n\t" : : "a" (entry.at), "a"(entry.as));
#endif
}
#endif /* C code */
#endif /*XTENSA_CACHE_H*/

156
components/xtensa/include/xtensa/coreasm.h
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@ -13,7 +13,7 @@
* here until we have a proper configuration-independent header file.
*/
/* $Id: //depot/rel/Eaglenest/Xtensa/OS/include/xtensa/coreasm.h#3 $ */
/* $Id: //depot/rel/Foxhill/dot.9/Xtensa/OS/include/xtensa/coreasm.h#1 $ */
/*
* Copyright (c) 2000-2014 Tensilica Inc.
@ -302,7 +302,7 @@
#if XCHAL_HAVE_OLD_EXC_ARCH || XCHAL_HAVE_INTERRUPTS
rsil \ar, \newlevel
#else
rsr \ar, PS
rsr.ps \ar
#endif
.endm // crsil
@ -358,7 +358,7 @@
* the call to the spilling function.
*
* Example usage:
*
*
* .text
* .align 4
* .global some_function
@ -558,7 +558,7 @@
* macro implements version of beqi for arbitrary 32-bit immediate value
*
* beqi32 ax, ay, imm32, label
*
*
* Compares value in register ax with imm32 value and jumps to label if
* equal. Clobbers register ay if needed
*
@ -573,7 +573,7 @@
.ifeq (\imm) // 0 ?
beqz \ax, \label
.else
// We could also handle immediates 10,12,16,32,64,128,256
// We could also handle immediates 10,12,16,32,64,128,256
// but it would be a long macro...
movi \ay, \imm
beq \ax, \ay, \label
@ -601,6 +601,18 @@
#endif
.endm
/*----------------------------------------------------------------------
* isync_return_nop
*
* This macro should be used instead of isync_retw_nop in code that is
* intended to run on both the windowed and call0 ABIs
*/
.macro isync_return_nop
#ifdef __XTENSA_WINDOWED_ABI__
isync_retw_nop
#endif
.endm
/*----------------------------------------------------------------------
* isync_erratum453
*
@ -615,20 +627,90 @@
.endm
/*----------------------------------------------------------------------
* readsr
*
* wrapper for 'rsr' that constructs register names that involve levels
* e.g. EPCn etc. Use like so:
* readsr epc XCHAL_DEBUGLEVEL a2
*/
.macro readsr reg suf ar
rsr.\reg\suf \ar
.endm
/*----------------------------------------------------------------------
* writesr
*
* wrapper for 'wsr' that constructs register names that involve levels
* e.g. EPCn etc. Use like so:
* writesr epc XCHAL_DEBUGLEVEL a2
*/
.macro writesr reg suf ar
wsr.\reg\suf \ar
.endm
/*----------------------------------------------------------------------
* xchgsr
*
* wrapper for 'xsr' that constructs register names that involve levels
* e.g. EPCn etc. Use like so:
* xchgsr epc XCHAL_DEBUGLEVEL a2
*/
.macro xchgsr reg suf ar
xsr.\reg\suf \ar
.endm
/*----------------------------------------------------------------------
* INDEX_SR
*
* indexing wrapper for rsr/wsr/xsr that constructs register names from
* the provided base name and the current index. Use like so:
* .set _idx, 0
* INDEX_SR rsr.ccompare a2
*
* this yields: rsr.ccompare0 a2
*/
.macro INDEX_SR instr ar
.ifeq (_idx)
&instr&0 \ar
.endif
.ifeq (_idx-1)
&instr&1 \ar
.endif
.ifeq (_idx-2)
&instr&2 \ar
.endif
.ifeq (_idx-3)
&instr&3 \ar
.endif
.ifeq (_idx-4)
&instr&4 \ar
.endif
.ifeq (_idx-5)
&instr&5 \ar
.endif
.ifeq (_idx-6)
&instr&6 \ar
.endif
.ifeq (_idx-7)
&instr&7 \ar
.endif
.endm
/*----------------------------------------------------------------------
* abs
*
* implements abs on machines that do not have it configured
*/
#if !XCHAL_HAVE_ABS
.macro abs arr, ars
.ifc \arr, \ars
//src equal dest is less efficient
bgez \arr, 1f
neg \arr, \arr
1:
1:
.else
neg \arr, \ars
movgez \arr, \ars, \ars
@ -639,9 +721,9 @@
/*----------------------------------------------------------------------
* addx2
*
*
* implements addx2 on machines that do not have it configured
*
*
*/
#if !XCHAL_HAVE_ADDX
@ -663,14 +745,14 @@
.endif
.endm
#endif /* !XCHAL_HAVE_ADDX */
/*----------------------------------------------------------------------
* addx4
*
*
* implements addx4 on machines that do not have it configured
*
*/
#if !XCHAL_HAVE_ADDX
.macro addx4 arr, ars, art
.ifc \arr, \art
@ -696,9 +778,9 @@
/*----------------------------------------------------------------------
* addx8
*
*
* implements addx8 on machines that do not have it configured
*
*
*/
#if !XCHAL_HAVE_ADDX
@ -731,7 +813,7 @@
/*----------------------------------------------------------------------
* rfe_rfue
*
*
* Maps to RFUE on XEA1, and RFE on XEA2. No mapping on XEAX.
*/
@ -744,11 +826,11 @@
rfe
.endm
#endif
/*----------------------------------------------------------------------
* abi_entry
*
*
* Generate proper function entry sequence for the current ABI
* (windowed or call0). Takes care of allocating stack space (up to 1kB)
* and saving the return PC, if necessary. The corresponding abi_return
@ -850,6 +932,7 @@
.endif
abi_entry_size \locsize, \callsize
#if XCHAL_HAVE_WINDOWED && !__XTENSA_CALL0_ABI__
# define ABI_ENTRY_MINSIZE 3 /* size of abi_entry (no arguments) instructions in bytes */
.ifgt .locsz - 32760 /* .locsz > 32760 (ENTRY's max range)? */
/* Funky computation to try to have assembler use addmi efficiently if possible: */
entry sp, 0x7F00 + (.locsz & 0xF0)
@ -859,6 +942,7 @@
entry sp, .locsz
.endif
#else
# define ABI_ENTRY_MINSIZE 0 /* size of abi_entry (no arguments) instructions in bytes */
.if .locsz
.ifle .locsz - 128 /* if locsz <= 128 */
addi sp, sp, -.locsz
@ -882,7 +966,7 @@
/*----------------------------------------------------------------------
* abi_return
*
*
* Generate proper function exit sequence for the current ABI
* (windowed or call0). Takes care of freeing stack space and
* restoring the return PC, if necessary.
@ -934,6 +1018,42 @@
#endif
.endm
/*
* These macros are internal, subject to change, and should not be used in
* any new code.
*/
#define _GBL(x) .global x
#define _TYP(x) .type x,@function
#define _ALN(x) .align x
#define _SIZ(x) .size x, . - x
#define _MKEND(x) .purgem endfunc ; .macro endfunc ; _SIZ(x) ; .purgem endfunc ; .macro endfunc ; .endm ; .endm
#define _SYMT(x) _GBL(x); _MKEND(x); _TYP(x); _ALN(4); x:
#define _SYM2(x) _GBL(x); _TYP(x); x:
#define _SYM(x) _GBL(x); _MKEND(x); _ALN(4); x:
.macro endfunc ; .endm
/*
* the DECLFUNC() macro provides a mechanism for implementing both the
* standard and _nw interface with a single copy of the code.
*
* For Call0 ABI there is one function definition which is labeled with
* both the xthal_..._nw and xthal_... symbols.
*
* For windowed ABI, two compilations are involved (one with the __NW_FUNCTION__
* symbol defined) resulting in two separate functions (the _nw one without
* the window adjustments).
*/
#if defined(__NW_FUNCTION__)
# define DECLFUNC(x) _SYMT(x ## _nw)
#else
# if defined (__XTENSA_CALL0_ABI__)
# define DECLFUNC(x) _SYMT(x); _SYM2(x ## _nw)
# else
# define DECLFUNC(x) _SYMT(x)
# endif
#endif
#endif /*XTENSA_COREASM_H*/

18
components/xtensa/include/xtensa/corebits.h
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@ -5,7 +5,7 @@
* This file is not generated, ie. it is processor configuration independent.)
*/
/* $Id: //depot/rel/Eaglenest/Xtensa/OS/include/xtensa/corebits.h#2 $ */
/* $Id: //depot/rel/Foxhill/dot.9/Xtensa/OS/include/xtensa/corebits.h#1 $ */
/*
* Copyright (c) 2005-2011 Tensilica Inc.
@ -52,10 +52,12 @@
# define EXCCAUSE_LEVEL1INTERRUPT 4 /* (backward compatibility macro, deprecated, avoid) */
#define EXCCAUSE_ALLOCA 5 /* Stack Extension Assist (MOVSP instruction) for alloca */
#define EXCCAUSE_DIVIDE_BY_ZERO 6 /* Integer Divide by Zero */
#define EXCCAUSE_SPECULATION 7 /* Use of Failed Speculative Access (not implemented) */
# define EXCCAUSE_SPECULATION 7 /* Use of Failed Speculative Access (deprecated) */
#define EXCCAUSE_PC_ERROR 7 /* Next PC Value Illegal */
#define EXCCAUSE_PRIVILEGED 8 /* Privileged Instruction */
#define EXCCAUSE_UNALIGNED 9 /* Unaligned Load or Store */
/* Reserved 10..11 */
#define EXCCAUSE_EXTREG_PRIVILEGE 10 /* External Register Privilege Error */
#define EXCCAUSE_EXCLUSIVE_ERROR 11 /* Load exclusive to unsupported memory type or unaligned address */
#define EXCCAUSE_INSTR_DATA_ERROR 12 /* PIF Data Error on Instruction Fetch (RB-200x and later) */
#define EXCCAUSE_LOAD_STORE_DATA_ERROR 13 /* PIF Data Error on Load or Store (RB-200x and later) */
#define EXCCAUSE_INSTR_ADDR_ERROR 14 /* PIF Address Error on Instruction Fetch (RB-200x and later) */
@ -106,6 +108,14 @@
#define PS_INTLEVEL_SHIFT 0
#define PS_INTLEVEL_MASK 0x0000000F
#define PS_INTLEVEL(n) ((n)&PS_INTLEVEL_MASK) /* n = 0..15 */
/* ABI-derived field values: */
#ifdef __XTENSA_CALL0_ABI__
#define PS_WOE_ABI 0
#define PS_WOECALL4_ABI 0
#else
#define PS_WOE_ABI PS_WOE /* 0x40000 */
#define PS_WOECALL4_ABI (PS_WOE | PS_CALLINC(1)) /* 0x50000, per call4 */
#endif
/* Backward compatibility (deprecated): */
#define PS_PROGSTACK_SHIFT PS_UM_SHIFT
#define PS_PROGSTACK_MASK PS_UM_MASK
@ -142,7 +152,7 @@
#define MESR_DME_SHIFT 1
#define MESR_RCE 0x00000010 /* recorded memory error */
#define MESR_RCE_SHIFT 4
#define MESR_LCE
#define MESR_LCE
#define MESR_LCE_SHIFT ?
#define MESR_LCE_L
#define MESR_ERRENAB 0x00000100

612
components/xtensa/include/xtensa/hal.h
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@ -12,9 +12,9 @@
the XTHAL_RELEASE_xxx macros (or additions made in later versions).
$Id: //depot/rel/Eaglenest/Xtensa/OS/target-os-src/hal.h.tpp#4 $
$Id: //depot/rel/Foxhill/dot.9/Xtensa/OS/target-os-src/hal.h.tpp#1 $
Copyright (c) 1999-2014 Cadence Design Systems, Inc.
Copyright (c) 1999-2015 Cadence Design Systems, Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
@ -39,7 +39,6 @@
#ifndef XTENSA_HAL_H
#define XTENSA_HAL_H
/****************************************************************************
Definitions Useful for Any Code, USER or PRIVILEGED
****************************************************************************/
@ -58,12 +57,12 @@
* In the past, release and version names all matched in T####.# form,
* making the distinction irrelevant. This is no longer the case.
*/
#define XTHAL_RELEASE_MAJOR 11000
#define XTHAL_RELEASE_MINOR 3
#define XTHAL_RELEASE_NAME "11.0.3"
#define XTHAL_REL_11 1
#define XTHAL_REL_11_0 1
#define XTHAL_REL_11_0_3 1
#define XTHAL_RELEASE_MAJOR 12000
#define XTHAL_RELEASE_MINOR 9
#define XTHAL_RELEASE_NAME "12.0.9"
#define XTHAL_REL_12 1
#define XTHAL_REL_12_0 1
#define XTHAL_REL_12_0_9 1
/* HAL version numbers (these names are for backward compatibility): */
#define XTHAL_MAJOR_REV XTHAL_RELEASE_MAJOR
@ -140,6 +139,9 @@
extern "C" {
#endif
#include <stdint.h>
#include <stddef.h>
/*----------------------------------------------------------------------
HAL
----------------------------------------------------------------------*/
@ -255,22 +257,17 @@ extern const unsigned int Xthal_dcache_size;
/* cache features */
extern const unsigned char Xthal_dcache_is_writeback;
/* invalidate the caches */
/* cache region operations*/
extern void xthal_icache_region_invalidate( void *addr, unsigned size );
extern void xthal_dcache_region_invalidate( void *addr, unsigned size );
# ifndef XTHAL_USE_CACHE_MACROS
extern void xthal_dcache_region_writeback( void *addr, unsigned size );
extern void xthal_dcache_region_writeback_inv( void *addr, unsigned size );
#ifndef XTHAL_USE_CACHE_MACROS
/* cache line operations*/
extern void xthal_icache_line_invalidate(void *addr);
extern void xthal_dcache_line_invalidate(void *addr);
# endif
/* write dirty data back */
extern void xthal_dcache_region_writeback( void *addr, unsigned size );
# ifndef XTHAL_USE_CACHE_MACROS
extern void xthal_dcache_line_writeback(void *addr);
# endif
/* write dirty data back and invalidate */
extern void xthal_dcache_region_writeback_inv( void *addr, unsigned size );
# ifndef XTHAL_USE_CACHE_MACROS
extern void xthal_dcache_line_writeback_inv(void *addr);
/* sync icache and memory */
extern void xthal_icache_sync( void );
@ -278,14 +275,12 @@ extern void xthal_icache_sync( void );
extern void xthal_dcache_sync( void );
#endif
/* get number of icache ways enabled */
/* get/set number of icache ways enabled */
extern unsigned int xthal_icache_get_ways(void);
/* set number of icache ways enabled */
extern void xthal_icache_set_ways(unsigned int ways);
/* get number of dcache ways enabled */
extern void xthal_icache_set_ways(unsigned int ways);
/* get/set number of dcache ways enabled */
extern unsigned int xthal_dcache_get_ways(void);
/* set number of dcache ways enabled */
extern void xthal_dcache_set_ways(unsigned int ways);
extern void xthal_dcache_set_ways(unsigned int ways);
/* coherency (low-level -- not normally called directly) */
extern void xthal_cache_coherence_on( void );
@ -476,7 +471,11 @@ extern void xthal_clear_regcached_code( void );
#define XTHAL_INTTYPE_NMI 5
#define XTHAL_INTTYPE_WRITE_ERROR 6
#define XTHAL_INTTYPE_PROFILING 7
#define XTHAL_MAX_INTTYPES 8 /* number of interrupt types */
#define XTHAL_INTTYPE_IDMA_DONE 8
#define XTHAL_INTTYPE_IDMA_ERR 9
#define XTHAL_INTTYPE_GS_ERR 10
#define XTHAL_INTTYPE_SG_ERR 10 /* backward compatibility name - deprecated */
#define XTHAL_MAX_INTTYPES 11 /* number of interrupt types */
/* Timer related: */
#define XTHAL_TIMER_UNCONFIGURED -1 /* Xthal_timer_interrupt[] value for non-existent timers */
@ -699,6 +698,9 @@ extern unsigned xthal_get_intenable( void );
extern void xthal_set_intenable( unsigned );
extern unsigned xthal_get_interrupt( void );
#define xthal_get_intread xthal_get_interrupt /* backward compatibility */
/* These two functions are deprecated. Use the newer functions
xthal_interrupt_trigger and xthal_interrupt_clear instead. */
extern void xthal_set_intset( unsigned );
extern void xthal_set_intclear( unsigned );
@ -751,6 +753,7 @@ extern unsigned xthal_vpri_to_intlevel(unsigned vpri);
extern unsigned xthal_intlevel_to_vpri(unsigned intlevel);
/* Enables/disables given set (mask) of interrupts; returns previous enabled-mask of all ints: */
/* These functions are deprecated. Use xthal_interrupt_enable and xthal_interrupt_disable instead. */
extern unsigned xthal_int_enable(unsigned);
extern unsigned xthal_int_disable(unsigned);
@ -865,26 +868,34 @@ extern void xthal_dcache_enable( void ); /* DEPRECATED */
extern void xthal_icache_disable( void ); /* DEPRECATED */
extern void xthal_dcache_disable( void ); /* DEPRECATED */
/* invalidate the caches */
/* whole cache operations (privileged) */
extern void xthal_icache_all_invalidate( void );
extern void xthal_dcache_all_invalidate( void );
/* write dirty data back */
extern void xthal_dcache_all_writeback( void );
/* write dirty data back and invalidate */
extern void xthal_dcache_all_writeback_inv( void );
extern void xthal_icache_all_unlock( void );
extern void xthal_dcache_all_unlock( void );
/* address-range cache operations (privileged) */
/* prefetch and lock specified memory range into cache */
extern void xthal_icache_region_lock( void *addr, unsigned size );
extern void xthal_dcache_region_lock( void *addr, unsigned size );
# ifndef XTHAL_USE_CACHE_MACROS
extern void xthal_icache_line_lock(void *addr);
extern void xthal_dcache_line_lock(void *addr);
# endif
/* unlock from cache */
extern void xthal_icache_all_unlock( void );
extern void xthal_dcache_all_unlock( void );
extern void xthal_icache_region_unlock( void *addr, unsigned size );
extern void xthal_dcache_region_unlock( void *addr, unsigned size );
/* huge-range cache operations (privileged) (EXPERIMENTAL) */
extern void xthal_icache_hugerange_invalidate( void *addr, unsigned size );
extern void xthal_icache_hugerange_unlock( void *addr, unsigned size );
extern void xthal_dcache_hugerange_invalidate( void *addr, unsigned size );
extern void xthal_dcache_hugerange_unlock( void *addr, unsigned size );
extern void xthal_dcache_hugerange_writeback( void *addr, unsigned size );
extern void xthal_dcache_hugerange_writeback_inv( void *addr, unsigned size );
# ifndef XTHAL_USE_CACHE_MACROS
/* cache line operations (privileged) */
extern void xthal_icache_line_lock(void *addr);
extern void xthal_dcache_line_lock(void *addr);
extern void xthal_icache_line_unlock(void *addr);
extern void xthal_dcache_line_unlock(void *addr);
# endif
@ -927,29 +938,514 @@ extern const unsigned char Xthal_dtlb_way_bits;
extern const unsigned char Xthal_dtlb_ways;
extern const unsigned char Xthal_dtlb_arf_ways;
/* Convert between virtual and physical addresses (through static maps only): */
/*** WARNING: these two functions may go away in a future release; don't depend on them! ***/
/* Return error codes for hal functions */
/* function sucessful, operation completed as expected */
#define XTHAL_SUCCESS 0
/* XTHAL_CAFLAGS_NO_PARTIAL was specified, and no full region is
* covered by the address range. */
#define XTHAL_NO_REGIONS_COVERED -1
/* The XTHAL_CAFLAGS_EXACT flag was given, but no exact mapping is possible. */
#define XTHAL_INEXACT -2
/* The supplied address doesn't correspond to the start of a region. */
#define XTHAL_INVALID_ADDRESS -3
/* This functionality is not available on this architecture. */
#define XTHAL_UNSUPPORTED -4
/* Translation failed because vaddr and paddr were not aligned. */
#define XTHAL_ADDRESS_MISALIGNED -5
/* There is mapping for the supplied address. */
#define XTHAL_NO_MAPPING -6
/* The requested access rights are not supported */
#define XTHAL_BAD_ACCESS_RIGHTS -7
/* The requested memory type is not supported */
#define XTHAL_BAD_MEMORY_TYPE -8
/* The entries supplied are not properly aligned to the MPU's background map. */
#define XTHAL_MAP_NOT_ALIGNED -9
/* There are not enough MPU entries available to do the requeste mapping. */
#define XTHAL_OUT_OF_ENTRIES -10
/* The entries supplied are not properly ordered for the MPU. */
#define XTHAL_OUT_OF_ORDER_MAP -11
/* an invalid argument such as a null pointer was supplied to the function */
#define XTHAL_INVALID -12
/* specified region is of zero size, therefore no mapping is done. */
#define XTHAL_ZERO_SIZED_REGION -13
/* specified range wraps around '0' */
#define XTHAL_INVALID_ADDRESS_RANGE -14
/*
For backward compatibility we retain the following inconsistenly named
constants. Do not use them as they may be removed in a future release.
*/
#define XCHAL_SUCCESS XTHAL_SUCCESS
#define XCHAL_ADDRESS_MISALIGNED XTHAL_ADDRESS_MISALIGNED
#define XCHAL_INEXACT XTHAL_INEXACT
#define XCHAL_INVALID_ADDRESS XTHAL_INVALID_ADDRESS
#define XCHAL_UNSUPPORTED_ON_THIS_ARCH XTHAL_UNSUPPORTED
#define XCHAL_NO_PAGES_MAPPED XTHAL_NO_REGIONS_COVERED
/* Convert between virtual and physical addresses (through static maps only)
* WARNING: these two functions may go away in a future release;
* don't depend on them!
*/
extern int xthal_static_v2p( unsigned vaddr, unsigned *paddrp );
extern int xthal_static_p2v( unsigned paddr, unsigned *vaddrp, unsigned cached );
#define XCHAL_SUCCESS 0
#define XCHAL_ADDRESS_MISALIGNED -1
#define XCHAL_INEXACT -2
#define XCHAL_INVALID_ADDRESS -3
#define XCHAL_UNSUPPORTED_ON_THIS_ARCH -4
#define XCHAL_NO_PAGES_MAPPED -5
#define XTHAL_NO_MAPPING -6
#define XCHAL_CA_R (0xC0 | 0x40000000)
#define XCHAL_CA_RX (0xD0 | 0x40000000)
#define XCHAL_CA_RW (0xE0 | 0x40000000)
#define XCHAL_CA_RWX (0xF0 | 0x40000000)
extern int xthal_set_region_translation(void* vaddr, void* paddr, unsigned size, unsigned cache_atr, unsigned flags);
extern int xthal_set_region_translation(void* vaddr, void* paddr,
unsigned size, unsigned cache_atr, unsigned flags);
extern int xthal_v2p(void*, void**, unsigned*, unsigned*);
extern int xthal_invalidate_region(void* addr);
extern int xthal_set_region_translation_raw(void *vaddr, void *paddr, unsigned cattr);
/*------------------------------------------------------------------------
MPU (Memory Protection Unit)
-------------------------------------------------------------------------*/
/*
* General notes on MPU (Memory Protection Unit):
*
* The MPU supports setting the access rights (read, write, execute) as
* well as the memory type (cacheablity, ...)
* for regions of memory. The granularity can be as small as 32 bytes.
* (XCHAL_MPU_ALIGN specifies the granularity for any specific MPU config)
*
* The MPU doesn't support mapping between virtual and physical addresses.
*
* The MPU contains a fixed number of map changeable forground map entries,
* and a background map which is fixed at configuration time.
*
* Each entry has a start address (up to 27 bits), valid flag,
* access rights (4 bits), and memory type (9 bits);
*
*/
/*
MPU access rights constants:
Only the combinations listed below are supported by the MPU.
*/
#define XTHAL_AR_NONE 0 /* no access */
#define XTHAL_AR_R 4 /* Kernel read, User no access*/
#define XTHAL_AR_RX 5 /* Kernel read/execute, User no access */
#define XTHAL_AR_RW 6 /* Kernel read/write, User no access */
#define XTHAL_AR_RWX 7 /* Kernel read/write/execute, User no access */
#define XTHAL_AR_Ww 8 /* Kernel write, User write */
#define XTHAL_AR_RWrwx 9 /* Kernel read/write , User read/write/execute */
#define XTHAL_AR_RWr 10 /* Kernel read/write, User read */
#define XTHAL_AR_RWXrx 11 /* Kernel read/write/execute, User read/execute */
#define XTHAL_AR_Rr 12 /* Kernel read, User read */
#define XTHAL_AR_RXrx 13 /* Kernel read/execute, User read/execute */
#define XTHAL_AR_RWrw 14 /* Kernel read/write, User read/write */
#define XTHAL_AR_RWXrwx 15 /* Kernel read/write/execute,
User read/write/execute */
#define XTHAL_AR_WIDTH 4 /* # bits used to encode access rights */
/* If the bit XTHAL_MPU_USE_EXISTING_ACCESS_RIGHTS is set in the accessRights
* argument to xthal_mpu_set_region_attribute(), or to the cattr argument of
* xthal_set_region_attribute() then the existing access rights for the first
* byte of the region will be used as the access rights of the new region.
*/
#define XTHAL_MPU_USE_EXISTING_ACCESS_RIGHTS 0x00002000
/* If the bit XTHAL_MPU_USE_EXISTING_MEMORY_TYPE is set in the memoryType
* argument to xthal_mpu_set_region_attribute(), or to the cattr argument of
* xthal_set_region_attribute() then the existing memory type for the first
* byte of the region will be used as the memory type of the new region.
*/
#define XTHAL_MPU_USE_EXISTING_MEMORY_TYPE 0x00004000
/* The following groups of constants are bit-wise or'd together to specify
* the memory type as input to the macros and functions that accept an
* unencoded memory type specifier:
* XTHAL_ENCODE_MEMORY_TYPE, xthal_encode_memory_type,
* xthal_mpu_set_region_attribute(), and xthal_set_region_attribute().
*
* example:
* XTHAL_MEM_DEVICE | XTHAL_MEM_INTERRUPTIBLE | XTHAL_MEM_SYSTEM_SHARABLE
*
* or
* XTHAL_MEM_WRITEBACK | XTHAL_MEM_INNER_SHAREABLE
*
* If it is desired to specify different attributes for the system and
* local cache, then macro XTHAL_MEM_PROC_CACHE is used:
*
* XTHAL_MEM_PROC_CACHE(XTHAL_MEM_WRITEBACK, XTHAL_MEM_WRITETHRU)
*
* indicates the shared cache is writeback, but the processor's local cache
* is writethrough.
*
*/
/* The following group of constants are used to specify cache attributes of
* an MPU entry. If the processors local cache and the system's shared cache
* have the same attributes (or if there aren't distinct local and shared
* caches) then the constant can be used directly. If different attributes
* for the shared and local caches, then use these constants as the parameters
* to the XTHAL_MEM_PROC_CACHE() macro.
*/
#define XTHAL_MEM_DEVICE 0x00008000
#define XTHAL_MEM_NON_CACHEABLE 0x00090000
#define XTHAL_MEM_WRITETHRU_NOALLOC 0x00080000
#define XTHAL_MEM_WRITETHRU 0x00040000
#define XTHAL_MEM_WRITETHRU_WRITEALLOC 0x00060000
#define XTHAL_MEM_WRITEBACK_NOALLOC 0x00050000
#define XTHAL_MEM_WRITEBACK 0x00070000
/* Indicates a read is interruptible. Only applicable to devices */
#define XTHAL_MEM_INTERRUPTIBLE 0x08000000
/* Indicates if writes to this memory are bufferable ... only applicable
* to devices, and non-cacheable memory.
*/
#define XTHAL_MEM_BUFFERABLE 0x01000000
/* The following group of constants indicates the scope of the sharing of
* the memory region. XTHAL_MEM_INNER_SHAREABLE and XTHAL_MEM_OUTER_SHARABLE are
* only applicable to cacheable regions. XTHAL_MEM_SYSTEM_SHAREABLE is only
* applicable to devices and non-cacheable regions.
*/
#define XTHAL_MEM_NON_SHAREABLE 0x00000000
#define XTHAL_MEM_INNER_SHAREABLE 0x02000000
#define XTHAL_MEM_OUTER_SHAREABLE 0x04000000
#define XTHAL_MEM_SYSTEM_SHAREABLE 0x06000000
/*
* This macro is needed when the cache attributes are different for the shared
* and processor's local caches. For example:
*
* XTHAL_MEM_PROC_CACHE(XTHAL_MEM_WRITEBACK, XTHAL_MEM_NON_CACHEABLE)
* creates a memory type that is writeback cacheable in the system cache, and not
* cacheable in the processor's local cache.
*/
#define XTHAL_MEM_PROC_CACHE(system, processor) \
(((system) & 0x000f0000) | (((processor) & 0x000f0000 ) << 4) | \
(((system) & XTHAL_MEM_DEVICE) | ((processor) & XTHAL_MEM_DEVICE)))
/*
* This macro converts a bit-wise combination of the XTHAL_MEM_... constants
* to the corresponding MPU memory type (9-bits).
*
* Unsupported combinations are mapped to the best available substitute.
*
* The same functionality plus error checking is available from
* xthal_encode_memory_type().
*/
#define XTHAL_ENCODE_MEMORY_TYPE(x) \
(((x) & 0xffffe000) ? \
(_XTHAL_MEM_IS_DEVICE((x)) ? _XTHAL_ENCODE_DEVICE((x)) : \
(_XTHAL_IS_SYSTEM_NONCACHEABLE((x)) ? \
_XTHAL_ENCODE_SYSTEM_NONCACHEABLE((x)) : \
_XTHAL_ENCODE_SYSTEM_CACHEABLE((x)))) : (x))
/*
* This structure is used to represent each MPU entry (both foreground and
* background). The internal representation of the structure is subject to
* change, so it should only be accessed by the XTHAL_MPU_ENTRY_... macros
* below.
*/
typedef struct xthal_MPU_entry
{
uint32_t as; /* virtual start address, and valid bit */
uint32_t at; /* access rights, and memory type (and space for entry index) */
} xthal_MPU_entry;
extern const xthal_MPU_entry Xthal_mpu_bgmap[];
/*
* XTHAL_MPU_ENTRY creates an MPU entry from its component values. It is
* intended for initializing an MPU map. Example:
* const struct xthal_MPU_entry mpumap[] =
{ XTHAL_MPU_ENTRY( 0x00000000, 1, XTHAL_AR_RWXrwx, XTHAL_MEM_WRITEBACK),
XTHAL_MPU_ENTRY( 0xE0000000, 1, XTHAL_AR_RWXrwx,
XTHAL_MEM_NON_CACHEABLE | XTHAL_MEM_BUFFERABLE),
XTHAL_MPU_ENTRY( 0xF0000000, 1, XTHAL_AR_RWX,
XTHAL_MEM_NON_CACHEABLE | XTHAL_MEM_BUFFERABLE) };
xthal_write_map(mpumap, sizeof(mpumap) / sizeof(struct xthal_MPU_entry));
*
*/
#define XTHAL_MPU_ENTRY(vaddr, valid, access, memtype) \
{ (((vaddr) & 0xffffffe0) | ((valid & 0x1))), \
(((XTHAL_ENCODE_MEMORY_TYPE(memtype)) << 12) | (((access) & 0xf) << 8)) }
/*
* These macros get (or set) the specified field of the MPU entry.
*/
#define XTHAL_MPU_ENTRY_GET_VSTARTADDR(x) ((x).as & 0xffffffe0)
#define XTHAL_MPU_ENTRY_SET_VSTARTADDR(x, vaddr) (x).as = \
(((x).as) & 0x1) | ((vaddr) & 0xffffffe0)
#define XTHAL_MPU_ENTRY_GET_VALID(x) (((x).as & 0x1))
#define XTHAL_MPU_ENTRY_SET_VALID(x, valid) (x).as = \
(((x).as & 0xfffffffe) | ((valid) & 0x1))
#define XTHAL_MPU_ENTRY_GET_ACCESS(x) ((((x).at) >> 8) & 0xf)
#define XTHAL_MPU_ENTRY_SET_ACCESS(x, accessRights) ((x).at = \
((x).at & 0xfffff0ff) | (((accessRights) & 0xf) << 8))
#define XTHAL_MPU_ENTRY_GET_MEMORY_TYPE(x) ((((x).at) >> 12) & 0x1ff)
#define XTHAL_MPU_ENTRY_SET_MEMORY_TYPE(x, memtype) ((x).at = \
((x).at & 0xffe00fff) | (((XTHAL_ENCODE_MEMORY_TYPE(memtype)) & 0x1ff) << 12))
/*
* These functions accept encoded access rights, and return 1 if the
* supplied memory type has the property specified by the function name,
* otherwise they return 0.
*/
extern int32_t xthal_is_kernel_readable(uint32_t accessRights);
extern int32_t xthal_is_kernel_writeable(uint32_t accessRights);
extern int32_t xthal_is_kernel_executable(uint32_t accessRights);
extern int32_t xthal_is_user_readable(uint32_t accessRights);
extern int32_t xthal_is_user_writeable (uint32_t accessRights);
extern int32_t xthal_is_user_executable(uint32_t accessRights);
/*
* This function converts a bit-wise combination of the XTHAL_MEM_.. constants
* to the corresponding MPU memory type (9-bits).
*
* If none of the XTHAL_MEM_.. bits are present in the argument, then
* bits 4-12 (9-bits) are returned ... this supports using an already encoded
* memoryType (perhaps obtained from an xthal_MPU_entry structure) as input
* to xthal_set_region_attribute().
*
* This function first checks that the supplied constants are a valid and
* supported combination. If not, it returns XTHAL_BAD_MEMORY_TYPE.
*/
extern int xthal_encode_memory_type(uint32_t x);
/*
* This function accepts a 9-bit memory type value (such as returned by
* XTHAL_MEM_ENTRY_GET_MEMORY_TYPE() or xthal_encode_memory_type(). They
* return 1 if the memoryType has the property specified in the function
* name and 0 otherwise.
*/
extern int32_t xthal_is_cacheable(uint32_t memoryType);
extern int32_t xthal_is_writeback(uint32_t memoryType);
extern int32_t xthal_is_device(uint32_t memoryType);
/*
* Copies the current MPU entry list into 'entries' which
* must point to available memory of at least
* sizeof(struct xthal_MPU_entry) * XCHAL_MPU_ENTRIES.
*
* This function returns XTHAL_SUCCESS.
* XTHAL_INVALID, or
* XTHAL_UNSUPPORTED.
*/
extern int32_t xthal_read_map(struct xthal_MPU_entry* entries);
/*
* Writes the map pointed to by 'entries' to the MPU. Before updating
* the map, it commits any uncommitted
* cache writes, and invalidates the cache if necessary.
*
* This function does not check for the correctness of the map. Generally
* xthal_check_map() should be called first to check the map.
*
* If n == 0 then the existing map is cleared, and no new map is written
* (useful for returning to reset state)
*
* If (n > 0 && n < XCHAL_MPU_ENTRIES) then a new map is written with
* (XCHAL_MPU_ENTRIES-n) padding entries added to ensure a properly ordered
* map. The resulting foreground map will be equivalent to the map vector
* fg, but the position of the padding entries should not be relied upon.
*
* If n == XCHAL_MPU_ENTRIES then the complete map as specified by fg is
* written.
*
* The CACHEADRDIS register will be set to enable caching any 512MB region
* that is overlapped by an MPU region with a cacheable memory type.
* Caching will be disabled if none of the 512 MB region is cacheable.
*
* xthal_write_map() disables the MPU foreground map during the MPU
* update and relies on the background map.
*
* As a result any interrupt that does not meet the following conditions
* must be disabled before calling xthal_write_map():
* 1) All code and data needed for the interrupt must be
* mapped by the background map with sufficient access rights.
* 2) The interrupt code must not access the MPU.
*
*/
extern void xthal_write_map(const struct xthal_MPU_entry* entries, uint32_t n);
/*
* Checks if entry vector 'entries' of length 'n' is a valid MPU access map.
* Returns:
* XTHAL_SUCCESS if valid,
* XTHAL_OUT_OF_ENTRIES
* XTHAL_MAP_NOT_ALIGNED,
* XTHAL_BAD_ACCESS_RIGHTS,
* XTHAL_OUT_OF_ORDER_MAP, or
* XTHAL_UNSUPPORTED if config doesn't have an MPU.
*/
extern int xthal_check_map(const struct xthal_MPU_entry* entries, uint32_t n);
/*
* Returns the MPU entry that maps 'vaddr'. If 'infgmap' is non-NULL then
* *infgmap is set to 1 if 'vaddr' is mapped by the foreground map, and
* *infgmap is set to 0 if 'vaddr' is mapped by the background map.
*/
extern struct xthal_MPU_entry xthal_get_entry_for_address(void* vaddr,
int32_t* infgmap);
/*
* Scans the supplied MPU map and returns a value suitable for writing to
* the CACHEADRDIS register:
* Bits 0-7 -> 1 if there are no cacheable areas in the corresponding 512MB
* region and 0 otherwise.
* Bits 8-31 -> undefined.
* This function can accept a partial memory map in the same manner
* xthal_write_map() does, */
extern uint32_t
xthal_calc_cacheadrdis(const struct xthal_MPU_entry* e, uint32_t n);
/*
* This function is intended as an MPU specific version of
* xthal_set_region_attributes(). xthal_set_region_attributes() calls
* this function for MPU configurations.
*
* This function sets the attributes for the region [vaddr, vaddr+size)
* in the MPU.
*
* Depending on the state of the MPU this function will require from
* 0 to 3 unused MPU entries.
*
* This function typically will move, add, and subtract entries from
* the MPU map during execution, so that the resulting map may
* be quite different than when the function was called.
*
* This function does make the following guarantees:
* 1) The MPU access map remains in a valid state at all times
* during its execution.
* 2) At all points during (and after) completion the memoryType
* and accessRights remain the same for all addresses
* that are not in the range [vaddr, vaddr+size).
* 3) If XTHAL_SUCCESS is returned, then the range
* [vaddr, vaddr+size) will have the accessRights and memoryType
* specified.
* 4) The CACHEADRDIS register will be set to enable caching any 512MB region
* that is overlapped by an MPU region with a cacheable memory type.
* Caching will be disabled if none of the 512 MB region is cacheable.
*
* The accessRights parameter should be either a 4-bit value corresponding
* to an MPU access mode (as defined by the XTHAL_AR_.. constants), or
* XTHAL_MPU_USE_EXISTING_ACCESS_RIGHTS.
*
* The memoryType parameter should be either a bit-wise or-ing of XTHAL_MEM_..
* constants that represent a valid MPU memoryType, a 9-bit MPU memoryType
* value, or XTHAL_MPU_USE_EXISTING_MEMORY_TYPE.
*
* In addition to the error codes that xthal_set_region_attribute()
* returns, this function can also return: XTHAL_BAD_ACCESS_RIGHTS
* (if the access rights bits map to an unsupported combination), or
* XTHAL_OUT_OF_MAP_ENTRIES (if there are not enough unused MPU entries)
*
* If this function is called with an invalid MPU map, then this function
* will return one of the codes that is returned by xthal_check_map().
*
* The flag, XTHAL_CAFLAG_EXPAND, is not supported
*
*/
extern int xthal_mpu_set_region_attribute(void* vaddr, size_t size,
int32_t accessRights, int32_t memoryType, uint32_t flags);
/* The following are internal implementation macros. These should not
* be directly used except by the hal code and headers.
*/
/*
* Layout of the MPU specifier for: XTHAL_ENCODE_MEMORY_TYPE(),
* xthal_encode_memory_type(), xthal_set_region_attribute(),
* and xthal_mpu_set_region_attribute(). THIS IS SUBJECT TO CHANGE:
*
* Bits 0-3 - reserved for pass through of accessRights
* Bits 4-12 - reserved for pass through of memoryType bits
* Bit 13 - indicates to use existing access rights of region
* Bit 14 - indicates to use existing memory type of region
* Bit 15 - indicates device
* Bit 16-19- system cache properties
* Bit 20-23- local cache properties
* Bit 24 - indicates bufferable
* Bit 25-26- encodes shareability (1=inner, 2=outer, 3=system)
* Bit 27 - indicates interruptible
* Bits 28-31- reserved for future use
*/
#define _XTHAL_SYSTEM_CACHE_BITS 0x000f0000
#define _XTHAL_LOCAL_CACHE_BITS 0x00f00000
#define _XTHAL_MEM_SYSTEM_RWC_MASK 0x00070000
#define _XTHAL_MEM_LOCAL_RWC_MASK 0x00700000
#define _XTHAL_SHIFT_RWC 16
#define _XTHAL_MEM_ANY_SHAREABLE(x) (((x) & XTHAL_MEM_SYSTEM_SHAREABLE) ? 1 : 0)
#define _XTHAL_MEM_INNER_SHAREABLE(x) ((((x) & XTHAL_MEM_SYSTEM_SHAREABLE) \
== XTHAL_MEM_INNER_SHAREABLE) ? 1 : 0)
#define _XTHAL_MEM_IS_BUFFERABLE(x) (((x) & XTHAL_MEM_BUFFERABLE) ? 1 : 0)
#define _XTHAL_MEM_IS_DEVICE(x) (((x) & XTHAL_MEM_DEVICE) ? 1 : 0)
#define _XTHAL_NON_CACHEABLE_DOMAIN(x) \
(_XTHAL_MEM_IS_DEVICE(x) || _XTHAL_MEM_ANY_SHAREABLE(x)? 0x3 : 0)
#define _XTHAL_CACHEABLE_DOMAIN(x) (_XTHAL_MEM_ANY_SHAREABLE(x) ? \
0x3 : 0x1)
#define _XTHAL_MEM_CACHE_MASK(x) ((x) & _XTHAL_SYSTEM_CACHE_BITS)
#define _XTHAL_IS_SYSTEM_NONCACHEABLE(x) \
(((_XTHAL_MEM_CACHE_MASK(x) & XTHAL_MEM_NON_CACHEABLE) == \
XTHAL_MEM_NON_CACHEABLE) ? 1 : 0)
#define _XTHAL_ENCODE_DEVICE(x) \
(((((x) & XTHAL_MEM_INTERRUPTIBLE) ? 1 : 0) << 3) | \
(_XTHAL_NON_CACHEABLE_DOMAIN(x) << 1) | _XTHAL_MEM_IS_BUFFERABLE(x))
#define _XTHAL_ENCODE_SYSTEM_NONCACHEABLE(x) \
(0x18 | (_XTHAL_NON_CACHEABLE_DOMAIN(x) << 1) \
| _XTHAL_MEM_IS_BUFFERABLE(x))
#define _XTHAL_ENCODE_SYSTEM_CACHEABLE(x) \
(((((((x) & _XTHAL_LOCAL_CACHE_BITS) >> 4) & XTHAL_MEM_NON_CACHEABLE) == \
XTHAL_MEM_NON_CACHEABLE) ? 1 : 0) ? \
(_XTHAL_CACHEABLE_DOMAIN(x) << 4) : \
_XTHAL_ENCODE_SYSTEM_CACHEABLE_LOCAL_CACHEABLE(x)) | \
((_XTHAL_MEM_INNER_SHAREABLE(x) << 3) | \
(_XTHAL_MEM_CACHE_MASK(x) & _XTHAL_MEM_SYSTEM_RWC_MASK) \
>> _XTHAL_SHIFT_RWC)
#define _XTHAL_ENCODE_SYSTEM_CACHEABLE_LOCAL_CACHEABLE(x) \
((_XTHAL_CACHEABLE_DOMAIN(x) << 7) | (((((x) & _XTHAL_LOCAL_CACHE_BITS) ? \
((x) & _XTHAL_LOCAL_CACHE_BITS) : \
(_XTHAL_MEM_CACHE_MASK(x) << 4)) \
& (_XTHAL_MEM_LOCAL_RWC_MASK)) >> _XTHAL_SHIFT_RWC ))
/* End of internal macros */
/* The functions and constants below here have been deprecated.*/
#define XTHAL_MEM_NON_CACHED XTHAL_MEM_NON_CACHEABLE
#define XTHAL_MEM_NON_SHARED XTHAL_MEM_NON_SHAREABLE
#define XTHAL_MEM_INNER_SHARED XTHAL_MEM_INNER_SHAREABLE
#define XTHAL_MEM_OUTER_SHARED XTHAL_MEM_OUTER_SHAREABLE
#define XTHAL_MEM_SYSTEM_SHARED XTHAL_MEM_SYSTEM_SHAREABLE
#define XTHAL_MEM_SW_SHAREABLE 0
#define xthal_is_cached(memoryType) (xthal_is_cacheable((memoryType)))
extern int32_t xthal_read_background_map(struct xthal_MPU_entry* entries);
/* end deprecated functions and constants */
#ifdef __cplusplus
}
#endif
@ -970,18 +1466,6 @@ extern int xthal_set_region_translation_raw(void *vaddr, void *paddr, unsigned c
extern "C" {
#endif
#ifdef INCLUDE_DEPRECATED_HAL_CODE
extern const unsigned char Xthal_have_old_exc_arch;
extern const unsigned char Xthal_have_mmu;
extern const unsigned int Xthal_num_regs;
extern const unsigned char Xthal_num_iroms;
extern const unsigned char Xthal_num_irams;
extern const unsigned char Xthal_num_droms;
extern const unsigned char Xthal_num_drams;
extern const unsigned int Xthal_configid0;
extern const unsigned int Xthal_configid1;
#endif
#ifdef INCLUDE_DEPRECATED_HAL_DEBUG_CODE
#define XTHAL_24_BIT_BREAK 0x80000000
#define XTHAL_16_BIT_BREAK 0x40000000

72
components/xtensa/include/xtensa/idmaasm.h 100644
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@ -0,0 +1,72 @@
/* $Id: //depot/dev/Foxhill/Xtensa/OS/include/xtensa/mpuasm.h#5 $ */
/*
* Copyright (c) 2016 Cadence Design Systems, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _IDMAASM_H_
#define _IDMAASM_H_
#if XCHAL_HAVE_IDMA
#include <xtensa/idma.h>
#endif
/*
* Macro for restore IDMA regs
*
* Parameters:
* a_save => address register containing pointer to IDMA save area
* a_temp1, a_temp2, a_temp3. => address register temporaries
*/
// IDMA_REG_SETTINGS,
// IDMA_REG_TIMEOUT,
// IDMA_REG_DESC_START,
// IDMA_REG_CONTROL,
// IDMA_REG_USERPRIV,
.macro _idma_restore a_save, a_temp1, a_temp2, a_temp3
#if XCHAL_HAVE_IDMA
l32i \a_temp1, \a_save, 0
movi \a_temp3, idmareg_base
movi \a_temp2, IDMA_REG_SETTINGS
add \a_temp2, \a_temp2, \a_temp3
wer \a_temp1, \a_temp2
l32i \a_temp1, \a_save, 4
movi \a_temp2, IDMA_REG_TIMEOUT
add \a_temp2, \a_temp2, \a_temp3
wer \a_temp1, \a_temp2
l32i \a_temp1, \a_save, 8
movi \a_temp2, IDMA_REG_DESC_START
add \a_temp2, \a_temp2, \a_temp3
wer \a_temp1, \a_temp2
l32i \a_temp1, \a_save, 12
movi \a_temp2, IDMA_REG_CONTROL
add \a_temp2, \a_temp2, \a_temp3
wer \a_temp1, \a_temp2
l32i \a_temp1, \a_save, 16
movi \a_temp2, IDMA_REG_USERPRIV
add \a_temp2, \a_temp2, \a_temp3
wer \a_temp1, \a_temp2
#endif
.endm
#endif //_IDMAASM_H_

111
components/xtensa/include/xtensa/mpuasm.h 100644
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@ -0,0 +1,111 @@
/* $Id: //depot/dev/Foxhill/Xtensa/OS/include/xtensa/mpuasm.h#5 $ */
/*
* Copyright (c) 2016 Cadence Design Systems, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _MPUASM_H_
#define _MPUASM_H_
#include <xtensa/config/core.h>
/*
* Macro for writing MPU map.
*
* Parameters:
* a_map => address register containing pointer to MPU map
* a_num_entries => number of entries in the forementioned map
* a_temp1, a_temp2. => address register temporaries
* a_temp3, a_temp4
*/
.macro mpu_write_map a_map, a_num_entries, a_temp1, a_temp2, a_temp3, a_temp4
#if XCHAL_HAVE_MPU
movi \a_temp1, 0
wsr.cacheadrdis \a_temp1 // enable the cache in all regions
wsr.mpuenb \a_temp1 // disable all foreground entries
// Clear out the unused entries.
//
// Currently we are clearing out all the entries because currently
// the entries must be ordered even if they are all disabled.
// If out of order entries were permitted when all are disabled,
// performance could be improved by clearing XCHAL_MPU_ENTRIES - n
// (n = number of entries) rather than XCHAL_MPU_ENTRIES - 1 entries.
//
movi \a_temp2, 0
movi \a_temp3, XCHAL_MPU_ENTRIES - 1
j 1f
.align 16 // this alignment is done to ensure that
1:
memw // todo currently wptlb must be preceeded by a memw. The instructions must
// be aligned to ensure that both are in the same cache line. These statements should be
// properly conditionalized when that restriction is removed from the HW
wptlb \a_temp2, \a_temp1
addi \a_temp2, \a_temp2, 1
bltu \a_temp2, \a_temp3, 1b
// Write the new entries.
//
beqz \a_num_entries, 4f // if no entries, skip loop
addx8 \a_map, \a_num_entries, \a_map // compute end of provided map
j 3f
.align 16
2: memw // todo currently wptlb must be preceeded by a memw. The instructions must
// be aligned to ensure that both are in the same cache line. These statements should be
// properly conditionalized when that restriction is removed from the HW
wptlb \a_temp2, \a_temp4
addi \a_temp3, \a_temp3, -1
beqz \a_num_entries, 4f // loop until done
3: addi \a_map, \a_map, -8
l32i \a_temp2, \a_map, 4 // get at (acc.rights, memtype)
l32i \a_temp4, \a_map, 0 // get as (vstart, valid)
addi \a_num_entries, \a_num_entries, -1
extui \a_temp1, \a_temp2, 0, 5 // entry index portion
xor \a_temp2, \a_temp2, \a_temp1 // zero it
or \a_temp2, \a_temp2, \a_temp3 // set index = \a_temp3
j 2b
4:
#endif
.endm
/*
* Macro for reading MPU map
*
* Parameters:
* a_map_ptr => address register pointing to memory where map is written
* a_temp1, a_temp2 => address register temporaries
*/
.macro mpu_read_map a_map_ptr, a_temp1, a_temp2
#if XCHAL_HAVE_MPU
movi \a_temp1, XCHAL_MPU_ENTRIES // set index to last entry + 1
addx8 \a_map_ptr, \a_temp1, \a_map_ptr // set map ptr to last entry + 1
1: addi \a_temp1, \a_temp1, -1 // decrement index
addi \a_map_ptr, \a_map_ptr, -8 // decrement index
rptlb0 \a_temp2, \a_temp1 // read 1/2 of entry
s32i \a_temp2, \a_map_ptr, 0 // write 1/2 of entry
rptlb1 \a_temp2, \a_temp1
s32i \a_temp2, \a_map_ptr, 4
bnez \a_temp1, 1b // loop until done
#endif
.endm
#endif

5
components/xtensa/include/xtensa/specreg.h
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@ -2,7 +2,7 @@
* Xtensa Special Register symbolic names
*/
/* $Id: //depot/rel/Eaglenest/Xtensa/OS/include/xtensa/specreg.h#2 $ */
/* $Id: //depot/rel/Foxhill/dot.9/Xtensa/OS/include/xtensa/specreg.h#1 $ */
/*
* Copyright (c) 2005-2011 Tensilica Inc.
@ -53,7 +53,8 @@
#define DTLBCFG 92
#define IBREAKENABLE 96
#define MEMCTL 97
#define CACHEATTR 98
#define CACHEATTR 98 /* until T1050, XEA1 */
#define CACHEADRDIS 98 /* LX7+ */
#define ATOMCTL 99
#define DDR 104
#define MECR 110

15
components/xtensa/include/xtensa/traxreg.h
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@ -65,8 +65,7 @@
#define TRAX_ID_PRODNO 0xf0000000 /* product number (0=TRAX) */
#define TRAX_ID_PRODOPT 0x0f000000 /* product options */
#define TRAX_ID_MIW64 0x08000000 /* opt: instruction width */
#define TRAX_ID_AMTRAX 0x04000000 /* opt: collection of options,
internal (VER_2_0 or later)*/
#define TRAX_ID_AMTRAX 0x04000000 /* opt: collection of options, internal (VER_2_0 or later)*/
#define TRAX_ID_MAJVER(id) (((id) >> 20) & 0x0f)
#define TRAX_ID_MINVER(id) (((id) >> 17) & 0x07)
#define TRAX_ID_VER(id) ((TRAX_ID_MAJVER(id)<<4)|TRAX_ID_MINVER(id))
@ -78,14 +77,11 @@
/* TRAX versions of interest (TRAX_ID_VER(), ie. MAJVER*16 + MINVER): */
#define TRAX_VER_1_0 0x10 /* RA */
#define TRAX_VER_1_1 0x11 /* RB thru RC-2010.1 */
#define TRAX_VER_2_0 0x20 /* RC-2010.2, RD-2010.0,
RD-2011.1 */
#define TRAX_VER_2_1 0x21 /* RC-2011.3 / RD-2011.2 and
later */
#define TRAX_VER_2_0 0x20 /* RC-2010.2, RD-2010.0, RD-2011.1 */
#define TRAX_VER_2_1 0x21 /* RC-2011.3 / RD-2011.2 and later */
#define TRAX_VER_3_0 0x30 /* RE-2012.0 */
#define TRAX_VER_3_1 0x31 /* RE-2012.1 */
#define TRAX_VER_HUAWEI_3 TRAX_VER_3_0 /* For Huawei, PRs: 25223, 25224
, 24880 */
#define TRAX_VER_HUAWEI_3 TRAX_VER_3_0 /* For Huawei, PRs: 25223, 25224, 24880 */
/* TRAX version 1.0 requires a couple software workarounds: */
@ -181,7 +177,8 @@ typedef struct {
extern const trax_regdef_t trax_reglist[];
extern const signed char trax_readable_regs[];
extern const signed int trax_readable_regs[];
extern const signed int trax_unamed_header_regs[];
#ifdef __cplusplus
extern "C" {

298
components/xtensa/include/xtensa/xdm-regs.h
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@ -1,7 +1,7 @@
/* xdm-regs.h - Common register and related definitions for the XDM
(Xtensa Debug Module) */
/* Copyright (c) 2011-2012 Tensilica Inc.
/* Copyright (c) 2016 Cadence Design Systems Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
@ -48,110 +48,113 @@
/* XDM_.... ERI addr [NAR addr] Description...... */
/* TRAX */
#define XDM_TRAX_ID 0x0000 /*[0x00] ID */
#define XDM_TRAX_CONTROL 0x0004 /*[0x01] Control */
#define XDM_TRAX_STATUS 0x0008 /*[0x02] Status */
#define XDM_TRAX_DATA 0x000C /*[0x03] Data */
#define XDM_TRAX_ADDRESS 0x0010 /*[0x04] Address */
#define XDM_TRAX_TRIGGER 0x0014 /*[0x05] Stop PC */
#define XDM_TRAX_MATCH 0x0018 /*[0x06] Stop PC Range */
#define XDM_TRAX_DELAY 0x001C /*[0x07] Post Stop Trigger Capture Size */
#define XDM_TRAX_STARTADDR 0x0020 /*[0x08] Trace Memory Start */
#define XDM_TRAX_ENDADDR 0x0024 /*[0x09] Trace Memory End */
#define XDM_TRAX_DEBUGPC 0x003C /*[0x0F] Debug PC */
#define XDM_TRAX_P4CHANGE 0x0040 /*[0x10] X */
#define XDM_TRAX_TIME0 0x0040 /*[0x10] First Time Register */
#define XDM_TRAX_P4REV 0x0044 /*[0x11] X */
#define XDM_TRAX_TIME1 0x0044 /*[0x11] Second Time Register */
#define XDM_TRAX_P4DATE 0x0048 /*[0x12] X */
#define XDM_TRAX_INTTIME_MAX 0x0048 /*[0x12] maximal Value of Timestamp IntTime */
#define XDM_TRAX_P4TIME 0x004C /*[0x13] X */
#define XDM_TRAX_PDSTATUS 0x0050 /*[0x14] Sample of PDebugStatus */
#define XDM_TRAX_PDDATA 0x0054 /*[0x15] Sample of PDebugData */
#define XDM_TRAX_STOP_PC 0x0058 /*[0x16] X */
#define XDM_TRAX_STOP_ICNT 0x005C /*[0x16] X */
#define XDM_TRAX_MSG_STATUS 0x0060 /*[0x17] X */
#define XDM_TRAX_FSM_STATUS 0x0064 /*[0x18] X */
#define XDM_TRAX_IB_STATUS 0x0068 /*[0x19] X */
#define XDM_TRAX_STOPCNT 0x006C /*[0x1A] X */
#define XDM_TRAX_ID 0x100000 /*[0x00] ID */
#define XDM_TRAX_CONTROL 0x100004 /*[0x01] Control */
#define XDM_TRAX_STATUS 0x100008 /*[0x02] Status */
#define XDM_TRAX_DATA 0x10000C /*[0x03] Data */
#define XDM_TRAX_ADDRESS 0x100010 /*[0x04] Address */
#define XDM_TRAX_TRIGGER 0x100014 /*[0x05] Stop PC */
#define XDM_TRAX_MATCH 0x100018 /*[0x06] Stop PC Range */
#define XDM_TRAX_DELAY 0x10001C /*[0x07] Post Stop Trigger Capture Size */
#define XDM_TRAX_STARTADDR 0x100020 /*[0x08] Trace Memory Start */
#define XDM_TRAX_ENDADDR 0x100024 /*[0x09] Trace Memory End */
#define XDM_TRAX_DEBUGPC 0x10003C /*[0x0F] Debug PC */
#define XDM_TRAX_P4CHANGE 0x100040 /*[0x10] X */
#define XDM_TRAX_TIME0 0x100040 /*[0x10] First Time Register */
#define XDM_TRAX_P4REV 0x100044 /*[0x11] X */
#define XDM_TRAX_TIME1 0x100044 /*[0x11] Second Time Register */
#define XDM_TRAX_P4DATE 0x100048 /*[0x12] X */
#define XDM_TRAX_INTTIME_MAX 0x100048 /*[0x12] maximal Value of Timestamp IntTime */
#define XDM_TRAX_P4TIME 0x10004C /*[0x13] X */
#define XDM_TRAX_PDSTATUS 0x100050 /*[0x14] Sample of PDebugStatus */
#define XDM_TRAX_PDDATA 0x100054 /*[0x15] Sample of PDebugData */
#define XDM_TRAX_STOP_PC 0x100058 /*[0x16] X */
#define XDM_TRAX_STOP_ICNT 0x10005C /*[0x16] X */
#define XDM_TRAX_MSG_STATUS 0x100060 /*[0x17] X */
#define XDM_TRAX_FSM_STATUS 0x100064 /*[0x18] X */
#define XDM_TRAX_IB_STATUS 0x100068 /*[0x19] X */
#define XDM_TRAX_STOPCNT 0x10006C /*[0x1A] X */
/* Performance Monitoring Counters */
#define XDM_PERF_PMG 0x1000 /*[0x20] perf. mon. global control register */
#define XDM_PERF_INTPC 0x1010 /*[0x24] perf. mon. interrupt PC */
#define XDM_PERF_PM0 0x1080 /*[0x28] perf. mon. counter 0 value */
#define XDM_PERF_PM1 0x1084 /*[0x29] perf. mon. counter 1 value */
#define XDM_PERF_PM2 0x1088 /*[0x2A] perf. mon. counter 2 value */
#define XDM_PERF_PM3 0x108C /*[0x2B] perf. mon. counter 3 value */
#define XDM_PERF_PM4 0x1090 /*[0x2C] perf. mon. counter 4 value */
#define XDM_PERF_PM5 0x1094 /*[0x2D] perf. mon. counter 5 value */
#define XDM_PERF_PM6 0x1098 /*[0x2E] perf. mon. counter 6 value */
#define XDM_PERF_PM7 0x109C /*[0x2F] perf. mon. counter 7 value */
#define XDM_PERF_PM(n) (0x1080+((n)<<2)) /* perfmon cnt n=0..7 value */
#define XDM_PERF_PMCTRL0 0x1100 /*[0x30] perf. mon. counter 0 control */
#define XDM_PERF_PMCTRL1 0x1104 /*[0x31] perf. mon. counter 1 control */
#define XDM_PERF_PMCTRL2 0x1108 /*[0x32] perf. mon. counter 2 control */
#define XDM_PERF_PMCTRL3 0x110C /*[0x33] perf. mon. counter 3 control */
#define XDM_PERF_PMCTRL4 0x1110 /*[0x34] perf. mon. counter 4 control */
#define XDM_PERF_PMCTRL5 0x1114 /*[0x35] perf. mon. counter 5 control */
#define XDM_PERF_PMCTRL6 0x1118 /*[0x36] perf. mon. counter 6 control */
#define XDM_PERF_PMCTRL7 0x111C /*[0x37] perf. mon. counter 7 control */
#define XDM_PERF_PMCTRL(n) (0x1100+((n)<<2)) /* perfmon cnt n=0..7 control */
#define XDM_PERF_PMSTAT0 0x1180 /*[0x38] perf. mon. counter 0 status */
#define XDM_PERF_PMSTAT1 0x1184 /*[0x39] perf. mon. counter 1 status */
#define XDM_PERF_PMSTAT2 0x1188 /*[0x3A] perf. mon. counter 2 status */
#define XDM_PERF_PMSTAT3 0x118C /*[0x3B] perf. mon. counter 3 status */
#define XDM_PERF_PMSTAT4 0x1190 /*[0x3C] perf. mon. counter 4 status */
#define XDM_PERF_PMSTAT5 0x1194 /*[0x3D] perf. mon. counter 5 status */
#define XDM_PERF_PMSTAT6 0x1198 /*[0x3E] perf. mon. counter 6 status */
#define XDM_PERF_PMSTAT7 0x119C /*[0x3F] perf. mon. counter 7 status */
#define XDM_PERF_PMSTAT(n) (0x1180+((n)<<2)) /* perfmon cnt n=0..7 status */
#define XDM_PERF_PMG 0x101000 /*[0x20] perf. mon. global control register */
#define XDM_PERF_INTPC 0x101010 /*[0x24] perf. mon. interrupt PC */
#define XDM_PERF_PM0 0x101080 /*[0x28] perf. mon. counter 0 value */
#define XDM_PERF_PM1 0x101084 /*[0x29] perf. mon. counter 1 value */
#define XDM_PERF_PM2 0x101088 /*[0x2A] perf. mon. counter 2 value */
#define XDM_PERF_PM3 0x10108C /*[0x2B] perf. mon. counter 3 value */
#define XDM_PERF_PM4 0x101090 /*[0x2C] perf. mon. counter 4 value */
#define XDM_PERF_PM5 0x101094 /*[0x2D] perf. mon. counter 5 value */
#define XDM_PERF_PM6 0x101098 /*[0x2E] perf. mon. counter 6 value */
#define XDM_PERF_PM7 0x10109C /*[0x2F] perf. mon. counter 7 value */
#define XDM_PERF_PM(n) (0x101080+((n)<<2)) /* perfmon cnt n=0..7 value */
#define XDM_PERF_PMCTRL0 0x101100 /*[0x30] perf. mon. counter 0 control */
#define XDM_PERF_PMCTRL1 0x101104 /*[0x31] perf. mon. counter 1 control */
#define XDM_PERF_PMCTRL2 0x101108 /*[0x32] perf. mon. counter 2 control */
#define XDM_PERF_PMCTRL3 0x10110C /*[0x33] perf. mon. counter 3 control */
#define XDM_PERF_PMCTRL4 0x101110 /*[0x34] perf. mon. counter 4 control */
#define XDM_PERF_PMCTRL5 0x101114 /*[0x35] perf. mon. counter 5 control */
#define XDM_PERF_PMCTRL6 0x101118 /*[0x36] perf. mon. counter 6 control */
#define XDM_PERF_PMCTRL7 0x10111C /*[0x37] perf. mon. counter 7 control */
#define XDM_PERF_PMCTRL(n) (0x101100+((n)<<2)) /* perfmon cnt n=0..7 control */
#define XDM_PERF_PMSTAT0 0x101180 /*[0x38] perf. mon. counter 0 status */
#define XDM_PERF_PMSTAT1 0x101184 /*[0x39] perf. mon. counter 1 status */
#define XDM_PERF_PMSTAT2 0x101188 /*[0x3A] perf. mon. counter 2 status */
#define XDM_PERF_PMSTAT3 0x10118C /*[0x3B] perf. mon. counter 3 status */
#define XDM_PERF_PMSTAT4 0x101190 /*[0x3C] perf. mon. counter 4 status */
#define XDM_PERF_PMSTAT5 0x101194 /*[0x3D] perf. mon. counter 5 status */
#define XDM_PERF_PMSTAT6 0x101198 /*[0x3E] perf. mon. counter 6 status */
#define XDM_PERF_PMSTAT7 0x10119C /*[0x3F] perf. mon. counter 7 status */
#define XDM_PERF_PMSTAT(n) (0x101180+((n)<<2)) /* perfmon cnt n=0..7 status */
/* On-Chip-Debug (OCD) */
#define XDM_OCD_ID 0x2000 /*[0x40] ID register */
#define XDM_OCD_DCR_CLR 0x2008 /*[0x42] Debug Control reg clear */
#define XDM_OCD_DCR_SET 0x200C /*[0x43] Debug Control reg set */
#define XDM_OCD_DSR 0x2010 /*[0x44] Debug Status reg */
#define XDM_OCD_DDR 0x2014 /*[0x45] Debug Data reg */
#define XDM_OCD_DDREXEC 0x2018 /*[0x46] Debug Data reg + execute-DIR */
#define XDM_OCD_DIR0EXEC 0x201C /*[0x47] Debug Instruction reg, word 0 + execute-DIR */
#define XDM_OCD_DIR0 0x2020 /*[0x48] Debug Instruction reg, word 1 */
#define XDM_OCD_DIR1 0x2024 /*[0x49] Debug Instruction reg, word 2 */
#define XDM_OCD_DIR2 0x2028 /*[0x4A] Debug Instruction reg, word 3 */
#define XDM_OCD_DIR3 0x202C /*[0x49] Debug Instruction reg, word 4 */
#define XDM_OCD_DIR4 0x2030 /*[0x4C] Debug Instruction reg, word 5 */
#define XDM_OCD_DIR5 0x2034 /*[0x4D] Debug Instruction reg, word 5 */
#define XDM_OCD_DIR6 0x2038 /*[0x4E] Debug Instruction reg, word 6 */
#define XDM_OCD_DIR7 0x203C /*[0x4F] Debug Instruction reg, word 7 */
#define XDM_OCD_ID 0x102000 /*[0x40] ID register */
#define XDM_OCD_DCR_CLR 0x102008 /*[0x42] Debug Control reg clear */
#define XDM_OCD_DCR_SET 0x10200C /*[0x43] Debug Control reg set */
#define XDM_OCD_DSR 0x102010 /*[0x44] Debug Status reg */
#define XDM_OCD_DDR 0x102014 /*[0x45] Debug Data reg */
#define XDM_OCD_DDREXEC 0x102018 /*[0x46] Debug Data reg + execute-DIR */
#define XDM_OCD_DIR0EXEC 0x10201C /*[0x47] Debug Instruction reg, word 0 + execute-DIR */
#define XDM_OCD_DIR0 0x102020 /*[0x48] Debug Instruction reg, word 1 */
#define XDM_OCD_DIR1 0x102024 /*[0x49] Debug Instruction reg, word 2 */
#define XDM_OCD_DIR2 0x102028 /*[0x4A] Debug Instruction reg, word 3 */
#define XDM_OCD_DIR3 0x10202C /*[0x49] Debug Instruction reg, word 4 */
#define XDM_OCD_DIR4 0x102030 /*[0x4C] Debug Instruction reg, word 5 */
#define XDM_OCD_DIR5 0x102034 /*[0x4D] Debug Instruction reg, word 5 */
#define XDM_OCD_DIR6 0x102038 /*[0x4E] Debug Instruction reg, word 6 */
#define XDM_OCD_DIR7 0x10203C /*[0x4F] Debug Instruction reg, word 7 */
/* Miscellaneous Registers */
#define XDM_MISC_PWRCTL 0x3020 /*[0x58] Power and Reset Control */
#define XDM_MISC_PWRSTAT 0x3024 /*[0x59] Power and Reset Status */
#define XDM_MISC_ERISTAT 0x3028 /*[0x5A] ERI Transaction Status */
#define XDM_MISC_DATETIME 0x3034 /*[0x5D] [INTERNAL] Timestamps of build */
#define XDM_MISC_UBID 0x3038 /*[0x5E] [INTERNAL] Build Unique ID */
#define XDM_MISC_CID 0x303C /*[0x5F] [INTERNAL] Customer ID */
#define XDM_MISC_PWRCTL 0x103020 /*[0x58] Power and Reset Control */
#define XDM_MISC_PWRSTAT 0x103024 /*[0x59] Power and Reset Status */
#define XDM_MISC_ERISTAT 0x103028 /*[0x5A] ERI Transaction Status */
#define XDM_MISC_DATETIME 0x103034
#define XDM_MISC_CONFIGID1_V0 0x103034 /*[0x5D] [INTERNAL] ConfigID1 in XDM v0/1 */
#define XDM_MISC_CONFIGID1_V2 0x10007c /*[0x1F] [INTERNAL] ConfigID1 since XDM v2 */
#define XDM_MISC_CONFIGID0_V2 0x100078 /*[0x1E] [INTERNAL] ConfigID0 since XDM v2 */
#define XDM_MISC_UBID 0x103038 /*[0x5E] [INTERNAL] Build Unique ID */
#define XDM_MISC_CID 0x10303C /*[0x5F] [INTERNAL] Customer ID */
/* CoreSight compatibility */
#define XDM_CS_ITCTRL 0x3F00 /*[0x60] InTegration Mode control reg */
#define XDM_CS_CLAIMSET 0x3FA0 /*[0x68] Claim Tag Set reg */
#define XDM_CS_CLAIMCLR 0x3FA4 /*[0x69] Claim Tag Clear reg */
#define XDM_CS_LOCK_ACCESS 0x3FB0 /*[0x6B] Lock Access (writing 0xC5ACCE55 unlocks) */
#define XDM_CS_LOCK_STATUS 0x3FB4 /*[0x6D] Lock Status */
#define XDM_CS_AUTH_STATUS 0x3FB8 /*[0x6E] Authentication Status */
#define XDM_CS_DEV_ID 0x3FC8 /*[0x72] Device ID */
#define XDM_CS_DEV_TYPE 0x3FCC /*[0x73] Device Type */
#define XDM_CS_PER_ID4 0x3FD0 /*[0x74] Peripheral ID reg byte 4 */
#define XDM_CS_PER_ID5 0x3FD4 /*[0x75] Peripheral ID reg byte 5 */
#define XDM_CS_PER_ID6 0x3FD8 /*[0x76] Peripheral ID reg byte 6 */
#define XDM_CS_PER_ID7 0x3FDC /*[0x77] Peripheral ID reg byte 7 */
#define XDM_CS_PER_ID0 0x3FE0 /*[0x78] Peripheral ID reg byte 0 */
#define XDM_CS_PER_ID1 0x3FE4 /*[0x79] Peripheral ID reg byte 1 */
#define XDM_CS_PER_ID2 0x3FE8 /*[0x7A] Peripheral ID reg byte 2 */
#define XDM_CS_PER_ID3 0x3FEC /*[0x7B] Peripheral ID reg byte 3 */
#define XDM_CS_COMP_ID0 0x3FF0 /*[0x7C] Component ID reg byte 0 */
#define XDM_CS_COMP_ID1 0x3FF4 /*[0x7D] Component ID reg byte 1 */
#define XDM_CS_COMP_ID2 0x3FF8 /*[0x7E] Component ID reg byte 2 */
#define XDM_CS_COMP_ID3 0x3FFC /*[0x7F] Component ID reg byte 3 */
#define XDM_CS_ITCTRL 0x103F00 /*[0x60] InTegration Mode control reg */
#define XDM_CS_CLAIMSET 0x103FA0 /*[0x68] Claim Tag Set reg */
#define XDM_CS_CLAIMCLR 0x103FA4 /*[0x69] Claim Tag Clear reg */
#define XDM_CS_LOCK_ACCESS 0x103FB0 /*[0x6B] Lock Access (writing 0xC5ACCE55 unlocks) */
#define XDM_CS_LOCK_STATUS 0x103FB4 /*[0x6D] Lock Status */
#define XDM_CS_AUTH_STATUS 0x103FB8 /*[0x6E] Authentication Status */
#define XDM_CS_DEV_ID 0x103FC8 /*[0x72] Device ID */
#define XDM_CS_DEV_TYPE 0x103FCC /*[0x73] Device Type */
#define XDM_CS_PER_ID4 0x103FD0 /*[0x74] Peripheral ID reg byte 4 */
#define XDM_CS_PER_ID5 0x103FD4 /*[0x75] Peripheral ID reg byte 5 */
#define XDM_CS_PER_ID6 0x103FD8 /*[0x76] Peripheral ID reg byte 6 */
#define XDM_CS_PER_ID7 0x103FDC /*[0x77] Peripheral ID reg byte 7 */
#define XDM_CS_PER_ID0 0x103FE0 /*[0x78] Peripheral ID reg byte 0 */
#define XDM_CS_PER_ID1 0x103FE4 /*[0x79] Peripheral ID reg byte 1 */
#define XDM_CS_PER_ID2 0x103FE8 /*[0x7A] Peripheral ID reg byte 2 */
#define XDM_CS_PER_ID3 0x103FEC /*[0x7B] Peripheral ID reg byte 3 */
#define XDM_CS_COMP_ID0 0x103FF0 /*[0x7C] Component ID reg byte 0 */
#define XDM_CS_COMP_ID1 0x103FF4 /*[0x7D] Component ID reg byte 1 */
#define XDM_CS_COMP_ID2 0x103FF8 /*[0x7E] Component ID reg byte 2 */
#define XDM_CS_COMP_ID3 0x103FFC /*[0x7F] Component ID reg byte 3 */
#define CS_PER_ID0 0x00000003
#define CS_PER_ID1 0x00000021
@ -168,7 +171,9 @@
#define XTENSA_IDCODE 0x120034e5 // FIXME (upper bits not spec. out but BE is !)
#define XTENSA_MFC_ID (XTENSA_IDCODE & 0xFFF)
#define CS_DEV_ID XTENSA_IDCODE
#define CS_DEV_ID XTENSA_IDCODE //FIXME - for XDM v0 only, for v2 is the new ID, that includes vars like PRID but also can be custom
#define CS_DEV_ID_v0_MASK 0x00000FFF // can compare only the lower 12 bits
#define CS_DEV_ID_v2_MASK 0xF0000000 // can compare only the upper 4 bits
#define NXS_OCD_REG(val) ((val >= 0x40) && (val <= 0x5F))
#define NXS_TRAX_REG(val) val <= 0x3F
@ -197,7 +202,7 @@
: -1)
#define XDM_NAR_TO_APB(a) _XDM_NAR_TO_APB((a & 0xFFFF))
#define XDM_NAR_TO_ERI(a) _XDM_NAR_TO_APB((a & 0xFFFF)) | 0x000000
#define XDM_NAR_TO_ERI(a) _XDM_NAR_TO_APB((a & 0xFFFF)) | 0x100000
/* Convert APB to ERI address */
#define XDM_APB_TO_ERI(a) ((a) | (0x100000))
@ -213,6 +218,8 @@
#define OCD_ID_TRACEPORT 0x00000080
#define OCD_ID_TRACEPORT_SHIFT 7
#define OCD_ID_LSDDRP_XEA3 0x00000400
/* Power Status register. NOTE: different bit positions in JTAG vs. ERI/APB !! */
/* ERI/APB: */
#define PWRSTAT_CORE_DOMAIN_ON 0x00000001 /* set if core is powered on */
@ -228,7 +235,7 @@
#define PWRSTAT_MEM_DOMAIN_ON_SHIFT 8
#define PWRSTAT_DEBUG_DOMAIN_ON 0x00001000 /* set if debug domain is powered on */
#define PWRSTAT_DEBUG_DOMAIN_ON_SHIFT 12
#define PWRSTAT_ALL_ON PWRSTAT_CORE_DOMAIN_ON | PWRSTAT_MEM_DOMAIN_ON | PWRSTAT_DEBUG_DOMAIN_ON
#define PWRSTAT_ALL_ON (PWRSTAT_CORE_DOMAIN_ON | PWRSTAT_MEM_DOMAIN_ON | PWRSTAT_DEBUG_DOMAIN_ON)
#define PWRSTAT_CORE_WAS_RESET 0x00010000 /* [APB only] set if core got reset */
#define PWRSTAT_CORE_WAS_RESET_SHIFT 16
#define PWRSTAT_DEBUG_WAS_RESET 0x10000000 /* set if debug module got reset */
@ -237,7 +244,7 @@
#define J_PWRSTAT_CORE_DOMAIN_ON 0x01 /* set if core is powered on */
#define J_PWRSTAT_MEM_DOMAIN_ON 0x02 /* set if memory domain is powered on */
#define J_PWRSTAT_DEBUG_DOMAIN_ON 0x04 /* set if debug domain is powered on */
#define J_PWRSTAT_ALL_ON J_PWRSTAT_CORE_DOMAIN_ON | J_PWRSTAT_MEM_DOMAIN_ON | J_PWRSTAT_DEBUG_DOMAIN_ON
#define J_PWRSTAT_ALL_ON (J_PWRSTAT_CORE_DOMAIN_ON | J_PWRSTAT_MEM_DOMAIN_ON | J_PWRSTAT_DEBUG_DOMAIN_ON)
#define J_PWRSTAT_CORE_STILL_NEEDED 0x08 /* set if others keeping core awake */
#define J_PWRSTAT_CORE_WAS_RESET 0x10 /* set if core got reset */
#define J_PWRSTAT_DEBUG_WAS_RESET 0x40 /* set if debug module got reset */
@ -252,7 +259,7 @@
#define PWRCTL_MEM_WAKEUP_SHIFT 8
#define PWRCTL_DEBUG_WAKEUP 0x00001000 /* set to force debug domain to stay powered on */
#define PWRCTL_DEBUG_WAKEUP_SHIFT 12
#define PWRCTL_ALL_ON PWRCTL_CORE_WAKEUP | PWRCTL_MEM_WAKEUP | PWRCTL_DEBUG_WAKEUP
#define PWRCTL_ALL_ON (PWRCTL_CORE_WAKEUP | PWRCTL_MEM_WAKEUP | PWRCTL_DEBUG_WAKEUP)
#define PWRCTL_CORE_RESET 0x00010000 /* [APB only] set to assert core reset */
#define PWRCTL_CORE_RESET_SHIFT 16
#define PWRCTL_DEBUG_RESET 0x10000000 /* set to assert debug module reset */
@ -262,7 +269,7 @@
#define J_PWRCTL_MEM_WAKEUP 0x02 /* set to force memory domain to stay powered on */
#define J_PWRCTL_DEBUG_WAKEUP 0x04 /* set to force debug domain to stay powered on */
#define J_DEBUG_USE 0x80 /* */
#define J_PWRCTL_ALL_ON J_DEBUG_USE | J_PWRCTL_CORE_WAKEUP | J_PWRCTL_MEM_WAKEUP | J_PWRCTL_DEBUG_WAKEUP
#define J_PWRCTL_ALL_ON (J_DEBUG_USE | J_PWRCTL_CORE_WAKEUP | J_PWRCTL_MEM_WAKEUP | J_PWRCTL_DEBUG_WAKEUP)
#define J_PWRCTL_DEBUG_ON J_DEBUG_USE | J_PWRCTL_DEBUG_WAKEUP
#define J_PWRCTL_CORE_RESET 0x10 /* set to assert core reset */
#define J_PWRCTL_DEBUG_RESET 0x40 /* set to assert debug module reset */
@ -303,10 +310,12 @@
#define DCR_ENABLEOCD_SHIFT 0
#define DCR_DEBUG_INT 0x0000002
#define DCR_DEBUG_INT_SHIFT 1
#define DCR_DEBUG_OVERRIDE 0x0000004
#define DCR_DEBUG_OVERRIDE 0x0000004 //ER or later
#define DCR_DEBUG_OVERRIDE_SHIFT 2
#define DCR_DEBUG_INTERCEPT 0x0000008
#define DCR_DEBUG_INTERCEPT_SHIFT 3
#define DCR_DEBUG_SS_REQ 0x0000008
#define DCR_DEBUG_SS_REQ_SHIFT 3
#define DCR_DEBUG_OVERRIDE_CW 0x0000010 //RD and earlier
#define DCR_DEBUG_OVERRIDE_CW_SHIFT 4
#define DCR_MASK_NMI 0x0000020
#define DCR_MASK_NMI_SHIFT 5
#define DCR_STEP_ENABLE 0x0000040
@ -329,6 +338,10 @@
/************ Define DSR register bits **************/
#define DOSR_STOP_CAUSE_SHIFT 5
#define DOSR_STOP_CAUSE_MASK 0xF
#define DOSR_EXECDONE_SHIFT 0
#define DOSR_EXECDONE_ER 0x01
#define DOSR_EXECDONE_SHIFT 0
#define DOSR_EXCEPTION_ER 0x02
@ -351,7 +364,7 @@
#define DOSR_DEBUG_PEND_BIN 0x10000
#define DOSR_DEBUG_PEND_HOST 0x20000
#define DOSR_DEBUG_PEND_TRAX 0x40000
#define DOSR_DEBUG_BIN 0x100000
#define DOSR_DEBUG_BIN 0x100000
#define DOSR_DEBUG_HOST 0x200000
#define DOSR_DEBUG_TRAX 0x400000
#define DOSR_DEBUG_PEND_BIN_SHIFT 16
@ -398,26 +411,17 @@ typedef struct {
char* name;
} regdef_t;
/*char* regname(regdef_t* list, int regno)
{
unsigned i;
for(i = 0 ; i < (sizeof(list) / sizeof(regdef_t)); i++){
if(list[i].reg == regno)
return list[i].name;
}
return "???";
}*/
/*
* Returns the name of the specified XDM register number,
* or simply "???" if the register number is not recognized.
* FIXME - requires -1 as the last entry - change to compare the name to ???
* or even better, make the code above to work.
*/
static char * regname(regdef_t* list, int reg)
static char*
regname(regdef_t* list, int reg)
{
int i = 0;
while (list[i].reg != -1){
while (list[i].reg != -1) {
if (list[i].reg == reg)
break;
i++;
@ -426,38 +430,40 @@ static char * regname(regdef_t* list, int reg)
}
#if defined (USE_XDM_REGNAME)
regdef_t xdm_reglist[] =
static regdef_t xdm_reglist[] =
{
{XDM_TRAX_ID ,"TRAX_ID" },
{XDM_TRAX_CONTROL ,"CONTROL" },
{XDM_TRAX_STATUS ,"STATUS" },
{XDM_TRAX_DATA ,"DATA" },
{XDM_TRAX_ADDRESS ,"ADDRESS" },
{XDM_TRAX_TRIGGER ,"TRIGGER PC" },
{XDM_TRAX_MATCH ,"PC MATCH" },
{XDM_TRAX_DELAY ,"DELAY CNT." },
{XDM_TRAX_STARTADDR ,"START ADDRESS"},
{XDM_TRAX_ENDADDR ,"END ADDRESS" },
{XDM_TRAX_DEBUGPC ,"DEBUG PC" },
{XDM_TRAX_P4CHANGE ,"P4 CHANGE" },
{XDM_TRAX_P4REV ,"P4 REV." },
{XDM_TRAX_P4DATE ,"P4 DATE" },
{XDM_TRAX_P4TIME ,"P4 TIME" },
{XDM_TRAX_PDSTATUS ,"PD STATUS" },
{XDM_TRAX_PDDATA ,"PD DATA" },
{XDM_TRAX_STOP_PC ,"STOP PC" },
{XDM_TRAX_STOP_ICNT ,"STOP ICNT" },
{XDM_TRAX_MSG_STATUS ,"MSG STAT." },
{XDM_TRAX_FSM_STATUS ,"FSM STAT." },
{XDM_TRAX_IB_STATUS ,"IB STAT." },
{XDM_OCD_ID ,"OCD_ID" },
{XDM_OCD_DCR_CLR ,"DCR_CLR" },
{XDM_OCD_DCR_SET ,"DCR_SET" },
{XDM_OCD_DSR ,"DOSR" },
{XDM_OCD_DDR ,"DDR" },
{XDM_OCD_DDREXEC ,"DDREXEC" },
{XDM_OCD_DIR0EXEC ,"DIR0EXEC"},
{XDM_OCD_DCR_CLR ,"DCR_CLR" },
{XDM_OCD_DCR_SET ,"DCR_SET" },
{XDM_TRAX_CONTROL ,"CONTROL" },
{XDM_TRAX_STATUS ,"STATUS" },
{XDM_TRAX_DATA ,"DATA" },
{XDM_TRAX_ADDRESS ,"ADDRESS" },
{XDM_TRAX_ID ,"TRAX_ID" },
{XDM_TRAX_TRIGGER ,"TRIGGER PC" },
{XDM_TRAX_MATCH ,"PC MATCH" },
{XDM_TRAX_DELAY ,"DELAY CNT." },
{XDM_TRAX_STARTADDR ,"START ADDRESS"},
{XDM_TRAX_ENDADDR ,"END ADDRESS" },
{XDM_TRAX_DEBUGPC ,"DEBUG PC" },
{XDM_TRAX_P4CHANGE ,"P4 CHANGE" },
{XDM_TRAX_P4REV ,"P4 REV." },
{XDM_TRAX_P4DATE ,"P4 DATE" },
{XDM_TRAX_P4TIME ,"P4 TIME" },
{XDM_TRAX_PDSTATUS ,"PD STATUS" },
{XDM_TRAX_PDDATA ,"PD DATA" },
{XDM_TRAX_STOP_PC ,"STOP PC" },
{XDM_TRAX_STOP_ICNT ,"STOP ICNT" },
{XDM_TRAX_MSG_STATUS,"MSG STAT." },
{XDM_TRAX_FSM_STATUS,"FSM STAT." },
{XDM_TRAX_IB_STATUS ,"IB STAT." },
{XDM_OCD_ID ,"OCD_ID" },
{XDM_OCD_DIR0 ,"DIR0" },
{XDM_OCD_DIR1 ,"DIR1" },
{XDM_OCD_DIR2 ,"DIR2" },

22
components/xtensa/include/xtensa/xt_perf_consts.h
Wyświetl plik

@ -1,5 +1,5 @@
/*
* Customer ID=11656; Build=0x5f626; Copyright (c) 2012 by Tensilica Inc. ALL RIGHTS RESERVED.
* Copyright (c) 2012 by Tensilica Inc. ALL RIGHTS RESERVED.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -23,6 +23,8 @@
#ifndef __XT_PERF_CONSTS_H__
#define __XT_PERF_CONSTS_H__
#include <xtensa/config/core.h>
/*
* Performance monitor counter selectors
*/
@ -34,7 +36,7 @@
#define XTPERF_CNT_DCACHE_MISSES 0x8006 /* DCache misses penalty in cycles */
#define XTPERF_CNT_CYCLES 0 /* Count cycles */
#define XTPERF_CNT_OVERFLOW 1 /* Overflow of counter n-1 (assuming this is counter n) */
#define XTPERF_CNT_OVERFLOW 1 /* Overflow of counter n-1 (assuming this is counter n) */
#define XTPERF_CNT_INSN 2 /* Successfully completed instructions */
#define XTPERF_CNT_D_STALL 3 /* Data-related GlobalStall cycles */
#define XTPERF_CNT_I_STALL 4 /* Instruction-related and other GlobalStall cycles */
@ -56,9 +58,14 @@
#define XTPERF_CNT_OUTBOUND_PIF 23 /* Outbound PIF transactions */
#define XTPERF_CNT_INBOUND_PIF 24 /* Inbound PIF transactions */
#define XTPERF_CNT_PREFETCH 26 /* Prefetch events */
#if XCHAL_HW_VERSION >= 270004
#define XTPERF_CNT_IDMA 27 /* iDMA counters */
#define XTPERF_CNT_INSN_LENGTH 28 /* Instruction length counters */
#endif /* HW version >= 270004 */
/*
* Masks for each of the selector listed above
*/
@ -68,18 +75,18 @@
#define XTPERF_MASK_COMMITTED_INSN 0x0001
/* XTPERF_CNT_BRANCH_PENALTY selector mask */
#define XTPERF_MASK_BRANCH_PENALTY 0x0001
/* XTPERF_CNT_PIPELINE_INTERLOCKS selector mask */
#define XTPERF_MASK_PIPELINE_INTERLOCKS 0x0001
/* XTPERF_CNT_ICACHE_MISSES selector mask */
/* XTPERF_CNT_ICACHE_MISSES selector mask */
#define XTPERF_MASK_ICACHE_MISSES 0x0001
/* XTPERF_CNT_DCACHE_MISSES selector mask */
/* XTPERF_CNT_DCACHE_MISSES selector mask */
#define XTPERF_MASK_DCACHE_MISSES 0x0001
@ -281,6 +288,8 @@
#define XTPERF_MASK_PREFETCH_D_MISS 0x0008 /* D prefetch-buffer-lookup miss */
#define XTPERF_MASK_PREFETCH_D_L1_FILL 0x0020 /* Fill directly to DCache L1 */
#if XCHAL_HW_VERSION >= 270004
/*
* XTPERF_CNT_IDMA selector mask
*/
@ -310,4 +319,7 @@
#define XTPERF_MASK_INSN_LENGTH_112 0x1000 /* 112-bit instruction length */
#define XTPERF_MASK_INSN_LENGTH_120 0x2000 /* 120-bit instruction length */
#define XTPERF_MASK_INSN_LENGTH_128 0x4000 /* 128-bit instruction length */
#endif /* HW version >= 270004 */
#endif /* __XT_PERF_CONSTS_H__ */

4
components/xtensa/include/xtensa/xtensa-libdb-macros.h
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@ -2,7 +2,7 @@
* xtensa-libdb-macros.h
*/
/* $Id: //depot/rel/Eaglenest/Xtensa/Software/libdb/xtensa-libdb-macros.h#1 $ */
/* $Id: //depot/rel/Foxhill/dot.9/Xtensa/Software/libdb/xtensa-libdb-macros.h#1 $ */
/* Copyright (c) 2004-2008 Tensilica Inc.
@ -156,6 +156,6 @@ extern "C" {
#ifdef __cplusplus
}
#endif
#endif /* __H_LIBDB_MACROS */

111
components/xtensa/include/xtensa/xtensa-versions.h
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@ -6,10 +6,11 @@
It also provides a bit of information about which ones are current.
This file changes every release, as versions/releases get added.
*/
// $Id: //depot/rel/Foxhill/dot.9/Xtensa/Software/misc/xtensa-versions.h.tpp#1 $
$Id: //depot/rel/Eaglenest/Xtensa/Software/misc/xtensa-versions.h.tpp#2 $
Copyright (c) 2006-2010 Tensilica Inc.
/*
Copyright (c) 2006-2018 Tensilica Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
@ -51,12 +52,12 @@
#define XTENSA_HWVERSION_T1020_1 102001 /* versions T1020.1 */
#define XTENSA_HWCIDSCHEME_T1020_1 10
#define XTENSA_HWCIDVERS_T1020_1 3
#define XTENSA_HWVERSION_T1020_2B 102002 /* versions T1020.2b */
#define XTENSA_HWCIDSCHEME_T1020_2B 10
#define XTENSA_HWCIDVERS_T1020_2B 5
#define XTENSA_HWVERSION_T1020_2 102002 /* versions T1020.2 */
#define XTENSA_HWCIDSCHEME_T1020_2 10
#define XTENSA_HWCIDVERS_T1020_2 4
#define XTENSA_HWVERSION_T1020_2B 102002 /* versions T1020.2b */
#define XTENSA_HWCIDSCHEME_T1020_2B 10
#define XTENSA_HWCIDVERS_T1020_2B 5
#define XTENSA_HWVERSION_T1020_3 102003 /* versions T1020.3 */
#define XTENSA_HWCIDSCHEME_T1020_3 10
#define XTENSA_HWCIDVERS_T1020_3 6
@ -79,16 +80,16 @@
#define XTENSA_HWCIDSCHEME_T1040_0 10
#define XTENSA_HWCIDVERS_T1040_0 15
#define XTENSA_HWVERSION_T1040_1 104001 /* versions T1040.1 */
#define XTENSA_HWCIDSCHEME_T1040_1 01
#define XTENSA_HWCIDSCHEME_T1040_1 1
#define XTENSA_HWCIDVERS_T1040_1 32
#define XTENSA_HWVERSION_T1040_1P 104001 /* versions T1040.1-prehotfix */
#define XTENSA_HWCIDSCHEME_T1040_1P 10
#define XTENSA_HWCIDVERS_T1040_1P 16
#define XTENSA_HWVERSION_T1040_2 104002 /* versions T1040.2 */
#define XTENSA_HWCIDSCHEME_T1040_2 01
#define XTENSA_HWCIDSCHEME_T1040_2 1
#define XTENSA_HWCIDVERS_T1040_2 33
#define XTENSA_HWVERSION_T1040_3 104003 /* versions T1040.3 */
#define XTENSA_HWCIDSCHEME_T1040_3 01
#define XTENSA_HWCIDSCHEME_T1040_3 1
#define XTENSA_HWCIDVERS_T1040_3 34
#define XTENSA_HWVERSION_T1050_0 105000 /* versions T1050.0 */
#define XTENSA_HWCIDSCHEME_T1050_0 1100
@ -186,28 +187,28 @@
#define XTENSA_HWVERSION_RD_2012_5 240005 /* versions LX4.0.5, X9.0.5, MX1.1.5, TX1.0.5 */
#define XTENSA_HWCIDSCHEME_RD_2012_5 1100
#define XTENSA_HWCIDVERS_RD_2012_5 85
#define XTENSA_HWVERSION_RE_2012_0 250000 /* versions LX5.0.0, X10.0.0, MX1.2.0, TX2.0.0 */
#define XTENSA_HWVERSION_RE_2012_0 250000 /* versions LX5.0.0, X10.0.0, MX1.2.0 */
#define XTENSA_HWCIDSCHEME_RE_2012_0 1100
#define XTENSA_HWCIDVERS_RE_2012_0 96
#define XTENSA_HWVERSION_RE_2012_1 250001 /* versions LX5.0.1, X10.0.1, MX1.2.1, TX2.0.1 */
#define XTENSA_HWVERSION_RE_2012_1 250001 /* versions LX5.0.1, X10.0.1, MX1.2.1 */
#define XTENSA_HWCIDSCHEME_RE_2012_1 1100
#define XTENSA_HWCIDVERS_RE_2012_1 97
#define XTENSA_HWVERSION_RE_2013_2 250002 /* versions LX5.0.2, X10.0.2, MX1.2.2, TX2.0.2 */
#define XTENSA_HWVERSION_RE_2013_2 250002 /* versions LX5.0.2, X10.0.2, MX1.2.2 */
#define XTENSA_HWCIDSCHEME_RE_2013_2 1100
#define XTENSA_HWCIDVERS_RE_2013_2 98
#define XTENSA_HWVERSION_RE_2013_3 250003 /* versions LX5.0.3, X10.0.3, MX1.2.3, TX2.0.3 */
#define XTENSA_HWVERSION_RE_2013_3 250003 /* versions LX5.0.3, X10.0.3, MX1.2.3 */
#define XTENSA_HWCIDSCHEME_RE_2013_3 1100
#define XTENSA_HWCIDVERS_RE_2013_3 99
#define XTENSA_HWVERSION_RE_2013_4 250004 /* versions LX5.0.4, X10.0.4, MX1.2.4, TX2.0.4 */
#define XTENSA_HWVERSION_RE_2013_4 250004 /* versions LX5.0.4, X10.0.4, MX1.2.4 */
#define XTENSA_HWCIDSCHEME_RE_2013_4 1100
#define XTENSA_HWCIDVERS_RE_2013_4 100
#define XTENSA_HWVERSION_RE_2014_5 250005 /* versions LX5.0.5, X10.0.5, MX1.2.5, TX2.0.5 */
#define XTENSA_HWVERSION_RE_2014_5 250005 /* versions LX5.0.5, X10.0.5, MX1.2.5 */
#define XTENSA_HWCIDSCHEME_RE_2014_5 1100
#define XTENSA_HWCIDVERS_RE_2014_5 101
#define XTENSA_HWVERSION_RE_2015_6 250006 /* versions LX5.0.6, X10.0.6, MX1.2.6, TX2.0.6 */
#define XTENSA_HWVERSION_RE_2015_6 250006 /* versions LX5.0.6, X10.0.6, MX1.2.6 */
#define XTENSA_HWCIDSCHEME_RE_2015_6 1100
#define XTENSA_HWCIDVERS_RE_2015_6 102
#define XTENSA_HWVERSION_RF_2014_0 260000 /* versions LX6.0.0, X11.0.0, MX1.3.0, TX3.0.0 */
#define XTENSA_HWVERSION_RF_2014_0 260000 /* versions LX6.0.0, X11.0.0, MX1.3.0 */
#define XTENSA_HWCIDSCHEME_RF_2014_0 1100
#define XTENSA_HWCIDVERS_RF_2014_0 112
#define XTENSA_HWVERSION_RF_2014_1 260001 /* versions LX6.0.1, X11.0.1 */
@ -219,15 +220,48 @@
#define XTENSA_HWVERSION_RF_2015_3 260003 /* versions LX6.0.3, X11.0.3 */
#define XTENSA_HWCIDSCHEME_RF_2015_3 1100
#define XTENSA_HWCIDVERS_RF_2015_3 115
#define XTENSA_HWVERSION_RG_2015_0 270000 /* versions LX7.0.0, X12.0.0, NX1.0.0, SX1.0.0, MX1.4.0, TX4.0.0 */
#define XTENSA_HWVERSION_RF_2016_4 260004 /* versions LX6.0.4, X11.0.4 */
#define XTENSA_HWCIDSCHEME_RF_2016_4 1100
#define XTENSA_HWCIDVERS_RF_2016_4 116
#define XTENSA_HWVERSION_RG_2015_0 270000 /* versions LX7.0.0 */
#define XTENSA_HWCIDSCHEME_RG_2015_0 1100
#define XTENSA_HWCIDVERS_RG_2015_0 128
#define XTENSA_HWVERSION_RG_2015_1 270001 /* versions LX7.0.1 */
#define XTENSA_HWCIDSCHEME_RG_2015_1 1100
#define XTENSA_HWCIDVERS_RG_2015_1 129
#define XTENSA_HWVERSION_RG_2015_2 270002 /* versions LX7.0.2 */
#define XTENSA_HWCIDSCHEME_RG_2015_2 1100
#define XTENSA_HWCIDVERS_RG_2015_2 130
#define XTENSA_HWVERSION_RG_2016_3 270003 /* versions LX7.0.3 */
#define XTENSA_HWCIDSCHEME_RG_2016_3 1100
#define XTENSA_HWCIDVERS_RG_2016_3 131
#define XTENSA_HWVERSION_RG_2016_4 270004 /* versions LX7.0.4 */
#define XTENSA_HWCIDSCHEME_RG_2016_4 1100
#define XTENSA_HWCIDVERS_RG_2016_4 132
#define XTENSA_HWVERSION_RG_2017_5 270005 /* versions LX7.0.5 */
#define XTENSA_HWCIDSCHEME_RG_2017_5 1100
#define XTENSA_HWCIDVERS_RG_2017_5 133
#define XTENSA_HWVERSION_RG_2017_6 270006 /* versions LX7.0.6 */
#define XTENSA_HWCIDSCHEME_RG_2017_6 1100
#define XTENSA_HWCIDVERS_RG_2017_6 134
#define XTENSA_HWVERSION_RG_2017_7 270007 /* versions LX7.0.7 */
#define XTENSA_HWCIDSCHEME_RG_2017_7 1100
#define XTENSA_HWCIDVERS_RG_2017_7 135
#define XTENSA_HWVERSION_RG_2017_8 270008 /* versions LX7.0.8 */
#define XTENSA_HWCIDSCHEME_RG_2017_8 1100
#define XTENSA_HWCIDVERS_RG_2017_8 136
#define XTENSA_HWVERSION_RG_2018_9 270009 /* versions LX7.0.9 */
#define XTENSA_HWCIDSCHEME_RG_2018_9 1100
#define XTENSA_HWCIDVERS_RG_2018_9 137
#define XTENSA_HWVERSION_RH_2016_0 280000 /* versions LX8.0.0, NX1.0.0, SX1.0.0 */
#define XTENSA_HWCIDSCHEME_RH_2016_0 1100
#define XTENSA_HWCIDVERS_RH_2016_0 144
/* Software (Xtensa Tools) versions: */
#define XTENSA_SWVERSION_T1020_0 102000 /* versions T1020.0 */
#define XTENSA_SWVERSION_T1020_1 102001 /* versions T1020.1 */
#define XTENSA_SWVERSION_T1020_2B 102002 /* versions T1020.2b */
#define XTENSA_SWVERSION_T1020_2 102002 /* versions T1020.2 */
#define XTENSA_SWVERSION_T1020_2B 102002 /* versions T1020.2b */
#define XTENSA_SWVERSION_T1020_3 102003 /* versions T1020.3 */
#define XTENSA_SWVERSION_T1020_4 102004 /* versions T1020.4 */
#define XTENSA_SWVERSION_T1030_0 103000 /* versions T1030.0 */
@ -282,7 +316,18 @@
#define XTENSA_SWVERSION_RF_2014_1 1100001 /* versions 11.0.1 */
#define XTENSA_SWVERSION_RF_2015_2 1100002 /* versions 11.0.2 */
#define XTENSA_SWVERSION_RF_2015_3 1100003 /* versions 11.0.3 */
#define XTENSA_SWVERSION_RF_2016_4 1100004 /* versions 11.0.4 */
#define XTENSA_SWVERSION_RG_2015_0 1200000 /* versions 12.0.0 */
#define XTENSA_SWVERSION_RG_2015_1 1200001 /* versions 12.0.1 */
#define XTENSA_SWVERSION_RG_2015_2 1200002 /* versions 12.0.2 */
#define XTENSA_SWVERSION_RG_2016_3 1200003 /* versions 12.0.3 */
#define XTENSA_SWVERSION_RG_2016_4 1200004 /* versions 12.0.4 */
#define XTENSA_SWVERSION_RG_2017_5 1200005 /* versions 12.0.5 */
#define XTENSA_SWVERSION_RG_2017_6 1200006 /* versions 12.0.6 */
#define XTENSA_SWVERSION_RG_2017_7 1200007 /* versions 12.0.7 */
#define XTENSA_SWVERSION_RG_2017_8 1200008 /* versions 12.0.8 */
#define XTENSA_SWVERSION_RG_2018_9 1200009 /* versions 12.0.9 */
#define XTENSA_SWVERSION_RH_2016_0 1300000 /* versions 13.0.0 */
#define XTENSA_SWVERSION_T1040_1_PREHOTFIX XTENSA_SWVERSION_T1040_1P /* T1040.1-prehotfix */
#define XTENSA_SWVERSION_6_0_0 XTENSA_SWVERSION_RA_2004_1 /* 6.0.0 */
#define XTENSA_SWVERSION_6_0_1 XTENSA_SWVERSION_RA_2005_1 /* 6.0.1 */
@ -321,21 +366,33 @@
#define XTENSA_SWVERSION_11_0_1 XTENSA_SWVERSION_RF_2014_1 /* 11.0.1 */
#define XTENSA_SWVERSION_11_0_2 XTENSA_SWVERSION_RF_2015_2 /* 11.0.2 */
#define XTENSA_SWVERSION_11_0_3 XTENSA_SWVERSION_RF_2015_3 /* 11.0.3 */
#define XTENSA_SWVERSION_11_0_4 XTENSA_SWVERSION_RF_2016_4 /* 11.0.4 */
#define XTENSA_SWVERSION_12_0_0 XTENSA_SWVERSION_RG_2015_0 /* 12.0.0 */
#define XTENSA_SWVERSION_12_0_1 XTENSA_SWVERSION_RG_2015_1 /* 12.0.1 */
#define XTENSA_SWVERSION_12_0_2 XTENSA_SWVERSION_RG_2015_2 /* 12.0.2 */
#define XTENSA_SWVERSION_12_0_3 XTENSA_SWVERSION_RG_2016_3 /* 12.0.3 */
#define XTENSA_SWVERSION_12_0_4 XTENSA_SWVERSION_RG_2016_4 /* 12.0.4 */
#define XTENSA_SWVERSION_12_0_5 XTENSA_SWVERSION_RG_2017_5 /* 12.0.5 */
#define XTENSA_SWVERSION_12_0_6 XTENSA_SWVERSION_RG_2017_6 /* 12.0.6 */
#define XTENSA_SWVERSION_12_0_7 XTENSA_SWVERSION_RG_2017_7 /* 12.0.7 */
#define XTENSA_SWVERSION_12_0_8 XTENSA_SWVERSION_RG_2017_8 /* 12.0.8 */
#define XTENSA_SWVERSION_12_0_9 XTENSA_SWVERSION_RG_2018_9 /* 12.0.9 */
#define XTENSA_SWVERSION_13_0_0 XTENSA_SWVERSION_RH_2016_0 /* 13.0.0 */
/* The current release: */
#define XTENSA_RELEASE_NAME "RF-2015.3"
#define XTENSA_RELEASE_CANONICAL_NAME "RF-2015.3"
#define XTENSA_RELEASE_NAME "RG-2018.9"
#define XTENSA_RELEASE_CANONICAL_NAME "RG-2018.9"
/* The product versions within the current release: */
#define XTENSA_SWVERSION XTENSA_SWVERSION_RF_2015_3
#define XTENSA_SWVERSION_NAME "11.0.3"
#define XTENSA_SWVERSION_CANONICAL_NAME "11.0.3"
#define XTENSA_SWVERSION_MAJORMID_NAME "11.0"
#define XTENSA_SWVERSION_MAJOR_NAME "11"
#define XTENSA_SWVERSION XTENSA_SWVERSION_RG_2018_9
#define XTENSA_SWVERSION_NAME "12.0.9"
#define XTENSA_SWVERSION_NAME_IDENT 12_0_9
#define XTENSA_SWVERSION_CANONICAL_NAME "12.0.9"
#define XTENSA_SWVERSION_MAJORMID_NAME "12.0"
#define XTENSA_SWVERSION_MAJOR_NAME "12"
/* For product licensing (not necessarily same as *_MAJORMID_NAME): */
#define XTENSA_SWVERSION_LICENSE_NAME "11.0"
#define XTENSA_SWVERSION_LICENSE_NAME "12.0"
/* Note: there may be multiple hardware products in one release,
and software can target older hardware, so the notion of

30
components/xtensa/include/xtensa/xtruntime-core-state.h
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@ -1,5 +1,5 @@
/* xtruntime-core-state.h - core state save area (used eg. by PSO) */
/* $Id: //depot/rel/Eaglenest/Xtensa/OS/include/xtensa/xtruntime-core-state.h#1 $ */
/* $Id: //depot/rel/Foxhill/dot.9/Xtensa/OS/include/xtensa/xtruntime-core-state.h#1 $ */
/*
* Copyright (c) 2012-2013 Tensilica Inc.
@ -31,6 +31,9 @@
#include <xtensa/xtruntime-frames.h>
#include <xtensa/config/core.h>
#include <xtensa/config/tie.h>
#if XCHAL_HAVE_IDMA
#include <xtensa/idma.h>
#endif
//#define XTOS_PSO_TEST 1 // uncommented for internal PSO testing only
@ -155,6 +158,15 @@ STRUCT_AFIELD(long,4,CS_SA_,tlbs,((4*ARF_ENTRIES+4)*2+3)*2)
STRUCT_AFIELD(long,4,CS_SA_,tlbs_ways56,(4+8)*2*2)
# endif
#endif
/* MPU state */
#if XCHAL_HAVE_MPU
STRUCT_AFIELD(long,4,CS_SA_,mpuentry,8*XCHAL_MPU_ENTRIES)
STRUCT_FIELD (long,4,CS_SA_,cacheadrdis)
#endif
#if XCHAL_HAVE_IDMA
STRUCT_AFIELD(long,4,CS_SA_,idmaregs, IDMA_PSO_SAVE_SIZE)
#endif
/* TIE state */
/* NOTE: NCP area is aligned to XCHAL_TOTAL_SA_ALIGN not XCHAL_NCP_SA_ALIGN,
@ -162,14 +174,30 @@ STRUCT_AFIELD(long,4,CS_SA_,tlbs_ways56,(4+8)*2*2)
to the NCP save area. */
STRUCT_AFIELD_A(char,1,XCHAL_TOTAL_SA_ALIGN,CS_SA_,ncp,XCHAL_NCP_SA_SIZE)
#if XCHAL_HAVE_CP
#if XCHAL_CP0_SA_SIZE > 0
STRUCT_AFIELD_A(char,1,XCHAL_CP0_SA_ALIGN,CS_SA_,cp0,XCHAL_CP0_SA_SIZE)
#endif
#if XCHAL_CP1_SA_SIZE > 0
STRUCT_AFIELD_A(char,1,XCHAL_CP1_SA_ALIGN,CS_SA_,cp1,XCHAL_CP1_SA_SIZE)
#endif
#if XCHAL_CP2_SA_SIZE > 0
STRUCT_AFIELD_A(char,1,XCHAL_CP2_SA_ALIGN,CS_SA_,cp2,XCHAL_CP2_SA_SIZE)
#endif
#if XCHAL_CP3_SA_SIZE > 0
STRUCT_AFIELD_A(char,1,XCHAL_CP3_SA_ALIGN,CS_SA_,cp3,XCHAL_CP3_SA_SIZE)
#endif
#if XCHAL_CP4_SA_SIZE > 0
STRUCT_AFIELD_A(char,1,XCHAL_CP4_SA_ALIGN,CS_SA_,cp4,XCHAL_CP4_SA_SIZE)
#endif
#if XCHAL_CP5_SA_SIZE > 0
STRUCT_AFIELD_A(char,1,XCHAL_CP5_SA_ALIGN,CS_SA_,cp5,XCHAL_CP5_SA_SIZE)
#endif
#if XCHAL_CP6_SA_SIZE > 0
STRUCT_AFIELD_A(char,1,XCHAL_CP6_SA_ALIGN,CS_SA_,cp6,XCHAL_CP6_SA_SIZE)
#endif
#if XCHAL_CP7_SA_SIZE > 0
STRUCT_AFIELD_A(char,1,XCHAL_CP7_SA_ALIGN,CS_SA_,cp7,XCHAL_CP7_SA_SIZE)
#endif
//STRUCT_AFIELD_A(char,1,XCHAL_CP8_SA_ALIGN,CS_SA_,cp8,XCHAL_CP8_SA_SIZE)
//STRUCT_AFIELD_A(char,1,XCHAL_CP9_SA_ALIGN,CS_SA_,cp9,XCHAL_CP9_SA_SIZE)
//STRUCT_AFIELD_A(char,1,XCHAL_CP10_SA_ALIGN,CS_SA_,cp10,XCHAL_CP10_SA_SIZE)

2
components/xtensa/include/xtensa/xtruntime-frames.h
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@ -1,5 +1,5 @@
/* xtruntime-frames.h - exception stack frames for single-threaded run-time */
/* $Id: //depot/rel/Eaglenest/Xtensa/OS/include/xtensa/xtruntime-frames.h#1 $ */
/* $Id: //depot/rel/Foxhill/dot.9/Xtensa/OS/include/xtensa/xtruntime-frames.h#1 $ */
/*
* Copyright (c) 2002-2012 Tensilica Inc.

32
components/xtensa/include/xtensa/xtruntime.h
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@ -41,6 +41,9 @@
#define XTOS_KEEPON_DEBUG 0x00001000 /* ==PWRCTL_DEBUG_WAKEUP */
#define XTOS_KEEPON_DEBUG_SHIFT 12
#define XTOS_IDMA_NO_WAIT 0x00010000 /* Do not wait for idma to finish. Disable if necessary */
#define XTOS_IDMA_WAIT_STANDBY 0x00020000 /* Also treat standby state as the end of wait */
#define XTOS_COREF_PSO 0x00000001 /* do power shutoff */
#define XTOS_COREF_PSO_SHIFT 0
@ -54,8 +57,9 @@
extern "C" {
#endif
/*typedef void (_xtos_timerdelta_func)(int);*/
#ifdef __cplusplus
#if defined(XTOS_MISRA)
typedef void (_xtos_handler_func)(void *);
#elif defined(__cplusplus)
typedef void (_xtos_handler_func)(...);
#else
typedef void (_xtos_handler_func)(void);
@ -84,12 +88,12 @@ typedef _xtos_handler_func *_xtos_handler;
* these macros are sometimes used to delineate critical sections;
* function calls are natural barriers (the compiler does not know
* whether a function modifies memory) unless declared to be inlined. */
# define XTOS_SET_INTLEVEL(intlevel) ({ unsigned __tmp; \
# define XTOS_SET_INTLEVEL(intlevel) __extension__({ unsigned __tmp; \
__asm__ __volatile__( "rsil %0, " XTSTR(intlevel) "\n" \
: "=a" (__tmp) : : "memory" ); \
__tmp;})
# define XTOS_SET_MIN_INTLEVEL(intlevel) ({ unsigned __tmp, __tmp2, __tmp3; \
__asm__ __volatile__( "rsr %0, " XTSTR(PS) "\n" /* get old (current) PS.INTLEVEL */ \
__asm__ __volatile__( "rsr.ps %0\n" /* get old (current) PS.INTLEVEL */ \
"movi %2, " XTSTR(intlevel) "\n" \
"extui %1, %0, 0, 4\n" /* keep only INTLEVEL bits of parameter */ \
"blt %2, %1, 1f\n" \
@ -98,7 +102,7 @@ typedef _xtos_handler_func *_xtos_handler;
: "=a" (__tmp), "=&a" (__tmp2), "=&a" (__tmp3) : : "memory" ); \
__tmp;})
# define XTOS_RESTORE_INTLEVEL(restoreval) do{ unsigned __tmp = (restoreval); \
__asm__ __volatile__( "wsr %0, " XTSTR(PS) " ; rsync\n" \
__asm__ __volatile__( "wsr.ps %0 ; rsync\n" \
: : "a" (__tmp) : "memory" ); \
}while(0)
# define XTOS_RESTORE_JUST_INTLEVEL(restoreval) _xtos_set_intlevel(restoreval)
@ -147,9 +151,21 @@ extern unsigned _xtos_vpri_enabled; /* current virtual priority */
* configuration has high-level interrupts and one cares about their latency): */
#define XTOS_DISABLE_ALL_INTERRUPTS XTOS_SET_INTLEVEL(15)
/* These two are deprecated. Use the newer functions below. */
extern unsigned int _xtos_ints_off( unsigned int mask );
extern unsigned int _xtos_ints_on( unsigned int mask );
/* Newer functions to enable/disable the specified interrupt. */
static inline void _xtos_interrupt_enable(unsigned int intnum)
{
_xtos_ints_on(1 << intnum);
}
static inline void _xtos_interrupt_disable(unsigned int intnum)
{
_xtos_ints_off(1 << intnum);
}
extern unsigned _xtos_set_intlevel( int intlevel );
extern unsigned _xtos_set_min_intlevel( int intlevel );
extern unsigned _xtos_restore_intlevel( unsigned restoreval );
@ -182,8 +198,8 @@ extern void _xtos_dispatch_level6_interrupts( void );
#endif
/* Deprecated (but kept because they were documented): */
extern unsigned int _xtos_read_ints( void ); /* use xthal_get_interrupt() instead */
extern void _xtos_clear_ints( unsigned int mask ); /* use xthal_set_intclear() instead */
extern unsigned int _xtos_read_ints( void );
extern void _xtos_clear_ints( unsigned int mask );
/* Power shut-off related routines. */